am335x-sl50.dts 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
  4. */
  5. /dts-v1/;
  6. #include "am33xx.dtsi"
  7. #include <dt-bindings/pwm/pwm.h>
  8. #include <dt-bindings/interrupt-controller/irq.h>
  9. / {
  10. model = "Toby Churchill SL50 Series";
  11. compatible = "tcl,am335x-sl50", "ti,am33xx";
  12. cpus {
  13. cpu@0 {
  14. cpu0-supply = <&dcdc2_reg>;
  15. };
  16. };
  17. memory@80000000 {
  18. device_type = "memory";
  19. reg = <0x80000000 0x20000000>; /* 512 MB */
  20. };
  21. chosen {
  22. stdout-path = &uart0;
  23. };
  24. leds {
  25. compatible = "gpio-leds";
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&led_pins>;
  28. led0 {
  29. label = "sl50:red:usr0";
  30. gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
  31. default-state = "off";
  32. };
  33. led1 {
  34. label = "sl50:green:usr1";
  35. gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
  36. default-state = "off";
  37. };
  38. led2 {
  39. label = "sl50:red:usr2";
  40. gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
  41. default-state = "off";
  42. };
  43. led3 {
  44. label = "sl50:green:usr3";
  45. gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  46. default-state = "off";
  47. };
  48. };
  49. backlight0: disp0 {
  50. compatible = "pwm-backlight";
  51. pinctrl-names = "default";
  52. pinctrl-0 = <&backlight0_pins>;
  53. pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>;
  54. brightness-levels = < 0 1 2 3 4 5 6 7 8 9
  55. 10 11 12 13 14 15 16 17 18 19
  56. 20 21 22 23 24 25 26 27 28 29
  57. 30 31 32 33 34 35 36 37 38 39
  58. 40 41 42 43 44 45 46 47 48 49
  59. 50 51 52 53 54 55 56 57 58 59
  60. 60 61 62 63 64 65 66 67 68 69
  61. 70 71 72 73 74 75 76 77 78 79
  62. 80 81 82 83 84 85 86 87 88 89
  63. 90 91 92 93 94 95 96 97 98 99
  64. 100>;
  65. default-brightness-level = <50>;
  66. enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
  67. power-supply = <&vdd_sys_reg>;
  68. };
  69. backlight1: disp1 {
  70. compatible = "pwm-backlight";
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&backlight1_pins>;
  73. pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>;
  74. brightness-levels = < 0 1 2 3 4 5 6 7 8 9
  75. 10 11 12 13 14 15 16 17 18 19
  76. 20 21 22 23 24 25 26 27 28 29
  77. 30 31 32 33 34 35 36 37 38 39
  78. 40 41 42 43 44 45 46 47 48 49
  79. 50 51 52 53 54 55 56 57 58 59
  80. 60 61 62 63 64 65 66 67 68 69
  81. 70 71 72 73 74 75 76 77 78 79
  82. 80 81 82 83 84 85 86 87 88 89
  83. 90 91 92 93 94 95 96 97 98 99
  84. 100>;
  85. default-brightness-level = <50>;
  86. enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
  87. power-supply = <&vdd_sys_reg>;
  88. };
  89. clocks {
  90. compatible = "simple-bus";
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. /* audio external oscillator */
  94. audio_mclk_fixed: oscillator@0 {
  95. compatible = "fixed-clock";
  96. #clock-cells = <0>;
  97. clock-frequency = <24576000>; /* 24.576MHz */
  98. };
  99. audio_mclk: audio_mclk_gate@0 {
  100. compatible = "gpio-gate-clock";
  101. #clock-cells = <0>;
  102. pinctrl-names = "default";
  103. pinctrl-0 = <&audio_mclk_pins>;
  104. clocks = <&audio_mclk_fixed>;
  105. enable-gpios = <&gpio1 27 0>;
  106. };
  107. };
  108. panel: lcd_panel {
  109. compatible = "ti,tilcdc,panel";
  110. pinctrl-names = "default";
  111. pinctrl-0 = <&lcd_pins>;
  112. panel-info {
  113. ac-bias = <255>;
  114. ac-bias-intrpt = <0>;
  115. dma-burst-sz = <16>;
  116. bpp = <16>;
  117. fdd = <0x80>;
  118. tft-alt-mode = <0>;
  119. mono-8bit-mode = <0>;
  120. sync-edge = <0>;
  121. sync-ctrl = <1>;
  122. raster-order = <0>;
  123. fifo-th = <0>;
  124. };
  125. display-timings {
  126. native-mode = <&timing0>;
  127. timing0: 960x128 {
  128. clock-frequency = <18000000>;
  129. hactive = <960>;
  130. vactive = <272>;
  131. hback-porch = <40>;
  132. hfront-porch = <16>;
  133. hsync-len = <24>;
  134. hsync-active = <0>;
  135. vback-porch = <3>;
  136. vfront-porch = <8>;
  137. vsync-len = <4>;
  138. vsync-active = <0>;
  139. };
  140. };
  141. };
  142. sound {
  143. compatible = "audio-graph-card";
  144. label = "sound-card";
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&audio_pa_pins>;
  147. widgets = "Headphone", "Headphone Jack",
  148. "Speaker", "Speaker External",
  149. "Line", "Line In",
  150. "Microphone", "Microphone Jack";
  151. routing = "Headphone Jack", "HPLOUT",
  152. "Headphone Jack", "HPROUT",
  153. "Amplifier", "MONO_LOUT",
  154. "Speaker External", "Amplifier",
  155. "LINE1R", "Line In",
  156. "LINE1L", "Line In",
  157. "MIC3L", "Microphone Jack",
  158. "MIC3R", "Microphone Jack",
  159. "Microphone Jack", "Mic Bias";
  160. dais = <&cpu_port>;
  161. pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
  162. };
  163. emmc_pwrseq: pwrseq@0 {
  164. compatible = "mmc-pwrseq-emmc";
  165. pinctrl-names = "default";
  166. pinctrl-0 = <&emmc_pwrseq_pins>;
  167. reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
  168. };
  169. vdd_sys_reg: regulator@0 {
  170. compatible = "regulator-fixed";
  171. regulator-name = "vdd_sys_reg";
  172. regulator-min-microvolt = <5000000>;
  173. regulator-max-microvolt = <5000000>;
  174. regulator-always-on;
  175. };
  176. vmmcsd_fixed: fixedregulator0 {
  177. compatible = "regulator-fixed";
  178. regulator-name = "vmmcsd_fixed";
  179. regulator-min-microvolt = <3300000>;
  180. regulator-max-microvolt = <3300000>;
  181. };
  182. };
  183. &am33xx_pinmux {
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&lwb_pins>;
  186. audio_pins: pinmux_audio_pins {
  187. pinctrl-single,pins = <
  188. AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
  189. AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
  190. AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
  191. AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
  192. AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
  193. >;
  194. };
  195. audio_pa_pins: pinmux_audio_pa_pins {
  196. pinctrl-single,pins = <
  197. AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */
  198. >;
  199. };
  200. audio_mclk_pins: pinmux_audio_mclk_pins {
  201. pinctrl-single,pins = <
  202. AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */
  203. >;
  204. };
  205. backlight0_pins: pinmux_backlight0_pins {
  206. pinctrl-single,pins = <
  207. AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */
  208. >;
  209. };
  210. backlight1_pins: pinmux_backlight1_pins {
  211. pinctrl-single,pins = <
  212. AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */
  213. >;
  214. };
  215. lcd_pins: pinmux_lcd_pins {
  216. pinctrl-single,pins = <
  217. AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
  218. AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
  219. AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
  220. AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
  221. AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
  222. AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
  223. AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
  224. AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
  225. AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
  226. AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
  227. AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
  228. AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
  229. AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
  230. AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
  231. AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
  232. AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
  233. AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  234. AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  235. AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  236. AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  237. >;
  238. };
  239. led_pins: pinmux_led_pins {
  240. pinctrl-single,pins = <
  241. AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */
  242. AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */
  243. AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */
  244. AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */
  245. >;
  246. };
  247. uart0_pins: pinmux_uart0_pins {
  248. pinctrl-single,pins = <
  249. AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
  250. AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  251. >;
  252. };
  253. uart1_pins: pinmux_uart1_pins {
  254. pinctrl-single,pins = <
  255. AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
  256. AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  257. >;
  258. };
  259. uart4_pins: pinmux_uart4_pins {
  260. pinctrl-single,pins = <
  261. AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */
  262. AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */
  263. >;
  264. };
  265. i2c0_pins: pinmux_i2c0_pins {
  266. pinctrl-single,pins = <
  267. AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
  268. AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
  269. >;
  270. };
  271. i2c2_pins: pinmux_i2c2_pins {
  272. pinctrl-single,pins = <
  273. AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */
  274. AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */
  275. >;
  276. };
  277. cpsw_default: cpsw_default {
  278. pinctrl-single,pins = <
  279. /* Slave 1 */
  280. AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
  281. AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  282. AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
  283. AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  284. AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  285. AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  286. AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  287. AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
  288. AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
  289. AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
  290. AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
  291. AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
  292. AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
  293. >;
  294. };
  295. cpsw_sleep: cpsw_sleep {
  296. pinctrl-single,pins = <
  297. /* Slave 1 reset value */
  298. AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
  299. AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
  300. AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
  301. AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
  302. AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
  303. AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
  304. AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
  305. AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
  306. AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
  307. AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
  308. AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
  309. AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
  310. AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
  311. >;
  312. };
  313. davinci_mdio_default: davinci_mdio_default {
  314. pinctrl-single,pins = <
  315. /* MDIO */
  316. AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
  317. AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
  318. /* Ethernet */
  319. AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */
  320. >;
  321. };
  322. davinci_mdio_sleep: davinci_mdio_sleep {
  323. pinctrl-single,pins = <
  324. /* MDIO reset value */
  325. AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
  326. AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
  327. >;
  328. };
  329. mmc1_pins: pinmux_mmc1_pins {
  330. pinctrl-single,pins = <
  331. AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */
  332. >;
  333. };
  334. emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
  335. pinctrl-single,pins = <
  336. AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */
  337. >;
  338. };
  339. emmc_pins: pinmux_emmc_pins {
  340. pinctrl-single,pins = <
  341. AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
  342. AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
  343. AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
  344. AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
  345. AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
  346. AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
  347. AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
  348. AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
  349. AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
  350. AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
  351. >;
  352. };
  353. ehrpwm1_pins: pinmux_ehrpwm1a_pins {
  354. pinctrl-single,pins = <
  355. AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */
  356. AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */
  357. >;
  358. };
  359. rtc0_irq_pins: pinmux_rtc0_irq_pins {
  360. pinctrl-single,pins = <
  361. AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */
  362. >;
  363. };
  364. spi0_pins: pinmux_spi0_pins {
  365. pinctrl-single,pins = <
  366. AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */
  367. AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */
  368. AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
  369. AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */
  370. AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */
  371. >;
  372. };
  373. lwb_pins: pinmux_lwb_pins {
  374. pinctrl-single,pins = <
  375. AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */
  376. AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */
  377. AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
  378. /* PDI Bus - Battery system */
  379. AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */
  380. AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */
  381. /* FPGA */
  382. AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */
  383. AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */
  384. AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */
  385. AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */
  386. AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */
  387. >;
  388. };
  389. };
  390. &i2c0 {
  391. status = "okay";
  392. pinctrl-names = "default";
  393. pinctrl-0 = <&i2c0_pins>;
  394. clock-frequency = <400000>;
  395. tps: tps@24 {
  396. reg = <0x24>;
  397. };
  398. rtc0: rtc@68 {
  399. compatible = "dallas,ds1339";
  400. pinctrl-names = "default";
  401. pinctrl-0 = <&rtc0_irq_pins>;
  402. interrupt-parent = <&gpio0>;
  403. interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */
  404. wakeup-source;
  405. trickle-resistor-ohms = <2000>;
  406. reg = <0x68>;
  407. };
  408. eeprom: eeprom@50 {
  409. compatible = "atmel,24c256";
  410. reg = <0x50>;
  411. };
  412. gpio_exp: mcp23017@20 {
  413. compatible = "microchip,mcp23017";
  414. reg = <0x20>;
  415. };
  416. };
  417. &i2c2 {
  418. status = "okay";
  419. pinctrl-names = "default";
  420. pinctrl-0 = <&i2c2_pins>;
  421. clock-frequency = <400000>;
  422. audio_codec: tlv320aic3106@1b {
  423. status = "okay";
  424. compatible = "ti,tlv320aic3106";
  425. #sound-dai-cells = <0>;
  426. reg = <0x1b>;
  427. ai3x-micbias-vg = <2>; /* 2.5V */
  428. AVDD-supply = <&ldo4_reg>;
  429. IOVDD-supply = <&ldo4_reg>;
  430. DRVDD-supply = <&ldo4_reg>;
  431. DVDD-supply = <&ldo3_reg>;
  432. codec_port: port {
  433. codec_endpoint: endpoint {
  434. remote-endpoint = <&cpu_endpoint>;
  435. clocks = <&audio_mclk>;
  436. };
  437. };
  438. };
  439. /* Ambient Light Sensor */
  440. als: isl29023@44 {
  441. compatible = "isil,isl29023";
  442. reg = <0x44>;
  443. };
  444. };
  445. &rtc {
  446. status = "disabled";
  447. };
  448. &usb0 {
  449. dr_mode = "otg";
  450. };
  451. &usb1 {
  452. dr_mode = "host";
  453. };
  454. &mmc1 {
  455. status = "okay";
  456. pinctrl-names = "default";
  457. pinctrl-0 = <&mmc1_pins>;
  458. bus-width = <4>;
  459. cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  460. vmmc-supply = <&vmmcsd_fixed>;
  461. };
  462. &mmc2 {
  463. status = "okay";
  464. pinctrl-names = "default";
  465. pinctrl-0 = <&emmc_pins>;
  466. bus-width = <8>;
  467. vmmc-supply = <&vmmcsd_fixed>;
  468. mmc-pwrseq = <&emmc_pwrseq>;
  469. };
  470. &mcasp0 {
  471. status = "okay";
  472. pinctrl-names = "default";
  473. pinctrl-0 = <&audio_pins>;
  474. #sound-dai-cells = <0>;
  475. op-mode = <0>; /* MCASP_ISS_MODE */
  476. tdm-slots = <2>;
  477. /* 4 serializers */
  478. serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
  479. 0 0 1 2
  480. >;
  481. tx-num-evt = <32>;
  482. rx-num-evt = <32>;
  483. cpu_port: port {
  484. cpu_endpoint: endpoint {
  485. remote-endpoint = <&codec_endpoint>;
  486. dai-format = "dsp_b";
  487. bitclock-master = <&codec_port>;
  488. frame-master = <&codec_port>;
  489. bitclock-inversion;
  490. clocks = <&audio_mclk>;
  491. };
  492. };
  493. };
  494. &uart0 {
  495. status = "okay";
  496. pinctrl-names = "default";
  497. pinctrl-0 = <&uart0_pins>;
  498. };
  499. &uart1 {
  500. status = "okay";
  501. pinctrl-names = "default";
  502. pinctrl-0 = <&uart1_pins>;
  503. };
  504. &uart4 {
  505. status = "okay";
  506. pinctrl-names = "default";
  507. pinctrl-0 = <&uart4_pins>;
  508. };
  509. &spi0 {
  510. status = "okay";
  511. pinctrl-names = "default";
  512. pinctrl-0 = <&spi0_pins>;
  513. flash: flash@1 {
  514. #address-cells = <1>;
  515. #size-cells = <1>;
  516. compatible = "micron,n25q032";
  517. reg = <1>;
  518. spi-max-frequency = <5000000>;
  519. };
  520. };
  521. #include "tps65217.dtsi"
  522. &tps {
  523. ti,pmic-shutdown-controller;
  524. interrupt-parent = <&intc>;
  525. interrupts = <7>; /* NNMI */
  526. regulators {
  527. dcdc1_reg: regulator@0 {
  528. /* VDDS_DDR */
  529. regulator-min-microvolt = <1500000>;
  530. regulator-max-microvolt = <1500000>;
  531. regulator-always-on;
  532. };
  533. dcdc2_reg: regulator@1 {
  534. /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  535. regulator-name = "vdd_mpu";
  536. regulator-min-microvolt = <925000>;
  537. regulator-max-microvolt = <1325000>;
  538. regulator-boot-on;
  539. regulator-always-on;
  540. };
  541. dcdc3_reg: regulator@2 {
  542. /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  543. regulator-name = "vdd_core";
  544. regulator-min-microvolt = <925000>;
  545. regulator-max-microvolt = <1150000>;
  546. regulator-boot-on;
  547. regulator-always-on;
  548. };
  549. ldo1_reg: regulator@3 {
  550. /* VRTC / VIO / VDDS*/
  551. regulator-always-on;
  552. regulator-min-microvolt = <1800000>;
  553. regulator-max-microvolt = <1800000>;
  554. };
  555. ldo2_reg: regulator@4 {
  556. /* VDD_3V3AUX */
  557. regulator-always-on;
  558. regulator-min-microvolt = <3300000>;
  559. regulator-max-microvolt = <3300000>;
  560. };
  561. ldo3_reg: regulator@5 {
  562. /* VDD_1V8 */
  563. regulator-min-microvolt = <1800000>;
  564. regulator-max-microvolt = <1800000>;
  565. regulator-always-on;
  566. };
  567. ldo4_reg: regulator@6 {
  568. /* VDD_3V3A */
  569. regulator-min-microvolt = <3300000>;
  570. regulator-max-microvolt = <3300000>;
  571. regulator-always-on;
  572. };
  573. };
  574. };
  575. &cpsw_port1 {
  576. phy-mode = "mii";
  577. phy-handle = <&ethphy0>;
  578. ti,dual-emac-pvid = <1>;
  579. };
  580. &cpsw_port2 {
  581. status = "disabled";
  582. };
  583. &mac_sw {
  584. status = "okay";
  585. pinctrl-names = "default", "sleep";
  586. pinctrl-0 = <&cpsw_default>;
  587. pinctrl-1 = <&cpsw_sleep>;
  588. };
  589. &davinci_mdio_sw {
  590. pinctrl-names = "default", "sleep";
  591. pinctrl-0 = <&davinci_mdio_default>;
  592. pinctrl-1 = <&davinci_mdio_sleep>;
  593. reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  594. reset-delay-us = <100>; /* PHY datasheet states 100us min */
  595. ethphy0: ethernet-phy@0 {
  596. reg = <0>;
  597. };
  598. };
  599. &sham {
  600. status = "okay";
  601. };
  602. &aes {
  603. status = "okay";
  604. };
  605. &epwmss1 {
  606. status = "okay";
  607. };
  608. &ehrpwm1 {
  609. status = "okay";
  610. pinctrl-names = "default";
  611. pinctrl-0 = <&ehrpwm1_pins>;
  612. };
  613. &lcdc {
  614. status = "okay";
  615. };
  616. &tscadc {
  617. status = "okay";
  618. };
  619. &am335x_adc {
  620. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  621. };