vdk_axc003.dtsi 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
  4. */
  5. /*
  6. * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
  7. */
  8. /include/ "skeleton_hs.dtsi"
  9. / {
  10. compatible = "snps,arc";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. cpu_card {
  14. compatible = "simple-bus";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. ranges = <0x00000000 0xf0000000 0x10000000>;
  18. core_clk: core_clk {
  19. #clock-cells = <0>;
  20. compatible = "fixed-clock";
  21. clock-frequency = <50000000>;
  22. };
  23. core_intc: archs-intc@cpu {
  24. compatible = "snps,archs-intc";
  25. interrupt-controller;
  26. #interrupt-cells = <1>;
  27. };
  28. debug_uart: dw-apb-uart@5000 {
  29. compatible = "snps,dw-apb-uart";
  30. reg = <0x5000 0x100>;
  31. clock-frequency = <2403200>;
  32. interrupt-parent = <&core_intc>;
  33. interrupts = <19>;
  34. baud = <115200>;
  35. reg-shift = <2>;
  36. reg-io-width = <4>;
  37. };
  38. };
  39. mb_intc: interrupt-controller@e0012000 {
  40. #interrupt-cells = <1>;
  41. compatible = "snps,dw-apb-ictl";
  42. reg = < 0xe0012000 0x200 >;
  43. interrupt-controller;
  44. interrupt-parent = <&core_intc>;
  45. interrupts = < 18 >;
  46. };
  47. memory {
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. ranges = <0x00000000 0x80000000 0x40000000>;
  51. device_type = "memory";
  52. reg = <0x80000000 0x20000000>; /* 512MiB */
  53. };
  54. };