hsdk.dts 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
  4. */
  5. /*
  6. * Device Tree for ARC HS Development Kit
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/reset/snps,hsdk-reset.h>
  11. / {
  12. model = "snps,hsdk";
  13. compatible = "snps,hsdk";
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. chosen {
  17. bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
  18. };
  19. aliases {
  20. ethernet = &gmac;
  21. };
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. cpu@0 {
  26. device_type = "cpu";
  27. compatible = "snps,archs38";
  28. reg = <0>;
  29. clocks = <&core_clk>;
  30. };
  31. cpu@1 {
  32. device_type = "cpu";
  33. compatible = "snps,archs38";
  34. reg = <1>;
  35. clocks = <&core_clk>;
  36. };
  37. cpu@2 {
  38. device_type = "cpu";
  39. compatible = "snps,archs38";
  40. reg = <2>;
  41. clocks = <&core_clk>;
  42. };
  43. cpu@3 {
  44. device_type = "cpu";
  45. compatible = "snps,archs38";
  46. reg = <3>;
  47. clocks = <&core_clk>;
  48. };
  49. };
  50. input_clk: input-clk {
  51. #clock-cells = <0>;
  52. compatible = "fixed-clock";
  53. clock-frequency = <33333333>;
  54. };
  55. reg_5v0: regulator-5v0 {
  56. compatible = "regulator-fixed";
  57. regulator-name = "5v0-supply";
  58. regulator-min-microvolt = <5000000>;
  59. regulator-max-microvolt = <5000000>;
  60. };
  61. cpu_intc: cpu-interrupt-controller {
  62. compatible = "snps,archs-intc";
  63. interrupt-controller;
  64. #interrupt-cells = <1>;
  65. };
  66. idu_intc: idu-interrupt-controller {
  67. compatible = "snps,archs-idu-intc";
  68. interrupt-controller;
  69. #interrupt-cells = <1>;
  70. interrupt-parent = <&cpu_intc>;
  71. };
  72. arcpct: pct {
  73. compatible = "snps,archs-pct";
  74. interrupt-parent = <&cpu_intc>;
  75. interrupts = <20>;
  76. };
  77. /* TIMER0 with interrupt for clockevent */
  78. timer {
  79. compatible = "snps,arc-timer";
  80. interrupts = <16>;
  81. interrupt-parent = <&cpu_intc>;
  82. clocks = <&core_clk>;
  83. };
  84. /* 64-bit Global Free Running Counter */
  85. gfrc {
  86. compatible = "snps,archs-timer-gfrc";
  87. clocks = <&core_clk>;
  88. };
  89. soc {
  90. compatible = "simple-bus";
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. interrupt-parent = <&idu_intc>;
  94. ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
  95. cgu_rst: reset-controller@8a0 {
  96. compatible = "snps,hsdk-reset";
  97. #reset-cells = <1>;
  98. reg = <0x8a0 0x4>, <0xff0 0x4>;
  99. };
  100. core_clk: core-clk@0 {
  101. compatible = "snps,hsdk-core-pll-clock";
  102. reg = <0x00 0x10>, <0x14b8 0x4>;
  103. #clock-cells = <0>;
  104. clocks = <&input_clk>;
  105. /*
  106. * Set initial core pll output frequency to 1GHz.
  107. * It will be applied at the core pll driver probing
  108. * on early boot.
  109. */
  110. assigned-clocks = <&core_clk>;
  111. assigned-clock-rates = <1000000000>;
  112. };
  113. serial: serial@5000 {
  114. compatible = "snps,dw-apb-uart";
  115. reg = <0x5000 0x100>;
  116. clock-frequency = <33330000>;
  117. interrupts = <6>;
  118. baud = <115200>;
  119. reg-shift = <2>;
  120. reg-io-width = <4>;
  121. };
  122. gmacclk: gmacclk {
  123. compatible = "fixed-clock";
  124. clock-frequency = <400000000>;
  125. #clock-cells = <0>;
  126. };
  127. mmcclk_ciu: mmcclk-ciu {
  128. compatible = "fixed-clock";
  129. /*
  130. * DW sdio controller has external ciu clock divider
  131. * controlled via register in SDIO IP. Due to its
  132. * unexpected default value (it should divide by 1
  133. * but it divides by 8) SDIO IP uses wrong clock and
  134. * works unstable (see STAR 9001204800)
  135. * We switched to the minimum possible value of the
  136. * divisor (div-by-2) in HSDK platform code.
  137. * So add temporary fix and change clock frequency
  138. * to 50000000 Hz until we fix dw sdio driver itself.
  139. */
  140. clock-frequency = <50000000>;
  141. #clock-cells = <0>;
  142. };
  143. mmcclk_biu: mmcclk-biu {
  144. compatible = "fixed-clock";
  145. clock-frequency = <400000000>;
  146. #clock-cells = <0>;
  147. };
  148. gpu_core_clk: gpu-core-clk {
  149. compatible = "fixed-clock";
  150. clock-frequency = <400000000>;
  151. #clock-cells = <0>;
  152. };
  153. gpu_dma_clk: gpu-dma-clk {
  154. compatible = "fixed-clock";
  155. clock-frequency = <400000000>;
  156. #clock-cells = <0>;
  157. };
  158. gpu_cfg_clk: gpu-cfg-clk {
  159. compatible = "fixed-clock";
  160. clock-frequency = <200000000>;
  161. #clock-cells = <0>;
  162. };
  163. dmac_core_clk: dmac-core-clk {
  164. compatible = "fixed-clock";
  165. clock-frequency = <400000000>;
  166. #clock-cells = <0>;
  167. };
  168. dmac_cfg_clk: dmac-gpu-cfg-clk {
  169. compatible = "fixed-clock";
  170. clock-frequency = <200000000>;
  171. #clock-cells = <0>;
  172. };
  173. gmac: ethernet@8000 {
  174. #interrupt-cells = <1>;
  175. compatible = "snps,dwmac";
  176. reg = <0x8000 0x2000>;
  177. interrupts = <10>;
  178. interrupt-names = "macirq";
  179. phy-mode = "rgmii-id";
  180. snps,pbl = <32>;
  181. snps,multicast-filter-bins = <256>;
  182. clocks = <&gmacclk>;
  183. clock-names = "stmmaceth";
  184. phy-handle = <&phy0>;
  185. resets = <&cgu_rst HSDK_ETH_RESET>;
  186. reset-names = "stmmaceth";
  187. mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
  188. dma-coherent;
  189. tx-fifo-depth = <4096>;
  190. rx-fifo-depth = <4096>;
  191. mdio {
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. compatible = "snps,dwmac-mdio";
  195. phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
  196. reg = <0>;
  197. };
  198. };
  199. };
  200. usb@60000 {
  201. compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
  202. reg = <0x60000 0x100>;
  203. interrupts = <15>;
  204. resets = <&cgu_rst HSDK_USB_RESET>;
  205. dma-coherent;
  206. };
  207. usb@40000 {
  208. compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
  209. reg = <0x40000 0x100>;
  210. interrupts = <15>;
  211. resets = <&cgu_rst HSDK_USB_RESET>;
  212. dma-coherent;
  213. };
  214. mmc@a000 {
  215. compatible = "altr,socfpga-dw-mshc";
  216. reg = <0xa000 0x400>;
  217. num-slots = <1>;
  218. fifo-depth = <16>;
  219. card-detect-delay = <200>;
  220. clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
  221. clock-names = "biu", "ciu";
  222. interrupts = <12>;
  223. bus-width = <4>;
  224. dma-coherent;
  225. };
  226. spi0: spi@20000 {
  227. compatible = "snps,dw-apb-ssi";
  228. reg = <0x20000 0x100>;
  229. #address-cells = <1>;
  230. #size-cells = <0>;
  231. interrupts = <16>;
  232. num-cs = <2>;
  233. reg-io-width = <4>;
  234. clocks = <&input_clk>;
  235. cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
  236. <&creg_gpio 1 GPIO_ACTIVE_LOW>;
  237. flash@0 {
  238. compatible = "sst26wf016b", "jedec,spi-nor";
  239. reg = <0>;
  240. #address-cells = <1>;
  241. #size-cells = <1>;
  242. spi-max-frequency = <4000000>;
  243. };
  244. adc@1 {
  245. compatible = "ti,adc108s102";
  246. reg = <1>;
  247. vref-supply = <&reg_5v0>;
  248. spi-max-frequency = <1000000>;
  249. };
  250. };
  251. creg_gpio: gpio@14b0 {
  252. compatible = "snps,creg-gpio-hsdk";
  253. reg = <0x14b0 0x4>;
  254. gpio-controller;
  255. #gpio-cells = <2>;
  256. ngpios = <2>;
  257. };
  258. gpio: gpio@3000 {
  259. compatible = "snps,dw-apb-gpio";
  260. reg = <0x3000 0x20>;
  261. #address-cells = <1>;
  262. #size-cells = <0>;
  263. gpio_port_a: gpio-controller@0 {
  264. compatible = "snps,dw-apb-gpio-port";
  265. gpio-controller;
  266. #gpio-cells = <2>;
  267. snps,nr-gpios = <24>;
  268. reg = <0>;
  269. };
  270. };
  271. gpu_3d: gpu@90000 {
  272. compatible = "vivante,gc";
  273. reg = <0x90000 0x4000>;
  274. clocks = <&gpu_dma_clk>,
  275. <&gpu_cfg_clk>,
  276. <&gpu_core_clk>,
  277. <&gpu_core_clk>;
  278. clock-names = "bus", "reg", "core", "shader";
  279. interrupts = <28>;
  280. };
  281. dmac: dmac@80000 {
  282. compatible = "snps,axi-dma-1.01a";
  283. reg = <0x80000 0x400>;
  284. interrupts = <27>;
  285. clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
  286. clock-names = "core-clk", "cfgr-clk";
  287. dma-channels = <4>;
  288. snps,dma-masters = <2>;
  289. snps,data-width = <3>;
  290. snps,block-size = <4096 4096 4096 4096>;
  291. snps,priority = <0 1 2 3>;
  292. snps,axi-max-burst-len = <16>;
  293. };
  294. };
  295. memory@80000000 {
  296. #address-cells = <2>;
  297. #size-cells = <2>;
  298. device_type = "memory";
  299. reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
  300. /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
  301. };
  302. };