xics.rst 3.2 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. =========================
  3. XICS interrupt controller
  4. =========================
  5. Device type supported: KVM_DEV_TYPE_XICS
  6. Groups:
  7. 1. KVM_DEV_XICS_GRP_SOURCES
  8. Attributes:
  9. One per interrupt source, indexed by the source number.
  10. 2. KVM_DEV_XICS_GRP_CTRL
  11. Attributes:
  12. 2.1 KVM_DEV_XICS_NR_SERVERS (write only)
  13. The kvm_device_attr.addr points to a __u32 value which is the number of
  14. interrupt server numbers (ie, highest possible vcpu id plus one).
  15. Errors:
  16. ======= ==========================================
  17. -EINVAL Value greater than KVM_MAX_VCPU_IDS.
  18. -EFAULT Invalid user pointer for attr->addr.
  19. -EBUSY A vcpu is already connected to the device.
  20. ======= ==========================================
  21. This device emulates the XICS (eXternal Interrupt Controller
  22. Specification) defined in PAPR. The XICS has a set of interrupt
  23. sources, each identified by a 20-bit source number, and a set of
  24. Interrupt Control Presentation (ICP) entities, also called "servers",
  25. each associated with a virtual CPU.
  26. The ICP entities are created by enabling the KVM_CAP_IRQ_ARCH
  27. capability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and
  28. the interrupt server number (i.e. the vcpu number from the XICS's
  29. point of view) in args[1] of the kvm_enable_cap struct. Each ICP has
  30. 64 bits of state which can be read and written using the
  31. KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit
  32. state word has the following bitfields, starting at the
  33. least-significant end of the word:
  34. * Unused, 16 bits
  35. * Pending interrupt priority, 8 bits
  36. Zero is the highest priority, 255 means no interrupt is pending.
  37. * Pending IPI (inter-processor interrupt) priority, 8 bits
  38. Zero is the highest priority, 255 means no IPI is pending.
  39. * Pending interrupt source number, 24 bits
  40. Zero means no interrupt pending, 2 means an IPI is pending
  41. * Current processor priority, 8 bits
  42. Zero is the highest priority, meaning no interrupts can be
  43. delivered, and 255 is the lowest priority.
  44. Each source has 64 bits of state that can be read and written using
  45. the KVM_GET_DEVICE_ATTR and KVM_SET_DEVICE_ATTR ioctls, specifying the
  46. KVM_DEV_XICS_GRP_SOURCES attribute group, with the attribute number being
  47. the interrupt source number. The 64 bit state word has the following
  48. bitfields, starting from the least-significant end of the word:
  49. * Destination (server number), 32 bits
  50. This specifies where the interrupt should be sent, and is the
  51. interrupt server number specified for the destination vcpu.
  52. * Priority, 8 bits
  53. This is the priority specified for this interrupt source, where 0 is
  54. the highest priority and 255 is the lowest. An interrupt with a
  55. priority of 255 will never be delivered.
  56. * Level sensitive flag, 1 bit
  57. This bit is 1 for a level-sensitive interrupt source, or 0 for
  58. edge-sensitive (or MSI).
  59. * Masked flag, 1 bit
  60. This bit is set to 1 if the interrupt is masked (cannot be delivered
  61. regardless of its priority), for example by the ibm,int-off RTAS
  62. call, or 0 if it is not masked.
  63. * Pending flag, 1 bit
  64. This bit is 1 if the source has a pending interrupt, otherwise 0.
  65. Only one XICS instance may be created per VM.