spi-lm70llp.rst 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384
  1. ==============================================
  2. spi_lm70llp : LM70-LLP parport-to-SPI adapter
  3. ==============================================
  4. Supported board/chip:
  5. * National Semiconductor LM70 LLP evaluation board
  6. Datasheet: http://www.national.com/pf/LM/LM70.html
  7. Author:
  8. Kaiwan N Billimoria <[email protected]>
  9. Description
  10. -----------
  11. This driver provides glue code connecting a National Semiconductor LM70 LLP
  12. temperature sensor evaluation board to the kernel's SPI core subsystem.
  13. This is a SPI master controller driver. It can be used in conjunction with
  14. (layered under) the LM70 logical driver (a "SPI protocol driver").
  15. In effect, this driver turns the parallel port interface on the eval board
  16. into a SPI bus with a single device, which will be driven by the generic
  17. LM70 driver (drivers/hwmon/lm70.c).
  18. Hardware Interfacing
  19. --------------------
  20. The schematic for this particular board (the LM70EVAL-LLP) is
  21. available (on page 4) here:
  22. http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
  23. The hardware interfacing on the LM70 LLP eval board is as follows:
  24. ======== == ========= ==========
  25. Parallel LM70 LLP
  26. Port . Direction JP2 Header
  27. ======== == ========= ==========
  28. D0 2 - -
  29. D1 3 --> V+ 5
  30. D2 4 --> V+ 5
  31. D3 5 --> V+ 5
  32. D4 6 --> V+ 5
  33. D5 7 --> nCS 8
  34. D6 8 --> SCLK 3
  35. D7 9 --> SI/O 5
  36. GND 25 - GND 7
  37. Select 13 <-- SI/O 1
  38. ======== == ========= ==========
  39. Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
  40. is connected to both pin D7 (as Master Out) and Select (as Master In)
  41. using an arrangement that lets either the parport or the LM70 pull the
  42. pin low. This can't be shared with true SPI devices, but other 3-wire
  43. devices might share the same SI/SO pin.
  44. The bitbanger routine in this driver (lm70_txrx) is called back from
  45. the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
  46. spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.
  47. The lm70 driver then inteprets the resulting digital temperature value
  48. and exports it through sysfs.
  49. A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
  50. shows that the SI/O line from the LM70 chip is connected to the base of a
  51. transistor Q1 (and also a pullup, and a zener diode to D7); while the
  52. collector is tied to VCC.
  53. Interpreting this circuit, when the LM70 SI/O line is High (or tristate
  54. and not grounded by the host via D7), the transistor conducts and switches
  55. the collector to zero, which is reflected on pin 13 of the DB25 parport
  56. connector. When SI/O is Low (driven by the LM70 or the host) on the other
  57. hand, the transistor is cut off and the voltage tied to it's collector is
  58. reflected on pin 13 as a High level.
  59. So: the getmiso inline routine in this driver takes this fact into account,
  60. inverting the value read at pin 13.
  61. Thanks to
  62. ---------
  63. - David Brownell for mentoring the SPI-side driver development.
  64. - Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
  65. - Nadir Billimoria for help interpreting the circuit schematic.