max16601.rst 3.4 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. Kernel driver max16601
  3. ======================
  4. Supported chips:
  5. * Maxim MAX16508
  6. Prefix: 'max16508'
  7. Addresses scanned: -
  8. Datasheet: Not published
  9. * Maxim MAX16601
  10. Prefix: 'max16601'
  11. Addresses scanned: -
  12. Datasheet: Not published
  13. * Maxim MAX16602
  14. Prefix: 'max16602'
  15. Addresses scanned: -
  16. Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX16602.pdf
  17. Author: Guenter Roeck <[email protected]>
  18. Description
  19. -----------
  20. This driver supports the MAX16508 VR13 Dual-Output Voltage Regulator
  21. as well as the MAX16601 VR13.HC Dual-Output Voltage Regulator chipsets.
  22. The driver is a client driver to the core PMBus driver.
  23. Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers.
  24. Usage Notes
  25. -----------
  26. This driver does not auto-detect devices. You will have to instantiate the
  27. devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for
  28. details.
  29. Platform data support
  30. ---------------------
  31. The driver supports standard PMBus driver platform data.
  32. Sysfs entries
  33. -------------
  34. The following attributes are supported.
  35. =============================== ===============================================
  36. in1_label "vin1"
  37. in1_input VCORE input voltage.
  38. in1_alarm Input voltage alarm.
  39. in2_label "vout1"
  40. in2_input VCORE output voltage.
  41. in2_alarm Output voltage alarm.
  42. curr1_label "iin1"
  43. curr1_input VCORE input current, derived from duty cycle
  44. and output current.
  45. curr1_max Maximum input current.
  46. curr1_max_alarm Current high alarm.
  47. curr[P+2]_label "iin1.P"
  48. curr[P+2]_input VCORE phase P input current.
  49. curr[N+2]_label "iin2"
  50. curr[N+2]_input VCORE input current, derived from sensor
  51. element.
  52. 'N' is the number of enabled/populated phases.
  53. curr[N+3]_label "iin3"
  54. curr[N+3]_input VSA input current.
  55. curr[N+4]_label "iout1"
  56. curr[N+4]_input VCORE output current.
  57. curr[N+4]_crit Critical output current.
  58. curr[N+4]_crit_alarm Output current critical alarm.
  59. curr[N+4]_max Maximum output current.
  60. curr[N+4]_max_alarm Output current high alarm.
  61. curr[N+P+5]_label "iout1.P"
  62. curr[N+P+5]_input VCORE phase P output current.
  63. curr[2*N+5]_label "iout3"
  64. curr[2*N+5]_input VSA output current.
  65. curr[2*N+5]_highest Historical maximum VSA output current.
  66. curr[2*N+5]_reset_history Write any value to reset curr21_highest.
  67. curr[2*N+5]_crit Critical output current.
  68. curr[2*N+5]_crit_alarm Output current critical alarm.
  69. curr[2*N+5]_max Maximum output current.
  70. curr[2*N+5]_max_alarm Output current high alarm.
  71. power1_label "pin1"
  72. power1_input Input power, derived from duty cycle and output
  73. current.
  74. power1_alarm Input power alarm.
  75. power2_label "pin2"
  76. power2_input Input power, derived from input current sensor.
  77. power3_label "pout"
  78. power3_input Output power.
  79. temp1_input VCORE temperature.
  80. temp1_crit Critical high temperature.
  81. temp1_crit_alarm Chip temperature critical high alarm.
  82. temp1_max Maximum temperature.
  83. temp1_max_alarm Chip temperature high alarm.
  84. temp2_input TSENSE_0 temperature
  85. temp3_input TSENSE_1 temperature
  86. temp4_input TSENSE_2 temperature
  87. temp5_input TSENSE_3 temperature
  88. temp6_input VSA temperature.
  89. temp6_crit Critical high temperature.
  90. temp6_crit_alarm Chip temperature critical high alarm.
  91. temp6_max Maximum temperature.
  92. temp6_max_alarm Chip temperature high alarm.
  93. =============================== ===============================================