i915.rst 23 KB

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  1. ===========================
  2. drm/i915 Intel GFX Driver
  3. ===========================
  4. The drm/i915 driver supports all (with the exception of some very early
  5. models) integrated GFX chipsets with both Intel display and rendering
  6. blocks. This excludes a set of SoC platforms with an SGX rendering unit,
  7. those have basic support through the gma500 drm driver.
  8. Core Driver Infrastructure
  9. ==========================
  10. This section covers core driver infrastructure used by both the display
  11. and the GEM parts of the driver.
  12. Runtime Power Management
  13. ------------------------
  14. .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
  15. :doc: runtime pm
  16. .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
  17. :internal:
  18. .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
  19. :internal:
  20. Interrupt Handling
  21. ------------------
  22. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  23. :doc: interrupt handling
  24. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  25. :functions: intel_irq_init intel_irq_init_hw intel_hpd_init
  26. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  27. :functions: intel_runtime_pm_disable_interrupts
  28. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  29. :functions: intel_runtime_pm_enable_interrupts
  30. Intel GVT-g Guest Support(vGPU)
  31. -------------------------------
  32. .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
  33. :doc: Intel GVT-g guest support
  34. .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
  35. :internal:
  36. Intel GVT-g Host Support(vGPU device model)
  37. -------------------------------------------
  38. .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
  39. :doc: Intel GVT-g host support
  40. .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
  41. :internal:
  42. Workarounds
  43. -----------
  44. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c
  45. :doc: Hardware workarounds
  46. Display Hardware Handling
  47. =========================
  48. This section covers everything related to the display hardware including
  49. the mode setting infrastructure, plane, sprite and cursor handling and
  50. display, output probing and related topics.
  51. Mode Setting Infrastructure
  52. ---------------------------
  53. The i915 driver is thus far the only DRM driver which doesn't use the
  54. common DRM helper code to implement mode setting sequences. Thus it has
  55. its own tailor-made infrastructure for executing a display configuration
  56. change.
  57. Frontbuffer Tracking
  58. --------------------
  59. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
  60. :doc: frontbuffer tracking
  61. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
  62. :internal:
  63. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
  64. :internal:
  65. Display FIFO Underrun Reporting
  66. -------------------------------
  67. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
  68. :doc: fifo underrun handling
  69. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
  70. :internal:
  71. Plane Configuration
  72. -------------------
  73. This section covers plane configuration and composition with the primary
  74. plane, sprites, cursors and overlays. This includes the infrastructure
  75. to do atomic vsync'ed updates of all this state and also tightly coupled
  76. topics like watermark setup and computation, framebuffer compression and
  77. panel self refresh.
  78. Atomic Plane Helpers
  79. --------------------
  80. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
  81. :doc: atomic plane helpers
  82. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
  83. :internal:
  84. Asynchronous Page Flip
  85. ----------------------
  86. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
  87. :doc: asynchronous flip implementation
  88. Output Probing
  89. --------------
  90. This section covers output probing and related infrastructure like the
  91. hotplug interrupt storm detection and mitigation code. Note that the
  92. i915 driver still uses most of the common DRM helper code for output
  93. probing, so those sections fully apply.
  94. Hotplug
  95. -------
  96. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
  97. :doc: Hotplug
  98. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
  99. :internal:
  100. High Definition Audio
  101. ---------------------
  102. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
  103. :doc: High Definition Audio over HDMI and Display Port
  104. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
  105. :internal:
  106. .. kernel-doc:: include/drm/i915_component.h
  107. :internal:
  108. Intel HDMI LPE Audio Support
  109. ----------------------------
  110. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
  111. :doc: LPE Audio integration for HDMI or DP playback
  112. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
  113. :internal:
  114. Panel Self Refresh PSR (PSR/SRD)
  115. --------------------------------
  116. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
  117. :doc: Panel Self Refresh (PSR/SRD)
  118. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
  119. :internal:
  120. Frame Buffer Compression (FBC)
  121. ------------------------------
  122. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
  123. :doc: Frame Buffer Compression (FBC)
  124. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
  125. :internal:
  126. Display Refresh Rate Switching (DRRS)
  127. -------------------------------------
  128. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
  129. :doc: Display Refresh Rate Switching (DRRS)
  130. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
  131. :internal:
  132. DPIO
  133. ----
  134. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
  135. :doc: DPIO
  136. DMC Firmware Support
  137. --------------------
  138. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
  139. :doc: DMC Firmware Support
  140. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
  141. :internal:
  142. Video BIOS Table (VBT)
  143. ----------------------
  144. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
  145. :doc: Video BIOS Table (VBT)
  146. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
  147. :internal:
  148. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h
  149. :internal:
  150. Display clocks
  151. --------------
  152. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
  153. :doc: CDCLK / RAWCLK
  154. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
  155. :internal:
  156. Display PLLs
  157. ------------
  158. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
  159. :doc: Display PLLs
  160. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
  161. :internal:
  162. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
  163. :internal:
  164. Display State Buffer
  165. --------------------
  166. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
  167. :doc: DSB
  168. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
  169. :internal:
  170. GT Programming
  171. ==============
  172. Multicast/Replicated (MCR) Registers
  173. ------------------------------------
  174. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
  175. :doc: GT Multicast/Replicated (MCR) Register Support
  176. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
  177. :internal:
  178. Memory Management and Command Submission
  179. ========================================
  180. This sections covers all things related to the GEM implementation in the
  181. i915 driver.
  182. Intel GPU Basics
  183. ----------------
  184. An Intel GPU has multiple engines. There are several engine types.
  185. - RCS engine is for rendering 3D and performing compute, this is named
  186. `I915_EXEC_RENDER` in user space.
  187. - BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
  188. space.
  189. - VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
  190. in user space
  191. - VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
  192. space.
  193. - The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
  194. instead it is to be used by user space to specify a default rendering
  195. engine (for 3D) that may or may not be the same as RCS.
  196. The Intel GPU family is a family of integrated GPU's using Unified
  197. Memory Access. For having the GPU "do work", user space will feed the
  198. GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
  199. or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
  200. instruct the GPU to perform work (for example rendering) and that work
  201. needs memory from which to read and memory to which to write. All memory
  202. is encapsulated within GEM buffer objects (usually created with the ioctl
  203. `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
  204. to create will also list all GEM buffer objects that the batchbuffer reads
  205. and/or writes. For implementation details of memory management see
  206. `GEM BO Management Implementation Details`_.
  207. The i915 driver allows user space to create a context via the ioctl
  208. `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
  209. integer. Such a context should be viewed by user-space as -loosely-
  210. analogous to the idea of a CPU process of an operating system. The i915
  211. driver guarantees that commands issued to a fixed context are to be
  212. executed so that writes of a previously issued command are seen by
  213. reads of following commands. Actions issued between different contexts
  214. (even if from the same file descriptor) are NOT given that guarantee
  215. and the only way to synchronize across contexts (even from the same
  216. file descriptor) is through the use of fences. At least as far back as
  217. Gen4, also have that a context carries with it a GPU HW context;
  218. the HW context is essentially (most of atleast) the state of a GPU.
  219. In addition to the ordering guarantees, the kernel will restore GPU
  220. state via HW context when commands are issued to a context, this saves
  221. user space the need to restore (most of atleast) the GPU state at the
  222. start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
  223. work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
  224. to identify what context to use with the command.
  225. The GPU has its own memory management and address space. The kernel
  226. driver maintains the memory translation table for the GPU. For older
  227. GPUs (i.e. those before Gen8), there is a single global such translation
  228. table, a global Graphics Translation Table (GTT). For newer generation
  229. GPUs each context has its own translation table, called Per-Process
  230. Graphics Translation Table (PPGTT). Of important note, is that although
  231. PPGTT is named per-process it is actually per context. When user space
  232. submits a batchbuffer, the kernel walks the list of GEM buffer objects
  233. used by the batchbuffer and guarantees that not only is the memory of
  234. each such GEM buffer object resident but it is also present in the
  235. (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
  236. then it is given an address. Two consequences of this are: the kernel
  237. needs to edit the batchbuffer submitted to write the correct value of
  238. the GPU address when a GEM BO is assigned a GPU address and the kernel
  239. might evict a different GEM BO from the (PP)GTT to make address room
  240. for another GEM BO. Consequently, the ioctls submitting a batchbuffer
  241. for execution also include a list of all locations within buffers that
  242. refer to GPU-addresses so that the kernel can edit the buffer correctly.
  243. This process is dubbed relocation.
  244. Locking Guidelines
  245. ------------------
  246. .. note::
  247. This is a description of how the locking should be after
  248. refactoring is done. Does not necessarily reflect what the locking
  249. looks like while WIP.
  250. #. All locking rules and interface contracts with cross-driver interfaces
  251. (dma-buf, dma_fence) need to be followed.
  252. #. No struct_mutex anywhere in the code
  253. #. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx
  254. is to be hoisted at highest level and passed down within i915_gem_ctx
  255. in the call chain
  256. #. While holding lru/memory manager (buddy, drm_mm, whatever) locks
  257. system memory allocations are not allowed
  258. * Enforce this by priming lockdep (with fs_reclaim). If we
  259. allocate memory while holding these looks we get a rehash
  260. of the shrinker vs. struct_mutex saga, and that would be
  261. real bad.
  262. #. Do not nest different lru/memory manager locks within each other.
  263. Take them in turn to update memory allocations, relying on the object’s
  264. dma_resv ww_mutex to serialize against other operations.
  265. #. The suggestion for lru/memory managers locks is that they are small
  266. enough to be spinlocks.
  267. #. All features need to come with exhaustive kernel selftests and/or
  268. IGT tests when appropriate
  269. #. All LMEM uAPI paths need to be fully restartable (_interruptible()
  270. for all locks/waits/sleeps)
  271. * Error handling validation through signal injection.
  272. Still the best strategy we have for validating GEM uAPI
  273. corner cases.
  274. Must be excessively used in the IGT, and we need to check
  275. that we really have full path coverage of all error cases.
  276. * -EDEADLK handling with ww_mutex
  277. GEM BO Management Implementation Details
  278. ----------------------------------------
  279. .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
  280. :doc: Virtual Memory Address
  281. Buffer Object Eviction
  282. ----------------------
  283. This section documents the interface functions for evicting buffer
  284. objects to make space available in the virtual gpu address spaces. Note
  285. that this is mostly orthogonal to shrinking buffer objects caches, which
  286. has the goal to make main memory (shared with the gpu through the
  287. unified memory architecture) available.
  288. .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
  289. :internal:
  290. Buffer Object Memory Shrinking
  291. ------------------------------
  292. This section documents the interface function for shrinking memory usage
  293. of buffer object caches. Shrinking is used to make main memory
  294. available. Note that this is mostly orthogonal to evicting buffer
  295. objects, which has the goal to make space in gpu virtual address spaces.
  296. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
  297. :internal:
  298. Batchbuffer Parsing
  299. -------------------
  300. .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
  301. :doc: batch buffer command parser
  302. .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
  303. :internal:
  304. User Batchbuffer Execution
  305. --------------------------
  306. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h
  307. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
  308. :doc: User command execution
  309. Scheduling
  310. ----------
  311. .. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h
  312. :functions: i915_sched_engine
  313. Logical Rings, Logical Ring Contexts and Execlists
  314. --------------------------------------------------
  315. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c
  316. :doc: Logical Rings, Logical Ring Contexts and Execlists
  317. Global GTT views
  318. ----------------
  319. .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
  320. :doc: Global GTT views
  321. .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
  322. :internal:
  323. GTT Fences and Swizzling
  324. ------------------------
  325. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
  326. :internal:
  327. Global GTT Fence Handling
  328. ~~~~~~~~~~~~~~~~~~~~~~~~~
  329. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
  330. :doc: fence register handling
  331. Hardware Tiling and Swizzling Details
  332. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  333. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
  334. :doc: tiling swizzling details
  335. Object Tiling IOCTLs
  336. --------------------
  337. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
  338. :internal:
  339. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
  340. :doc: buffer object tiling
  341. Protected Objects
  342. -----------------
  343. .. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c
  344. :doc: PXP
  345. .. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h
  346. Microcontrollers
  347. ================
  348. Starting from gen9, three microcontrollers are available on the HW: the
  349. graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the
  350. display microcontroller (DMC). The driver is responsible for loading the
  351. firmwares on the microcontrollers; the GuC and HuC firmwares are transferred
  352. to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
  353. WOPCM
  354. -----
  355. WOPCM Layout
  356. ~~~~~~~~~~~~
  357. .. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
  358. :doc: WOPCM Layout
  359. GuC
  360. ---
  361. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
  362. :doc: GuC
  363. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h
  364. GuC Firmware Layout
  365. ~~~~~~~~~~~~~~~~~~~
  366. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
  367. :doc: Firmware Layout
  368. GuC Memory Management
  369. ~~~~~~~~~~~~~~~~~~~~~
  370. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
  371. :doc: GuC Memory Management
  372. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
  373. :functions: intel_guc_allocate_vma
  374. GuC-specific firmware loader
  375. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  376. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
  377. :internal:
  378. GuC-based command submission
  379. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  380. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
  381. :doc: GuC-based command submission
  382. GuC ABI
  383. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  384. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
  385. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
  386. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
  387. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
  388. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
  389. HuC
  390. ---
  391. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
  392. :doc: HuC
  393. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
  394. :functions: intel_huc_auth
  395. HuC Memory Management
  396. ~~~~~~~~~~~~~~~~~~~~~
  397. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
  398. :doc: HuC Memory Management
  399. HuC Firmware Layout
  400. ~~~~~~~~~~~~~~~~~~~
  401. The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
  402. DMC
  403. ---
  404. See `DMC Firmware Support`_
  405. Tracing
  406. =======
  407. This sections covers all things related to the tracepoints implemented
  408. in the i915 driver.
  409. i915_ppgtt_create and i915_ppgtt_release
  410. ----------------------------------------
  411. .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
  412. :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
  413. i915_context_create and i915_context_free
  414. -----------------------------------------
  415. .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
  416. :doc: i915_context_create and i915_context_free tracepoints
  417. Perf
  418. ====
  419. Overview
  420. --------
  421. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  422. :doc: i915 Perf Overview
  423. Comparison with Core Perf
  424. -------------------------
  425. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  426. :doc: i915 Perf History and Comparison with Core Perf
  427. i915 Driver Entry Points
  428. ------------------------
  429. This section covers the entrypoints exported outside of i915_perf.c to
  430. integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
  431. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  432. :functions: i915_perf_init
  433. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  434. :functions: i915_perf_fini
  435. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  436. :functions: i915_perf_register
  437. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  438. :functions: i915_perf_unregister
  439. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  440. :functions: i915_perf_open_ioctl
  441. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  442. :functions: i915_perf_release
  443. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  444. :functions: i915_perf_add_config_ioctl
  445. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  446. :functions: i915_perf_remove_config_ioctl
  447. i915 Perf Stream
  448. ----------------
  449. This section covers the stream-semantics-agnostic structures and functions
  450. for representing an i915 perf stream FD and associated file operations.
  451. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
  452. :functions: i915_perf_stream
  453. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
  454. :functions: i915_perf_stream_ops
  455. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  456. :functions: read_properties_unlocked
  457. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  458. :functions: i915_perf_open_ioctl_locked
  459. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  460. :functions: i915_perf_destroy_locked
  461. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  462. :functions: i915_perf_read
  463. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  464. :functions: i915_perf_ioctl
  465. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  466. :functions: i915_perf_enable_locked
  467. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  468. :functions: i915_perf_disable_locked
  469. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  470. :functions: i915_perf_poll
  471. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  472. :functions: i915_perf_poll_locked
  473. i915 Perf Observation Architecture Stream
  474. -----------------------------------------
  475. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
  476. :functions: i915_oa_ops
  477. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  478. :functions: i915_oa_stream_init
  479. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  480. :functions: i915_oa_read
  481. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  482. :functions: i915_oa_stream_enable
  483. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  484. :functions: i915_oa_stream_disable
  485. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  486. :functions: i915_oa_wait_unlocked
  487. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  488. :functions: i915_oa_poll_wait
  489. Other i915 Perf Internals
  490. -------------------------
  491. This section simply includes all other currently documented i915 perf internals,
  492. in no particular order, but may include some more minor utilities or platform
  493. specific details than found in the more high-level sections.
  494. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  495. :internal:
  496. :no-identifiers:
  497. i915_perf_init
  498. i915_perf_fini
  499. i915_perf_register
  500. i915_perf_unregister
  501. i915_perf_open_ioctl
  502. i915_perf_release
  503. i915_perf_add_config_ioctl
  504. i915_perf_remove_config_ioctl
  505. read_properties_unlocked
  506. i915_perf_open_ioctl_locked
  507. i915_perf_destroy_locked
  508. i915_perf_read i915_perf_ioctl
  509. i915_perf_enable_locked
  510. i915_perf_disable_locked
  511. i915_perf_poll i915_perf_poll_locked
  512. i915_oa_stream_init i915_oa_read
  513. i915_oa_stream_enable
  514. i915_oa_stream_disable
  515. i915_oa_wait_unlocked
  516. i915_oa_poll_wait
  517. Style
  518. =====
  519. The drm/i915 driver codebase has some style rules in addition to (and, in some
  520. cases, deviating from) the kernel coding style.
  521. Register macro definition style
  522. -------------------------------
  523. The style guide for ``i915_reg.h``.
  524. .. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
  525. :doc: The i915 register macro definition style guide
  526. .. _i915-usage-stats:
  527. i915 DRM client usage stats implementation
  528. ==========================================
  529. The drm/i915 driver implements the DRM client usage stats specification as
  530. documented in :ref:`drm-client-usage-stats`.
  531. Example of the output showing the implemented key value pairs and entirety of
  532. the currently possible format options:
  533. ::
  534. pos: 0
  535. flags: 0100002
  536. mnt_id: 21
  537. drm-driver: i915
  538. drm-pdev: 0000:00:02.0
  539. drm-client-id: 7
  540. drm-engine-render: 9288864723 ns
  541. drm-engine-copy: 2035071108 ns
  542. drm-engine-video: 0 ns
  543. drm-engine-capacity-video: 2
  544. drm-engine-video-enhance: 0 ns
  545. Possible `drm-engine-` key names are: `render`, `copy`, `video` and
  546. `video-enhance`.