chromeos-acpi-device.rst 8.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363
  1. .. SPDX-License-Identifier: GPL-2.0
  2. =====================
  3. Chrome OS ACPI Device
  4. =====================
  5. Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
  6. The plug and play ID of a Chrome OS ACPI device is GGL0001. GGL is a valid PNP ID of Google.
  7. PNP ID can be used with the ACPI devices according to the guidelines. The following ACPI
  8. objects are supported:
  9. .. flat-table:: Supported ACPI Objects
  10. :widths: 1 2
  11. :header-rows: 1
  12. * - Object
  13. - Description
  14. * - CHSW
  15. - Chrome OS switch positions
  16. * - HWID
  17. - Chrome OS hardware ID
  18. * - FWID
  19. - Chrome OS firmware version
  20. * - FRID
  21. - Chrome OS read-only firmware version
  22. * - BINF
  23. - Chrome OS boot information
  24. * - GPIO
  25. - Chrome OS GPIO assignments
  26. * - VBNV
  27. - Chrome OS NVRAM locations
  28. * - VDTA
  29. - Chrome OS verified boot data
  30. * - FMAP
  31. - Chrome OS flashmap base address
  32. * - MLST
  33. - Chrome OS method list
  34. CHSW (Chrome OS switch positions)
  35. =================================
  36. This control method returns the switch positions for Chrome OS specific hardware switches.
  37. Arguments:
  38. ----------
  39. None
  40. Result code:
  41. ------------
  42. An integer containing the switch positions as bitfields:
  43. .. flat-table::
  44. :widths: 1 2
  45. * - 0x00000002
  46. - Recovery button was pressed when x86 firmware booted.
  47. * - 0x00000004
  48. - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
  49. rewritable; otherwise optional)
  50. * - 0x00000020
  51. - Developer switch was enabled when x86 firmware booted.
  52. * - 0x00000200
  53. - Firmware write protection was disabled when x86 firmware booted. (required if
  54. firmware write protection is controlled through x86 BIOS; otherwise optional)
  55. All other bits are reserved and should be set to 0.
  56. HWID (Chrome OS hardware ID)
  57. ============================
  58. This control method returns the hardware ID for the Chromebook.
  59. Arguments:
  60. ----------
  61. None
  62. Result code:
  63. ------------
  64. A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
  65. EEPROM.
  66. Note that the hardware ID can be up to 256 characters long, including the terminating null.
  67. FWID (Chrome OS firmware version)
  68. =================================
  69. This control method returns the firmware version for the rewritable portion of the main
  70. processor firmware.
  71. Arguments:
  72. ----------
  73. None
  74. Result code:
  75. ------------
  76. A null-terminated ASCII string containing the complete firmware version for the rewritable
  77. portion of the main processor firmware.
  78. FRID (Chrome OS read-only firmware version)
  79. ===========================================
  80. This control method returns the firmware version for the read-only portion of the main
  81. processor firmware.
  82. Arguments:
  83. ----------
  84. None
  85. Result code:
  86. ------------
  87. A null-terminated ASCII string containing the complete firmware version for the read-only
  88. (bootstrap + recovery ) portion of the main processor firmware.
  89. BINF (Chrome OS boot information)
  90. =================================
  91. This control method returns information about the current boot.
  92. Arguments:
  93. ----------
  94. None
  95. Result code:
  96. ------------
  97. .. code-block::
  98. Package {
  99. Reserved1
  100. Reserved2
  101. Active EC Firmware
  102. Active Main Firmware Type
  103. Reserved5
  104. }
  105. .. flat-table::
  106. :widths: 1 1 2
  107. :header-rows: 1
  108. * - Field
  109. - Format
  110. - Description
  111. * - Reserved1
  112. - DWORD
  113. - Set to 256 (0x100). This indicates this field is no longer used.
  114. * - Reserved2
  115. - DWORD
  116. - Set to 256 (0x100). This indicates this field is no longer used.
  117. * - Active EC firmware
  118. - DWORD
  119. - The EC firmware which was used during boot.
  120. - 0 - Read-only (recovery) firmware
  121. - 1 - Rewritable firmware.
  122. Set to 0 if EC firmware is always read-only.
  123. * - Active Main Firmware Type
  124. - DWORD
  125. - The main firmware type which was used during boot.
  126. - 0 - Recovery
  127. - 1 - Normal
  128. - 2 - Developer
  129. - 3 - netboot (factory installation only)
  130. Other values are reserved.
  131. * - Reserved5
  132. - DWORD
  133. - Set to 256 (0x100). This indicates this field is no longer used.
  134. GPIO (Chrome OS GPIO assignments)
  135. =================================
  136. This control method returns information about Chrome OS specific GPIO assignments for
  137. Chrome OS hardware, so the kernel can directly control that hardware.
  138. Arguments:
  139. ----------
  140. None
  141. Result code:
  142. ------------
  143. .. code-block::
  144. Package {
  145. Package {
  146. // First GPIO assignment
  147. Signal Type //DWORD
  148. Attributes //DWORD
  149. Controller Offset //DWORD
  150. Controller Name //ASCIIZ
  151. },
  152. ...
  153. Package {
  154. // Last GPIO assignment
  155. Signal Type //DWORD
  156. Attributes //DWORD
  157. Controller Offset //DWORD
  158. Controller Name //ASCIIZ
  159. }
  160. }
  161. Where ASCIIZ means a null-terminated ASCII string.
  162. .. flat-table::
  163. :widths: 1 1 2
  164. :header-rows: 1
  165. * - Field
  166. - Format
  167. - Description
  168. * - Signal Type
  169. - DWORD
  170. - Type of GPIO signal
  171. - 0x00000001 - Recovery button
  172. - 0x00000002 - Developer mode switch
  173. - 0x00000003 - Firmware write protection switch
  174. - 0x00000100 - Debug header GPIO 0
  175. - ...
  176. - 0x000001FF - Debug header GPIO 255
  177. Other values are reserved.
  178. * - Attributes
  179. - DWORD
  180. - Signal attributes as bitfields:
  181. - 0x00000001 - Signal is active-high (for button, a GPIO value
  182. of 1 means the button is pressed; for switches, a GPIO value
  183. of 1 means the switch is enabled). If this bit is 0, the signal
  184. is active low. Set to 0 for debug header GPIOs.
  185. * - Controller Offset
  186. - DWORD
  187. - GPIO number on the specified controller.
  188. * - Controller Name
  189. - ASCIIZ
  190. - Name of the controller for the GPIO.
  191. Currently supported names:
  192. "NM10" - Intel NM10 chip
  193. VBNV (Chrome OS NVRAM locations)
  194. ================================
  195. This control method returns information about the NVRAM (CMOS) locations used to
  196. communicate with the BIOS.
  197. Arguments:
  198. ----------
  199. None
  200. Result code:
  201. ------------
  202. .. code-block::
  203. Package {
  204. NV Storage Block Offset //DWORD
  205. NV Storage Block Size //DWORD
  206. }
  207. .. flat-table::
  208. :widths: 1 1 2
  209. :header-rows: 1
  210. * - Field
  211. - Format
  212. - Description
  213. * - NV Storage Block Offset
  214. - DWORD
  215. - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
  216. the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
  217. clock data).
  218. * - NV Storage Block Size
  219. - DWORD
  220. - Size in bytes of the verified boot non-volatile storage block.
  221. FMAP (Chrome OS flashmap address)
  222. =================================
  223. This control method returns the physical memory address of the start of the main processor
  224. firmware flashmap.
  225. Arguments:
  226. ----------
  227. None
  228. NoneResult code:
  229. ----------------
  230. A DWORD containing the physical memory address of the start of the main processor firmware
  231. flashmap.
  232. VDTA (Chrome OS verified boot data)
  233. ===================================
  234. This control method returns the verified boot data block shared between the firmware
  235. verification step and the kernel verification step.
  236. Arguments:
  237. ----------
  238. None
  239. Result code:
  240. ------------
  241. A buffer containing the verified boot data block.
  242. MECK (Management Engine Checksum)
  243. =================================
  244. This control method returns the SHA-1 or SHA-256 hash that is read out of the Management
  245. Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that
  246. the ME firmware has not changed. If Management Engine is not present, or if the firmware was
  247. unable to read the extended registers, this buffer can be zero.
  248. Arguments:
  249. ----------
  250. None
  251. Result code:
  252. ------------
  253. A buffer containing the ME hash.
  254. MLST (Chrome OS method list)
  255. ============================
  256. This control method returns a list of the other control methods supported by the Chrome OS
  257. hardware device.
  258. Arguments:
  259. ----------
  260. None
  261. Result code:
  262. ------------
  263. A package containing a list of null-terminated ASCII strings, one for each control method
  264. supported by the Chrome OS hardware device, not including the MLST method itself.
  265. For this version of the specification, the result is:
  266. .. code-block::
  267. Package {
  268. "CHSW",
  269. "FWID",
  270. "HWID",
  271. "FRID",
  272. "BINF",
  273. "GPIO",
  274. "VBNV",
  275. "FMAP",
  276. "VDTA",
  277. "MECK"
  278. }