dma-attributes.rst 5.7 KB

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  1. ==============
  2. DMA attributes
  3. ==============
  4. This document describes the semantics of the DMA attributes that are
  5. defined in linux/dma-mapping.h.
  6. DMA_ATTR_WEAK_ORDERING
  7. ----------------------
  8. DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
  9. may be weakly ordered, that is that reads and writes may pass each other.
  10. Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
  11. those that do not will simply ignore the attribute and exhibit default
  12. behavior.
  13. DMA_ATTR_WRITE_COMBINE
  14. ----------------------
  15. DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
  16. buffered to improve performance.
  17. Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
  18. those that do not will simply ignore the attribute and exhibit default
  19. behavior.
  20. DMA_ATTR_NO_KERNEL_MAPPING
  21. --------------------------
  22. DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
  23. virtual mapping for the allocated buffer. On some architectures creating
  24. such mapping is non-trivial task and consumes very limited resources
  25. (like kernel virtual address space or dma consistent address space).
  26. Buffers allocated with this attribute can be only passed to user space
  27. by calling dma_mmap_attrs(). By using this API, you are guaranteeing
  28. that you won't dereference the pointer returned by dma_alloc_attr(). You
  29. can treat it as a cookie that must be passed to dma_mmap_attrs() and
  30. dma_free_attrs(). Make sure that both of these also get this attribute
  31. set on each call.
  32. Since it is optional for platforms to implement
  33. DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
  34. attribute and exhibit default behavior.
  35. DMA_ATTR_SKIP_CPU_SYNC
  36. ----------------------
  37. By default dma_map_{single,page,sg} functions family transfer a given
  38. buffer from CPU domain to device domain. Some advanced use cases might
  39. require sharing a buffer between more than one device. This requires
  40. having a mapping created separately for each device and is usually
  41. performed by calling dma_map_{single,page,sg} function more than once
  42. for the given buffer with device pointer to each device taking part in
  43. the buffer sharing. The first call transfers a buffer from 'CPU' domain
  44. to 'device' domain, what synchronizes CPU caches for the given region
  45. (usually it means that the cache has been flushed or invalidated
  46. depending on the dma direction). However, next calls to
  47. dma_map_{single,page,sg}() for other devices will perform exactly the
  48. same synchronization operation on the CPU cache. CPU cache synchronization
  49. might be a time consuming operation, especially if the buffers are
  50. large, so it is highly recommended to avoid it if possible.
  51. DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
  52. the CPU cache for the given buffer assuming that it has been already
  53. transferred to 'device' domain. This attribute can be also used for
  54. dma_unmap_{single,page,sg} functions family to force buffer to stay in
  55. device domain after releasing a mapping for it. Use this attribute with
  56. care!
  57. DMA_ATTR_FORCE_CONTIGUOUS
  58. -------------------------
  59. By default DMA-mapping subsystem is allowed to assemble the buffer
  60. allocated by dma_alloc_attrs() function from individual pages if it can
  61. be mapped as contiguous chunk into device dma address space. By
  62. specifying this attribute the allocated buffer is forced to be contiguous
  63. also in physical memory.
  64. DMA_ATTR_ALLOC_SINGLE_PAGES
  65. ---------------------------
  66. This is a hint to the DMA-mapping subsystem that it's probably not worth
  67. the time to try to allocate memory to in a way that gives better TLB
  68. efficiency (AKA it's not worth trying to build the mapping out of larger
  69. pages). You might want to specify this if:
  70. - You know that the accesses to this memory won't thrash the TLB.
  71. You might know that the accesses are likely to be sequential or
  72. that they aren't sequential but it's unlikely you'll ping-pong
  73. between many addresses that are likely to be in different physical
  74. pages.
  75. - You know that the penalty of TLB misses while accessing the
  76. memory will be small enough to be inconsequential. If you are
  77. doing a heavy operation like decryption or decompression this
  78. might be the case.
  79. - You know that the DMA mapping is fairly transitory. If you expect
  80. the mapping to have a short lifetime then it may be worth it to
  81. optimize allocation (avoid coming up with large pages) instead of
  82. getting the slight performance win of larger pages.
  83. Setting this hint doesn't guarantee that you won't get huge pages, but it
  84. means that we won't try quite as hard to get them.
  85. .. note:: At the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM,
  86. though ARM64 patches will likely be posted soon.
  87. DMA_ATTR_NO_WARN
  88. ----------------
  89. This tells the DMA-mapping subsystem to suppress allocation failure reports
  90. (similarly to __GFP_NOWARN).
  91. On some architectures allocation failures are reported with error messages
  92. to the system logs. Although this can help to identify and debug problems,
  93. drivers which handle failures (eg, retry later) have no problems with them,
  94. and can actually flood the system logs with error messages that aren't any
  95. problem at all, depending on the implementation of the retry mechanism.
  96. So, this provides a way for drivers to avoid those error messages on calls
  97. where allocation failures are not a problem, and shouldn't bother the logs.
  98. .. note:: At the moment DMA_ATTR_NO_WARN is only implemented on PowerPC.
  99. DMA_ATTR_PRIVILEGED
  100. -------------------
  101. Some advanced peripherals such as remote processors and GPUs perform
  102. accesses to DMA buffers in both privileged "supervisor" and unprivileged
  103. "user" modes. This attribute is used to indicate to the DMA-mapping
  104. subsystem that the buffer is fully accessible at the elevated privilege
  105. level (and ideally inaccessible or at least read-only at the
  106. lesser-privileged levels).