pci.rst 23 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. ==============================
  3. How To Write Linux PCI Drivers
  4. ==============================
  5. :Authors: - Martin Mares <[email protected]>
  6. - Grant Grundler <[email protected]>
  7. The world of PCI is vast and full of (mostly unpleasant) surprises.
  8. Since each CPU architecture implements different chip-sets and PCI devices
  9. have different requirements (erm, "features"), the result is the PCI support
  10. in the Linux kernel is not as trivial as one would wish. This short paper
  11. tries to introduce all potential driver authors to Linux APIs for
  12. PCI device drivers.
  13. A more complete resource is the third edition of "Linux Device Drivers"
  14. by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
  15. LDD3 is available for free (under Creative Commons License) from:
  16. https://lwn.net/Kernel/LDD3/.
  17. However, keep in mind that all documents are subject to "bit rot".
  18. Refer to the source code if things are not working as described here.
  19. Please send questions/comments/patches about Linux PCI API to the
  20. "Linux PCI" <[email protected]> mailing list.
  21. Structure of PCI drivers
  22. ========================
  23. PCI drivers "discover" PCI devices in a system via pci_register_driver().
  24. Actually, it's the other way around. When the PCI generic code discovers
  25. a new device, the driver with a matching "description" will be notified.
  26. Details on this below.
  27. pci_register_driver() leaves most of the probing for devices to
  28. the PCI layer and supports online insertion/removal of devices [thus
  29. supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
  30. pci_register_driver() call requires passing in a table of function
  31. pointers and thus dictates the high level structure of a driver.
  32. Once the driver knows about a PCI device and takes ownership, the
  33. driver generally needs to perform the following initialization:
  34. - Enable the device
  35. - Request MMIO/IOP resources
  36. - Set the DMA mask size (for both coherent and streaming DMA)
  37. - Allocate and initialize shared control data (pci_allocate_coherent())
  38. - Access device configuration space (if needed)
  39. - Register IRQ handler (request_irq())
  40. - Initialize non-PCI (i.e. LAN/SCSI/etc parts of the chip)
  41. - Enable DMA/processing engines
  42. When done using the device, and perhaps the module needs to be unloaded,
  43. the driver needs to take the follow steps:
  44. - Disable the device from generating IRQs
  45. - Release the IRQ (free_irq())
  46. - Stop all DMA activity
  47. - Release DMA buffers (both streaming and coherent)
  48. - Unregister from other subsystems (e.g. scsi or netdev)
  49. - Release MMIO/IOP resources
  50. - Disable the device
  51. Most of these topics are covered in the following sections.
  52. For the rest look at LDD3 or <linux/pci.h> .
  53. If the PCI subsystem is not configured (CONFIG_PCI is not set), most of
  54. the PCI functions described below are defined as inline functions either
  55. completely empty or just returning an appropriate error codes to avoid
  56. lots of ifdefs in the drivers.
  57. pci_register_driver() call
  58. ==========================
  59. PCI device drivers call ``pci_register_driver()`` during their
  60. initialization with a pointer to a structure describing the driver
  61. (``struct pci_driver``):
  62. .. kernel-doc:: include/linux/pci.h
  63. :functions: pci_driver
  64. The ID table is an array of ``struct pci_device_id`` entries ending with an
  65. all-zero entry. Definitions with static const are generally preferred.
  66. .. kernel-doc:: include/linux/mod_devicetable.h
  67. :functions: pci_device_id
  68. Most drivers only need ``PCI_DEVICE()`` or ``PCI_DEVICE_CLASS()`` to set up
  69. a pci_device_id table.
  70. New PCI IDs may be added to a device driver pci_ids table at runtime
  71. as shown below::
  72. echo "vendor device subvendor subdevice class class_mask driver_data" > \
  73. /sys/bus/pci/drivers/{driver}/new_id
  74. All fields are passed in as hexadecimal values (no leading 0x).
  75. The vendor and device fields are mandatory, the others are optional. Users
  76. need pass only as many optional fields as necessary:
  77. - subvendor and subdevice fields default to PCI_ANY_ID (FFFFFFFF)
  78. - class and classmask fields default to 0
  79. - driver_data defaults to 0UL.
  80. - override_only field defaults to 0.
  81. Note that driver_data must match the value used by any of the pci_device_id
  82. entries defined in the driver. This makes the driver_data field mandatory
  83. if all the pci_device_id entries have a non-zero driver_data value.
  84. Once added, the driver probe routine will be invoked for any unclaimed
  85. PCI devices listed in its (newly updated) pci_ids list.
  86. When the driver exits, it just calls pci_unregister_driver() and the PCI layer
  87. automatically calls the remove hook for all devices handled by the driver.
  88. "Attributes" for driver functions/data
  89. --------------------------------------
  90. Please mark the initialization and cleanup functions where appropriate
  91. (the corresponding macros are defined in <linux/init.h>):
  92. ====== =================================================
  93. __init Initialization code. Thrown away after the driver
  94. initializes.
  95. __exit Exit code. Ignored for non-modular drivers.
  96. ====== =================================================
  97. Tips on when/where to use the above attributes:
  98. - The module_init()/module_exit() functions (and all
  99. initialization functions called _only_ from these)
  100. should be marked __init/__exit.
  101. - Do not mark the struct pci_driver.
  102. - Do NOT mark a function if you are not sure which mark to use.
  103. Better to not mark the function than mark the function wrong.
  104. How to find PCI devices manually
  105. ================================
  106. PCI drivers should have a really good reason for not using the
  107. pci_register_driver() interface to search for PCI devices.
  108. The main reason PCI devices are controlled by multiple drivers
  109. is because one PCI device implements several different HW services.
  110. E.g. combined serial/parallel port/floppy controller.
  111. A manual search may be performed using the following constructs:
  112. Searching by vendor and device ID::
  113. struct pci_dev *dev = NULL;
  114. while (dev = pci_get_device(VENDOR_ID, DEVICE_ID, dev))
  115. configure_device(dev);
  116. Searching by class ID (iterate in a similar way)::
  117. pci_get_class(CLASS_ID, dev)
  118. Searching by both vendor/device and subsystem vendor/device ID::
  119. pci_get_subsys(VENDOR_ID,DEVICE_ID, SUBSYS_VENDOR_ID, SUBSYS_DEVICE_ID, dev).
  120. You can use the constant PCI_ANY_ID as a wildcard replacement for
  121. VENDOR_ID or DEVICE_ID. This allows searching for any device from a
  122. specific vendor, for example.
  123. These functions are hotplug-safe. They increment the reference count on
  124. the pci_dev that they return. You must eventually (possibly at module unload)
  125. decrement the reference count on these devices by calling pci_dev_put().
  126. Device Initialization Steps
  127. ===========================
  128. As noted in the introduction, most PCI drivers need the following steps
  129. for device initialization:
  130. - Enable the device
  131. - Request MMIO/IOP resources
  132. - Set the DMA mask size (for both coherent and streaming DMA)
  133. - Allocate and initialize shared control data (pci_allocate_coherent())
  134. - Access device configuration space (if needed)
  135. - Register IRQ handler (request_irq())
  136. - Initialize non-PCI (i.e. LAN/SCSI/etc parts of the chip)
  137. - Enable DMA/processing engines.
  138. The driver can access PCI config space registers at any time.
  139. (Well, almost. When running BIST, config space can go away...but
  140. that will just result in a PCI Bus Master Abort and config reads
  141. will return garbage).
  142. Enable the PCI device
  143. ---------------------
  144. Before touching any device registers, the driver needs to enable
  145. the PCI device by calling pci_enable_device(). This will:
  146. - wake up the device if it was in suspended state,
  147. - allocate I/O and memory regions of the device (if BIOS did not),
  148. - allocate an IRQ (if BIOS did not).
  149. .. note::
  150. pci_enable_device() can fail! Check the return value.
  151. .. warning::
  152. OS BUG: we don't check resource allocations before enabling those
  153. resources. The sequence would make more sense if we called
  154. pci_request_resources() before calling pci_enable_device().
  155. Currently, the device drivers can't detect the bug when two
  156. devices have been allocated the same range. This is not a common
  157. problem and unlikely to get fixed soon.
  158. This has been discussed before but not changed as of 2.6.19:
  159. https://lore.kernel.org/r/[email protected]/
  160. pci_set_master() will enable DMA by setting the bus master bit
  161. in the PCI_COMMAND register. It also fixes the latency timer value if
  162. it's set to something bogus by the BIOS. pci_clear_master() will
  163. disable DMA by clearing the bus master bit.
  164. If the PCI device can use the PCI Memory-Write-Invalidate transaction,
  165. call pci_set_mwi(). This enables the PCI_COMMAND bit for Mem-Wr-Inval
  166. and also ensures that the cache line size register is set correctly.
  167. Check the return value of pci_set_mwi() as not all architectures
  168. or chip-sets may support Memory-Write-Invalidate. Alternatively,
  169. if Mem-Wr-Inval would be nice to have but is not required, call
  170. pci_try_set_mwi() to have the system do its best effort at enabling
  171. Mem-Wr-Inval.
  172. Request MMIO/IOP resources
  173. --------------------------
  174. Memory (MMIO), and I/O port addresses should NOT be read directly
  175. from the PCI device config space. Use the values in the pci_dev structure
  176. as the PCI "bus address" might have been remapped to a "host physical"
  177. address by the arch/chip-set specific kernel support.
  178. See Documentation/driver-api/io-mapping.rst for how to access device registers
  179. or device memory.
  180. The device driver needs to call pci_request_region() to verify
  181. no other device is already using the same address resource.
  182. Conversely, drivers should call pci_release_region() AFTER
  183. calling pci_disable_device().
  184. The idea is to prevent two devices colliding on the same address range.
  185. .. tip::
  186. See OS BUG comment above. Currently (2.6.19), The driver can only
  187. determine MMIO and IO Port resource availability _after_ calling
  188. pci_enable_device().
  189. Generic flavors of pci_request_region() are request_mem_region()
  190. (for MMIO ranges) and request_region() (for IO Port ranges).
  191. Use these for address resources that are not described by "normal" PCI
  192. BARs.
  193. Also see pci_request_selected_regions() below.
  194. Set the DMA mask size
  195. ---------------------
  196. .. note::
  197. If anything below doesn't make sense, please refer to
  198. Documentation/core-api/dma-api.rst. This section is just a reminder that
  199. drivers need to indicate DMA capabilities of the device and is not
  200. an authoritative source for DMA interfaces.
  201. While all drivers should explicitly indicate the DMA capability
  202. (e.g. 32 or 64 bit) of the PCI bus master, devices with more than
  203. 32-bit bus master capability for streaming data need the driver
  204. to "register" this capability by calling dma_set_mask() with
  205. appropriate parameters. In general this allows more efficient DMA
  206. on systems where System RAM exists above 4G _physical_ address.
  207. Drivers for all PCI-X and PCIe compliant devices must call
  208. dma_set_mask() as they are 64-bit DMA devices.
  209. Similarly, drivers must also "register" this capability if the device
  210. can directly address "coherent memory" in System RAM above 4G physical
  211. address by calling dma_set_coherent_mask().
  212. Again, this includes drivers for all PCI-X and PCIe compliant devices.
  213. Many 64-bit "PCI" devices (before PCI-X) and some PCI-X devices are
  214. 64-bit DMA capable for payload ("streaming") data but not control
  215. ("coherent") data.
  216. Setup shared control data
  217. -------------------------
  218. Once the DMA masks are set, the driver can allocate "coherent" (a.k.a. shared)
  219. memory. See Documentation/core-api/dma-api.rst for a full description of
  220. the DMA APIs. This section is just a reminder that it needs to be done
  221. before enabling DMA on the device.
  222. Initialize device registers
  223. ---------------------------
  224. Some drivers will need specific "capability" fields programmed
  225. or other "vendor specific" register initialized or reset.
  226. E.g. clearing pending interrupts.
  227. Register IRQ handler
  228. --------------------
  229. While calling request_irq() is the last step described here,
  230. this is often just another intermediate step to initialize a device.
  231. This step can often be deferred until the device is opened for use.
  232. All interrupt handlers for IRQ lines should be registered with IRQF_SHARED
  233. and use the devid to map IRQs to devices (remember that all PCI IRQ lines
  234. can be shared).
  235. request_irq() will associate an interrupt handler and device handle
  236. with an interrupt number. Historically interrupt numbers represent
  237. IRQ lines which run from the PCI device to the Interrupt controller.
  238. With MSI and MSI-X (more below) the interrupt number is a CPU "vector".
  239. request_irq() also enables the interrupt. Make sure the device is
  240. quiesced and does not have any interrupts pending before registering
  241. the interrupt handler.
  242. MSI and MSI-X are PCI capabilities. Both are "Message Signaled Interrupts"
  243. which deliver interrupts to the CPU via a DMA write to a Local APIC.
  244. The fundamental difference between MSI and MSI-X is how multiple
  245. "vectors" get allocated. MSI requires contiguous blocks of vectors
  246. while MSI-X can allocate several individual ones.
  247. MSI capability can be enabled by calling pci_alloc_irq_vectors() with the
  248. PCI_IRQ_MSI and/or PCI_IRQ_MSIX flags before calling request_irq(). This
  249. causes the PCI support to program CPU vector data into the PCI device
  250. capability registers. Many architectures, chip-sets, or BIOSes do NOT
  251. support MSI or MSI-X and a call to pci_alloc_irq_vectors with just
  252. the PCI_IRQ_MSI and PCI_IRQ_MSIX flags will fail, so try to always
  253. specify PCI_IRQ_LEGACY as well.
  254. Drivers that have different interrupt handlers for MSI/MSI-X and
  255. legacy INTx should chose the right one based on the msi_enabled
  256. and msix_enabled flags in the pci_dev structure after calling
  257. pci_alloc_irq_vectors.
  258. There are (at least) two really good reasons for using MSI:
  259. 1) MSI is an exclusive interrupt vector by definition.
  260. This means the interrupt handler doesn't have to verify
  261. its device caused the interrupt.
  262. 2) MSI avoids DMA/IRQ race conditions. DMA to host memory is guaranteed
  263. to be visible to the host CPU(s) when the MSI is delivered. This
  264. is important for both data coherency and avoiding stale control data.
  265. This guarantee allows the driver to omit MMIO reads to flush
  266. the DMA stream.
  267. See drivers/infiniband/hw/mthca/ or drivers/net/tg3.c for examples
  268. of MSI/MSI-X usage.
  269. PCI device shutdown
  270. ===================
  271. When a PCI device driver is being unloaded, most of the following
  272. steps need to be performed:
  273. - Disable the device from generating IRQs
  274. - Release the IRQ (free_irq())
  275. - Stop all DMA activity
  276. - Release DMA buffers (both streaming and coherent)
  277. - Unregister from other subsystems (e.g. scsi or netdev)
  278. - Disable device from responding to MMIO/IO Port addresses
  279. - Release MMIO/IO Port resource(s)
  280. Stop IRQs on the device
  281. -----------------------
  282. How to do this is chip/device specific. If it's not done, it opens
  283. the possibility of a "screaming interrupt" if (and only if)
  284. the IRQ is shared with another device.
  285. When the shared IRQ handler is "unhooked", the remaining devices
  286. using the same IRQ line will still need the IRQ enabled. Thus if the
  287. "unhooked" device asserts IRQ line, the system will respond assuming
  288. it was one of the remaining devices asserted the IRQ line. Since none
  289. of the other devices will handle the IRQ, the system will "hang" until
  290. it decides the IRQ isn't going to get handled and masks the IRQ (100,000
  291. iterations later). Once the shared IRQ is masked, the remaining devices
  292. will stop functioning properly. Not a nice situation.
  293. This is another reason to use MSI or MSI-X if it's available.
  294. MSI and MSI-X are defined to be exclusive interrupts and thus
  295. are not susceptible to the "screaming interrupt" problem.
  296. Release the IRQ
  297. ---------------
  298. Once the device is quiesced (no more IRQs), one can call free_irq().
  299. This function will return control once any pending IRQs are handled,
  300. "unhook" the drivers IRQ handler from that IRQ, and finally release
  301. the IRQ if no one else is using it.
  302. Stop all DMA activity
  303. ---------------------
  304. It's extremely important to stop all DMA operations BEFORE attempting
  305. to deallocate DMA control data. Failure to do so can result in memory
  306. corruption, hangs, and on some chip-sets a hard crash.
  307. Stopping DMA after stopping the IRQs can avoid races where the
  308. IRQ handler might restart DMA engines.
  309. While this step sounds obvious and trivial, several "mature" drivers
  310. didn't get this step right in the past.
  311. Release DMA buffers
  312. -------------------
  313. Once DMA is stopped, clean up streaming DMA first.
  314. I.e. unmap data buffers and return buffers to "upstream"
  315. owners if there is one.
  316. Then clean up "coherent" buffers which contain the control data.
  317. See Documentation/core-api/dma-api.rst for details on unmapping interfaces.
  318. Unregister from other subsystems
  319. --------------------------------
  320. Most low level PCI device drivers support some other subsystem
  321. like USB, ALSA, SCSI, NetDev, Infiniband, etc. Make sure your
  322. driver isn't losing resources from that other subsystem.
  323. If this happens, typically the symptom is an Oops (panic) when
  324. the subsystem attempts to call into a driver that has been unloaded.
  325. Disable Device from responding to MMIO/IO Port addresses
  326. --------------------------------------------------------
  327. io_unmap() MMIO or IO Port resources and then call pci_disable_device().
  328. This is the symmetric opposite of pci_enable_device().
  329. Do not access device registers after calling pci_disable_device().
  330. Release MMIO/IO Port Resource(s)
  331. --------------------------------
  332. Call pci_release_region() to mark the MMIO or IO Port range as available.
  333. Failure to do so usually results in the inability to reload the driver.
  334. How to access PCI config space
  335. ==============================
  336. You can use `pci_(read|write)_config_(byte|word|dword)` to access the config
  337. space of a device represented by `struct pci_dev *`. All these functions return
  338. 0 when successful or an error code (`PCIBIOS_...`) which can be translated to a
  339. text string by pcibios_strerror. Most drivers expect that accesses to valid PCI
  340. devices don't fail.
  341. If you don't have a struct pci_dev available, you can call
  342. `pci_bus_(read|write)_config_(byte|word|dword)` to access a given device
  343. and function on that bus.
  344. If you access fields in the standard portion of the config header, please
  345. use symbolic names of locations and bits declared in <linux/pci.h>.
  346. If you need to access Extended PCI Capability registers, just call
  347. pci_find_capability() for the particular capability and it will find the
  348. corresponding register block for you.
  349. Other interesting functions
  350. ===========================
  351. ============================= ================================================
  352. pci_get_domain_bus_and_slot() Find pci_dev corresponding to given domain,
  353. bus and slot and number. If the device is
  354. found, its reference count is increased.
  355. pci_set_power_state() Set PCI Power Management state (0=D0 ... 3=D3)
  356. pci_find_capability() Find specified capability in device's capability
  357. list.
  358. pci_resource_start() Returns bus start address for a given PCI region
  359. pci_resource_end() Returns bus end address for a given PCI region
  360. pci_resource_len() Returns the byte length of a PCI region
  361. pci_set_drvdata() Set private driver data pointer for a pci_dev
  362. pci_get_drvdata() Return private driver data pointer for a pci_dev
  363. pci_set_mwi() Enable Memory-Write-Invalidate transactions.
  364. pci_clear_mwi() Disable Memory-Write-Invalidate transactions.
  365. ============================= ================================================
  366. Miscellaneous hints
  367. ===================
  368. When displaying PCI device names to the user (for example when a driver wants
  369. to tell the user what card has it found), please use pci_name(pci_dev).
  370. Always refer to the PCI devices by a pointer to the pci_dev structure.
  371. All PCI layer functions use this identification and it's the only
  372. reasonable one. Don't use bus/slot/function numbers except for very
  373. special purposes -- on systems with multiple primary buses their semantics
  374. can be pretty complex.
  375. Don't try to turn on Fast Back to Back writes in your driver. All devices
  376. on the bus need to be capable of doing it, so this is something which needs
  377. to be handled by platform and generic code, not individual drivers.
  378. Vendor and device identifications
  379. =================================
  380. Do not add new device or vendor IDs to include/linux/pci_ids.h unless they
  381. are shared across multiple drivers. You can add private definitions in
  382. your driver if they're helpful, or just use plain hex constants.
  383. The device IDs are arbitrary hex numbers (vendor controlled) and normally used
  384. only in a single location, the pci_device_id table.
  385. Please DO submit new vendor/device IDs to https://pci-ids.ucw.cz/.
  386. There's a mirror of the pci.ids file at https://github.com/pciutils/pciids.
  387. Obsolete functions
  388. ==================
  389. There are several functions which you might come across when trying to
  390. port an old driver to the new PCI interface. They are no longer present
  391. in the kernel as they aren't compatible with hotplug or PCI domains or
  392. having sane locking.
  393. ================= ===========================================
  394. pci_find_device() Superseded by pci_get_device()
  395. pci_find_subsys() Superseded by pci_get_subsys()
  396. pci_find_slot() Superseded by pci_get_domain_bus_and_slot()
  397. pci_get_slot() Superseded by pci_get_domain_bus_and_slot()
  398. ================= ===========================================
  399. The alternative is the traditional PCI device driver that walks PCI
  400. device lists. This is still possible but discouraged.
  401. MMIO Space and "Write Posting"
  402. ==============================
  403. Converting a driver from using I/O Port space to using MMIO space
  404. often requires some additional changes. Specifically, "write posting"
  405. needs to be handled. Many drivers (e.g. tg3, acenic, sym53c8xx_2)
  406. already do this. I/O Port space guarantees write transactions reach the PCI
  407. device before the CPU can continue. Writes to MMIO space allow the CPU
  408. to continue before the transaction reaches the PCI device. HW weenies
  409. call this "Write Posting" because the write completion is "posted" to
  410. the CPU before the transaction has reached its destination.
  411. Thus, timing sensitive code should add readl() where the CPU is
  412. expected to wait before doing other work. The classic "bit banging"
  413. sequence works fine for I/O Port space::
  414. for (i = 8; --i; val >>= 1) {
  415. outb(val & 1, ioport_reg); /* write bit */
  416. udelay(10);
  417. }
  418. The same sequence for MMIO space should be::
  419. for (i = 8; --i; val >>= 1) {
  420. writeb(val & 1, mmio_reg); /* write bit */
  421. readb(safe_mmio_reg); /* flush posted write */
  422. udelay(10);
  423. }
  424. It is important that "safe_mmio_reg" not have any side effects that
  425. interferes with the correct operation of the device.
  426. Another case to watch out for is when resetting a PCI device. Use PCI
  427. Configuration space reads to flush the writel(). This will gracefully
  428. handle the PCI master abort on all platforms if the PCI device is
  429. expected to not respond to a readl(). Most x86 platforms will allow
  430. MMIO reads to master abort (a.k.a. "Soft Fail") and return garbage
  431. (e.g. ~0). But many RISC platforms will crash (a.k.a."Hard Fail").