pci-ntb-function.rst 15 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. =================
  3. PCI NTB Function
  4. =================
  5. :Author: Kishon Vijay Abraham I <[email protected]>
  6. PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
  7. with each other by exposing each host as a device to the other host.
  8. NTBs typically support the ability to generate interrupts on the remote
  9. machine, expose memory ranges as BARs, and perform DMA. They also support
  10. scratchpads, which are areas of memory within the NTB that are accessible
  11. from both machines.
  12. PCI NTB Function allows two different systems (or hosts) to communicate
  13. with each other by configuring the endpoint instances in such a way that
  14. transactions from one system are routed to the other system.
  15. In the below diagram, PCI NTB function configures the SoC with multiple
  16. PCI Endpoint (EP) instances in such a way that transactions from one EP
  17. controller are routed to the other EP controller. Once PCI NTB function
  18. configures the SoC with multiple EP instances, HOST1 and HOST2 can
  19. communicate with each other using SoC as a bridge.
  20. .. code-block:: text
  21. +-------------+ +-------------+
  22. | | | |
  23. | HOST1 | | HOST2 |
  24. | | | |
  25. +------^------+ +------^------+
  26. | |
  27. | |
  28. +---------|-------------------------------------------------|---------+
  29. | +------v------+ +------v------+ |
  30. | | | | | |
  31. | | EP | | EP | |
  32. | | CONTROLLER1 | | CONTROLLER2 | |
  33. | | <-----------------------------------> | |
  34. | | | | | |
  35. | | | | | |
  36. | | | SoC With Multiple EP Instances | | |
  37. | | | (Configured using NTB Function) | | |
  38. | +-------------+ +-------------+ |
  39. +---------------------------------------------------------------------+
  40. Constructs used for Implementing NTB
  41. ====================================
  42. 1) Config Region
  43. 2) Self Scratchpad Registers
  44. 3) Peer Scratchpad Registers
  45. 4) Doorbell (DB) Registers
  46. 5) Memory Window (MW)
  47. Config Region:
  48. --------------
  49. Config Region is a construct that is specific to NTB implemented using NTB
  50. Endpoint Function Driver. The host and endpoint side NTB function driver will
  51. exchange information with each other using this region. Config Region has
  52. Control/Status Registers for configuring the Endpoint Controller. Host can
  53. write into this region for configuring the outbound Address Translation Unit
  54. (ATU) and to indicate the link status. Endpoint can indicate the status of
  55. commands issued by host in this region. Endpoint can also indicate the
  56. scratchpad offset and number of memory windows to the host using this region.
  57. The format of Config Region is given below. All the fields here are 32 bits.
  58. .. code-block:: text
  59. +------------------------+
  60. | COMMAND |
  61. +------------------------+
  62. | ARGUMENT |
  63. +------------------------+
  64. | STATUS |
  65. +------------------------+
  66. | TOPOLOGY |
  67. +------------------------+
  68. | ADDRESS (LOWER 32) |
  69. +------------------------+
  70. | ADDRESS (UPPER 32) |
  71. +------------------------+
  72. | SIZE |
  73. +------------------------+
  74. | NO OF MEMORY WINDOW |
  75. +------------------------+
  76. | MEMORY WINDOW1 OFFSET |
  77. +------------------------+
  78. | SPAD OFFSET |
  79. +------------------------+
  80. | SPAD COUNT |
  81. +------------------------+
  82. | DB ENTRY SIZE |
  83. +------------------------+
  84. | DB DATA |
  85. +------------------------+
  86. | : |
  87. +------------------------+
  88. | : |
  89. +------------------------+
  90. | DB DATA |
  91. +------------------------+
  92. COMMAND:
  93. NTB function supports three commands:
  94. CMD_CONFIGURE_DOORBELL (0x1): Command to configure doorbell. Before
  95. invoking this command, the host should allocate and initialize
  96. MSI/MSI-X vectors (i.e., initialize the MSI/MSI-X Capability in the
  97. Endpoint). The endpoint on receiving this command will configure
  98. the outbound ATU such that transactions to Doorbell BAR will be routed
  99. to the MSI/MSI-X address programmed by the host. The ARGUMENT
  100. register should be populated with number of DBs to configure (in the
  101. lower 16 bits) and if MSI or MSI-X should be configured (BIT 16).
  102. CMD_CONFIGURE_MW (0x2): Command to configure memory window (MW). The
  103. host invokes this command after allocating a buffer that can be
  104. accessed by remote host. The allocated address should be programmed
  105. in the ADDRESS register (64 bit), the size should be programmed in
  106. the SIZE register and the memory window index should be programmed
  107. in the ARGUMENT register. The endpoint on receiving this command
  108. will configure the outbound ATU such that transactions to MW BAR
  109. are routed to the address provided by the host.
  110. CMD_LINK_UP (0x3): Command to indicate an NTB application is
  111. bound to the EP device on the host side. Once the endpoint
  112. receives this command from both the hosts, the endpoint will
  113. raise a LINK_UP event to both the hosts to indicate the host
  114. NTB applications can start communicating with each other.
  115. ARGUMENT:
  116. The value of this register is based on the commands issued in
  117. command register. See COMMAND section for more information.
  118. TOPOLOGY:
  119. Set to NTB_TOPO_B2B_USD for Primary interface
  120. Set to NTB_TOPO_B2B_DSD for Secondary interface
  121. ADDRESS/SIZE:
  122. Address and Size to be used while configuring the memory window.
  123. See "CMD_CONFIGURE_MW" for more info.
  124. MEMORY WINDOW1 OFFSET:
  125. Memory Window 1 and Doorbell registers are packed together in the
  126. same BAR. The initial portion of the region will have doorbell
  127. registers and the latter portion of the region is for memory window 1.
  128. This register will specify the offset of the memory window 1.
  129. NO OF MEMORY WINDOW:
  130. Specifies the number of memory windows supported by the NTB device.
  131. SPAD OFFSET:
  132. Self scratchpad region and config region are packed together in the
  133. same BAR. The initial portion of the region will have config region
  134. and the latter portion of the region is for self scratchpad. This
  135. register will specify the offset of the self scratchpad registers.
  136. SPAD COUNT:
  137. Specifies the number of scratchpad registers supported by the NTB
  138. device.
  139. DB ENTRY SIZE:
  140. Used to determine the offset within the DB BAR that should be written
  141. in order to raise doorbell. EPF NTB can use either MSI or MSI-X to
  142. ring doorbell (MSI-X support will be added later). MSI uses same
  143. address for all the interrupts and MSI-X can provide different
  144. addresses for different interrupts. The MSI/MSI-X address is provided
  145. by the host and the address it gives is based on the MSI/MSI-X
  146. implementation supported by the host. For instance, ARM platform
  147. using GIC ITS will have the same MSI-X address for all the interrupts.
  148. In order to support all the combinations and use the same mechanism
  149. for both MSI and MSI-X, EPF NTB allocates a separate region in the
  150. Outbound Address Space for each of the interrupts. This region will
  151. be mapped to the MSI/MSI-X address provided by the host. If a host
  152. provides the same address for all the interrupts, all the regions
  153. will be translated to the same address. If a host provides different
  154. addresses, the regions will be translated to different addresses. This
  155. will ensure there is no difference while raising the doorbell.
  156. DB DATA:
  157. EPF NTB supports 32 interrupts, so there are 32 DB DATA registers.
  158. This holds the MSI/MSI-X data that has to be written to MSI address
  159. for raising doorbell interrupt. This will be populated by EPF NTB
  160. while invoking CMD_CONFIGURE_DOORBELL.
  161. Scratchpad Registers:
  162. ---------------------
  163. Each host has its own register space allocated in the memory of NTB endpoint
  164. controller. They are both readable and writable from both sides of the bridge.
  165. They are used by applications built over NTB and can be used to pass control
  166. and status information between both sides of a device.
  167. Scratchpad registers has 2 parts
  168. 1) Self Scratchpad: Host's own register space
  169. 2) Peer Scratchpad: Remote host's register space.
  170. Doorbell Registers:
  171. -------------------
  172. Doorbell Registers are used by the hosts to interrupt each other.
  173. Memory Window:
  174. --------------
  175. Actual transfer of data between the two hosts will happen using the
  176. memory window.
  177. Modeling Constructs:
  178. ====================
  179. There are 5 or more distinct regions (config, self scratchpad, peer
  180. scratchpad, doorbell, one or more memory windows) to be modeled to achieve
  181. NTB functionality. At least one memory window is required while more than
  182. one is permitted. All these regions should be mapped to BARs for hosts to
  183. access these regions.
  184. If one 32-bit BAR is allocated for each of these regions, the scheme would
  185. look like this:
  186. ====== ===============
  187. BAR NO CONSTRUCTS USED
  188. ====== ===============
  189. BAR0 Config Region
  190. BAR1 Self Scratchpad
  191. BAR2 Peer Scratchpad
  192. BAR3 Doorbell
  193. BAR4 Memory Window 1
  194. BAR5 Memory Window 2
  195. ====== ===============
  196. However if we allocate a separate BAR for each of the regions, there would not
  197. be enough BARs for all the regions in a platform that supports only 64-bit
  198. BARs.
  199. In order to be supported by most of the platforms, the regions should be
  200. packed and mapped to BARs in a way that provides NTB functionality and
  201. also makes sure the host doesn't access any region that it is not supposed
  202. to.
  203. The following scheme is used in EPF NTB Function:
  204. ====== ===============================
  205. BAR NO CONSTRUCTS USED
  206. ====== ===============================
  207. BAR0 Config Region + Self Scratchpad
  208. BAR1 Peer Scratchpad
  209. BAR2 Doorbell + Memory Window 1
  210. BAR3 Memory Window 2
  211. BAR4 Memory Window 3
  212. BAR5 Memory Window 4
  213. ====== ===============================
  214. With this scheme, for the basic NTB functionality 3 BARs should be sufficient.
  215. Modeling Config/Scratchpad Region:
  216. ----------------------------------
  217. .. code-block:: text
  218. +-----------------+------->+------------------+ +-----------------+
  219. | BAR0 | | CONFIG REGION | | BAR0 |
  220. +-----------------+----+ +------------------+<-------+-----------------+
  221. | BAR1 | | |SCRATCHPAD REGION | | BAR1 |
  222. +-----------------+ +-->+------------------+<-------+-----------------+
  223. | BAR2 | Local Memory | BAR2 |
  224. +-----------------+ +-----------------+
  225. | BAR3 | | BAR3 |
  226. +-----------------+ +-----------------+
  227. | BAR4 | | BAR4 |
  228. +-----------------+ +-----------------+
  229. | BAR5 | | BAR5 |
  230. +-----------------+ +-----------------+
  231. EP CONTROLLER 1 EP CONTROLLER 2
  232. Above diagram shows Config region + Scratchpad region for HOST1 (connected to
  233. EP controller 1) allocated in local memory. The HOST1 can access the config
  234. region and scratchpad region (self scratchpad) using BAR0 of EP controller 1.
  235. The peer host (HOST2 connected to EP controller 2) can also access this
  236. scratchpad region (peer scratchpad) using BAR1 of EP controller 2. This
  237. diagram shows the case where Config region and Scratchpad regions are allocated
  238. for HOST1, however the same is applicable for HOST2.
  239. Modeling Doorbell/Memory Window 1:
  240. ----------------------------------
  241. .. code-block:: text
  242. +-----------------+ +----->+----------------+-----------+-----------------+
  243. | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
  244. +-----------------+ | +----------------+ +-----------------+
  245. | BAR1 | | | Doorbell 2 +---------+ | |
  246. +-----------------+----+ +----------------+ | | |
  247. | BAR2 | | Doorbell 3 +-------+ | +-----------------+
  248. +-----------------+----+ +----------------+ | +-> MSI-X ADDRESS 2 |
  249. | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
  250. +-----------------+ | |----------------+ | | | |
  251. | BAR4 | | | | | | +-----------------+
  252. +-----------------+ | | MW1 +---+ | +-->+ MSI-X ADDRESS 3||
  253. | BAR5 | | | | | | +-----------------+
  254. +-----------------+ +----->-----------------+ | | | |
  255. EP CONTROLLER 1 | | | | +-----------------+
  256. | | | +---->+ MSI-X ADDRESS 4 |
  257. +----------------+ | +-----------------+
  258. EP CONTROLLER 2 | | |
  259. (OB SPACE) | | |
  260. +-------> MW1 |
  261. | |
  262. | |
  263. +-----------------+
  264. | |
  265. | |
  266. | |
  267. | |
  268. | |
  269. +-----------------+
  270. PCI Address Space
  271. (Managed by HOST2)
  272. Above diagram shows how the doorbell and memory window 1 is mapped so that
  273. HOST1 can raise doorbell interrupt on HOST2 and also how HOST1 can access
  274. buffers exposed by HOST2 using memory window1 (MW1). Here doorbell and
  275. memory window 1 regions are allocated in EP controller 2 outbound (OB) address
  276. space. Allocating and configuring BARs for doorbell and memory window1
  277. is done during the initialization phase of NTB endpoint function driver.
  278. Mapping from EP controller 2 OB space to PCI address space is done when HOST2
  279. sends CMD_CONFIGURE_MW/CMD_CONFIGURE_DOORBELL.
  280. Modeling Optional Memory Windows:
  281. ---------------------------------
  282. This is modeled the same was as MW1 but each of the additional memory windows
  283. is mapped to separate BARs.