// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. * */ #include #include #include #include #include #include #include #include #include #include #include "icc-rpmh.h" #include "qnoc-qos.h" static const struct regmap_config icc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, }; static struct qcom_icc_qosbox qhm_qup1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x7000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", .id = MASTER_QUP_1, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_qup1_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", .id = MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_A1NOC }, }; static struct qcom_icc_qosbox xm_ufs_mem_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x8000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .id = MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_ufs_mem_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; static struct qcom_icc_qosbox xm_usb3_0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x9000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", .id = MASTER_USB3_0, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_usb3_0_qos, .num_links = 1, .links = { SLAVE_A1NOC_SNOC }, }; static struct qcom_icc_qosbox qhm_qdss_bam_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x12000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .id = MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_qdss_bam_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_qosbox qhm_qup0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x13000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", .id = MASTER_QUP_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_qup0_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", .id = MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_A2NOC }, }; static struct qcom_icc_qosbox qnm_cnoc_datapath_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x14000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", .id = MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_cnoc_datapath_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_qosbox qxm_crypto_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x15000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", .id = MASTER_CRYPTO, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qxm_crypto_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_qosbox qxm_ipa_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xe000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .id = MASTER_IPA, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qxm_ipa_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", .id = MASTER_SP, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x10000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", .id = MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_qdss_etr_0_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xd000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", .id = MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_qdss_etr_1_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_qosbox xm_sdc2_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x11000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", .id = MASTER_SDCC_2, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_sdc2_qos, .num_links = 1, .links = { SLAVE_A2NOC_SNOC }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", .id = MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_QUP_CORE_0 }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", .id = MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_QUP_CORE_1 }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", .id = MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 44, .links = { SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH, SLAVE_AOSS, SLAVE_CAMERA_CFG, SLAVE_CLK_CTL, SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG, SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MXA_CFG, SLAVE_RBCPR_MXC_CFG, SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM, SLAVE_DISPLAY_CFG, SLAVE_DISPLAY1_CFG, SLAVE_GFX3D_CFG, SLAVE_IMEM_CFG, SLAVE_IPA_CFG, SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS, SLAVE_MX_RDPM, SLAVE_PDM, SLAVE_PRNG, SLAVE_QDSS_CFG, SLAVE_QUP_0, SLAVE_QUP_1, SLAVE_SDCC_2, SLAVE_SPSS_CFG, SLAVE_TCSR, SLAVE_TLMM, SLAVE_TME_CFG, SLAVE_UFS_MEM_CFG, SLAVE_USB3_0, SLAVE_VENUS_CFG, SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG, SLAVE_A2NOC_CFG, SLAVE_DDRSS_CFG, SLAVE_CNOC_MNOC_CFG, SLAVE_PCIE_ANOC_CFG, SLAVE_SNOC_CFG, SLAVE_IMEM, SLAVE_SERVICE_CNOC, SLAVE_QDSS_STM, SLAVE_TCU }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", .id = MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 45, .links = { SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH, SLAVE_AOSS, SLAVE_CAMERA_CFG, SLAVE_CLK_CTL, SLAVE_CDSP_CFG, SLAVE_RBCPR_CX_CFG, SLAVE_RBCPR_MMCX_CFG, SLAVE_RBCPR_MXA_CFG, SLAVE_RBCPR_MXC_CFG, SLAVE_CRYPTO_0_CFG, SLAVE_CX_RDPM, SLAVE_DISPLAY_CFG, SLAVE_DISPLAY1_CFG, SLAVE_GFX3D_CFG, SLAVE_IMEM_CFG, SLAVE_IPA_CFG, SLAVE_IPC_ROUTER_CFG, SLAVE_LPASS, SLAVE_MX_RDPM, SLAVE_PDM, SLAVE_PRNG, SLAVE_QDSS_CFG, SLAVE_QUP_0, SLAVE_QUP_1, SLAVE_SDCC_2, SLAVE_SPSS_CFG, SLAVE_TCSR, SLAVE_TLMM, SLAVE_TME_CFG, SLAVE_UFS_MEM_CFG, SLAVE_USB3_0, SLAVE_VENUS_CFG, SLAVE_VSENSE_CTRL_CFG, SLAVE_A1NOC_CFG, SLAVE_A2NOC_CFG, SLAVE_CNOC_A2NOC, SLAVE_DDRSS_CFG, SLAVE_CNOC_MNOC_CFG, SLAVE_PCIE_ANOC_CFG, SLAVE_SNOC_CFG, SLAVE_IMEM, SLAVE_SERVICE_CNOC, SLAVE_QDSS_STM, SLAVE_TCU }, }; static struct qcom_icc_qosbox alm_gpu_tcu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xa5000 }, .config = &(struct qos_config) { .prio = 6, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", .id = MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &alm_gpu_tcu_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox alm_sys_tcu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xa6000 }, .config = &(struct qos_config) { .prio = 6, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", .id = MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &alm_sys_tcu_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", .id = MASTER_APPSS_PROC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_gpu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x19000, 0x59000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", .id = MASTER_GFX3D, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_gpu_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x1a000, 0x5a000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .id = MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x1b000, 0x5b000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .id = MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x1c000, 0x5c000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", .id = MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_nsp_gemnoc_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_pcie_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xa7000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", .id = MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_pcie_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_snoc_gc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xa8000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", .id = MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_snoc_gc_qos, .num_links = 1, .links = { SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_snoc_sf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xa9000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .id = MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_snoc_sf_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", .id = MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 6, .links = { SLAVE_LPASS_CORE_CFG, SLAVE_LPASS_LPI_CFG, SLAVE_LPASS_MPU_CFG, SLAVE_LPASS_TOP_CFG, SLAVE_SERVICES_LPASS_AML_NOC, SLAVE_SERVICE_LPASS_AG_NOC }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", .id = MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 4, .links = { SLAVE_LPASS_TOP_CFG, SLAVE_LPASS_SNOC, SLAVE_SERVICES_LPASS_AML_NOC, SLAVE_SERVICE_LPASS_AG_NOC }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", .id = MASTER_LLCC, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_EBI1 }, }; static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x15000, 0x15080 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", .id = MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_camnoc_hf_qos, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x16000 }, .config = &(struct qos_config) { .prio = 4, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", .id = MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_camnoc_icp_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x17000, 0x17080 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", .id = MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_camnoc_sf_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_mdp0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x1b000, 0x1b080 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_mdp0 = { .name = "qnm_mdp0", .id = MASTER_MDP0, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_mdp0_qos, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_mdp1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x1c000, 0x1c080 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_mdp1 = { .name = "qnm_mdp1", .id = MASTER_MDP1, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_mdp1_qos, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", .id = MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_MNOC }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", .id = MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_video_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 2, .offsets = { 0x19000, 0x19080 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", .id = MASTER_VIDEO, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_video_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x1a080 }, .config = &(struct qos_config) { .prio = 4, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", .id = MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_video_cv_cpu_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_video_cvp_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x1a000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", .id = MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_video_cvp_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_qosbox qnm_video_v_cpu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x1a100 }, .config = &(struct qos_config) { .prio = 4, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", .id = MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_video_v_cpu_qos, .num_links = 1, .links = { SLAVE_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", .id = MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_NSP_NOC }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", .id = MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_CDSP_MEM_NOC }, }; static struct qcom_icc_node qnm_pcie_anoc_cfg = { .name = "qnm_pcie_anoc_cfg", .id = MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_PCIE_ANOC }, }; static struct qcom_icc_qosbox xm_pcie3_0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xa000 }, .config = &(struct qos_config) { .prio = 3, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", .id = MASTER_PCIE_0, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_pcie3_0_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_qosbox xm_pcie3_1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xb000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", .id = MASTER_PCIE_1, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_pcie3_1_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_qosbox xm_pcie4_0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xc000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_pcie4_0 = { .name = "xm_pcie4_0", .id = MASTER_PCIE_4, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_pcie4_0_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_qosbox qhm_gic_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x11000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", .id = MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_gic_qos, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_SF }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", .id = MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_SF }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", .id = MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_SF }, }; static struct qcom_icc_qosbox qnm_lpass_noc_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x12000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, }, }; static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", .id = MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_lpass_noc_qos, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_SF }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", .id = MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_SNOC }, }; static struct qcom_icc_qosbox xm_gic_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x13000 }, .config = &(struct qos_config) { .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", .id = MASTER_GIC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_gic_qos, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_GC }, }; static struct qcom_icc_node qnm_mnoc_hf_disp = { .name = "qnm_mnoc_hf_disp", .id = MASTER_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_LLCC_DISP }, }; static struct qcom_icc_node qnm_pcie_disp = { .name = "qnm_pcie_disp", .id = MASTER_ANOC_PCIE_GEM_NOC_DISP, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_LLCC_DISP }, }; static struct qcom_icc_node llcc_mc_disp = { .name = "llcc_mc_disp", .id = MASTER_LLCC_DISP, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_EBI1_DISP }, }; static struct qcom_icc_node qnm_mdp0_disp = { .name = "qnm_mdp0_disp", .id = MASTER_MDP0_DISP, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC_DISP }, }; static struct qcom_icc_node qnm_mnoc_hf_disp2 = { .name = "qnm_mnoc_hf_disp2", .id = MASTER_MNOC_HF_MEM_NOC_DISP2, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_LLCC_DISP2 }, }; static struct qcom_icc_node qnm_pcie_disp2 = { .name = "qnm_pcie_disp2", .id = MASTER_ANOC_PCIE_GEM_NOC_DISP2, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_LLCC_DISP2 }, }; static struct qcom_icc_node llcc_mc_disp2 = { .name = "llcc_mc_disp2", .id = MASTER_LLCC_DISP2, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_EBI1_DISP2 }, }; static struct qcom_icc_node qnm_mdp1_disp2 = { .name = "qnm_mdp1_disp2", .id = MASTER_MDP1_DISP2, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_MNOC_HF_MEM_NOC_DISP2 }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", .id = SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A1NOC_SNOC }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", .id = SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", .id = SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A2NOC_SNOC }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", .id = SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", .id = SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", .id = SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", .id = SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", .id = SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", .id = SLAVE_AOSS, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", .id = SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", .id = SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", .id = SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_CDSP_NOC_CFG }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", .id = SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", .id = SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", .id = SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", .id = SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", .id = SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", .id = SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_display_0_cfg = { .name = "qhs_display_0_cfg", .id = SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_display_1_cfg = { .name = "qhs_display_1_cfg", .id = SLAVE_DISPLAY1_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", .id = SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", .id = SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", .id = SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", .id = SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", .id = SLAVE_LPASS, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_CNOC_LPASS_AG_NOC }, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", .id = SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", .id = SLAVE_PDM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", .id = SLAVE_PRNG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", .id = SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", .id = SLAVE_QUP_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", .id = SLAVE_QUP_1, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", .id = SLAVE_SDCC_2, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", .id = SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", .id = SLAVE_TCSR, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", .id = SLAVE_TLMM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", .id = SLAVE_TME_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", .id = SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", .id = SLAVE_USB3_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", .id = SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", .id = SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", .id = SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A1NOC_CFG }, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", .id = SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_A2NOC_CFG }, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", .id = SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_CNOC_A2NOC }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", .id = SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", .id = SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_CNOC_MNOC_CFG }, }; static struct qcom_icc_node qns_pcie_anoc_cfg = { .name = "qns_pcie_anoc_cfg", .id = SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_PCIE_ANOC_CFG }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", .id = SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_CFG }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", .id = SLAVE_IMEM, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", .id = SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", .id = SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", .id = SLAVE_TCU, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", .id = SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_GEM_NOC_CNOC }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", .id = SLAVE_LLCC, .channels = 4, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_LLCC }, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", .id = SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", .id = SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", .id = SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", .id = SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", .id = SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_LPASS_ANOC }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", .id = SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", .id = SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", .id = SLAVE_EBI1, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", .id = SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_HF_MEM_NOC }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", .id = SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_SF_MEM_NOC }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", .id = SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", .id = SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_COMPUTE_NOC }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", .id = SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", .id = SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", .id = SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", .id = SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_GC_MEM_NOC }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", .id = SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_SF_MEM_NOC }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", .id = SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_llcc_disp = { .name = "qns_llcc_disp", .id = SLAVE_LLCC_DISP, .channels = 4, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_LLCC_DISP }, }; static struct qcom_icc_node ebi_disp = { .name = "ebi_disp", .id = SLAVE_EBI1_DISP, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf_disp = { .name = "qns_mem_noc_hf_disp", .id = SLAVE_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_HF_MEM_NOC_DISP }, }; static struct qcom_icc_node qns_llcc_disp2 = { .name = "qns_llcc_disp2", .id = SLAVE_LLCC_DISP2, .channels = 4, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_LLCC_DISP2 }, }; static struct qcom_icc_node ebi_disp2 = { .name = "ebi_disp2", .id = SLAVE_EBI1_DISP2, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf_disp2 = { .name = "qns_mem_noc_hf_disp2", .id = SLAVE_MNOC_HF_MEM_NOC_DISP2, .channels = 2, .buswidth = 32, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_MNOC_HF_MEM_NOC_DISP2 }, }; static struct qcom_icc_node master_ddr_rt = { .name = "master_ddr_rt", .id = MASTER_DDR_RT, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_DDR_RT }, }; static struct qcom_icc_node slv_ddr_rt = { .name = "slv_ddr_rt", .id = SLAVE_DDR_RT, .channels = 4, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { .name = "ACV", .voter_idx = 0, .enable_mask = 0x8, .perf_mode_mask = 0x2, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", .voter_idx = 0, .num_nodes = 1, .nodes = { &qxm_crypto }, }; static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .voter_idx = 0, .enable_mask = 0x1, .keepalive = true, .num_nodes = 47, .nodes = { &qnm_gemnoc_cnoc, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mxa, &qhs_cpr_mxc, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_display_0_cfg, &qhs_display_1_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mx_rdpm, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_sdc2, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_tme_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_cnoc_a2noc, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_pcie_anoc_cfg, &qns_snoc_cfg, &qxs_imem, &srvc_cnoc, &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", .voter_idx = 0, .enable_mask = 0x1, .num_nodes = 2, .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, }; static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .voter_idx = 0, .keepalive = true, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_mc4 = { .name = "MC4", .voter_idx = 0, .num_nodes = 1, .nodes = { &slv_ddr_rt }, }; static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", .voter_idx = 0, .keepalive_early = true, .num_nodes = 3, .nodes = { &qnm_mdp0, &qnm_mdp1, &qns_mem_noc_hf }, }; static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", .voter_idx = 0, .enable_mask = 0x1, .num_nodes = 10, .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_mnoc_cfg, &qnm_vapss_hcp, &qnm_video, &qnm_video_cv_cpu, &qnm_video_cvp, &qnm_video_v_cpu, &qns_mem_noc_sf }, }; static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .voter_idx = 0, .keepalive_early = true, .vote_scale = 1, .num_nodes = 1, .nodes = { &qup0_core_slave }, }; static struct qcom_icc_bcm bcm_qup1 = { .name = "QUP1", .voter_idx = 0, .keepalive_early = true, .vote_scale = 1, .num_nodes = 1, .nodes = { &qup1_core_slave }, }; static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .voter_idx = 0, .keepalive = true, .num_nodes = 1, .nodes = { &qns_llcc }, }; static struct qcom_icc_bcm bcm_sh1 = { .name = "SH1", .voter_idx = 0, .enable_mask = 0x1, .num_nodes = 6, .nodes = { &alm_gpu_tcu, &alm_sys_tcu, &qnm_nsp_gemnoc, &qnm_pcie, &qnm_snoc_gc, &qns_gem_noc_cnoc }, }; static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .voter_idx = 0, .keepalive = true, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", .voter_idx = 0, .enable_mask = 0x1, .num_nodes = 3, .nodes = { &qhm_gic, &xm_gic, &qns_gemnoc_gc }, }; static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", .voter_idx = 0, .num_nodes = 1, .nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", .voter_idx = 0, .num_nodes = 1, .nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", .voter_idx = 0, .num_nodes = 2, .nodes = { &qxm_lpass_dsp, &qnm_lpass_noc }, }; static struct qcom_icc_bcm bcm_sn7 = { .name = "SN7", .voter_idx = 0, .num_nodes = 1, .nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_bcm bcm_acv_disp = { .name = "ACV", .voter_idx = 1, .enable_mask = 0x1, .perf_mode_mask = 0x2, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mc0_disp = { .name = "MC0", .voter_idx = 1, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mm0_disp = { .name = "MM0", .voter_idx = 1, .num_nodes = 2, .nodes = { &qnm_mdp0_disp, &qns_mem_noc_hf_disp }, }; static struct qcom_icc_bcm bcm_sh0_disp = { .name = "SH0", .voter_idx = 1, .num_nodes = 1, .nodes = { &qns_llcc_disp }, }; static struct qcom_icc_bcm bcm_sh1_disp = { .name = "SH1", .voter_idx = 1, .enable_mask = 0x1, .num_nodes = 1, .nodes = { &qnm_pcie_disp }, }; static struct qcom_icc_bcm bcm_acv_disp2 = { .name = "ACV", .voter_idx = 2, .enable_mask = 0x1, .perf_mode_mask = 0x2, .num_nodes = 1, .nodes = { &ebi_disp2 }, }; static struct qcom_icc_bcm bcm_mc0_disp2 = { .name = "MC0", .voter_idx = 2, .num_nodes = 1, .nodes = { &ebi_disp2 }, }; static struct qcom_icc_bcm bcm_mm0_disp2 = { .name = "MM0", .voter_idx = 2, .num_nodes = 2, .nodes = { &qnm_mdp1_disp2, &qns_mem_noc_hf_disp2 }, }; static struct qcom_icc_bcm bcm_sh0_disp2 = { .name = "SH0", .voter_idx = 2, .num_nodes = 1, .nodes = { &qns_llcc_disp2 }, }; static struct qcom_icc_bcm bcm_sh1_disp2 = { .name = "SH1", .voter_idx = 2, .enable_mask = 0x1, .num_nodes = 1, .nodes = { &qnm_pcie_disp2 }, }; static struct qcom_icc_bcm *aggre1_noc_bcms[] = { }; static struct qcom_icc_node *aggre1_noc_nodes[] = { [MASTER_QUP_1] = &qhm_qup1, [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, [MASTER_UFS_MEM] = &xm_ufs_mem, [MASTER_USB3_0] = &xm_usb3_0, [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; static char *aggre1_noc_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_aggre1_noc = { .config = &icc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), .voters = aggre1_noc_voters, .num_voters = ARRAY_SIZE(aggre1_noc_voters), }; static struct qcom_icc_bcm *aggre2_noc_bcms[] = { &bcm_ce0, }; static struct qcom_icc_node *aggre2_noc_nodes[] = { [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QUP_0] = &qhm_qup0, [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, [MASTER_CRYPTO] = &qxm_crypto, [MASTER_IPA] = &qxm_ipa, [MASTER_SP] = &qxm_sp, [MASTER_QDSS_ETR] = &xm_qdss_etr_0, [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, [MASTER_SDCC_2] = &xm_sdc2, [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; static char *aggre2_noc_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_aggre2_noc = { .config = &icc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), .voters = aggre2_noc_voters, .num_voters = ARRAY_SIZE(aggre2_noc_voters), }; static struct qcom_icc_bcm *clk_virt_bcms[] = { &bcm_qup0, &bcm_qup1, }; static struct qcom_icc_node *clk_virt_nodes[] = { [MASTER_QUP_CORE_0] = &qup0_core_master, [MASTER_QUP_CORE_1] = &qup1_core_master, [SLAVE_QUP_CORE_0] = &qup0_core_slave, [SLAVE_QUP_CORE_1] = &qup1_core_slave, }; static char *clk_virt_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_clk_virt = { .config = &icc_regmap_config, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms), .voters = clk_virt_voters, .num_voters = ARRAY_SIZE(clk_virt_voters), }; static struct qcom_icc_bcm *config_noc_bcms[] = { &bcm_cn0, }; static struct qcom_icc_node *config_noc_nodes[] = { [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_QDSS_DAP] = &xm_qdss_dap, [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, [SLAVE_AOSS] = &qhs_aoss, [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, [SLAVE_CLK_CTL] = &qhs_clk_ctl, [SLAVE_CDSP_CFG] = &qhs_compute_cfg, [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, [SLAVE_CX_RDPM] = &qhs_cx_rdpm, [SLAVE_DISPLAY_CFG] = &qhs_display_0_cfg, [SLAVE_DISPLAY1_CFG] = &qhs_display_1_cfg, [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, [SLAVE_IMEM_CFG] = &qhs_imem_cfg, [SLAVE_IPA_CFG] = &qhs_ipa, [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, [SLAVE_LPASS] = &qhs_lpass_cfg, [SLAVE_MX_RDPM] = &qhs_mx_rdpm, [SLAVE_PDM] = &qhs_pdm, [SLAVE_PRNG] = &qhs_prng, [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, [SLAVE_QUP_0] = &qhs_qup0, [SLAVE_QUP_1] = &qhs_qup1, [SLAVE_SDCC_2] = &qhs_sdc2, [SLAVE_SPSS_CFG] = &qhs_spss_cfg, [SLAVE_TCSR] = &qhs_tcsr, [SLAVE_TLMM] = &qhs_tlmm, [SLAVE_TME_CFG] = &qhs_tme_cfg, [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, [SLAVE_USB3_0] = &qhs_usb3_0, [SLAVE_VENUS_CFG] = &qhs_venus_cfg, [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, [SLAVE_SNOC_CFG] = &qns_snoc_cfg, [SLAVE_IMEM] = &qxs_imem, [SLAVE_SERVICE_CNOC] = &srvc_cnoc, [SLAVE_QDSS_STM] = &xs_qdss_stm, [SLAVE_TCU] = &xs_sys_tcu_cfg, }; static char *config_noc_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_config_noc = { .config = &icc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, .num_bcms = ARRAY_SIZE(config_noc_bcms), .voters = config_noc_voters, .num_voters = ARRAY_SIZE(config_noc_voters), }; static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh0, &bcm_sh1, &bcm_sh0_disp, &bcm_sh1_disp, &bcm_sh0_disp2, &bcm_sh1_disp2, }; static struct qcom_icc_node *gem_noc_nodes[] = { [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, [MASTER_GFX3D] = &qnm_gpu, [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, [SLAVE_LLCC] = &qns_llcc, [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp, [SLAVE_LLCC_DISP] = &qns_llcc_disp, [MASTER_MNOC_HF_MEM_NOC_DISP2] = &qnm_mnoc_hf_disp2, [MASTER_ANOC_PCIE_GEM_NOC_DISP2] = &qnm_pcie_disp2, [SLAVE_LLCC_DISP2] = &qns_llcc_disp2, }; static char *gem_noc_voters[] = { "hlos", "disp0", "disp1" }; static struct qcom_icc_desc anorak_gem_noc = { .config = &icc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), .voters = gem_noc_voters, .num_voters = ARRAY_SIZE(gem_noc_voters), }; static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { &bcm_sn4, }; static struct qcom_icc_node *lpass_ag_noc_nodes[] = { [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, [MASTER_LPASS_PROC] = &qxm_lpass_dsp, [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, [SLAVE_LPASS_SNOC] = &qns_sysnoc, [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; static char *lpass_ag_noc_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_lpass_ag_noc = { .config = &icc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), .voters = lpass_ag_noc_voters, .num_voters = ARRAY_SIZE(lpass_ag_noc_voters), }; static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, &bcm_mc4, &bcm_acv_disp, &bcm_mc0_disp, &bcm_acv_disp2, &bcm_mc0_disp2, }; static struct qcom_icc_node *mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, [MASTER_LLCC_DISP] = &llcc_mc_disp, [SLAVE_EBI1_DISP] = &ebi_disp, [MASTER_DDR_RT] = &master_ddr_rt, [SLAVE_DDR_RT] = &slv_ddr_rt, [MASTER_LLCC_DISP2] = &llcc_mc_disp2, [SLAVE_EBI1_DISP2] = &ebi_disp2, }; static char *mc_virt_voters[] = { "hlos", "disp0", "disp1" }; static struct qcom_icc_desc anorak_mc_virt = { .config = &icc_regmap_config, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), .voters = mc_virt_voters, .num_voters = ARRAY_SIZE(mc_virt_voters), }; static struct qcom_icc_bcm *mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, &bcm_mm0_disp, &bcm_mm0_disp2, }; static struct qcom_icc_node *mmss_noc_nodes[] = { [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, [MASTER_MDP0] = &qnm_mdp0, [MASTER_MDP1] = &qnm_mdp1, [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, [MASTER_CDSP_HCP] = &qnm_vapss_hcp, [MASTER_VIDEO] = &qnm_video, [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, [MASTER_VIDEO_PROC] = &qnm_video_cvp, [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, [SLAVE_SERVICE_MNOC] = &srvc_mnoc, [MASTER_MDP0_DISP] = &qnm_mdp0_disp, [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, [MASTER_MDP1_DISP2] = &qnm_mdp1_disp2, [SLAVE_MNOC_HF_MEM_NOC_DISP2] = &qns_mem_noc_hf_disp2, }; static char *mmss_noc_voters[] = { "hlos", "disp0", "disp1" }; static struct qcom_icc_desc anorak_mmss_noc = { .config = &icc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), .voters = mmss_noc_voters, .num_voters = ARRAY_SIZE(mmss_noc_voters), }; static struct qcom_icc_bcm *nsp_noc_bcms[] = { &bcm_co0, }; static struct qcom_icc_node *nsp_noc_nodes[] = { [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, [MASTER_CDSP_PROC] = &qxm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; static char *nsp_noc_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_nsp_noc = { .config = &icc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, .num_bcms = ARRAY_SIZE(nsp_noc_bcms), .voters = nsp_noc_voters, .num_voters = ARRAY_SIZE(nsp_noc_voters), }; static struct qcom_icc_bcm *pcie_anoc_bcms[] = { &bcm_sn7, }; static struct qcom_icc_node *pcie_anoc_nodes[] = { [MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg, [MASTER_PCIE_0] = &xm_pcie3_0, [MASTER_PCIE_1] = &xm_pcie3_1, [MASTER_PCIE_4] = &xm_pcie4_0, [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, }; static char *pcie_anoc_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_pcie_anoc = { .config = &icc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), .voters = pcie_anoc_voters, .num_voters = ARRAY_SIZE(pcie_anoc_voters), }; static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn0, &bcm_sn1, &bcm_sn2, &bcm_sn3, &bcm_sn4, }; static struct qcom_icc_node *system_noc_nodes[] = { [MASTER_GIC_AHB] = &qhm_gic, [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, [MASTER_LPASS_ANOC] = &qnm_lpass_noc, [MASTER_SNOC_CFG] = &qnm_snoc_cfg, [MASTER_GIC] = &xm_gic, [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; static char *system_noc_voters[] = { "hlos", }; static struct qcom_icc_desc anorak_system_noc = { .config = &icc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, .num_bcms = ARRAY_SIZE(system_noc_bcms), .voters = system_noc_voters, .num_voters = ARRAY_SIZE(system_noc_voters), }; static int qnoc_probe(struct platform_device *pdev) { int ret; ret = qcom_icc_rpmh_probe(pdev); if (ret) dev_err(&pdev->dev, "failed to register ICC provider\n"); else dev_info(&pdev->dev, "Registered ANORAK ICC\n"); return ret; } static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,anorak-aggre1_noc", .data = &anorak_aggre1_noc }, { .compatible = "qcom,anorak-aggre2_noc", .data = &anorak_aggre2_noc }, { .compatible = "qcom,anorak-clk_virt", .data = &anorak_clk_virt }, { .compatible = "qcom,anorak-config_noc", .data = &anorak_config_noc }, { .compatible = "qcom,anorak-gem_noc", .data = &anorak_gem_noc }, { .compatible = "qcom,anorak-lpass_ag_noc", .data = &anorak_lpass_ag_noc }, { .compatible = "qcom,anorak-mc_virt", .data = &anorak_mc_virt }, { .compatible = "qcom,anorak-mmss_noc", .data = &anorak_mmss_noc }, { .compatible = "qcom,anorak-nsp_noc", .data = &anorak_nsp_noc }, { .compatible = "qcom,anorak-pcie_anoc", .data = &anorak_pcie_anoc }, { .compatible = "qcom,anorak-system_noc", .data = &anorak_system_noc }, { } }; MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qnoc_probe, .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-anorak", .of_match_table = qnoc_of_match, .sync_state = qcom_icc_rpmh_sync_state, }, }; static int __init qnoc_driver_init(void) { return platform_driver_register(&qnoc_driver); } core_initcall(qnoc_driver_init); MODULE_DESCRIPTION("Anorak NoC driver"); MODULE_LICENSE("GPL");