/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _SPI_Q2SPI_SLAVE_H_
#define _SPI_Q2SPI_SLAVE_H_

#define Q2SPI_SLAVE_BASE	0x42808000
#define Q2SPI_OFFSET_MASK	0x4
#define Q2SPI_HW_VERSION	0x00000000
#define Q2SPI_DRIVER_VERSION	0x00000004
#define Q2SPI_OP_MODE1		0x00000010
#define Q2SPI_OP_MODE2		0x00000014
#define Q2SPI_HRF_PUSH_ADDRESS	0x00000018
#define Q2SPI_CAP0		0x00000024
#define Q2SPI_CAP1		0x00000028
#define Q2SPI_SCRATCH0		0x00000030
#define Q2SPI_SCRATCH1		0x00000034
#define Q2SPI_SCRATCH2		0x00000038
#define Q2SPI_SCRATCH3		0x0000003C
#define Q2SPI_DB_STATUS		0x00000040
#define Q2SPI_ABORT_STATUS	0x00000044
#define Q2SPI_CLIENT_STATE	0x00000048
#define Q2SPI_RUNTIME_STATUS	0x0000004C
#define Q2SPI_TDB_FREE_SPACE	0x00000050
#define Q2SPI_SLAVE_ERROR	0x00000054
#define Q2SPI_HDR_ERROR		0x00000058
#define Q2SPI_ERROR_EN		0x0000005C
#define Q2SPI_SMA_DATA(n)	(0x00000070 + (0x4 * (n)))
#define Q2SPI_SMA_ADDR1		0x00000080
#define Q2SPI_SMA_ADDR2		0x00000084
#define Q2SPI_SMA_CTRL		0x00000088
#define Q2SPI_PURGE_COMPLETE	0x0000008C
#define Q2SPI_HOST_CFG		0x00000090
#define Q2SPI_SLAVE_END_ADDR	0x00000090
#endif /* _SPI_Q2SPI_SLAVE_H_ */