/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_VOLCANO_H #define __DT_BINDINGS_INTERCONNECT_QCOM_VOLCANO_H #define MASTER_GPU_TCU 0 #define MASTER_SYS_TCU 1 #define MASTER_APPSS_PROC 2 #define MASTER_LLCC 3 #define MASTER_QDSS_BAM 4 #define MASTER_QSPI_0 5 #define MASTER_QUP_0 6 #define MASTER_QUP_1 7 #define MASTER_A1NOC_SNOC 8 #define MASTER_A2NOC_SNOC 9 #define MASTER_APSS_NOC 10 #define MASTER_CAMNOC_HF 11 #define MASTER_CAMNOC_ICP 12 #define MASTER_CAMNOC_SF 13 #define MASTER_CNOC_SNOC 14 #define MASTER_GEM_NOC_CNOC 15 #define MASTER_GEM_NOC_PCIE_SNOC 16 #define MASTER_GFX3D 17 #define MASTER_LPASS_GEM_NOC 18 #define MASTER_MDP 19 #define MASTER_MSS_PROC 20 #define MASTER_MNOC_HF_MEM_NOC 21 #define MASTER_MNOC_SF_MEM_NOC 22 #define MASTER_COMPUTE_NOC 23 #define MASTER_ANOC_PCIE_GEM_NOC 24 #define MASTER_SNOC_GC_MEM_NOC 25 #define MASTER_SNOC_SF_MEM_NOC 26 #define MASTER_VIDEO 27 #define MASTER_CNOC_CFG 28 #define MASTER_CNOC_MNOC_HF_CFG 29 #define MASTER_PCIE_ANOC_CFG 30 #define MASTER_CNOC_MNOC_SF_CFG 31 #define MASTER_QUP_CORE_0 32 #define MASTER_QUP_CORE_1 33 #define MASTER_CRYPTO 34 #define MASTER_IPA 35 #define MASTER_LPASS_PROC 36 #define MASTER_CDSP_PROC 37 #define MASTER_PIMEM 38 #define MASTER_WLAN_Q6 39 #define MASTER_GIC 40 #define MASTER_PCIE_0 41 #define MASTER_PCIE_1 42 #define MASTER_QDSS_ETR 43 #define MASTER_QDSS_ETR_1 44 #define MASTER_SDCC_1 45 #define MASTER_SDCC_2 46 #define MASTER_UFS_MEM 47 #define MASTER_USB3_0 48 #define SLAVE_EBI1 512 #define SLAVE_AHB2PHY_SOUTH 513 #define SLAVE_AHB2PHY_NORTH 514 #define SLAVE_AOSS 515 #define SLAVE_CAMERA_CFG 516 #define SLAVE_CLK_CTL 517 #define SLAVE_RBCPR_CX_CFG 518 #define SLAVE_RBCPR_MXA_CFG 519 #define SLAVE_CRYPTO_0_CFG 520 #define SLAVE_CX_RDPM 521 #define SLAVE_DISPLAY_CFG 522 #define SLAVE_GFX3D_CFG 523 #define SLAVE_IMEM_CFG 524 #define SLAVE_IPA_CFG 525 #define SLAVE_IPC_ROUTER_CFG 526 #define SLAVE_CNOC_MSS 527 #define SLAVE_MX_2_RDPM 528 #define SLAVE_MX_RDPM 529 #define SLAVE_PCIE_0_CFG 530 #define SLAVE_PCIE_1_CFG 531 #define SLAVE_PDM 532 #define SLAVE_PRNG 533 #define SLAVE_QDSS_CFG 534 #define SLAVE_QSPI_0 535 #define SLAVE_QUP_0 536 #define SLAVE_QUP_1 537 #define SLAVE_SDC1 538 #define SLAVE_SDCC_2 539 #define SLAVE_TCSR 540 #define SLAVE_TLMM 541 #define SLAVE_TME_CFG 542 #define SLAVE_UFS_MEM_CFG 543 #define SLAVE_USB3_0 544 #define SLAVE_VENUS_CFG 545 #define SLAVE_VSENSE_CTRL_CFG 546 #define SLAVE_WLAN 547 #define SLAVE_A1NOC_SNOC 548 #define SLAVE_A2NOC_SNOC 549 #define SLAVE_GEM_NOC_CNOC 550 #define SLAVE_SNOC_GEM_NOC_GC 551 #define SLAVE_SNOC_GEM_NOC_SF 552 #define SLAVE_LLCC 553 #define SLAVE_LPASS_GEM_NOC 554 #define SLAVE_MNOC_HF_MEM_NOC 555 #define SLAVE_MNOC_SF_MEM_NOC 556 #define SLAVE_CDSP_MEM_NOC 557 #define SLAVE_MEM_NOC_PCIE_SNOC 558 #define SLAVE_ANOC_PCIE_GEM_NOC 559 #define SLAVE_APPSS 560 #define SLAVE_CNOC_CFG 561 #define SLAVE_DDRSS_CFG 562 #define SLAVE_CNOC_MNOC_HF_CFG 563 #define SLAVE_CNOC_MNOC_SF_CFG 564 #define SLAVE_NSP_QTB_CFG 565 #define SLAVE_PCIE_ANOC_CFG 566 #define SLAVE_WLAN_Q6_THROTTLE_CFG 567 #define SLAVE_QUP_CORE_0 568 #define SLAVE_QUP_CORE_1 569 #define SLAVE_IMEM 570 #define SLAVE_PIMEM 571 #define SLAVE_SERVICE_CNOC_CFG 572 #define SLAVE_SERVICE_CNOC 573 #define SLAVE_SERVICE_MNOC_HF 574 #define SLAVE_SERVICE_MNOC_SF 575 #define SLAVE_SERVICE_PCIE_ANOC 576 #define SLAVE_PCIE_0 577 #define SLAVE_PCIE_1 578 #define SLAVE_QDSS_STM 579 #define SLAVE_TCU 580 #define MASTER_LLCC_DISP 1000 #define MASTER_MDP_DISP 1001 #define MASTER_MNOC_HF_MEM_NOC_DISP 1002 #define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003 #define SLAVE_EBI1_DISP 1512 #define SLAVE_LLCC_DISP 1513 #define SLAVE_MNOC_HF_MEM_NOC_DISP 1514 #endif