/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H

#ifndef PM8550VS_C_SID
#define PM8550VS_C_SID		2
#endif

#ifndef PM8550VS_D_SID
#define PM8550VS_D_SID		3
#endif

#ifndef PM8550VS_E_SID
#define PM8550VS_E_SID		4
#endif

#ifndef PM8550VS_G_SID
#define PM8550VS_G_SID		6
#endif

#ifndef PM8550VE_SID
#define PM8550VE_SID		5
#endif

#ifndef PM8550VE_D_SID
#define PM8550VE_D_SID		3
#endif

/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
#define PM8550VS_C_ADC5_GEN3_OFFSET_REF			(PM8550VS_C_SID << 8 | 0x00)
#define PM8550VS_C_ADC5_GEN3_1P25VREF			(PM8550VS_C_SID << 8 | 0x01)
#define PM8550VS_C_ADC5_GEN3_VREF_VADC			(PM8550VS_C_SID << 8 | 0X02)
#define PM8550VS_C_ADC5_GEN3_DIE_TEMP			(PM8550VS_C_SID << 8 | 0x03)

#define PM8550VS_D_ADC5_GEN3_OFFSET_REF			(PM8550VS_D_SID << 8 | 0x00)
#define PM8550VS_D_ADC5_GEN3_1P25VREF			(PM8550VS_D_SID << 8 | 0x01)
#define PM8550VS_D_ADC5_GEN3_VREF_VADC			(PM8550VS_D_SID << 8 | 0X02)
#define PM8550VS_D_ADC5_GEN3_DIE_TEMP			(PM8550VS_D_SID << 8 | 0x03)

#define PM8550VS_E_ADC5_GEN3_OFFSET_REF			(PM8550VS_E_SID << 8 | 0x00)
#define PM8550VS_E_ADC5_GEN3_1P25VREF			(PM8550VS_E_SID << 8 | 0x01)
#define PM8550VS_E_ADC5_GEN3_VREF_VADC			(PM8550VS_E_SID << 8 | 0X02)
#define PM8550VS_E_ADC5_GEN3_DIE_TEMP			(PM8550VS_E_SID << 8 | 0x03)

#define PM8550VS_G_ADC5_GEN3_OFFSET_REF			(PM8550VS_G_SID << 8 | 0x00)
#define PM8550VS_G_ADC5_GEN3_1P25VREF			(PM8550VS_G_SID << 8 | 0x01)
#define PM8550VS_G_ADC5_GEN3_VREF_VADC			(PM8550VS_G_SID << 8 | 0X02)
#define PM8550VS_G_ADC5_GEN3_DIE_TEMP			(PM8550VS_G_SID << 8 | 0x03)

#define PM8550VE_ADC5_GEN3_OFFSET_REF			(PM8550VE_SID << 8 | 0x00)
#define PM8550VE_ADC5_GEN3_1P25VREF			(PM8550VE_SID << 8 | 0x01)
#define PM8550VE_ADC5_GEN3_VREF_VADC			(PM8550VE_SID << 8 | 0X02)
#define PM8550VE_ADC5_GEN3_DIE_TEMP			(PM8550VE_SID << 8 | 0x03)

#define PM8550VE_D_ADC5_GEN3_OFFSET_REF			(PM8550VE_D_SID << 8 | 0x00)
#define PM8550VE_D_ADC5_GEN3_1P25VREF			(PM8550VE_D_SID << 8 | 0x01)
#define PM8550VE_D_ADC5_GEN3_VREF_VADC			(PM8550VE_D_SID << 8 | 0X02)
#define PM8550VE_D_ADC5_GEN3_DIE_TEMP			(PM8550VE_D_SID << 8 | 0x03)

#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */