power.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/of.h>
  9. #include <linux/pinctrl/consumer.h>
  10. #include <linux/regulator/consumer.h>
  11. #include <soc/qcom/cmd-db.h>
  12. #include "main.h"
  13. #include "qmi.h"
  14. #include "debug.h"
  15. #include "power.h"
  16. #if IS_ENABLED(CONFIG_MSM_QMP)
  17. #include <linux/soc/qcom/qcom_aoss.h>
  18. #endif
  19. static struct icnss_vreg_cfg icnss_wcn6750_vreg_list[] = {
  20. {"vdd-cx-mx", 824000, 952000, 0, 0, 0, false, true},
  21. {"vdd-1.8-xo", 1872000, 1872000, 0, 0, 0, false, true},
  22. {"vdd-1.3-rfa", 1256000, 1352000, 0, 0, 0, false, true},
  23. {"vdd-ipa-2p2", 2200000, 2200000, 0, 0, 0, false, true},
  24. };
  25. static struct icnss_vreg_cfg icnss_adrestea_vreg_list[] = {
  26. {"vdd-cx-mx", 752000, 752000, 0, 0, 0, false, true},
  27. {"vdd-1.8-xo", 1800000, 1800000, 0, 0, 0, false, true},
  28. {"vdd-1.3-rfa", 1304000, 1304000, 0, 0, 0, false, true},
  29. {"vdd-3.3-ch1", 3312000, 3312000, 0, 0, 0, false, false},
  30. {"vdd-3.3-ch0", 3312000, 3312000, 0, 0, 0, false, true},
  31. };
  32. static struct icnss_battery_level icnss_battery_level[] = {
  33. {70, 3300000},
  34. {60, 3200000},
  35. {50, 3100000},
  36. {25, 3000000},
  37. {0, 2850000},
  38. };
  39. static struct icnss_vreg_cfg icnss_wcn6450_vreg_list[] = {
  40. {"vdd-cx-mx", 824000, 952000, 0, 0, 0, false, true},
  41. {"vdd-1.8-xo", 1872000, 1872000, 0, 0, 0, false, true},
  42. {"vdd-1.3-rfa", 1256000, 1352000, 0, 0, 0, false, true},
  43. {"vdd-aon", 1256000, 1352000, 0, 0, 0, false, true},
  44. };
  45. static struct icnss_clk_cfg icnss_clk_list[] = {
  46. {"rf_clk", 0, 0},
  47. };
  48. static struct icnss_clk_cfg icnss_adrestea_clk_list[] = {
  49. {"cxo_ref_clk_pin", 0, 0},
  50. };
  51. #define ICNSS_VREG_LIST_SIZE ARRAY_SIZE(icnss_wcn6750_vreg_list)
  52. #define ICNSS_VREG_ADRESTEA_LIST_SIZE ARRAY_SIZE(icnss_adrestea_vreg_list)
  53. #define ICNSS_VREG_EVROS_LIST_SIZE ARRAY_SIZE(icnss_wcn6450_vreg_list)
  54. #define ICNSS_CLK_LIST_SIZE ARRAY_SIZE(icnss_clk_list)
  55. #define ICNSS_CLK_ADRESTEA_LIST_SIZE ARRAY_SIZE(icnss_adrestea_clk_list)
  56. #define ICNSS_CHAIN1_REGULATOR "vdd-3.3-ch1"
  57. #define MAX_PROP_SIZE 32
  58. #define BT_CXMX_VOLTAGE_MV 950
  59. #define ICNSS_MBOX_MSG_MAX_LEN 64
  60. #define ICNSS_MBOX_TIMEOUT_MS 1000
  61. #define ICNSS_BATTERY_LEVEL_COUNT ARRAY_SIZE(icnss_battery_level)
  62. #define ICNSS_MAX_BATTERY_LEVEL 100
  63. /**
  64. * enum icnss_vreg_param: Voltage regulator TCS param
  65. * @ICNSS_VREG_VOLTAGE: Provides voltage level to be configured in TCS
  66. * @ICNSS_VREG_MODE: Regulator mode
  67. * @ICNSS_VREG_ENABLE: Set Voltage regulator enable config in TCS
  68. */
  69. enum icnss_vreg_param {
  70. ICNSS_VREG_VOLTAGE,
  71. ICNSS_VREG_MODE,
  72. ICNSS_VREG_ENABLE,
  73. };
  74. /**
  75. * enum icnss_tcs_seq: TCS sequence ID for trigger
  76. * ICNSS_TCS_UP_SEQ: TCS Sequence based on up trigger / Wake TCS
  77. * ICNSS_TCS_DOWN_SEQ: TCS Sequence based on down trigger / Sleep TCS
  78. * ICNSS_TCS_ALL_SEQ: Update for both up and down triggers
  79. */
  80. enum icnss_tcs_seq {
  81. ICNSS_TCS_UP_SEQ,
  82. ICNSS_TCS_DOWN_SEQ,
  83. ICNSS_TCS_ALL_SEQ,
  84. };
  85. static int icnss_get_vreg_single(struct icnss_priv *priv,
  86. struct icnss_vreg_info *vreg)
  87. {
  88. int ret = 0;
  89. struct device *dev = NULL;
  90. struct regulator *reg = NULL;
  91. const __be32 *prop = NULL;
  92. char prop_name[MAX_PROP_SIZE] = {0};
  93. int len = 0;
  94. int i;
  95. dev = &priv->pdev->dev;
  96. reg = devm_regulator_get_optional(dev, vreg->cfg.name);
  97. if (IS_ERR(reg)) {
  98. ret = PTR_ERR(reg);
  99. if (ret == -ENODEV) {
  100. return ret;
  101. } else if (ret == -EPROBE_DEFER) {
  102. icnss_pr_info("EPROBE_DEFER for regulator: %s\n",
  103. vreg->cfg.name);
  104. goto out;
  105. } else if (priv->device_id == ADRASTEA_DEVICE_ID) {
  106. if (vreg->cfg.required) {
  107. icnss_pr_err("Regulator %s doesn't exist: %d\n",
  108. vreg->cfg.name, ret);
  109. goto out;
  110. } else {
  111. icnss_pr_dbg("Optional regulator %s doesn't exist: %d\n",
  112. vreg->cfg.name, ret);
  113. goto done;
  114. }
  115. } else {
  116. icnss_pr_err("Failed to get regulator %s, err = %d\n",
  117. vreg->cfg.name, ret);
  118. goto out;
  119. }
  120. }
  121. vreg->reg = reg;
  122. snprintf(prop_name, MAX_PROP_SIZE, "qcom,%s-config",
  123. vreg->cfg.name);
  124. prop = of_get_property(dev->of_node, prop_name, &len);
  125. icnss_pr_dbg("Got regulator config, prop: %s, len: %d\n",
  126. prop_name, len);
  127. if (!prop || len < (2 * sizeof(__be32))) {
  128. icnss_pr_dbg("Property %s %s, use default\n", prop_name,
  129. prop ? "invalid format" : "doesn't exist");
  130. goto done;
  131. }
  132. for (i = 0; (i * sizeof(__be32)) < len; i++) {
  133. switch (i) {
  134. case 0:
  135. vreg->cfg.min_uv = be32_to_cpup(&prop[0]);
  136. break;
  137. case 1:
  138. vreg->cfg.max_uv = be32_to_cpup(&prop[1]);
  139. break;
  140. case 2:
  141. vreg->cfg.load_ua = be32_to_cpup(&prop[2]);
  142. break;
  143. case 3:
  144. vreg->cfg.delay_us = be32_to_cpup(&prop[3]);
  145. break;
  146. case 4:
  147. if (priv->device_id == WCN6750_DEVICE_ID)
  148. vreg->cfg.need_unvote = be32_to_cpup(&prop[4]);
  149. else
  150. vreg->cfg.need_unvote = 0;
  151. break;
  152. default:
  153. icnss_pr_dbg("Property %s, ignoring value at %d\n",
  154. prop_name, i);
  155. break;
  156. }
  157. }
  158. done:
  159. icnss_pr_dbg("Got regulator: %s, min_uv: %u, max_uv: %u, load_ua: %u, delay_us: %u, need_unvote: %u\n",
  160. vreg->cfg.name, vreg->cfg.min_uv,
  161. vreg->cfg.max_uv, vreg->cfg.load_ua,
  162. vreg->cfg.delay_us, vreg->cfg.need_unvote);
  163. return 0;
  164. out:
  165. return ret;
  166. }
  167. static int icnss_vreg_on_single(struct icnss_vreg_info *vreg)
  168. {
  169. int ret = 0;
  170. if (vreg->enabled) {
  171. icnss_pr_dbg("Regulator %s is already enabled\n",
  172. vreg->cfg.name);
  173. return 0;
  174. }
  175. icnss_pr_dbg("Regulator %s is being enabled\n", vreg->cfg.name);
  176. if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
  177. ret = regulator_set_voltage(vreg->reg,
  178. vreg->cfg.min_uv,
  179. vreg->cfg.max_uv);
  180. if (ret) {
  181. icnss_pr_err("Failed to set voltage for regulator %s, min_uv: %u, max_uv: %u, err = %d\n",
  182. vreg->cfg.name, vreg->cfg.min_uv,
  183. vreg->cfg.max_uv, ret);
  184. goto out;
  185. }
  186. }
  187. if (vreg->cfg.load_ua) {
  188. ret = regulator_set_load(vreg->reg,
  189. vreg->cfg.load_ua);
  190. if (ret < 0) {
  191. icnss_pr_err("Failed to set load for regulator %s, load: %u, err = %d\n",
  192. vreg->cfg.name, vreg->cfg.load_ua,
  193. ret);
  194. goto out;
  195. }
  196. }
  197. if (vreg->cfg.delay_us)
  198. udelay(vreg->cfg.delay_us);
  199. ret = regulator_enable(vreg->reg);
  200. if (ret) {
  201. icnss_pr_err("Failed to enable regulator %s, err = %d\n",
  202. vreg->cfg.name, ret);
  203. goto out;
  204. }
  205. vreg->enabled = true;
  206. out:
  207. return ret;
  208. }
  209. static int icnss_vreg_unvote_single(struct icnss_vreg_info *vreg)
  210. {
  211. int ret = 0;
  212. if (!vreg->enabled) {
  213. icnss_pr_dbg("Regulator %s is already disabled\n",
  214. vreg->cfg.name);
  215. return 0;
  216. }
  217. icnss_pr_dbg("Removing vote for Regulator %s\n", vreg->cfg.name);
  218. if (vreg->cfg.load_ua) {
  219. ret = regulator_set_load(vreg->reg, 0);
  220. if (ret < 0)
  221. icnss_pr_err("Failed to set load for regulator %s, err = %d\n",
  222. vreg->cfg.name, ret);
  223. }
  224. if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
  225. ret = regulator_set_voltage(vreg->reg, 0,
  226. vreg->cfg.max_uv);
  227. if (ret)
  228. icnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
  229. vreg->cfg.name, ret);
  230. }
  231. return ret;
  232. }
  233. static int icnss_vreg_off_single(struct icnss_vreg_info *vreg)
  234. {
  235. int ret = 0;
  236. if (!vreg->enabled) {
  237. icnss_pr_dbg("Regulator %s is already disabled\n",
  238. vreg->cfg.name);
  239. return 0;
  240. }
  241. icnss_pr_dbg("Regulator %s is being disabled\n",
  242. vreg->cfg.name);
  243. ret = regulator_disable(vreg->reg);
  244. if (ret)
  245. icnss_pr_err("Failed to disable regulator %s, err = %d\n",
  246. vreg->cfg.name, ret);
  247. if (vreg->cfg.load_ua) {
  248. ret = regulator_set_load(vreg->reg, 0);
  249. if (ret < 0)
  250. icnss_pr_err("Failed to set load for regulator %s, err = %d\n",
  251. vreg->cfg.name, ret);
  252. }
  253. if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
  254. ret = regulator_set_voltage(vreg->reg, 0,
  255. vreg->cfg.max_uv);
  256. if (ret)
  257. icnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
  258. vreg->cfg.name, ret);
  259. }
  260. vreg->enabled = false;
  261. return ret;
  262. }
  263. static struct icnss_vreg_cfg *get_vreg_list(u32 *vreg_list_size,
  264. unsigned long device_id)
  265. {
  266. switch (device_id) {
  267. case WCN6750_DEVICE_ID:
  268. *vreg_list_size = ICNSS_VREG_LIST_SIZE;
  269. return icnss_wcn6750_vreg_list;
  270. case ADRASTEA_DEVICE_ID:
  271. *vreg_list_size = ICNSS_VREG_ADRESTEA_LIST_SIZE;
  272. return icnss_adrestea_vreg_list;
  273. case WCN6450_DEVICE_ID:
  274. *vreg_list_size = ICNSS_VREG_EVROS_LIST_SIZE;
  275. return icnss_wcn6450_vreg_list;
  276. default:
  277. icnss_pr_err("Unsupported device_id 0x%x\n", device_id);
  278. *vreg_list_size = 0;
  279. return NULL;
  280. }
  281. }
  282. int icnss_get_vreg(struct icnss_priv *priv)
  283. {
  284. int ret = 0;
  285. int i;
  286. struct icnss_vreg_info *vreg;
  287. struct icnss_vreg_cfg *vreg_cfg = NULL;
  288. struct list_head *vreg_list = &priv->vreg_list;
  289. struct device *dev = &priv->pdev->dev;
  290. u32 vreg_list_size = 0;
  291. vreg_cfg = get_vreg_list(&vreg_list_size, priv->device_id);
  292. if (!vreg_cfg)
  293. return -EINVAL;
  294. for (i = 0; i < vreg_list_size; i++) {
  295. vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
  296. if (!vreg)
  297. return -ENOMEM;
  298. memcpy(&vreg->cfg, &vreg_cfg[i], sizeof(vreg->cfg));
  299. ret = icnss_get_vreg_single(priv, vreg);
  300. if (ret != 0) {
  301. if (ret == -ENODEV)
  302. continue;
  303. else
  304. return ret;
  305. }
  306. list_add_tail(&vreg->list, vreg_list);
  307. }
  308. return 0;
  309. }
  310. void icnss_put_vreg(struct icnss_priv *priv)
  311. {
  312. struct list_head *vreg_list = &priv->vreg_list;
  313. struct icnss_vreg_info *vreg = NULL;
  314. while (!list_empty(vreg_list)) {
  315. vreg = list_first_entry(vreg_list,
  316. struct icnss_vreg_info, list);
  317. list_del(&vreg->list);
  318. }
  319. }
  320. static int icnss_vreg_on(struct icnss_priv *priv)
  321. {
  322. struct list_head *vreg_list = &priv->vreg_list;
  323. struct icnss_vreg_info *vreg = NULL;
  324. int ret = 0;
  325. list_for_each_entry(vreg, vreg_list, list) {
  326. if (IS_ERR_OR_NULL(vreg->reg) || !vreg->cfg.is_supported)
  327. continue;
  328. ret = icnss_vreg_on_single(vreg);
  329. if (ret)
  330. break;
  331. }
  332. if (!ret)
  333. return 0;
  334. list_for_each_entry_continue_reverse(vreg, vreg_list, list) {
  335. if (IS_ERR_OR_NULL(vreg->reg) || !vreg->enabled)
  336. continue;
  337. icnss_vreg_off_single(vreg);
  338. }
  339. return ret;
  340. }
  341. static int icnss_vreg_off(struct icnss_priv *priv)
  342. {
  343. struct list_head *vreg_list = &priv->vreg_list;
  344. struct icnss_vreg_info *vreg = NULL;
  345. list_for_each_entry_reverse(vreg, vreg_list, list) {
  346. if (IS_ERR_OR_NULL(vreg->reg))
  347. continue;
  348. icnss_vreg_off_single(vreg);
  349. }
  350. return 0;
  351. }
  352. int icnss_vreg_unvote(struct icnss_priv *priv)
  353. {
  354. struct list_head *vreg_list = &priv->vreg_list;
  355. struct icnss_vreg_info *vreg = NULL;
  356. list_for_each_entry_reverse(vreg, vreg_list, list) {
  357. if (IS_ERR_OR_NULL(vreg->reg))
  358. continue;
  359. if (vreg->cfg.need_unvote)
  360. icnss_vreg_unvote_single(vreg);
  361. }
  362. return 0;
  363. }
  364. static int icnss_get_clk_single(struct icnss_priv *priv,
  365. struct icnss_clk_info *clk_info)
  366. {
  367. struct device *dev = &priv->pdev->dev;
  368. struct clk *clk;
  369. int ret;
  370. clk = devm_clk_get(dev, clk_info->cfg.name);
  371. if (IS_ERR(clk)) {
  372. ret = PTR_ERR(clk);
  373. if (clk_info->cfg.required)
  374. icnss_pr_err("Failed to get clock %s, err = %d\n",
  375. clk_info->cfg.name, ret);
  376. else
  377. icnss_pr_dbg("Failed to get optional clock %s, err = %d\n",
  378. clk_info->cfg.name, ret);
  379. return ret;
  380. }
  381. clk_info->clk = clk;
  382. icnss_pr_dbg("Got clock: %s, freq: %u\n",
  383. clk_info->cfg.name, clk_info->cfg.freq);
  384. return 0;
  385. }
  386. static int icnss_clk_on_single(struct icnss_clk_info *clk_info)
  387. {
  388. int ret;
  389. if (clk_info->enabled) {
  390. icnss_pr_dbg("Clock %s is already enabled\n",
  391. clk_info->cfg.name);
  392. return 0;
  393. }
  394. icnss_pr_dbg("Clock %s is being enabled\n", clk_info->cfg.name);
  395. if (clk_info->cfg.freq) {
  396. ret = clk_set_rate(clk_info->clk, clk_info->cfg.freq);
  397. if (ret) {
  398. icnss_pr_err("Failed to set frequency %u for clock %s, err = %d\n",
  399. clk_info->cfg.freq, clk_info->cfg.name,
  400. ret);
  401. return ret;
  402. }
  403. }
  404. ret = clk_prepare_enable(clk_info->clk);
  405. if (ret) {
  406. icnss_pr_err("Failed to enable clock %s, err = %d\n",
  407. clk_info->cfg.name, ret);
  408. return ret;
  409. }
  410. clk_info->enabled = true;
  411. return 0;
  412. }
  413. static int icnss_clk_off_single(struct icnss_clk_info *clk_info)
  414. {
  415. if (!clk_info->enabled) {
  416. icnss_pr_dbg("Clock %s is already disabled\n",
  417. clk_info->cfg.name);
  418. return 0;
  419. }
  420. icnss_pr_dbg("Clock %s is being disabled\n", clk_info->cfg.name);
  421. clk_disable_unprepare(clk_info->clk);
  422. clk_info->enabled = false;
  423. return 0;
  424. }
  425. int icnss_get_clk(struct icnss_priv *priv)
  426. {
  427. struct device *dev;
  428. struct list_head *clk_list;
  429. struct icnss_clk_info *clk_info;
  430. struct icnss_clk_cfg *clk_cfg;
  431. int ret, i;
  432. u32 clk_list_size = 0;
  433. if (!priv)
  434. return -ENODEV;
  435. dev = &priv->pdev->dev;
  436. clk_list = &priv->clk_list;
  437. if (priv->device_id == ADRASTEA_DEVICE_ID) {
  438. clk_cfg = icnss_adrestea_clk_list;
  439. clk_list_size = ICNSS_CLK_ADRESTEA_LIST_SIZE;
  440. } else if (priv->device_id == WCN6750_DEVICE_ID ||
  441. priv->device_id == WCN6450_DEVICE_ID) {
  442. clk_cfg = icnss_clk_list;
  443. clk_list_size = ICNSS_CLK_LIST_SIZE;
  444. }
  445. if (!list_empty(clk_list)) {
  446. icnss_pr_dbg("Clocks have already been updated\n");
  447. return 0;
  448. }
  449. for (i = 0; i < clk_list_size; i++) {
  450. clk_info = devm_kzalloc(dev, sizeof(*clk_info), GFP_KERNEL);
  451. if (!clk_info) {
  452. ret = -ENOMEM;
  453. goto cleanup;
  454. }
  455. memcpy(&clk_info->cfg, &clk_cfg[i],
  456. sizeof(clk_info->cfg));
  457. ret = icnss_get_clk_single(priv, clk_info);
  458. if (ret != 0) {
  459. if (clk_info->cfg.required)
  460. goto cleanup;
  461. else
  462. continue;
  463. }
  464. list_add_tail(&clk_info->list, clk_list);
  465. }
  466. return 0;
  467. cleanup:
  468. while (!list_empty(clk_list)) {
  469. clk_info = list_first_entry(clk_list, struct icnss_clk_info,
  470. list);
  471. list_del(&clk_info->list);
  472. }
  473. return ret;
  474. }
  475. void icnss_put_clk(struct icnss_priv *priv)
  476. {
  477. struct device *dev;
  478. struct list_head *clk_list;
  479. struct icnss_clk_info *clk_info;
  480. if (!priv)
  481. return;
  482. dev = &priv->pdev->dev;
  483. clk_list = &priv->clk_list;
  484. while (!list_empty(clk_list)) {
  485. clk_info = list_first_entry(clk_list, struct icnss_clk_info,
  486. list);
  487. list_del(&clk_info->list);
  488. }
  489. }
  490. static int icnss_clk_on(struct list_head *clk_list)
  491. {
  492. struct icnss_clk_info *clk_info;
  493. int ret = 0;
  494. list_for_each_entry(clk_info, clk_list, list) {
  495. if (IS_ERR_OR_NULL(clk_info->clk))
  496. continue;
  497. ret = icnss_clk_on_single(clk_info);
  498. if (ret)
  499. break;
  500. }
  501. if (!ret)
  502. return 0;
  503. list_for_each_entry_continue_reverse(clk_info, clk_list, list) {
  504. if (IS_ERR_OR_NULL(clk_info->clk))
  505. continue;
  506. icnss_clk_off_single(clk_info);
  507. }
  508. return ret;
  509. }
  510. static int icnss_clk_off(struct list_head *clk_list)
  511. {
  512. struct icnss_clk_info *clk_info;
  513. list_for_each_entry_reverse(clk_info, clk_list, list) {
  514. if (IS_ERR_OR_NULL(clk_info->clk))
  515. continue;
  516. icnss_clk_off_single(clk_info);
  517. }
  518. return 0;
  519. }
  520. int icnss_hw_power_on(struct icnss_priv *priv)
  521. {
  522. int ret = 0;
  523. icnss_pr_dbg("HW Power on: state: 0x%lx\n", priv->state);
  524. spin_lock(&priv->on_off_lock);
  525. if (test_bit(ICNSS_POWER_ON, &priv->state)) {
  526. spin_unlock(&priv->on_off_lock);
  527. return ret;
  528. }
  529. set_bit(ICNSS_POWER_ON, &priv->state);
  530. spin_unlock(&priv->on_off_lock);
  531. ret = icnss_vreg_on(priv);
  532. if (ret) {
  533. icnss_pr_err("Failed to turn on vreg, err = %d\n", ret);
  534. goto out;
  535. }
  536. ret = icnss_clk_on(&priv->clk_list);
  537. if (ret)
  538. goto vreg_off;
  539. return ret;
  540. vreg_off:
  541. icnss_vreg_off(priv);
  542. out:
  543. clear_bit(ICNSS_POWER_ON, &priv->state);
  544. return ret;
  545. }
  546. int icnss_hw_power_off(struct icnss_priv *priv)
  547. {
  548. int ret = 0;
  549. if (test_bit(HW_ALWAYS_ON, &priv->ctrl_params.quirks))
  550. return 0;
  551. if (test_bit(ICNSS_FW_DOWN, &priv->state))
  552. return 0;
  553. icnss_pr_dbg("HW Power off: 0x%lx\n", priv->state);
  554. spin_lock(&priv->on_off_lock);
  555. if (!test_bit(ICNSS_POWER_ON, &priv->state)) {
  556. spin_unlock(&priv->on_off_lock);
  557. return ret;
  558. }
  559. clear_bit(ICNSS_POWER_ON, &priv->state);
  560. spin_unlock(&priv->on_off_lock);
  561. icnss_clk_off(&priv->clk_list);
  562. ret = icnss_vreg_off(priv);
  563. return ret;
  564. }
  565. int icnss_power_on(struct device *dev)
  566. {
  567. struct icnss_priv *priv = dev_get_drvdata(dev);
  568. if (!priv) {
  569. icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
  570. dev, priv);
  571. return -EINVAL;
  572. }
  573. icnss_pr_dbg("Power On: 0x%lx\n", priv->state);
  574. return icnss_hw_power_on(priv);
  575. }
  576. EXPORT_SYMBOL(icnss_power_on);
  577. int icnss_power_off(struct device *dev)
  578. {
  579. struct icnss_priv *priv = dev_get_drvdata(dev);
  580. if (!priv) {
  581. icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
  582. dev, priv);
  583. return -EINVAL;
  584. }
  585. icnss_pr_dbg("Power Off: 0x%lx\n", priv->state);
  586. return icnss_hw_power_off(priv);
  587. }
  588. EXPORT_SYMBOL(icnss_power_off);
  589. int icnss_power_on_chain1_reg(struct icnss_priv *priv)
  590. {
  591. struct list_head *vreg_list = &priv->vreg_list;
  592. struct icnss_vreg_info *vreg = NULL;
  593. int ret = 0;
  594. list_for_each_entry(vreg, vreg_list, list) {
  595. if (!strcmp(ICNSS_CHAIN1_REGULATOR, vreg->cfg.name) && priv->is_chain1_supported) {
  596. vreg->cfg.is_supported = true;
  597. ret = icnss_vreg_on_single(vreg);
  598. break;
  599. }
  600. }
  601. /* Setting chain1 supported to false as chain1 regulator cfg already updated */
  602. priv->is_chain1_supported = false;
  603. return ret;
  604. }
  605. void icnss_put_resources(struct icnss_priv *priv)
  606. {
  607. icnss_put_clk(priv);
  608. icnss_put_vreg(priv);
  609. }
  610. #if IS_ENABLED(CONFIG_MSM_QMP)
  611. /**
  612. * icnss_aop_interface_init: Initialize AOP interface: either mbox channel or direct QMP
  613. * @priv: Pointer to icnss platform data
  614. *
  615. * Device tree file should have either mbox or qmp configured, but not both.
  616. * Based on device tree configuration setup mbox channel or QMP
  617. *
  618. * Return: 0 for success, otherwise error code
  619. */
  620. int icnss_aop_interface_init(struct icnss_priv *priv)
  621. {
  622. struct mbox_client *mbox = &priv->mbox_client_data;
  623. struct mbox_chan *chan;
  624. int ret = 0, ol_cpr = 0;
  625. ol_cpr = of_property_read_string(priv->pdev->dev.of_node,
  626. "qcom,vreg_ol_cpr",
  627. &priv->cpr_info.vreg_ol_cpr);
  628. if (ol_cpr && !priv->pdc_init_table) {
  629. icnss_pr_dbg("Vreg for OL CPR and pdc_init table not configured\n");
  630. return -EINVAL;
  631. }
  632. mbox->dev = &priv->pdev->dev;
  633. mbox->tx_block = true;
  634. mbox->tx_tout = ICNSS_MBOX_TIMEOUT_MS;
  635. mbox->knows_txdone = false;
  636. priv->mbox_chan = NULL;
  637. priv->qmp = NULL;
  638. priv->use_direct_qmp = false;
  639. /* First try to get mbox channel, if it fails then try qmp_get
  640. * In device tree file there should be either mboxes or qmp,
  641. * cannot have both properties at the same time.
  642. */
  643. chan = mbox_request_channel(mbox, 0);
  644. if (IS_ERR(chan)) {
  645. ret = PTR_ERR(chan);
  646. icnss_pr_dbg("Failed to get mbox channel with err %d\n", ret);
  647. priv->qmp = qmp_get(&priv->pdev->dev);
  648. if (IS_ERR(priv->qmp)) {
  649. icnss_pr_err("Failed to get qmp\n");
  650. return PTR_ERR(priv->qmp);
  651. } else {
  652. priv->use_direct_qmp = true;
  653. icnss_pr_dbg("QMP initialized\n");
  654. }
  655. } else {
  656. priv->mbox_chan = chan;
  657. icnss_pr_dbg("Mbox channel initialized\n");
  658. }
  659. ret = icnss_aop_pdc_reconfig(priv);
  660. if (ret)
  661. icnss_pr_err("Failed to reconfig WLAN PDC, err = %d\n", ret);
  662. return ret;
  663. }
  664. /**
  665. * icnss_aop_interface_deinit: Cleanup AOP interface
  666. * @priv: Pointer to icnss platform data
  667. *
  668. * Cleanup mbox channel or QMP whichever was configured during initialization.
  669. *
  670. * Return: None
  671. */
  672. void icnss_aop_interface_deinit(struct icnss_priv *priv)
  673. {
  674. if (!IS_ERR_OR_NULL(priv->mbox_chan))
  675. mbox_free_channel(priv->mbox_chan);
  676. if (!IS_ERR_OR_NULL(priv->qmp)) {
  677. qmp_put(priv->qmp);
  678. priv->use_direct_qmp = false;
  679. }
  680. }
  681. static int icnss_aop_set_vreg_param(struct icnss_priv *priv,
  682. const char *vreg_name,
  683. enum icnss_vreg_param param,
  684. enum icnss_tcs_seq seq, int val)
  685. {
  686. struct qmp_pkt pkt;
  687. char mbox_msg[ICNSS_MBOX_MSG_MAX_LEN];
  688. static const char * const vreg_param_str[] = {"v", "m", "e"};
  689. static const char *const tcs_seq_str[] = {"upval", "dwnval", "enable"};
  690. int ret = 0;
  691. if (param > ICNSS_VREG_ENABLE || seq > ICNSS_TCS_ALL_SEQ || !vreg_name)
  692. return -EINVAL;
  693. snprintf(mbox_msg, ICNSS_MBOX_MSG_MAX_LEN,
  694. "{class: wlan_pdc, res: %s.%s, %s: %d}", vreg_name,
  695. vreg_param_str[param], tcs_seq_str[seq], val);
  696. if (priv->use_direct_qmp) {
  697. icnss_pr_dbg("Sending AOP QMP msg: %s\n", mbox_msg);
  698. ret = qmp_send(priv->qmp, mbox_msg, ICNSS_MBOX_MSG_MAX_LEN);
  699. if (ret < 0)
  700. icnss_pr_err("Failed to send AOP QMP msg: %s\n", mbox_msg);
  701. else
  702. ret = 0;
  703. } else {
  704. icnss_pr_dbg("Sending AOP Mbox msg: %s\n", mbox_msg);
  705. pkt.size = ICNSS_MBOX_MSG_MAX_LEN;
  706. pkt.data = mbox_msg;
  707. ret = mbox_send_message(priv->mbox_chan, &pkt);
  708. if (ret < 0)
  709. icnss_pr_err("Failed to send AOP mbox msg: %s,ret: %d\n",
  710. mbox_msg, ret);
  711. else
  712. ret = 0;
  713. }
  714. return ret;
  715. }
  716. /* icnss_aop_pdc_reconfig: Send AOP msg to configure PDC table for WLAN device
  717. * @priv: Pointer to icnss platform data
  718. *
  719. * Send AOP QMP or Mbox msg to configure PDC table for WLAN device
  720. *
  721. * Return: 0 for success, otherwise error code
  722. */
  723. int icnss_aop_pdc_reconfig(struct icnss_priv *priv)
  724. {
  725. u32 i;
  726. int ret;
  727. char *mbox_msg;
  728. struct qmp_pkt pkt;
  729. if (priv->pdc_init_table_len <= 0 || !priv->pdc_init_table)
  730. return 0;
  731. icnss_pr_dbg("Setting PDC defaults for device ID: (0x%x)\n",
  732. priv->device_id);
  733. for (i = 0; i < priv->pdc_init_table_len; i++) {
  734. mbox_msg = (char *)priv->pdc_init_table[i];
  735. if (priv->use_direct_qmp) {
  736. icnss_pr_dbg("Sending AOP QMP msg: %s\n", mbox_msg);
  737. ret = qmp_send(priv->qmp, mbox_msg,
  738. ICNSS_MBOX_MSG_MAX_LEN);
  739. if (ret < 0)
  740. icnss_pr_err("Failed to send AOP QMP msg: %s\n",
  741. mbox_msg);
  742. else
  743. ret = 0;
  744. } else {
  745. icnss_pr_dbg("Sending AOP Mbox msg: %s\n", mbox_msg);
  746. pkt.size = ICNSS_MBOX_MSG_MAX_LEN;
  747. pkt.data = mbox_msg;
  748. ret = mbox_send_message(priv->mbox_chan, &pkt);
  749. if (ret < 0)
  750. icnss_pr_err("Failed to send AOP mbox msg: %s,ret: %d\n",
  751. mbox_msg, ret);
  752. else
  753. ret = 0;
  754. }
  755. }
  756. return ret;
  757. }
  758. #else
  759. int icnss_aop_interface_init(struct icnss_priv *priv)
  760. {
  761. return 0;
  762. }
  763. void icnss_aop_interface_deinit(struct icnss_priv *priv)
  764. {
  765. }
  766. static int icnss_aop_set_vreg_param(struct icnss_priv *priv,
  767. const char *vreg_name,
  768. enum icnss_vreg_param param,
  769. enum icnss_tcs_seq seq, int val)
  770. {
  771. return 0;
  772. }
  773. int icnss_aop_pdc_reconfig(struct icnss_priv *priv)
  774. {
  775. return 0;
  776. }
  777. #endif
  778. void icnss_power_misc_params_init(struct icnss_priv *priv)
  779. {
  780. struct device *dev = &priv->pdev->dev;
  781. int ret;
  782. /* common DT Entries */
  783. priv->pdc_init_table_len =
  784. of_property_count_strings(dev->of_node,
  785. "qcom,pdc_init_table");
  786. if (priv->pdc_init_table_len > 0) {
  787. priv->pdc_init_table =
  788. kcalloc(priv->pdc_init_table_len,
  789. sizeof(char *), GFP_KERNEL);
  790. if (priv->pdc_init_table) {
  791. ret = of_property_read_string_array(dev->of_node,
  792. "qcom,pdc_init_table",
  793. priv->pdc_init_table,
  794. priv->pdc_init_table_len);
  795. if (ret < 0)
  796. icnss_pr_err("Failed to get PDC Init Table\n");
  797. } else {
  798. icnss_pr_err("Failed to alloc PDC Init Table mem\n");
  799. }
  800. } else {
  801. icnss_pr_dbg("PDC Init Table not configured\n");
  802. }
  803. }
  804. int icnss_update_cpr_info(struct icnss_priv *priv)
  805. {
  806. struct icnss_cpr_info *cpr_info = &priv->cpr_info;
  807. if (!cpr_info->vreg_ol_cpr || (!priv->mbox_chan && !priv->use_direct_qmp)) {
  808. icnss_pr_dbg("Mbox channel / QMP / OL CPR Vreg not configured\n");
  809. return 0;
  810. }
  811. if (cpr_info->voltage == 0) {
  812. icnss_pr_err("Voltage %dmV is not valid\n", cpr_info->voltage);
  813. return -EINVAL;
  814. }
  815. cpr_info->voltage = cpr_info->voltage > BT_CXMX_VOLTAGE_MV ?
  816. cpr_info->voltage : BT_CXMX_VOLTAGE_MV;
  817. return icnss_aop_set_vreg_param(priv,
  818. cpr_info->vreg_ol_cpr,
  819. ICNSS_VREG_VOLTAGE,
  820. ICNSS_TCS_UP_SEQ,
  821. cpr_info->voltage);
  822. }
  823. static int icnss_get_battery_level(struct icnss_priv *priv)
  824. {
  825. int err = 0, battery_percentage = 0;
  826. union power_supply_propval psp = {0,};
  827. if (!priv->batt_psy)
  828. priv->batt_psy = power_supply_get_by_name("battery");
  829. if (priv->batt_psy) {
  830. err = power_supply_get_property(priv->batt_psy,
  831. POWER_SUPPLY_PROP_CAPACITY,
  832. &psp);
  833. if (err) {
  834. icnss_pr_err("battery percentage read error:%d\n", err);
  835. goto out;
  836. }
  837. battery_percentage = psp.intval;
  838. }
  839. icnss_pr_info("Battery Percentage: %d\n", battery_percentage);
  840. out:
  841. return battery_percentage;
  842. }
  843. static void icnss_update_soc_level(struct work_struct *work)
  844. {
  845. int battery_percentage = 0, current_updated_voltage = 0, err = 0;
  846. int level_count;
  847. struct icnss_priv *priv = container_of(work, struct icnss_priv, soc_update_work);
  848. battery_percentage = icnss_get_battery_level(priv);
  849. if (!battery_percentage ||
  850. battery_percentage > ICNSS_MAX_BATTERY_LEVEL) {
  851. icnss_pr_err("Battery percentage read failure\n");
  852. return;
  853. }
  854. for (level_count = 0; level_count < ICNSS_BATTERY_LEVEL_COUNT;
  855. level_count++) {
  856. if (battery_percentage >=
  857. icnss_battery_level[level_count].lower_battery_threshold) {
  858. current_updated_voltage =
  859. icnss_battery_level[level_count].ldo_voltage;
  860. break;
  861. }
  862. }
  863. if (level_count != ICNSS_BATTERY_LEVEL_COUNT &&
  864. priv->last_updated_voltage != current_updated_voltage) {
  865. err = icnss_send_vbatt_update(priv, current_updated_voltage);
  866. if (err < 0) {
  867. icnss_pr_err("Unable to update ldo voltage");
  868. return;
  869. }
  870. priv->last_updated_voltage = current_updated_voltage;
  871. }
  872. }
  873. static int icnss_battery_supply_callback(struct notifier_block *nb,
  874. unsigned long event, void *data)
  875. {
  876. struct power_supply *psy = data;
  877. struct icnss_priv *priv = container_of(nb, struct icnss_priv,
  878. psf_nb);
  879. if (strcmp(psy->desc->name, "battery"))
  880. return NOTIFY_OK;
  881. if (test_bit(ICNSS_WLFW_CONNECTED, &priv->state) &&
  882. !test_bit(ICNSS_FW_DOWN, &priv->state))
  883. queue_work(priv->soc_update_wq, &priv->soc_update_work);
  884. return NOTIFY_OK;
  885. }
  886. int icnss_get_psf_info(struct icnss_priv *priv)
  887. {
  888. int ret = 0;
  889. priv->soc_update_wq = alloc_workqueue("icnss_soc_update",
  890. WQ_UNBOUND, 1);
  891. if (!priv->soc_update_wq) {
  892. icnss_pr_err("Workqueue creation failed for soc update\n");
  893. ret = -EFAULT;
  894. goto out;
  895. }
  896. priv->psf_nb.notifier_call = icnss_battery_supply_callback;
  897. ret = power_supply_reg_notifier(&priv->psf_nb);
  898. if (ret < 0) {
  899. icnss_pr_err("Power supply framework registration err: %d\n",
  900. ret);
  901. goto err_psf_registration;
  902. }
  903. INIT_WORK(&priv->soc_update_work, icnss_update_soc_level);
  904. return 0;
  905. err_psf_registration:
  906. destroy_workqueue(priv->soc_update_wq);
  907. out:
  908. return ret;
  909. }