main.c 151 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/thermal.h>
  20. #include <linux/version.h>
  21. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  22. #include <linux/panic_notifier.h>
  23. #endif
  24. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  25. #include <soc/qcom/minidump.h>
  26. #endif
  27. #include "cnss_plat_ipc_qmi.h"
  28. #include "cnss_utils.h"
  29. #include "main.h"
  30. #include "bus.h"
  31. #include "debug.h"
  32. #include "genl.h"
  33. #include "reg.h"
  34. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  35. #ifdef CONFIG_CNSS_HW_SECURE_SMEM
  36. #include <linux/soc/qcom/smem.h>
  37. #define PERISEC_SMEM_ID 651
  38. #define HW_WIFI_UID 0x508
  39. #else
  40. #include "smcinvoke.h"
  41. #include "smcinvoke_object.h"
  42. #include "IClientEnv.h"
  43. #define HW_STATE_UID 0x108
  44. #define HW_OP_GET_STATE 1
  45. #define HW_WIFI_UID 0x508
  46. #define FEATURE_NOT_SUPPORTED 12
  47. #define PERIPHERAL_NOT_FOUND 10
  48. #endif
  49. #endif
  50. #define CNSS_DUMP_FORMAT_VER 0x11
  51. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  52. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  53. #define CNSS_DUMP_NAME "CNSS_WLAN"
  54. #define CNSS_DUMP_DESC_SIZE 0x1000
  55. #define CNSS_DUMP_SEG_VER 0x1
  56. #define FILE_SYSTEM_READY 1
  57. #define FW_READY_TIMEOUT 20000
  58. #define FW_ASSERT_TIMEOUT 5000
  59. #define CNSS_EVENT_PENDING 2989
  60. #define POWER_RESET_MIN_DELAY_MS 100
  61. #define MAX_NAME_LEN 12
  62. #define CNSS_QUIRKS_DEFAULT 0
  63. #ifdef CONFIG_CNSS_EMULATION
  64. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  65. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  66. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  67. #else
  68. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  69. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  70. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  71. #endif
  72. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  73. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  74. #define CNSS_MIN_TIME_SYNC_PERIOD 2000
  75. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  76. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  77. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  78. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  79. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  80. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  81. #define CNSS_TIME_SYNC_PERIOD_INVALID 0xFFFFFFFF
  82. enum cnss_cal_db_op {
  83. CNSS_CAL_DB_UPLOAD,
  84. CNSS_CAL_DB_DOWNLOAD,
  85. CNSS_CAL_DB_INVALID_OP,
  86. };
  87. enum cnss_recovery_type {
  88. CNSS_WLAN_RECOVERY = 0x1,
  89. CNSS_PCSS_RECOVERY = 0x2,
  90. };
  91. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  92. #define CNSS_MAX_DEV_NUM 2
  93. static struct cnss_plat_data *plat_env[CNSS_MAX_DEV_NUM];
  94. static atomic_t plat_env_count;
  95. #else
  96. static struct cnss_plat_data *plat_env;
  97. #endif
  98. static bool cnss_allow_driver_loading;
  99. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  100. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  101. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  102. };
  103. static struct cnss_fw_files FW_FILES_DEFAULT = {
  104. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  105. "utfbd.bin", "epping.bin", "evicted.bin"
  106. };
  107. struct cnss_driver_event {
  108. struct list_head list;
  109. enum cnss_driver_event_type type;
  110. bool sync;
  111. struct completion complete;
  112. int ret;
  113. void *data;
  114. };
  115. bool cnss_check_driver_loading_allowed(void)
  116. {
  117. return cnss_allow_driver_loading;
  118. }
  119. #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
  120. static void cnss_init_plat_env_count(void)
  121. {
  122. atomic_set(&plat_env_count, 0);
  123. }
  124. static void cnss_inc_plat_env_count(void)
  125. {
  126. atomic_inc(&plat_env_count);
  127. }
  128. static void cnss_dec_plat_env_count(void)
  129. {
  130. atomic_dec(&plat_env_count);
  131. }
  132. static int cnss_get_plat_env_count(void)
  133. {
  134. return atomic_read(&plat_env_count);
  135. }
  136. int cnss_get_max_plat_env_count(void)
  137. {
  138. return CNSS_MAX_DEV_NUM;
  139. }
  140. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  141. struct cnss_plat_data *plat_priv)
  142. {
  143. int env_count = cnss_get_plat_env_count();
  144. cnss_pr_dbg("Set plat_priv at %d", env_count);
  145. if (plat_priv) {
  146. plat_priv->plat_idx = env_count;
  147. plat_env[plat_priv->plat_idx] = plat_priv;
  148. cnss_inc_plat_env_count();
  149. }
  150. }
  151. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device
  152. *plat_dev)
  153. {
  154. int i;
  155. if (!plat_dev)
  156. return NULL;
  157. for (i = 0; i < CNSS_MAX_DEV_NUM; i++) {
  158. if (plat_env[i] && plat_env[i]->plat_dev == plat_dev)
  159. return plat_env[i];
  160. }
  161. return NULL;
  162. }
  163. struct cnss_plat_data *cnss_get_first_plat_priv(struct platform_device
  164. *plat_dev)
  165. {
  166. int i;
  167. if (!plat_dev) {
  168. for (i = 0; i < CNSS_MAX_DEV_NUM; i++) {
  169. if (plat_env[i])
  170. return plat_env[i];
  171. }
  172. }
  173. return NULL;
  174. }
  175. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  176. {
  177. cnss_pr_dbg("Clear plat_priv at %d", plat_priv->plat_idx);
  178. plat_env[plat_priv->plat_idx] = NULL;
  179. cnss_dec_plat_env_count();
  180. }
  181. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  182. {
  183. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  184. "wlan_%d", plat_priv->plat_idx);
  185. return 0;
  186. }
  187. static int cnss_plat_env_available(void)
  188. {
  189. int ret = 0;
  190. int env_count = cnss_get_plat_env_count();
  191. if (env_count >= CNSS_MAX_DEV_NUM) {
  192. cnss_pr_err("ERROR: No space to store plat_priv\n");
  193. ret = -ENOMEM;
  194. }
  195. return ret;
  196. }
  197. struct cnss_plat_data *cnss_get_plat_env(int index)
  198. {
  199. return plat_env[index];
  200. }
  201. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  202. {
  203. int i;
  204. for (i = 0; i < CNSS_MAX_DEV_NUM; i++) {
  205. if (plat_env[i] && plat_env[i]->rc_num == rc_num)
  206. return plat_env[i];
  207. }
  208. return NULL;
  209. }
  210. static inline int
  211. cnss_get_qrtr_node_id(struct cnss_plat_data *plat_priv)
  212. {
  213. return of_property_read_u32(plat_priv->dev_node,
  214. "qcom,qrtr_node_id", &plat_priv->qrtr_node_id);
  215. }
  216. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  217. {
  218. int ret = 0;
  219. ret = cnss_get_qrtr_node_id(plat_priv);
  220. if (ret) {
  221. cnss_pr_warn("Failed to find qrtr_node_id err=%d\n", ret);
  222. plat_priv->qrtr_node_id = 0;
  223. plat_priv->wlfw_service_instance_id = 0;
  224. } else {
  225. plat_priv->wlfw_service_instance_id = plat_priv->qrtr_node_id +
  226. QRTR_NODE_FW_ID_BASE;
  227. cnss_pr_dbg("service_instance_id=0x%x\n",
  228. plat_priv->wlfw_service_instance_id);
  229. }
  230. }
  231. static inline int
  232. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  233. {
  234. return of_property_read_string(plat_priv->plat_dev->dev.of_node,
  235. "qcom,pld_bus_ops_name",
  236. &plat_priv->pld_bus_ops_name);
  237. }
  238. #else
  239. static void cnss_init_plat_env_count(void)
  240. {
  241. }
  242. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  243. struct cnss_plat_data *plat_priv)
  244. {
  245. plat_env = plat_priv;
  246. }
  247. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  248. {
  249. return plat_env;
  250. }
  251. static void cnss_clear_plat_priv(struct cnss_plat_data *plat_priv)
  252. {
  253. plat_env = NULL;
  254. }
  255. static int cnss_set_device_name(struct cnss_plat_data *plat_priv)
  256. {
  257. snprintf(plat_priv->device_name, sizeof(plat_priv->device_name),
  258. "wlan");
  259. return 0;
  260. }
  261. static int cnss_plat_env_available(void)
  262. {
  263. return 0;
  264. }
  265. struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num)
  266. {
  267. return cnss_bus_dev_to_plat_priv(NULL);
  268. }
  269. void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv)
  270. {
  271. }
  272. static int
  273. cnss_get_pld_bus_ops_name(struct cnss_plat_data *plat_priv)
  274. {
  275. return 0;
  276. }
  277. #endif
  278. void cnss_get_sleep_clk_supported(struct cnss_plat_data *plat_priv)
  279. {
  280. plat_priv->sleep_clk = of_property_read_bool(plat_priv->dev_node,
  281. "qcom,sleep-clk-support");
  282. cnss_pr_dbg("qcom,sleep-clk-support is %d\n",
  283. plat_priv->sleep_clk);
  284. }
  285. void cnss_get_bwscal_info(struct cnss_plat_data *plat_priv)
  286. {
  287. plat_priv->no_bwscale = of_property_read_bool(plat_priv->dev_node,
  288. "qcom,no-bwscale");
  289. }
  290. static inline int
  291. cnss_get_rc_num(struct cnss_plat_data *plat_priv)
  292. {
  293. return of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  294. "qcom,wlan-rc-num", &plat_priv->rc_num);
  295. }
  296. bool cnss_is_dual_wlan_enabled(void)
  297. {
  298. return IS_ENABLED(CONFIG_CNSS_SUPPORT_DUAL_DEV);
  299. }
  300. /**
  301. * cnss_get_mem_seg_count - Get segment count of memory
  302. * @type: memory type
  303. * @seg: segment count
  304. *
  305. * Return: 0 on success, negative value on failure
  306. */
  307. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  308. {
  309. struct cnss_plat_data *plat_priv;
  310. plat_priv = cnss_get_plat_priv(NULL);
  311. if (!plat_priv)
  312. return -ENODEV;
  313. switch (type) {
  314. case CNSS_REMOTE_MEM_TYPE_FW:
  315. *seg = plat_priv->fw_mem_seg_len;
  316. break;
  317. case CNSS_REMOTE_MEM_TYPE_QDSS:
  318. *seg = plat_priv->qdss_mem_seg_len;
  319. break;
  320. default:
  321. return -EINVAL;
  322. }
  323. return 0;
  324. }
  325. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  326. /**
  327. * cnss_get_wifi_kobject -return wifi kobject
  328. * Return: Null, to maintain driver comnpatibilty
  329. */
  330. struct kobject *cnss_get_wifi_kobj(struct device *dev)
  331. {
  332. struct cnss_plat_data *plat_priv;
  333. plat_priv = cnss_get_plat_priv(NULL);
  334. if (!plat_priv)
  335. return NULL;
  336. return plat_priv->wifi_kobj;
  337. }
  338. EXPORT_SYMBOL(cnss_get_wifi_kobj);
  339. /**
  340. * cnss_get_mem_segment_info - Get memory info of different type
  341. * @type: memory type
  342. * @segment: array to save the segment info
  343. * @seg: segment count
  344. *
  345. * Return: 0 on success, negative value on failure
  346. */
  347. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  348. struct cnss_mem_segment segment[],
  349. u32 segment_count)
  350. {
  351. struct cnss_plat_data *plat_priv;
  352. u32 i;
  353. plat_priv = cnss_get_plat_priv(NULL);
  354. if (!plat_priv)
  355. return -ENODEV;
  356. switch (type) {
  357. case CNSS_REMOTE_MEM_TYPE_FW:
  358. if (segment_count > plat_priv->fw_mem_seg_len)
  359. segment_count = plat_priv->fw_mem_seg_len;
  360. for (i = 0; i < segment_count; i++) {
  361. segment[i].size = plat_priv->fw_mem[i].size;
  362. segment[i].va = plat_priv->fw_mem[i].va;
  363. segment[i].pa = plat_priv->fw_mem[i].pa;
  364. }
  365. break;
  366. case CNSS_REMOTE_MEM_TYPE_QDSS:
  367. if (segment_count > plat_priv->qdss_mem_seg_len)
  368. segment_count = plat_priv->qdss_mem_seg_len;
  369. for (i = 0; i < segment_count; i++) {
  370. segment[i].size = plat_priv->qdss_mem[i].size;
  371. segment[i].va = plat_priv->qdss_mem[i].va;
  372. segment[i].pa = plat_priv->qdss_mem[i].pa;
  373. }
  374. break;
  375. default:
  376. return -EINVAL;
  377. }
  378. return 0;
  379. }
  380. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  381. static int cnss_get_audio_iommu_domain(struct cnss_plat_data *plat_priv)
  382. {
  383. struct device_node *audio_ion_node;
  384. struct platform_device *audio_ion_pdev;
  385. audio_ion_node = of_find_compatible_node(NULL, NULL,
  386. "qcom,msm-audio-ion");
  387. if (!audio_ion_node) {
  388. cnss_pr_err("Unable to get Audio ion node");
  389. return -EINVAL;
  390. }
  391. audio_ion_pdev = of_find_device_by_node(audio_ion_node);
  392. of_node_put(audio_ion_node);
  393. if (!audio_ion_pdev) {
  394. cnss_pr_err("Unable to get Audio ion platform device");
  395. return -EINVAL;
  396. }
  397. plat_priv->audio_iommu_domain =
  398. iommu_get_domain_for_dev(&audio_ion_pdev->dev);
  399. put_device(&audio_ion_pdev->dev);
  400. if (!plat_priv->audio_iommu_domain) {
  401. cnss_pr_err("Unable to get Audio ion iommu domain");
  402. return -EINVAL;
  403. }
  404. return 0;
  405. }
  406. bool cnss_get_audio_shared_iommu_group_cap(struct device *dev)
  407. {
  408. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  409. struct device_node *audio_ion_node;
  410. struct device_node *cnss_iommu_group_node;
  411. struct device_node *audio_iommu_group_node;
  412. if (!plat_priv)
  413. return false;
  414. audio_ion_node = of_find_compatible_node(NULL, NULL,
  415. "qcom,msm-audio-ion");
  416. if (!audio_ion_node) {
  417. cnss_pr_err("Unable to get Audio ion node");
  418. return false;
  419. }
  420. audio_iommu_group_node = of_parse_phandle(audio_ion_node,
  421. "qcom,iommu-group", 0);
  422. of_node_put(audio_ion_node);
  423. if (!audio_iommu_group_node) {
  424. cnss_pr_err("Unable to get audio iommu group phandle");
  425. return false;
  426. }
  427. of_node_put(audio_iommu_group_node);
  428. cnss_iommu_group_node = of_parse_phandle(dev->of_node,
  429. "qcom,iommu-group", 0);
  430. if (!cnss_iommu_group_node) {
  431. cnss_pr_err("Unable to get cnss iommu group phandle");
  432. return false;
  433. }
  434. of_node_put(cnss_iommu_group_node);
  435. if (cnss_iommu_group_node == audio_iommu_group_node) {
  436. plat_priv->is_audio_shared_iommu_group = true;
  437. cnss_pr_info("CNSS and Audio share IOMMU group");
  438. } else {
  439. cnss_pr_info("CNSS and Audio do not share IOMMU group");
  440. }
  441. return plat_priv->is_audio_shared_iommu_group;
  442. }
  443. EXPORT_SYMBOL(cnss_get_audio_shared_iommu_group_cap);
  444. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  445. enum cnss_feature_v01 feature)
  446. {
  447. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  448. return -EINVAL;
  449. plat_priv->feature_list |= 1 << feature;
  450. return 0;
  451. }
  452. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  453. enum cnss_feature_v01 feature)
  454. {
  455. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  456. return -EINVAL;
  457. plat_priv->feature_list &= ~(1 << feature);
  458. return 0;
  459. }
  460. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  461. u64 *feature_list)
  462. {
  463. if (unlikely(!plat_priv))
  464. return -EINVAL;
  465. *feature_list = plat_priv->feature_list;
  466. return 0;
  467. }
  468. size_t cnss_get_platform_name(struct cnss_plat_data *plat_priv,
  469. char *buf, const size_t buf_len)
  470. {
  471. if (unlikely(!plat_priv || !buf || !buf_len))
  472. return 0;
  473. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  474. "platform-name-required")) {
  475. struct device_node *root;
  476. root = of_find_node_by_path("/");
  477. if (root) {
  478. const char *model;
  479. size_t model_len;
  480. model = of_get_property(root, "model", NULL);
  481. if (model) {
  482. model_len = strlcpy(buf, model, buf_len);
  483. cnss_pr_dbg("Platform name: %s (%zu)\n",
  484. buf, model_len);
  485. return model_len;
  486. }
  487. }
  488. }
  489. return 0;
  490. }
  491. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  492. {
  493. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  494. return;
  495. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  496. plat_priv->driver_state,
  497. atomic_read(&plat_priv->pm_count));
  498. pm_stay_awake(&plat_priv->plat_dev->dev);
  499. }
  500. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  501. {
  502. int r = atomic_dec_return(&plat_priv->pm_count);
  503. WARN_ON(r < 0);
  504. if (r != 0)
  505. return;
  506. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  507. plat_priv->driver_state,
  508. atomic_read(&plat_priv->pm_count));
  509. pm_relax(&plat_priv->plat_dev->dev);
  510. }
  511. int cnss_get_fw_files_for_target(struct device *dev,
  512. struct cnss_fw_files *pfw_files,
  513. u32 target_type, u32 target_version)
  514. {
  515. if (!pfw_files)
  516. return -ENODEV;
  517. switch (target_version) {
  518. case QCA6174_REV3_VERSION:
  519. case QCA6174_REV3_2_VERSION:
  520. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  521. break;
  522. default:
  523. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  524. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  525. target_type, target_version);
  526. break;
  527. }
  528. return 0;
  529. }
  530. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  531. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  532. {
  533. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  534. if (!plat_priv)
  535. return -ENODEV;
  536. if (!cap)
  537. return -EINVAL;
  538. *cap = plat_priv->cap;
  539. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  540. return 0;
  541. }
  542. EXPORT_SYMBOL(cnss_get_platform_cap);
  543. /**
  544. * cnss_get_fw_cap - Check whether FW supports specific capability or not
  545. * @dev: Device
  546. * @fw_cap: FW Capability which needs to be checked
  547. *
  548. * Return: TRUE if supported, FALSE on failure or if not supported
  549. */
  550. bool cnss_get_fw_cap(struct device *dev, enum cnss_fw_caps fw_cap)
  551. {
  552. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  553. bool is_supported = false;
  554. if (!plat_priv)
  555. return is_supported;
  556. if (!plat_priv->fw_caps)
  557. return is_supported;
  558. switch (fw_cap) {
  559. case CNSS_FW_CAP_DIRECT_LINK_SUPPORT:
  560. is_supported = !!(plat_priv->fw_caps &
  561. QMI_WLFW_DIRECT_LINK_SUPPORT_V01);
  562. break;
  563. case CNSS_FW_CAP_CALDB_SEG_DDR_SUPPORT:
  564. is_supported = !!(plat_priv->fw_caps &
  565. QMI_WLFW_CALDB_SEG_DDR_SUPPORT_V01);
  566. break;
  567. default:
  568. cnss_pr_err("Invalid FW Capability: 0x%x\n", fw_cap);
  569. }
  570. cnss_pr_dbg("FW Capability 0x%x is %s\n", fw_cap,
  571. is_supported ? "supported" : "not supported");
  572. return is_supported;
  573. }
  574. EXPORT_SYMBOL(cnss_get_fw_cap);
  575. /**
  576. * cnss_audio_is_direct_link_supported - Check whether Audio can be used for direct link support
  577. * @dev: Device
  578. *
  579. * Return: TRUE if supported, FALSE on failure or if not supported
  580. */
  581. bool cnss_audio_is_direct_link_supported(struct device *dev)
  582. {
  583. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  584. bool is_supported = false;
  585. if (!plat_priv) {
  586. cnss_pr_err("plat_priv not available to check audio direct link cap\n");
  587. return is_supported;
  588. }
  589. if (cnss_get_audio_iommu_domain(plat_priv) == 0)
  590. is_supported = true;
  591. return is_supported;
  592. }
  593. EXPORT_SYMBOL(cnss_audio_is_direct_link_supported);
  594. /**
  595. * cnss_ipa_wlan_shared_smmu_supported: Check whether shared SMMU context bank
  596. * can be used between IPA and WLAN.
  597. * @dev: Device
  598. *
  599. * Return: TRUE if supported, FALSE on failure or if not supported
  600. */
  601. bool cnss_ipa_wlan_shared_smmu_supported(struct device *dev)
  602. {
  603. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  604. struct device_node *ipa_wlan_smmu_node;
  605. struct device_node *cnss_iommu_group_node;
  606. struct device_node *ipa_iommu_group_node;
  607. if (!plat_priv) {
  608. cnss_pr_err("plat_priv not available for IPA Shared CB cap\n");
  609. return false;
  610. }
  611. ipa_wlan_smmu_node = of_find_compatible_node(NULL, NULL,
  612. "qcom,ipa-smmu-wlan-cb");
  613. if (!ipa_wlan_smmu_node) {
  614. cnss_pr_err("ipa-smmu-wlan-cb not enabled");
  615. return false;
  616. }
  617. ipa_iommu_group_node = of_parse_phandle(ipa_wlan_smmu_node,
  618. "qcom,iommu-group", 0);
  619. of_node_put(ipa_wlan_smmu_node);
  620. if (!ipa_iommu_group_node) {
  621. cnss_pr_err("Unable to get ipa iommu group phandle");
  622. return false;
  623. }
  624. of_node_put(ipa_iommu_group_node);
  625. cnss_iommu_group_node = of_parse_phandle(dev->of_node,
  626. "qcom,iommu-group", 0);
  627. if (!cnss_iommu_group_node) {
  628. cnss_pr_err("Unable to get cnss iommu group phandle");
  629. return false;
  630. }
  631. of_node_put(cnss_iommu_group_node);
  632. if (cnss_iommu_group_node == ipa_iommu_group_node) {
  633. plat_priv->ipa_shared_cb_enable = true;
  634. cnss_pr_info("CNSS and IPA share IOMMU group");
  635. } else {
  636. cnss_pr_info("CNSS and IPA do not share IOMMU group");
  637. }
  638. return plat_priv->ipa_shared_cb_enable;
  639. }
  640. EXPORT_SYMBOL(cnss_ipa_wlan_shared_smmu_supported);
  641. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  642. {
  643. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  644. if (!plat_priv)
  645. return;
  646. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  647. }
  648. EXPORT_SYMBOL(cnss_request_pm_qos);
  649. void cnss_remove_pm_qos(struct device *dev)
  650. {
  651. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  652. if (!plat_priv)
  653. return;
  654. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  655. }
  656. EXPORT_SYMBOL(cnss_remove_pm_qos);
  657. int cnss_wlan_enable(struct device *dev,
  658. struct cnss_wlan_enable_cfg *config,
  659. enum cnss_driver_mode mode,
  660. const char *host_version)
  661. {
  662. int ret = 0;
  663. struct cnss_plat_data *plat_priv;
  664. if (!dev) {
  665. cnss_pr_err("Invalid dev pointer\n");
  666. return -EINVAL;
  667. }
  668. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  669. if (!plat_priv)
  670. return -ENODEV;
  671. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  672. return 0;
  673. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  674. return 0;
  675. if (!config || !host_version) {
  676. cnss_pr_err("Invalid config or host_version pointer\n");
  677. return -EINVAL;
  678. }
  679. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  680. mode, config, host_version);
  681. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  682. goto skip_cfg;
  683. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  684. config->send_msi_ce = true;
  685. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  686. if (ret)
  687. goto out;
  688. skip_cfg:
  689. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  690. out:
  691. return ret;
  692. }
  693. EXPORT_SYMBOL(cnss_wlan_enable);
  694. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  695. {
  696. int ret = 0;
  697. struct cnss_plat_data *plat_priv;
  698. if (!dev) {
  699. cnss_pr_err("Invalid dev pointer\n");
  700. return -EINVAL;
  701. }
  702. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  703. if (!plat_priv)
  704. return -ENODEV;
  705. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  706. return 0;
  707. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  708. return 0;
  709. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  710. cnss_bus_free_qdss_mem(plat_priv);
  711. return ret;
  712. }
  713. EXPORT_SYMBOL(cnss_wlan_disable);
  714. #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0))
  715. int cnss_iommu_map(struct iommu_domain *domain,
  716. unsigned long iova, phys_addr_t paddr, size_t size, int prot)
  717. {
  718. return iommu_map(domain, iova, paddr, size, prot);
  719. }
  720. #else
  721. int cnss_iommu_map(struct iommu_domain *domain,
  722. unsigned long iova, phys_addr_t paddr, size_t size, int prot)
  723. {
  724. return iommu_map(domain, iova, paddr, size, prot, GFP_KERNEL);
  725. }
  726. #endif
  727. int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
  728. dma_addr_t iova, size_t size)
  729. {
  730. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  731. uint32_t page_offset;
  732. if (!plat_priv)
  733. return -ENODEV;
  734. if (!plat_priv->audio_iommu_domain)
  735. return -EINVAL;
  736. if (plat_priv->is_audio_shared_iommu_group)
  737. return 0;
  738. page_offset = iova & (PAGE_SIZE - 1);
  739. if (page_offset + size > PAGE_SIZE)
  740. size += PAGE_SIZE;
  741. iova -= page_offset;
  742. paddr -= page_offset;
  743. return cnss_iommu_map(plat_priv->audio_iommu_domain, iova, paddr,
  744. roundup(size, PAGE_SIZE), IOMMU_READ |
  745. IOMMU_WRITE | IOMMU_CACHE);
  746. }
  747. EXPORT_SYMBOL(cnss_audio_smmu_map);
  748. void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, size_t size)
  749. {
  750. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  751. uint32_t page_offset;
  752. if (!plat_priv || !plat_priv->audio_iommu_domain ||
  753. plat_priv->is_audio_shared_iommu_group)
  754. return;
  755. page_offset = iova & (PAGE_SIZE - 1);
  756. if (page_offset + size > PAGE_SIZE)
  757. size += PAGE_SIZE;
  758. iova -= page_offset;
  759. iommu_unmap(plat_priv->audio_iommu_domain, iova,
  760. roundup(size, PAGE_SIZE));
  761. }
  762. EXPORT_SYMBOL(cnss_audio_smmu_unmap);
  763. int cnss_get_fw_lpass_shared_mem(struct device *dev, dma_addr_t *iova,
  764. size_t *size)
  765. {
  766. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  767. uint8_t i;
  768. if (!plat_priv)
  769. return -EINVAL;
  770. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  771. if (plat_priv->fw_mem[i].type ==
  772. QMI_WLFW_MEM_LPASS_SHARED_V01) {
  773. *iova = plat_priv->fw_mem[i].pa;
  774. *size = plat_priv->fw_mem[i].size;
  775. return 0;
  776. }
  777. }
  778. return -EINVAL;
  779. }
  780. EXPORT_SYMBOL(cnss_get_fw_lpass_shared_mem);
  781. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  782. u32 data_len, u8 *output)
  783. {
  784. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  785. int ret = 0;
  786. if (!plat_priv) {
  787. cnss_pr_err("plat_priv is NULL!\n");
  788. return -EINVAL;
  789. }
  790. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  791. return 0;
  792. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  793. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  794. plat_priv->driver_state);
  795. ret = -EINVAL;
  796. goto out;
  797. }
  798. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  799. data_len, output);
  800. out:
  801. return ret;
  802. }
  803. EXPORT_SYMBOL(cnss_athdiag_read);
  804. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  805. u32 data_len, u8 *input)
  806. {
  807. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  808. int ret = 0;
  809. if (!plat_priv) {
  810. cnss_pr_err("plat_priv is NULL!\n");
  811. return -EINVAL;
  812. }
  813. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  814. return 0;
  815. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  816. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  817. plat_priv->driver_state);
  818. ret = -EINVAL;
  819. goto out;
  820. }
  821. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  822. data_len, input);
  823. out:
  824. return ret;
  825. }
  826. EXPORT_SYMBOL(cnss_athdiag_write);
  827. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  828. {
  829. struct cnss_plat_data *plat_priv;
  830. if (!dev) {
  831. cnss_pr_err("Invalid dev pointer\n");
  832. return -EINVAL;
  833. }
  834. plat_priv = cnss_bus_dev_to_plat_priv(dev);
  835. if (!plat_priv)
  836. return -ENODEV;
  837. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  838. return 0;
  839. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  840. }
  841. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  842. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  843. {
  844. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  845. if (!plat_priv)
  846. return -EINVAL;
  847. if (!plat_priv->fw_pcie_gen_switch) {
  848. cnss_pr_err("Firmware does not support PCIe gen switch\n");
  849. return -EOPNOTSUPP;
  850. }
  851. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  852. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  853. return -EINVAL;
  854. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  855. plat_priv->pcie_gen_speed = pcie_gen_speed;
  856. return 0;
  857. }
  858. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  859. static bool cnss_is_aux_support_enabled(struct cnss_plat_data *plat_priv)
  860. {
  861. switch (plat_priv->device_id) {
  862. case PEACH_DEVICE_ID:
  863. if (!plat_priv->fw_aux_uc_support) {
  864. cnss_pr_dbg("FW does not support aux uc capability\n");
  865. return false;
  866. }
  867. break;
  868. default:
  869. cnss_pr_dbg("Host does not support aux uc capability\n");
  870. return false;
  871. }
  872. return true;
  873. }
  874. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  875. {
  876. int ret = 0;
  877. if (!plat_priv)
  878. return -ENODEV;
  879. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  880. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  881. if (ret)
  882. goto out;
  883. cnss_bus_load_tme_patch(plat_priv);
  884. cnss_wlfw_tme_patch_dnld_send_sync(plat_priv,
  885. WLFW_TME_LITE_PATCH_FILE_V01);
  886. if (plat_priv->hds_enabled)
  887. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  888. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  889. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  890. plat_priv->ctrl_params.bdf_type = CNSS_BDF_BIN;
  891. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  892. plat_priv->ctrl_params.bdf_type);
  893. if (ret)
  894. goto out;
  895. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  896. return 0;
  897. ret = cnss_bus_load_m3(plat_priv);
  898. if (ret)
  899. goto out;
  900. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  901. if (ret)
  902. goto out;
  903. if (cnss_is_aux_support_enabled(plat_priv)) {
  904. ret = cnss_bus_load_aux(plat_priv);
  905. if (ret)
  906. goto out;
  907. ret = cnss_wlfw_aux_dnld_send_sync(plat_priv);
  908. if (ret)
  909. goto out;
  910. }
  911. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  912. return 0;
  913. out:
  914. return ret;
  915. }
  916. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  917. {
  918. int ret = 0;
  919. if (!plat_priv->antenna) {
  920. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  921. if (ret)
  922. goto out;
  923. }
  924. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  925. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  926. if (ret)
  927. goto out;
  928. }
  929. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  930. if (ret)
  931. goto out;
  932. return 0;
  933. out:
  934. return ret;
  935. }
  936. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  937. {
  938. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  939. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  940. }
  941. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  942. {
  943. u32 i;
  944. int ret = 0;
  945. struct cnss_plat_ipc_daemon_config *cfg;
  946. ret = cnss_qmi_get_dms_mac(plat_priv);
  947. if (ret == 0 && plat_priv->dms.mac_valid)
  948. goto qmi_send;
  949. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  950. * Thus assert on failure to get MAC from DMS even after retries
  951. */
  952. if (plat_priv->use_nv_mac) {
  953. /* Check if Daemon says platform support DMS MAC provisioning */
  954. cfg = cnss_plat_ipc_qmi_daemon_config();
  955. if (cfg) {
  956. if (!cfg->dms_mac_addr_supported) {
  957. cnss_pr_err("DMS MAC address not supported\n");
  958. CNSS_ASSERT(0);
  959. return -EINVAL;
  960. }
  961. }
  962. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  963. if (plat_priv->dms.mac_valid)
  964. break;
  965. ret = cnss_qmi_get_dms_mac(plat_priv);
  966. if (ret == 0)
  967. break;
  968. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  969. }
  970. if (!plat_priv->dms.mac_valid) {
  971. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  972. CNSS_ASSERT(0);
  973. return -EINVAL;
  974. }
  975. }
  976. qmi_send:
  977. if (plat_priv->dms.mac_valid)
  978. ret =
  979. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  980. ARRAY_SIZE(plat_priv->dms.mac));
  981. return ret;
  982. }
  983. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  984. enum cnss_cal_db_op op, u32 *size)
  985. {
  986. int ret = 0;
  987. u32 timeout = cnss_get_timeout(plat_priv,
  988. CNSS_TIMEOUT_DAEMON_CONNECTION);
  989. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  990. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  991. if (op >= CNSS_CAL_DB_INVALID_OP)
  992. return -EINVAL;
  993. if (!plat_priv->cbc_file_download) {
  994. cnss_pr_info("CAL DB file not required as per BDF\n");
  995. return 0;
  996. }
  997. if (*size == 0) {
  998. cnss_pr_err("Invalid cal file size\n");
  999. return -EINVAL;
  1000. }
  1001. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  1002. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  1003. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  1004. msecs_to_jiffies(timeout));
  1005. if (!ret) {
  1006. cnss_pr_err("Daemon not yet connected\n");
  1007. CNSS_ASSERT(0);
  1008. return ret;
  1009. }
  1010. }
  1011. if (!plat_priv->cal_mem->va) {
  1012. cnss_pr_err("CAL DB Memory not setup for FW\n");
  1013. return -EINVAL;
  1014. }
  1015. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  1016. if (op == CNSS_CAL_DB_DOWNLOAD) {
  1017. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  1018. ret = cnss_plat_ipc_qmi_file_download(client_id,
  1019. CNSS_CAL_DB_FILE_NAME,
  1020. plat_priv->cal_mem->va,
  1021. size);
  1022. } else {
  1023. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  1024. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  1025. CNSS_CAL_DB_FILE_NAME,
  1026. plat_priv->cal_mem->va,
  1027. *size);
  1028. }
  1029. if (ret)
  1030. cnss_pr_err("Cal DB file %s %s failure\n",
  1031. CNSS_CAL_DB_FILE_NAME,
  1032. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  1033. else
  1034. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  1035. CNSS_CAL_DB_FILE_NAME,
  1036. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  1037. *size);
  1038. return ret;
  1039. }
  1040. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  1041. {
  1042. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  1043. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  1044. return -EINVAL;
  1045. }
  1046. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  1047. &plat_priv->cal_file_size);
  1048. }
  1049. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  1050. u32 *cal_file_size)
  1051. {
  1052. /* To download pass the total size of cal DB mem allocated.
  1053. * After cal file is download to mem, its size is updated in
  1054. * return pointer
  1055. */
  1056. *cal_file_size = plat_priv->cal_mem->size;
  1057. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  1058. cal_file_size);
  1059. }
  1060. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  1061. {
  1062. int ret = 0;
  1063. u32 cal_file_size = 0;
  1064. if (!plat_priv)
  1065. return -ENODEV;
  1066. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1067. cnss_pr_err("Reboot is in progress, ignore FW ready\n");
  1068. return -EINVAL;
  1069. }
  1070. cnss_pr_dbg("Processing FW Init Done..\n");
  1071. del_timer(&plat_priv->fw_boot_timer);
  1072. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  1073. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  1074. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  1075. cnss_send_subsys_restart_level_msg(plat_priv);
  1076. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  1077. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  1078. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1079. }
  1080. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  1081. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  1082. CNSS_WALTEST);
  1083. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1084. cnss_request_antenna_sharing(plat_priv);
  1085. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  1086. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  1087. plat_priv->cal_time = jiffies;
  1088. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  1089. CNSS_CALIBRATION);
  1090. } else {
  1091. ret = cnss_setup_dms_mac(plat_priv);
  1092. ret = cnss_bus_call_driver_probe(plat_priv);
  1093. }
  1094. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1095. goto out;
  1096. else if (ret)
  1097. goto shutdown;
  1098. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  1099. return 0;
  1100. shutdown:
  1101. cnss_bus_dev_shutdown(plat_priv);
  1102. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  1103. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  1104. out:
  1105. return ret;
  1106. }
  1107. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  1108. {
  1109. switch (type) {
  1110. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1111. return "SERVER_ARRIVE";
  1112. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1113. return "SERVER_EXIT";
  1114. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1115. return "REQUEST_MEM";
  1116. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1117. return "FW_MEM_READY";
  1118. case CNSS_DRIVER_EVENT_FW_READY:
  1119. return "FW_READY";
  1120. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1121. return "COLD_BOOT_CAL_START";
  1122. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1123. return "COLD_BOOT_CAL_DONE";
  1124. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1125. return "REGISTER_DRIVER";
  1126. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1127. return "UNREGISTER_DRIVER";
  1128. case CNSS_DRIVER_EVENT_RECOVERY:
  1129. return "RECOVERY";
  1130. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1131. return "FORCE_FW_ASSERT";
  1132. case CNSS_DRIVER_EVENT_POWER_UP:
  1133. return "POWER_UP";
  1134. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1135. return "POWER_DOWN";
  1136. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1137. return "IDLE_RESTART";
  1138. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1139. return "IDLE_SHUTDOWN";
  1140. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1141. return "IMS_WFC_CALL_IND";
  1142. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1143. return "WLFW_TWC_CFG_IND";
  1144. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1145. return "QDSS_TRACE_REQ_MEM";
  1146. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1147. return "FW_MEM_FILE_SAVE";
  1148. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1149. return "QDSS_TRACE_FREE";
  1150. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1151. return "QDSS_TRACE_REQ_DATA";
  1152. case CNSS_DRIVER_EVENT_MAX:
  1153. return "EVENT_MAX";
  1154. }
  1155. return "UNKNOWN";
  1156. };
  1157. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  1158. enum cnss_driver_event_type type,
  1159. u32 flags, void *data)
  1160. {
  1161. struct cnss_driver_event *event;
  1162. unsigned long irq_flags;
  1163. int gfp = GFP_KERNEL;
  1164. int ret = 0;
  1165. if (!plat_priv)
  1166. return -ENODEV;
  1167. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  1168. cnss_driver_event_to_str(type), type,
  1169. flags ? "-sync" : "", plat_priv->driver_state, flags);
  1170. if (type >= CNSS_DRIVER_EVENT_MAX) {
  1171. cnss_pr_err("Invalid Event type: %d, can't post", type);
  1172. return -EINVAL;
  1173. }
  1174. if (in_interrupt() || irqs_disabled())
  1175. gfp = GFP_ATOMIC;
  1176. event = kzalloc(sizeof(*event), gfp);
  1177. if (!event)
  1178. return -ENOMEM;
  1179. cnss_pm_stay_awake(plat_priv);
  1180. event->type = type;
  1181. event->data = data;
  1182. init_completion(&event->complete);
  1183. event->ret = CNSS_EVENT_PENDING;
  1184. event->sync = !!(flags & CNSS_EVENT_SYNC);
  1185. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  1186. list_add_tail(&event->list, &plat_priv->event_list);
  1187. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1188. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  1189. if (!(flags & CNSS_EVENT_SYNC))
  1190. goto out;
  1191. if (flags & CNSS_EVENT_UNKILLABLE)
  1192. wait_for_completion(&event->complete);
  1193. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  1194. ret = wait_for_completion_killable(&event->complete);
  1195. else
  1196. ret = wait_for_completion_interruptible(&event->complete);
  1197. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  1198. cnss_driver_event_to_str(type), type,
  1199. plat_priv->driver_state, ret, event->ret);
  1200. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  1201. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  1202. event->sync = false;
  1203. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1204. ret = -EINTR;
  1205. goto out;
  1206. }
  1207. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  1208. ret = event->ret;
  1209. kfree(event);
  1210. out:
  1211. cnss_pm_relax(plat_priv);
  1212. return ret;
  1213. }
  1214. /**
  1215. * cnss_get_timeout - Get timeout for corresponding type.
  1216. * @plat_priv: Pointer to platform driver context.
  1217. * @cnss_timeout_type: Timeout type.
  1218. *
  1219. * Return: Timeout in milliseconds.
  1220. */
  1221. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  1222. enum cnss_timeout_type timeout_type)
  1223. {
  1224. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  1225. switch (timeout_type) {
  1226. case CNSS_TIMEOUT_QMI:
  1227. return qmi_timeout;
  1228. case CNSS_TIMEOUT_POWER_UP:
  1229. return (qmi_timeout << 2);
  1230. case CNSS_TIMEOUT_IDLE_RESTART:
  1231. /* In idle restart power up sequence, we have fw_boot_timer to
  1232. * handle FW initialization failure.
  1233. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  1234. * account for FW dump collection and FW re-initialization on
  1235. * retry.
  1236. */
  1237. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  1238. case CNSS_TIMEOUT_CALIBRATION:
  1239. /* Similar to mission mode, in CBC if FW init fails
  1240. * fw recovery is tried. Thus return 2x the CBC timeout.
  1241. */
  1242. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  1243. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  1244. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  1245. case CNSS_TIMEOUT_RDDM:
  1246. return CNSS_RDDM_TIMEOUT_MS;
  1247. case CNSS_TIMEOUT_RECOVERY:
  1248. return RECOVERY_TIMEOUT;
  1249. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  1250. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  1251. default:
  1252. return qmi_timeout;
  1253. }
  1254. }
  1255. unsigned int cnss_get_boot_timeout(struct device *dev)
  1256. {
  1257. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1258. if (!plat_priv) {
  1259. cnss_pr_err("plat_priv is NULL\n");
  1260. return 0;
  1261. }
  1262. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  1263. }
  1264. EXPORT_SYMBOL(cnss_get_boot_timeout);
  1265. int cnss_power_up(struct device *dev)
  1266. {
  1267. int ret = 0;
  1268. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1269. unsigned int timeout;
  1270. if (!plat_priv) {
  1271. cnss_pr_err("plat_priv is NULL\n");
  1272. return -ENODEV;
  1273. }
  1274. cnss_pr_dbg("Powering up device\n");
  1275. ret = cnss_driver_event_post(plat_priv,
  1276. CNSS_DRIVER_EVENT_POWER_UP,
  1277. CNSS_EVENT_SYNC, NULL);
  1278. if (ret)
  1279. goto out;
  1280. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1281. goto out;
  1282. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  1283. reinit_completion(&plat_priv->power_up_complete);
  1284. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1285. msecs_to_jiffies(timeout));
  1286. if (!ret) {
  1287. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  1288. timeout);
  1289. ret = -EAGAIN;
  1290. goto out;
  1291. }
  1292. return 0;
  1293. out:
  1294. return ret;
  1295. }
  1296. EXPORT_SYMBOL(cnss_power_up);
  1297. int cnss_power_down(struct device *dev)
  1298. {
  1299. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1300. if (!plat_priv) {
  1301. cnss_pr_err("plat_priv is NULL\n");
  1302. return -ENODEV;
  1303. }
  1304. cnss_pr_dbg("Powering down device\n");
  1305. return cnss_driver_event_post(plat_priv,
  1306. CNSS_DRIVER_EVENT_POWER_DOWN,
  1307. CNSS_EVENT_SYNC, NULL);
  1308. }
  1309. EXPORT_SYMBOL(cnss_power_down);
  1310. int cnss_idle_restart(struct device *dev)
  1311. {
  1312. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1313. unsigned int timeout;
  1314. int ret = 0;
  1315. if (!plat_priv) {
  1316. cnss_pr_err("plat_priv is NULL\n");
  1317. return -ENODEV;
  1318. }
  1319. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  1320. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  1321. return -EBUSY;
  1322. }
  1323. cnss_pr_dbg("Doing idle restart\n");
  1324. reinit_completion(&plat_priv->power_up_complete);
  1325. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1326. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1327. ret = -EINVAL;
  1328. goto out;
  1329. }
  1330. ret = cnss_driver_event_post(plat_priv,
  1331. CNSS_DRIVER_EVENT_IDLE_RESTART,
  1332. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1333. if (ret == -EINTR && plat_priv->device_id != QCA6174_DEVICE_ID)
  1334. cnss_pr_err("Idle restart has been interrupted but device power up is still in progress");
  1335. else if (ret)
  1336. goto out;
  1337. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1338. ret = cnss_bus_call_driver_probe(plat_priv);
  1339. goto out;
  1340. }
  1341. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  1342. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  1343. msecs_to_jiffies(timeout));
  1344. if (plat_priv->power_up_error) {
  1345. ret = plat_priv->power_up_error;
  1346. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1347. cnss_pr_dbg("Power up error:%d, exiting\n",
  1348. plat_priv->power_up_error);
  1349. goto out;
  1350. }
  1351. if (!ret) {
  1352. /* This exception occurs after attempting retry of FW recovery.
  1353. * Thus we can safely power off the device.
  1354. */
  1355. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  1356. timeout);
  1357. ret = -ETIMEDOUT;
  1358. cnss_power_down(dev);
  1359. CNSS_ASSERT(0);
  1360. goto out;
  1361. }
  1362. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1363. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  1364. del_timer(&plat_priv->fw_boot_timer);
  1365. ret = -EINVAL;
  1366. goto out;
  1367. }
  1368. /* In non-DRV mode, remove MHI satellite configuration. Switching to
  1369. * non-DRV is supported only once after device reboots and before wifi
  1370. * is turned on. We do not allow switching back to DRV.
  1371. * To bring device back into DRV, user needs to reboot device.
  1372. */
  1373. if (test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) {
  1374. cnss_pr_dbg("DRV is disabled\n");
  1375. cnss_bus_disable_mhi_satellite_cfg(plat_priv);
  1376. }
  1377. mutex_unlock(&plat_priv->driver_ops_lock);
  1378. return 0;
  1379. out:
  1380. mutex_unlock(&plat_priv->driver_ops_lock);
  1381. return ret;
  1382. }
  1383. EXPORT_SYMBOL(cnss_idle_restart);
  1384. int cnss_idle_shutdown(struct device *dev)
  1385. {
  1386. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1387. if (!plat_priv) {
  1388. cnss_pr_err("plat_priv is NULL\n");
  1389. return -ENODEV;
  1390. }
  1391. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  1392. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  1393. return -EAGAIN;
  1394. }
  1395. cnss_pr_dbg("Doing idle shutdown\n");
  1396. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) ||
  1397. test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) {
  1398. cnss_pr_dbg("Recovery in progress. Ignore IDLE Shutdown\n");
  1399. return -EBUSY;
  1400. }
  1401. return cnss_driver_event_post(plat_priv,
  1402. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  1403. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  1404. }
  1405. EXPORT_SYMBOL(cnss_idle_shutdown);
  1406. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  1407. {
  1408. int ret = 0;
  1409. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1410. if (ret < 0) {
  1411. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  1412. goto out;
  1413. }
  1414. ret = cnss_get_clk(plat_priv);
  1415. if (ret) {
  1416. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  1417. goto put_vreg;
  1418. }
  1419. ret = cnss_get_pinctrl(plat_priv);
  1420. if (ret) {
  1421. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  1422. goto put_clk;
  1423. }
  1424. return 0;
  1425. put_clk:
  1426. cnss_put_clk(plat_priv);
  1427. put_vreg:
  1428. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1429. out:
  1430. return ret;
  1431. }
  1432. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  1433. {
  1434. cnss_put_clk(plat_priv);
  1435. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  1436. }
  1437. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1438. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  1439. unsigned long code,
  1440. void *ss_handle)
  1441. {
  1442. struct cnss_plat_data *plat_priv =
  1443. container_of(nb, struct cnss_plat_data, modem_nb);
  1444. struct cnss_esoc_info *esoc_info;
  1445. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  1446. if (!plat_priv)
  1447. return NOTIFY_DONE;
  1448. esoc_info = &plat_priv->esoc_info;
  1449. if (code == SUBSYS_AFTER_POWERUP)
  1450. esoc_info->modem_current_status = 1;
  1451. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  1452. esoc_info->modem_current_status = 0;
  1453. else
  1454. return NOTIFY_DONE;
  1455. if (!cnss_bus_call_driver_modem_status(plat_priv,
  1456. esoc_info->modem_current_status))
  1457. return NOTIFY_DONE;
  1458. return NOTIFY_OK;
  1459. }
  1460. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1461. {
  1462. int ret = 0;
  1463. struct device *dev;
  1464. struct cnss_esoc_info *esoc_info;
  1465. struct esoc_desc *esoc_desc;
  1466. const char *client_desc;
  1467. dev = &plat_priv->plat_dev->dev;
  1468. esoc_info = &plat_priv->esoc_info;
  1469. esoc_info->notify_modem_status =
  1470. of_property_read_bool(dev->of_node,
  1471. "qcom,notify-modem-status");
  1472. if (!esoc_info->notify_modem_status)
  1473. goto out;
  1474. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  1475. &client_desc);
  1476. if (ret) {
  1477. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  1478. } else {
  1479. esoc_desc = devm_register_esoc_client(dev, client_desc);
  1480. if (IS_ERR_OR_NULL(esoc_desc)) {
  1481. ret = PTR_RET(esoc_desc);
  1482. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  1483. ret);
  1484. goto out;
  1485. }
  1486. esoc_info->esoc_desc = esoc_desc;
  1487. }
  1488. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1489. esoc_info->modem_current_status = 0;
  1490. esoc_info->modem_notify_handler =
  1491. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1492. esoc_info->esoc_desc->name :
  1493. "modem", &plat_priv->modem_nb);
  1494. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1495. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1496. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1497. ret);
  1498. goto unreg_esoc;
  1499. }
  1500. return 0;
  1501. unreg_esoc:
  1502. if (esoc_info->esoc_desc)
  1503. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1504. out:
  1505. return ret;
  1506. }
  1507. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1508. {
  1509. struct device *dev;
  1510. struct cnss_esoc_info *esoc_info;
  1511. dev = &plat_priv->plat_dev->dev;
  1512. esoc_info = &plat_priv->esoc_info;
  1513. if (esoc_info->notify_modem_status)
  1514. subsys_notif_unregister_notifier
  1515. (esoc_info->modem_notify_handler,
  1516. &plat_priv->modem_nb);
  1517. if (esoc_info->esoc_desc)
  1518. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1519. }
  1520. #else
  1521. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1522. {
  1523. return 0;
  1524. }
  1525. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1526. #endif
  1527. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1528. {
  1529. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1530. int ret = 0;
  1531. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1532. return 0;
  1533. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1534. if (ret)
  1535. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1536. ret);
  1537. return ret;
  1538. }
  1539. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1540. {
  1541. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1542. int ret = 0;
  1543. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1544. return 0;
  1545. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1546. if (ret)
  1547. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1548. ret);
  1549. return ret;
  1550. }
  1551. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1552. {
  1553. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1554. if (sol_gpio->dev_sol_gpio < 0)
  1555. return -EINVAL;
  1556. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1557. }
  1558. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1559. {
  1560. struct cnss_plat_data *plat_priv = data;
  1561. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1562. if (test_bit(CNSS_POWER_OFF, &plat_priv->driver_state)) {
  1563. cnss_pr_dbg("Ignore Dev SOL during device power off");
  1564. return IRQ_HANDLED;
  1565. }
  1566. sol_gpio->dev_sol_counter++;
  1567. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u, dev_sol_val: %d\n",
  1568. irq, sol_gpio->dev_sol_counter,
  1569. cnss_get_dev_sol_value(plat_priv));
  1570. /* Make sure abort current suspend */
  1571. cnss_pm_stay_awake(plat_priv);
  1572. cnss_pm_relax(plat_priv);
  1573. pm_system_wakeup();
  1574. cnss_bus_handle_dev_sol_irq(plat_priv);
  1575. return IRQ_HANDLED;
  1576. }
  1577. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1578. {
  1579. struct device *dev = &plat_priv->plat_dev->dev;
  1580. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1581. int ret = 0;
  1582. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1583. "wlan-dev-sol-gpio", 0);
  1584. if (sol_gpio->dev_sol_gpio < 0)
  1585. goto out;
  1586. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1587. sol_gpio->dev_sol_gpio);
  1588. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1589. if (ret) {
  1590. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1591. ret);
  1592. goto out;
  1593. }
  1594. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1595. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1596. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1597. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1598. if (ret) {
  1599. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1600. goto free_gpio;
  1601. }
  1602. return 0;
  1603. free_gpio:
  1604. gpio_free(sol_gpio->dev_sol_gpio);
  1605. out:
  1606. return ret;
  1607. }
  1608. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1609. {
  1610. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1611. if (sol_gpio->dev_sol_gpio < 0)
  1612. return;
  1613. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1614. gpio_free(sol_gpio->dev_sol_gpio);
  1615. }
  1616. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1617. {
  1618. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1619. if (sol_gpio->host_sol_gpio < 0)
  1620. return -EINVAL;
  1621. if (value)
  1622. cnss_pr_dbg("Assert host SOL GPIO\n");
  1623. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1624. return 0;
  1625. }
  1626. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1627. {
  1628. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1629. if (sol_gpio->host_sol_gpio < 0)
  1630. return -EINVAL;
  1631. return gpio_get_value(sol_gpio->host_sol_gpio);
  1632. }
  1633. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1634. {
  1635. struct device *dev = &plat_priv->plat_dev->dev;
  1636. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1637. int ret = 0;
  1638. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1639. "wlan-host-sol-gpio", 0);
  1640. if (sol_gpio->host_sol_gpio < 0)
  1641. goto out;
  1642. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1643. sol_gpio->host_sol_gpio);
  1644. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1645. if (ret) {
  1646. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1647. ret);
  1648. goto out;
  1649. }
  1650. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1651. return 0;
  1652. out:
  1653. return ret;
  1654. }
  1655. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1656. {
  1657. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1658. if (sol_gpio->host_sol_gpio < 0)
  1659. return;
  1660. gpio_free(sol_gpio->host_sol_gpio);
  1661. }
  1662. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1663. {
  1664. int ret;
  1665. ret = cnss_init_dev_sol_gpio(plat_priv);
  1666. if (ret)
  1667. goto out;
  1668. ret = cnss_init_host_sol_gpio(plat_priv);
  1669. if (ret)
  1670. goto deinit_dev_sol;
  1671. return 0;
  1672. deinit_dev_sol:
  1673. cnss_deinit_dev_sol_gpio(plat_priv);
  1674. out:
  1675. return ret;
  1676. }
  1677. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1678. {
  1679. cnss_deinit_host_sol_gpio(plat_priv);
  1680. cnss_deinit_dev_sol_gpio(plat_priv);
  1681. }
  1682. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1683. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1684. {
  1685. struct cnss_plat_data *plat_priv;
  1686. int ret = 0;
  1687. if (!subsys_desc->dev) {
  1688. cnss_pr_err("dev from subsys_desc is NULL\n");
  1689. return -ENODEV;
  1690. }
  1691. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1692. if (!plat_priv) {
  1693. cnss_pr_err("plat_priv is NULL\n");
  1694. return -ENODEV;
  1695. }
  1696. if (!plat_priv->driver_state) {
  1697. cnss_pr_dbg("subsys powerup is ignored\n");
  1698. return 0;
  1699. }
  1700. ret = cnss_bus_dev_powerup(plat_priv);
  1701. if (ret)
  1702. __pm_relax(plat_priv->recovery_ws);
  1703. return ret;
  1704. }
  1705. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1706. bool force_stop)
  1707. {
  1708. struct cnss_plat_data *plat_priv;
  1709. if (!subsys_desc->dev) {
  1710. cnss_pr_err("dev from subsys_desc is NULL\n");
  1711. return -ENODEV;
  1712. }
  1713. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1714. if (!plat_priv) {
  1715. cnss_pr_err("plat_priv is NULL\n");
  1716. return -ENODEV;
  1717. }
  1718. if (!plat_priv->driver_state) {
  1719. cnss_pr_dbg("subsys shutdown is ignored\n");
  1720. return 0;
  1721. }
  1722. return cnss_bus_dev_shutdown(plat_priv);
  1723. }
  1724. void cnss_device_crashed(struct device *dev)
  1725. {
  1726. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1727. struct cnss_subsys_info *subsys_info;
  1728. if (!plat_priv)
  1729. return;
  1730. subsys_info = &plat_priv->subsys_info;
  1731. if (subsys_info->subsys_device) {
  1732. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1733. subsys_set_crash_status(subsys_info->subsys_device, true);
  1734. subsystem_restart_dev(subsys_info->subsys_device);
  1735. }
  1736. }
  1737. EXPORT_SYMBOL(cnss_device_crashed);
  1738. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1739. {
  1740. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1741. if (!plat_priv) {
  1742. cnss_pr_err("plat_priv is NULL\n");
  1743. return;
  1744. }
  1745. cnss_bus_dev_crash_shutdown(plat_priv);
  1746. }
  1747. static int cnss_subsys_ramdump(int enable,
  1748. const struct subsys_desc *subsys_desc)
  1749. {
  1750. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1751. if (!plat_priv) {
  1752. cnss_pr_err("plat_priv is NULL\n");
  1753. return -ENODEV;
  1754. }
  1755. if (!enable)
  1756. return 0;
  1757. return cnss_bus_dev_ramdump(plat_priv);
  1758. }
  1759. static void cnss_recovery_work_handler(struct work_struct *work)
  1760. {
  1761. }
  1762. #else
  1763. void cnss_recovery_handler(struct cnss_plat_data *plat_priv)
  1764. {
  1765. int ret;
  1766. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1767. if (!plat_priv->recovery_enabled)
  1768. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1769. cnss_bus_dev_shutdown(plat_priv);
  1770. cnss_bus_dev_ramdump(plat_priv);
  1771. /* If recovery is triggered before Host driver registration,
  1772. * avoid device power up because eventually device will be
  1773. * power up as part of driver registration.
  1774. */
  1775. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state) ||
  1776. !test_bit(CNSS_DRIVER_REGISTERED, &plat_priv->driver_state)) {
  1777. cnss_pr_dbg("Host driver not registered yet, ignore Device Power Up, 0x%lx\n",
  1778. plat_priv->driver_state);
  1779. return;
  1780. }
  1781. msleep(POWER_RESET_MIN_DELAY_MS);
  1782. ret = cnss_bus_dev_powerup(plat_priv);
  1783. if (ret) {
  1784. __pm_relax(plat_priv->recovery_ws);
  1785. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1786. }
  1787. return;
  1788. }
  1789. static void cnss_recovery_work_handler(struct work_struct *work)
  1790. {
  1791. struct cnss_plat_data *plat_priv =
  1792. container_of(work, struct cnss_plat_data, recovery_work);
  1793. cnss_recovery_handler(plat_priv);
  1794. }
  1795. void cnss_device_crashed(struct device *dev)
  1796. {
  1797. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1798. if (!plat_priv)
  1799. return;
  1800. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1801. schedule_work(&plat_priv->recovery_work);
  1802. }
  1803. EXPORT_SYMBOL(cnss_device_crashed);
  1804. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1805. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1806. {
  1807. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1808. struct cnss_ramdump_info *ramdump_info;
  1809. if (!plat_priv)
  1810. return NULL;
  1811. ramdump_info = &plat_priv->ramdump_info;
  1812. *size = ramdump_info->ramdump_size;
  1813. return ramdump_info->ramdump_va;
  1814. }
  1815. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1816. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1817. {
  1818. switch (reason) {
  1819. case CNSS_REASON_DEFAULT:
  1820. return "DEFAULT";
  1821. case CNSS_REASON_LINK_DOWN:
  1822. return "LINK_DOWN";
  1823. case CNSS_REASON_RDDM:
  1824. return "RDDM";
  1825. case CNSS_REASON_TIMEOUT:
  1826. return "TIMEOUT";
  1827. }
  1828. return "UNKNOWN";
  1829. };
  1830. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1831. enum cnss_recovery_reason reason)
  1832. {
  1833. int ret;
  1834. plat_priv->recovery_count++;
  1835. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1836. goto self_recovery;
  1837. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1838. cnss_pr_dbg("Skip device recovery\n");
  1839. return 0;
  1840. }
  1841. /* FW recovery sequence has multiple steps and firmware load requires
  1842. * linux PM in awake state. Thus hold the cnss wake source until
  1843. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1844. * time taken in this process.
  1845. */
  1846. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1847. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1848. true);
  1849. switch (reason) {
  1850. case CNSS_REASON_LINK_DOWN:
  1851. if (!cnss_bus_check_link_status(plat_priv)) {
  1852. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1853. return 0;
  1854. }
  1855. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1856. &plat_priv->ctrl_params.quirks))
  1857. goto self_recovery;
  1858. if (!cnss_bus_recover_link_down(plat_priv)) {
  1859. /* clear recovery bit here to avoid skipping
  1860. * the recovery work for RDDM later
  1861. */
  1862. clear_bit(CNSS_DRIVER_RECOVERY,
  1863. &plat_priv->driver_state);
  1864. return 0;
  1865. }
  1866. break;
  1867. case CNSS_REASON_RDDM:
  1868. cnss_bus_collect_dump_info(plat_priv, false);
  1869. break;
  1870. case CNSS_REASON_DEFAULT:
  1871. case CNSS_REASON_TIMEOUT:
  1872. break;
  1873. default:
  1874. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1875. cnss_recovery_reason_to_str(reason), reason);
  1876. break;
  1877. }
  1878. cnss_bus_device_crashed(plat_priv);
  1879. return 0;
  1880. self_recovery:
  1881. cnss_pr_dbg("Going for self recovery\n");
  1882. cnss_bus_dev_shutdown(plat_priv);
  1883. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1884. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1885. &plat_priv->ctrl_params.quirks);
  1886. /* If link down self recovery is triggered before Host driver
  1887. * registration, avoid device power up because eventually device
  1888. * will be power up as part of driver registration.
  1889. */
  1890. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state) ||
  1891. !test_bit(CNSS_DRIVER_REGISTERED, &plat_priv->driver_state)) {
  1892. cnss_pr_dbg("Host driver not registered yet, ignore Device Power Up, 0x%lx\n",
  1893. plat_priv->driver_state);
  1894. return 0;
  1895. }
  1896. ret = cnss_bus_dev_powerup(plat_priv);
  1897. if (ret)
  1898. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1899. return 0;
  1900. }
  1901. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1902. void *data)
  1903. {
  1904. struct cnss_recovery_data *recovery_data = data;
  1905. int ret = 0;
  1906. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1907. cnss_recovery_reason_to_str(recovery_data->reason),
  1908. recovery_data->reason);
  1909. if (!plat_priv->driver_state) {
  1910. cnss_pr_err("Improper driver state, ignore recovery\n");
  1911. ret = -EINVAL;
  1912. goto out;
  1913. }
  1914. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1915. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1916. ret = -EINVAL;
  1917. goto out;
  1918. }
  1919. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1920. cnss_pr_err("Recovery is already in progress\n");
  1921. CNSS_ASSERT(0);
  1922. ret = -EINVAL;
  1923. goto out;
  1924. }
  1925. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1926. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1927. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1928. ret = -EINVAL;
  1929. goto out;
  1930. }
  1931. switch (plat_priv->device_id) {
  1932. case QCA6174_DEVICE_ID:
  1933. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1934. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1935. &plat_priv->driver_state)) {
  1936. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1937. ret = -EINVAL;
  1938. goto out;
  1939. }
  1940. break;
  1941. default:
  1942. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1943. set_bit(CNSS_FW_BOOT_RECOVERY,
  1944. &plat_priv->driver_state);
  1945. }
  1946. break;
  1947. }
  1948. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1949. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1950. out:
  1951. kfree(data);
  1952. return ret;
  1953. }
  1954. int cnss_self_recovery(struct device *dev,
  1955. enum cnss_recovery_reason reason)
  1956. {
  1957. cnss_schedule_recovery(dev, reason);
  1958. return 0;
  1959. }
  1960. EXPORT_SYMBOL(cnss_self_recovery);
  1961. void cnss_schedule_recovery(struct device *dev,
  1962. enum cnss_recovery_reason reason)
  1963. {
  1964. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1965. struct cnss_recovery_data *data;
  1966. int gfp = GFP_KERNEL;
  1967. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1968. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1969. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1970. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1971. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1972. return;
  1973. }
  1974. if (in_interrupt() || irqs_disabled())
  1975. gfp = GFP_ATOMIC;
  1976. data = kzalloc(sizeof(*data), gfp);
  1977. if (!data)
  1978. return;
  1979. data->reason = reason;
  1980. cnss_driver_event_post(plat_priv,
  1981. CNSS_DRIVER_EVENT_RECOVERY,
  1982. 0, data);
  1983. }
  1984. EXPORT_SYMBOL(cnss_schedule_recovery);
  1985. int cnss_force_fw_assert(struct device *dev)
  1986. {
  1987. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1988. if (!plat_priv) {
  1989. cnss_pr_err("plat_priv is NULL\n");
  1990. return -ENODEV;
  1991. }
  1992. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1993. cnss_pr_info("Forced FW assert is not supported\n");
  1994. return -EOPNOTSUPP;
  1995. }
  1996. if (cnss_bus_is_device_down(plat_priv)) {
  1997. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1998. return 0;
  1999. }
  2000. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  2001. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  2002. return 0;
  2003. }
  2004. if (in_interrupt() || irqs_disabled())
  2005. cnss_driver_event_post(plat_priv,
  2006. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  2007. 0, NULL);
  2008. else
  2009. cnss_bus_force_fw_assert_hdlr(plat_priv);
  2010. return 0;
  2011. }
  2012. EXPORT_SYMBOL(cnss_force_fw_assert);
  2013. int cnss_force_collect_rddm(struct device *dev)
  2014. {
  2015. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2016. unsigned int timeout;
  2017. int ret = 0;
  2018. if (!plat_priv) {
  2019. cnss_pr_err("plat_priv is NULL\n");
  2020. return -ENODEV;
  2021. }
  2022. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  2023. cnss_pr_info("Force collect rddm is not supported\n");
  2024. return -EOPNOTSUPP;
  2025. }
  2026. if (cnss_bus_is_device_down(plat_priv)) {
  2027. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  2028. goto wait_rddm;
  2029. }
  2030. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  2031. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  2032. goto wait_rddm;
  2033. }
  2034. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  2035. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  2036. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  2037. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  2038. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  2039. return 0;
  2040. }
  2041. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  2042. if (ret)
  2043. return ret;
  2044. wait_rddm:
  2045. reinit_completion(&plat_priv->rddm_complete);
  2046. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  2047. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  2048. msecs_to_jiffies(timeout));
  2049. if (!ret) {
  2050. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  2051. timeout);
  2052. ret = -ETIMEDOUT;
  2053. } else if (ret > 0) {
  2054. ret = 0;
  2055. }
  2056. return ret;
  2057. }
  2058. EXPORT_SYMBOL(cnss_force_collect_rddm);
  2059. int cnss_qmi_send_get(struct device *dev)
  2060. {
  2061. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2062. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  2063. return 0;
  2064. return cnss_bus_qmi_send_get(plat_priv);
  2065. }
  2066. EXPORT_SYMBOL(cnss_qmi_send_get);
  2067. int cnss_qmi_send_put(struct device *dev)
  2068. {
  2069. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2070. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  2071. return 0;
  2072. return cnss_bus_qmi_send_put(plat_priv);
  2073. }
  2074. EXPORT_SYMBOL(cnss_qmi_send_put);
  2075. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  2076. int cmd_len, void *cb_ctx,
  2077. int (*cb)(void *ctx, void *event, int event_len))
  2078. {
  2079. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2080. int ret;
  2081. if (!plat_priv)
  2082. return -ENODEV;
  2083. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  2084. return -EINVAL;
  2085. plat_priv->get_info_cb = cb;
  2086. plat_priv->get_info_cb_ctx = cb_ctx;
  2087. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  2088. if (ret) {
  2089. plat_priv->get_info_cb = NULL;
  2090. plat_priv->get_info_cb_ctx = NULL;
  2091. }
  2092. return ret;
  2093. }
  2094. EXPORT_SYMBOL(cnss_qmi_send);
  2095. int cnss_register_driver_async_data_cb(struct device *dev, void *cb_ctx,
  2096. int (*cb)(void *ctx, uint16_t type,
  2097. void *event, int event_len))
  2098. {
  2099. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  2100. if (!plat_priv)
  2101. return -ENODEV;
  2102. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  2103. return -EINVAL;
  2104. plat_priv->get_driver_async_data_cb = cb;
  2105. plat_priv->get_driver_async_data_ctx = cb_ctx;
  2106. return 0;
  2107. }
  2108. EXPORT_SYMBOL(cnss_register_driver_async_data_cb);
  2109. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  2110. {
  2111. int ret = 0;
  2112. u32 retry = 0, timeout;
  2113. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  2114. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  2115. goto out;
  2116. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  2117. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  2118. goto out;
  2119. } else if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  2120. cnss_pr_dbg("Calibration deferred as WLAN device disabled\n");
  2121. goto out;
  2122. }
  2123. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  2124. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  2125. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2126. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  2127. CNSS_ASSERT(0);
  2128. return -EINVAL;
  2129. }
  2130. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  2131. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  2132. break;
  2133. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  2134. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  2135. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  2136. CNSS_ASSERT(0);
  2137. ret = -EINVAL;
  2138. goto mark_cal_fail;
  2139. }
  2140. }
  2141. switch (plat_priv->device_id) {
  2142. case QCA6290_DEVICE_ID:
  2143. case QCA6390_DEVICE_ID:
  2144. case QCA6490_DEVICE_ID:
  2145. case KIWI_DEVICE_ID:
  2146. case MANGO_DEVICE_ID:
  2147. case PEACH_DEVICE_ID:
  2148. break;
  2149. default:
  2150. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2151. plat_priv->device_id);
  2152. ret = -EINVAL;
  2153. goto mark_cal_fail;
  2154. }
  2155. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2156. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  2157. timeout = cnss_get_timeout(plat_priv,
  2158. CNSS_TIMEOUT_CALIBRATION);
  2159. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  2160. timeout / 1000);
  2161. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2162. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2163. msecs_to_jiffies(timeout));
  2164. }
  2165. reinit_completion(&plat_priv->cal_complete);
  2166. ret = cnss_bus_dev_powerup(plat_priv);
  2167. mark_cal_fail:
  2168. if (ret) {
  2169. complete(&plat_priv->cal_complete);
  2170. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2171. /* Set CBC done in driver state to mark attempt and note error
  2172. * since calibration cannot be retried at boot.
  2173. */
  2174. plat_priv->cal_done = CNSS_CAL_FAILURE;
  2175. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  2176. if (plat_priv->device_id == QCA6174_DEVICE_ID ||
  2177. plat_priv->device_id == QCN7605_DEVICE_ID) {
  2178. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  2179. goto out;
  2180. cnss_pr_info("Schedule WLAN driver load\n");
  2181. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2182. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2183. 0);
  2184. }
  2185. }
  2186. out:
  2187. return ret;
  2188. }
  2189. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  2190. void *data)
  2191. {
  2192. struct cnss_cal_info *cal_info = data;
  2193. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  2194. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  2195. goto out;
  2196. switch (cal_info->cal_status) {
  2197. case CNSS_CAL_DONE:
  2198. cnss_pr_dbg("Calibration completed successfully\n");
  2199. plat_priv->cal_done = true;
  2200. break;
  2201. case CNSS_CAL_TIMEOUT:
  2202. case CNSS_CAL_FAILURE:
  2203. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  2204. cal_info->cal_status);
  2205. break;
  2206. default:
  2207. cnss_pr_err("Unknown calibration status: %u\n",
  2208. cal_info->cal_status);
  2209. break;
  2210. }
  2211. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  2212. cnss_bus_free_qdss_mem(plat_priv);
  2213. cnss_release_antenna_sharing(plat_priv);
  2214. if (plat_priv->device_id == QCN7605_DEVICE_ID)
  2215. goto skip_shutdown;
  2216. cnss_bus_dev_shutdown(plat_priv);
  2217. msleep(POWER_RESET_MIN_DELAY_MS);
  2218. skip_shutdown:
  2219. complete(&plat_priv->cal_complete);
  2220. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  2221. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  2222. if (cal_info->cal_status == CNSS_CAL_DONE) {
  2223. cnss_cal_mem_upload_to_file(plat_priv);
  2224. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  2225. goto out;
  2226. cnss_pr_dbg("Schedule WLAN driver load\n");
  2227. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  2228. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  2229. 0);
  2230. }
  2231. out:
  2232. kfree(data);
  2233. return 0;
  2234. }
  2235. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  2236. {
  2237. int ret;
  2238. ret = cnss_bus_dev_powerup(plat_priv);
  2239. if (ret)
  2240. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  2241. return ret;
  2242. }
  2243. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  2244. {
  2245. cnss_bus_dev_shutdown(plat_priv);
  2246. return 0;
  2247. }
  2248. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  2249. {
  2250. int ret = 0;
  2251. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  2252. if (ret < 0)
  2253. return ret;
  2254. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  2255. }
  2256. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  2257. u32 mem_seg_len, u64 pa, u32 size)
  2258. {
  2259. int i = 0;
  2260. u64 offset = 0;
  2261. void *va = NULL;
  2262. u64 local_pa;
  2263. u32 local_size;
  2264. for (i = 0; i < mem_seg_len; i++) {
  2265. if (i == QMI_WLFW_MEM_LPASS_SHARED_V01)
  2266. continue;
  2267. local_pa = (u64)fw_mem[i].pa;
  2268. local_size = (u32)fw_mem[i].size;
  2269. if (pa == local_pa && size <= local_size) {
  2270. va = fw_mem[i].va;
  2271. break;
  2272. }
  2273. if (pa > local_pa &&
  2274. pa < local_pa + local_size &&
  2275. pa + size <= local_pa + local_size) {
  2276. offset = pa - local_pa;
  2277. va = fw_mem[i].va + offset;
  2278. break;
  2279. }
  2280. }
  2281. return va;
  2282. }
  2283. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  2284. void *data)
  2285. {
  2286. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2287. struct cnss_fw_mem *fw_mem_seg;
  2288. int ret = 0L;
  2289. void *va = NULL;
  2290. u32 i, fw_mem_seg_len;
  2291. switch (event_data->mem_type) {
  2292. case QMI_WLFW_MEM_TYPE_DDR_V01:
  2293. if (!plat_priv->fw_mem_seg_len)
  2294. goto invalid_mem_save;
  2295. fw_mem_seg = plat_priv->fw_mem;
  2296. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  2297. break;
  2298. case QMI_WLFW_MEM_QDSS_V01:
  2299. if (!plat_priv->qdss_mem_seg_len)
  2300. goto invalid_mem_save;
  2301. fw_mem_seg = plat_priv->qdss_mem;
  2302. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  2303. break;
  2304. default:
  2305. goto invalid_mem_save;
  2306. }
  2307. for (i = 0; i < event_data->mem_seg_len; i++) {
  2308. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  2309. event_data->mem_seg[i].addr,
  2310. event_data->mem_seg[i].size);
  2311. if (!va) {
  2312. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  2313. &event_data->mem_seg[i].addr,
  2314. event_data->mem_type);
  2315. ret = -EINVAL;
  2316. break;
  2317. }
  2318. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  2319. event_data->file_name,
  2320. event_data->mem_seg[i].size);
  2321. if (ret < 0) {
  2322. cnss_pr_err("Fail to save fw mem data: %d\n",
  2323. ret);
  2324. break;
  2325. }
  2326. }
  2327. kfree(data);
  2328. return ret;
  2329. invalid_mem_save:
  2330. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  2331. event_data->mem_type);
  2332. kfree(data);
  2333. return -EINVAL;
  2334. }
  2335. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  2336. {
  2337. cnss_bus_free_qdss_mem(plat_priv);
  2338. return 0;
  2339. }
  2340. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  2341. void *data)
  2342. {
  2343. int ret = 0;
  2344. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  2345. if (!plat_priv)
  2346. return -ENODEV;
  2347. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  2348. event_data->total_size);
  2349. kfree(data);
  2350. return ret;
  2351. }
  2352. static void cnss_driver_event_work(struct work_struct *work)
  2353. {
  2354. struct cnss_plat_data *plat_priv =
  2355. container_of(work, struct cnss_plat_data, event_work);
  2356. struct cnss_driver_event *event;
  2357. unsigned long flags;
  2358. int ret = 0;
  2359. if (!plat_priv) {
  2360. cnss_pr_err("plat_priv is NULL!\n");
  2361. return;
  2362. }
  2363. cnss_pm_stay_awake(plat_priv);
  2364. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2365. while (!list_empty(&plat_priv->event_list)) {
  2366. event = list_first_entry(&plat_priv->event_list,
  2367. struct cnss_driver_event, list);
  2368. list_del(&event->list);
  2369. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2370. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  2371. cnss_driver_event_to_str(event->type),
  2372. event->sync ? "-sync" : "", event->type,
  2373. plat_priv->driver_state);
  2374. switch (event->type) {
  2375. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  2376. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  2377. break;
  2378. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  2379. ret = cnss_wlfw_server_exit(plat_priv);
  2380. break;
  2381. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  2382. ret = cnss_bus_alloc_fw_mem(plat_priv);
  2383. if (ret)
  2384. break;
  2385. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  2386. break;
  2387. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  2388. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  2389. break;
  2390. case CNSS_DRIVER_EVENT_FW_READY:
  2391. ret = cnss_fw_ready_hdlr(plat_priv);
  2392. break;
  2393. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  2394. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  2395. break;
  2396. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  2397. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  2398. event->data);
  2399. break;
  2400. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  2401. ret = cnss_bus_register_driver_hdlr(plat_priv,
  2402. event->data);
  2403. break;
  2404. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  2405. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  2406. break;
  2407. case CNSS_DRIVER_EVENT_RECOVERY:
  2408. ret = cnss_driver_recovery_hdlr(plat_priv,
  2409. event->data);
  2410. break;
  2411. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  2412. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  2413. break;
  2414. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  2415. set_bit(CNSS_DRIVER_IDLE_RESTART,
  2416. &plat_priv->driver_state);
  2417. fallthrough;
  2418. case CNSS_DRIVER_EVENT_POWER_UP:
  2419. ret = cnss_power_up_hdlr(plat_priv);
  2420. break;
  2421. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  2422. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  2423. &plat_priv->driver_state);
  2424. fallthrough;
  2425. case CNSS_DRIVER_EVENT_POWER_DOWN:
  2426. ret = cnss_power_down_hdlr(plat_priv);
  2427. break;
  2428. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  2429. ret = cnss_process_wfc_call_ind_event(plat_priv,
  2430. event->data);
  2431. break;
  2432. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  2433. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  2434. event->data);
  2435. break;
  2436. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  2437. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  2438. break;
  2439. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  2440. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  2441. event->data);
  2442. break;
  2443. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  2444. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  2445. break;
  2446. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  2447. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  2448. event->data);
  2449. break;
  2450. default:
  2451. cnss_pr_err("Invalid driver event type: %d",
  2452. event->type);
  2453. kfree(event);
  2454. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2455. continue;
  2456. }
  2457. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2458. if (event->sync) {
  2459. event->ret = ret;
  2460. complete(&event->complete);
  2461. continue;
  2462. }
  2463. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2464. kfree(event);
  2465. spin_lock_irqsave(&plat_priv->event_lock, flags);
  2466. }
  2467. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  2468. cnss_pm_relax(plat_priv);
  2469. }
  2470. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  2471. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2472. {
  2473. int ret = 0;
  2474. struct cnss_subsys_info *subsys_info;
  2475. subsys_info = &plat_priv->subsys_info;
  2476. subsys_info->subsys_desc.name = plat_priv->device_name;
  2477. subsys_info->subsys_desc.owner = THIS_MODULE;
  2478. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  2479. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  2480. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  2481. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  2482. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  2483. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  2484. if (IS_ERR(subsys_info->subsys_device)) {
  2485. ret = PTR_ERR(subsys_info->subsys_device);
  2486. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  2487. goto out;
  2488. }
  2489. subsys_info->subsys_handle =
  2490. subsystem_get(subsys_info->subsys_desc.name);
  2491. if (!subsys_info->subsys_handle) {
  2492. cnss_pr_err("Failed to get subsys_handle!\n");
  2493. ret = -EINVAL;
  2494. goto unregister_subsys;
  2495. } else if (IS_ERR(subsys_info->subsys_handle)) {
  2496. ret = PTR_ERR(subsys_info->subsys_handle);
  2497. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  2498. goto unregister_subsys;
  2499. }
  2500. return 0;
  2501. unregister_subsys:
  2502. subsys_unregister(subsys_info->subsys_device);
  2503. out:
  2504. return ret;
  2505. }
  2506. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2507. {
  2508. struct cnss_subsys_info *subsys_info;
  2509. subsys_info = &plat_priv->subsys_info;
  2510. subsystem_put(subsys_info->subsys_handle);
  2511. subsys_unregister(subsys_info->subsys_device);
  2512. }
  2513. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2514. {
  2515. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  2516. return create_ramdump_device(subsys_info->subsys_desc.name,
  2517. subsys_info->subsys_desc.dev);
  2518. }
  2519. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2520. void *ramdump_dev)
  2521. {
  2522. destroy_ramdump_device(ramdump_dev);
  2523. }
  2524. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2525. {
  2526. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2527. struct ramdump_segment segment;
  2528. memset(&segment, 0, sizeof(segment));
  2529. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  2530. segment.size = ramdump_info->ramdump_size;
  2531. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  2532. }
  2533. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2534. {
  2535. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2536. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2537. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2538. struct ramdump_segment *ramdump_segs, *s;
  2539. struct cnss_dump_meta_info meta_info = {0};
  2540. int i, ret = 0;
  2541. ramdump_segs = kcalloc(dump_data->nentries + 1,
  2542. sizeof(*ramdump_segs),
  2543. GFP_KERNEL);
  2544. if (!ramdump_segs)
  2545. return -ENOMEM;
  2546. s = ramdump_segs + 1;
  2547. for (i = 0; i < dump_data->nentries; i++) {
  2548. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2549. cnss_pr_err("Unsupported dump type: %d",
  2550. dump_seg->type);
  2551. continue;
  2552. }
  2553. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2554. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2555. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2556. }
  2557. meta_info.entry[dump_seg->type].entry_num++;
  2558. s->address = dump_seg->address;
  2559. s->v_address = (void __iomem *)dump_seg->v_address;
  2560. s->size = dump_seg->size;
  2561. s++;
  2562. dump_seg++;
  2563. }
  2564. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2565. meta_info.version = CNSS_RAMDUMP_VERSION;
  2566. meta_info.chipset = plat_priv->device_id;
  2567. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2568. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2569. ramdump_segs->size = sizeof(meta_info);
  2570. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2571. dump_data->nentries + 1);
  2572. kfree(ramdump_segs);
  2573. return ret;
  2574. }
  2575. #else
  2576. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2577. void *data)
  2578. {
  2579. struct cnss_plat_data *plat_priv =
  2580. container_of(nb, struct cnss_plat_data, panic_nb);
  2581. cnss_bus_dev_crash_shutdown(plat_priv);
  2582. return NOTIFY_DONE;
  2583. }
  2584. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2585. {
  2586. int ret;
  2587. if (!plat_priv)
  2588. return -ENODEV;
  2589. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2590. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2591. &plat_priv->panic_nb);
  2592. if (ret) {
  2593. cnss_pr_err("Failed to register panic handler\n");
  2594. return -EINVAL;
  2595. }
  2596. return 0;
  2597. }
  2598. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2599. {
  2600. int ret;
  2601. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2602. &plat_priv->panic_nb);
  2603. if (ret)
  2604. cnss_pr_err("Failed to unregister panic handler\n");
  2605. }
  2606. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2607. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2608. {
  2609. return &plat_priv->plat_dev->dev;
  2610. }
  2611. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2612. void *ramdump_dev)
  2613. {
  2614. }
  2615. #endif
  2616. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2617. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2618. {
  2619. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2620. struct qcom_dump_segment segment;
  2621. struct list_head head;
  2622. if (!dump_enabled()) {
  2623. cnss_pr_info("Dump collection is not enabled\n");
  2624. return 0;
  2625. }
  2626. INIT_LIST_HEAD(&head);
  2627. memset(&segment, 0, sizeof(segment));
  2628. segment.va = ramdump_info->ramdump_va;
  2629. segment.size = ramdump_info->ramdump_size;
  2630. list_add(&segment.node, &head);
  2631. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2632. }
  2633. #else
  2634. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2635. {
  2636. return 0;
  2637. }
  2638. /* Using completion event inside dynamically allocated ramdump_desc
  2639. * may result a race between freeing the event after setting it to
  2640. * complete inside dev coredump free callback and the thread that is
  2641. * waiting for completion.
  2642. */
  2643. DECLARE_COMPLETION(dump_done);
  2644. #define TIMEOUT_SAVE_DUMP_MS 30000
  2645. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2646. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2647. { \
  2648. if (class == ELFCLASS32) \
  2649. return sizeof(struct elf32_##__xhdr); \
  2650. else \
  2651. return sizeof(struct elf64_##__xhdr); \
  2652. }
  2653. SIZEOF_ELF_STRUCT(phdr)
  2654. SIZEOF_ELF_STRUCT(hdr)
  2655. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2656. do { \
  2657. if (class == ELFCLASS32) \
  2658. ((struct elf32_##__xhdr *)arg)->member = value; \
  2659. else \
  2660. ((struct elf64_##__xhdr *)arg)->member = value; \
  2661. } while (0)
  2662. #define set_ehdr_property(arg, class, member, value) \
  2663. set_xhdr_property(hdr, arg, class, member, value)
  2664. #define set_phdr_property(arg, class, member, value) \
  2665. set_xhdr_property(phdr, arg, class, member, value)
  2666. /* These replace qcom_ramdump driver APIs called from common API
  2667. * cnss_do_elf_dump() by the ones defined here.
  2668. */
  2669. #define qcom_dump_segment cnss_qcom_dump_segment
  2670. #define qcom_elf_dump cnss_qcom_elf_dump
  2671. #define dump_enabled cnss_dump_enabled
  2672. struct cnss_qcom_dump_segment {
  2673. struct list_head node;
  2674. dma_addr_t da;
  2675. void *va;
  2676. size_t size;
  2677. };
  2678. struct cnss_qcom_ramdump_desc {
  2679. void *data;
  2680. struct completion dump_done;
  2681. };
  2682. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2683. void *data, size_t datalen)
  2684. {
  2685. struct cnss_qcom_ramdump_desc *desc = data;
  2686. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2687. datalen);
  2688. }
  2689. static void cnss_qcom_devcd_freev(void *data)
  2690. {
  2691. struct cnss_qcom_ramdump_desc *desc = data;
  2692. cnss_pr_dbg("Free dump data for dev coredump\n");
  2693. complete(&dump_done);
  2694. vfree(desc->data);
  2695. kfree(desc);
  2696. }
  2697. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2698. gfp_t gfp)
  2699. {
  2700. struct cnss_qcom_ramdump_desc *desc;
  2701. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2702. int ret;
  2703. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2704. if (!desc)
  2705. return -ENOMEM;
  2706. desc->data = data;
  2707. reinit_completion(&dump_done);
  2708. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2709. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2710. ret = wait_for_completion_timeout(&dump_done,
  2711. msecs_to_jiffies(timeout));
  2712. if (!ret)
  2713. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2714. timeout);
  2715. return ret ? 0 : -ETIMEDOUT;
  2716. }
  2717. /* Since the elf32 and elf64 identification is identical apart from
  2718. * the class, use elf32 by default.
  2719. */
  2720. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2721. {
  2722. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2723. ehdr->e_ident[EI_CLASS] = class;
  2724. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2725. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2726. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2727. }
  2728. static int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2729. unsigned char class)
  2730. {
  2731. struct cnss_qcom_dump_segment *segment;
  2732. void *phdr, *ehdr;
  2733. size_t data_size, offset;
  2734. int phnum = 0;
  2735. void *data;
  2736. void __iomem *ptr;
  2737. if (!segs || list_empty(segs))
  2738. return -EINVAL;
  2739. data_size = sizeof_elf_hdr(class);
  2740. list_for_each_entry(segment, segs, node) {
  2741. data_size += sizeof_elf_phdr(class) + segment->size;
  2742. phnum++;
  2743. }
  2744. data = vmalloc(data_size);
  2745. if (!data)
  2746. return -ENOMEM;
  2747. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2748. ehdr = data;
  2749. memset(ehdr, 0, sizeof_elf_hdr(class));
  2750. init_elf_identification(ehdr, class);
  2751. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2752. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2753. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2754. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2755. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2756. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2757. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2758. phdr = data + sizeof_elf_hdr(class);
  2759. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2760. list_for_each_entry(segment, segs, node) {
  2761. memset(phdr, 0, sizeof_elf_phdr(class));
  2762. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2763. set_phdr_property(phdr, class, p_offset, offset);
  2764. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2765. set_phdr_property(phdr, class, p_paddr, segment->da);
  2766. set_phdr_property(phdr, class, p_filesz, segment->size);
  2767. set_phdr_property(phdr, class, p_memsz, segment->size);
  2768. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2769. set_phdr_property(phdr, class, p_align, 0);
  2770. if (segment->va) {
  2771. memcpy(data + offset, segment->va, segment->size);
  2772. } else {
  2773. ptr = devm_ioremap(dev, segment->da, segment->size);
  2774. if (!ptr) {
  2775. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2776. &segment->da, segment->size);
  2777. memset(data + offset, 0xff, segment->size);
  2778. } else {
  2779. memcpy_fromio(data + offset, ptr,
  2780. segment->size);
  2781. }
  2782. }
  2783. offset += segment->size;
  2784. phdr += sizeof_elf_phdr(class);
  2785. }
  2786. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2787. }
  2788. /* Saving dump to file system is always needed in this case. */
  2789. static bool cnss_dump_enabled(void)
  2790. {
  2791. return true;
  2792. }
  2793. #endif /* CONFIG_QCOM_RAMDUMP */
  2794. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2795. {
  2796. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2797. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2798. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2799. struct qcom_dump_segment *seg;
  2800. struct cnss_dump_meta_info meta_info = {0};
  2801. struct list_head head;
  2802. int i, ret = 0;
  2803. if (!dump_enabled()) {
  2804. cnss_pr_info("Dump collection is not enabled\n");
  2805. return ret;
  2806. }
  2807. INIT_LIST_HEAD(&head);
  2808. for (i = 0; i < dump_data->nentries; i++) {
  2809. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2810. cnss_pr_err("Unsupported dump type: %d",
  2811. dump_seg->type);
  2812. continue;
  2813. }
  2814. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2815. if (!seg) {
  2816. cnss_pr_err("%s: Failed to allocate mem for seg %d\n",
  2817. __func__, i);
  2818. continue;
  2819. }
  2820. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2821. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2822. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2823. }
  2824. meta_info.entry[dump_seg->type].entry_num++;
  2825. seg->da = dump_seg->address;
  2826. seg->va = dump_seg->v_address;
  2827. seg->size = dump_seg->size;
  2828. list_add_tail(&seg->node, &head);
  2829. dump_seg++;
  2830. }
  2831. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2832. if (!seg) {
  2833. cnss_pr_err("%s: Failed to allocate mem for elf ramdump seg\n",
  2834. __func__);
  2835. goto skip_elf_dump;
  2836. }
  2837. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2838. meta_info.version = CNSS_RAMDUMP_VERSION;
  2839. meta_info.chipset = plat_priv->device_id;
  2840. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2841. seg->va = &meta_info;
  2842. seg->size = sizeof(meta_info);
  2843. list_add(&seg->node, &head);
  2844. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2845. skip_elf_dump:
  2846. while (!list_empty(&head)) {
  2847. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2848. list_del(&seg->node);
  2849. kfree(seg);
  2850. }
  2851. return ret;
  2852. }
  2853. #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP
  2854. /**
  2855. * cnss_host_ramdump_dev_release() - callback function for device release
  2856. * @dev: device to be released
  2857. *
  2858. * Return: None
  2859. */
  2860. static void cnss_host_ramdump_dev_release(struct device *dev)
  2861. {
  2862. cnss_pr_dbg("free host ramdump device\n");
  2863. kfree(dev);
  2864. }
  2865. int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
  2866. struct cnss_ssr_driver_dump_entry *ssr_entry,
  2867. size_t num_entries_loaded)
  2868. {
  2869. struct qcom_dump_segment *seg;
  2870. struct cnss_host_dump_meta_info meta_info = {0};
  2871. struct list_head head;
  2872. int dev_ret = 0;
  2873. struct device *new_device;
  2874. static const char * const wlan_str[] = {
  2875. [CNSS_HOST_WLAN_LOGS] = "wlan_logs",
  2876. [CNSS_HOST_HTC_CREDIT] = "htc_credit",
  2877. [CNSS_HOST_WMI_TX_CMP] = "wmi_tx_cmp",
  2878. [CNSS_HOST_WMI_COMMAND_LOG] = "wmi_command_log",
  2879. [CNSS_HOST_WMI_EVENT_LOG] = "wmi_event_log",
  2880. [CNSS_HOST_WMI_RX_EVENT] = "wmi_rx_event",
  2881. [CNSS_HOST_HAL_SOC] = "hal_soc",
  2882. [CNSS_HOST_GWLAN_LOGGING] = "gwlan_logging",
  2883. [CNSS_HOST_WMI_DEBUG_LOG_INFO] = "wmi_debug_log_info",
  2884. [CNSS_HOST_HTC_CREDIT_IDX] = "htc_credit_history_idx",
  2885. [CNSS_HOST_HTC_CREDIT_LEN] = "htc_credit_history_length",
  2886. [CNSS_HOST_WMI_TX_CMP_IDX] = "wmi_tx_cmp_idx",
  2887. [CNSS_HOST_WMI_COMMAND_LOG_IDX] = "wmi_command_log_idx",
  2888. [CNSS_HOST_WMI_EVENT_LOG_IDX] = "wmi_event_log_idx",
  2889. [CNSS_HOST_WMI_RX_EVENT_IDX] = "wmi_rx_event_idx",
  2890. [CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF] = "hif_ce_desc_history_buff",
  2891. [CNSS_HOST_HANG_EVENT_DATA] = "hang_event_data",
  2892. [CNSS_HOST_CE_DESC_HIST] = "hif_ce_desc_hist",
  2893. [CNSS_HOST_CE_COUNT_MAX] = "hif_ce_count_max",
  2894. [CNSS_HOST_CE_HISTORY_MAX] = "hif_ce_history_max",
  2895. [CNSS_HOST_ONLY_FOR_CRIT_CE] = "hif_ce_only_for_crit",
  2896. [CNSS_HOST_HIF_EVENT_HISTORY] = "hif_event_history",
  2897. [CNSS_HOST_HIF_EVENT_HIST_MAX] = "hif_event_hist_max",
  2898. [CNSS_HOST_DP_WBM_DESC_REL] = "wbm_desc_rel_ring",
  2899. [CNSS_HOST_DP_WBM_DESC_REL_HANDLE] = "wbm_desc_rel_ring_handle",
  2900. [CNSS_HOST_DP_TCL_CMD] = "tcl_cmd_ring",
  2901. [CNSS_HOST_DP_TCL_CMD_HANDLE] = "tcl_cmd_ring_handle",
  2902. [CNSS_HOST_DP_TCL_STATUS] = "tcl_status_ring",
  2903. [CNSS_HOST_DP_TCL_STATUS_HANDLE] = "tcl_status_ring_handle",
  2904. [CNSS_HOST_DP_REO_REINJ] = "reo_reinject_ring",
  2905. [CNSS_HOST_DP_REO_REINJ_HANDLE] = "reo_reinject_ring_handle",
  2906. [CNSS_HOST_DP_RX_REL] = "rx_rel_ring",
  2907. [CNSS_HOST_DP_RX_REL_HANDLE] = "rx_rel_ring_handle",
  2908. [CNSS_HOST_DP_REO_EXP] = "reo_exception_ring",
  2909. [CNSS_HOST_DP_REO_EXP_HANDLE] = "reo_exception_ring_handle",
  2910. [CNSS_HOST_DP_REO_CMD] = "reo_cmd_ring",
  2911. [CNSS_HOST_DP_REO_CMD_HANDLE] = "reo_cmd_ring_handle",
  2912. [CNSS_HOST_DP_REO_STATUS] = "reo_status_ring",
  2913. [CNSS_HOST_DP_REO_STATUS_HANDLE] = "reo_status_ring_handle",
  2914. [CNSS_HOST_DP_TCL_DATA_0] = "tcl_data_ring_0",
  2915. [CNSS_HOST_DP_TCL_DATA_0_HANDLE] = "tcl_data_ring_0_handle",
  2916. [CNSS_HOST_DP_TX_COMP_0] = "tx_comp_ring_0",
  2917. [CNSS_HOST_DP_TX_COMP_0_HANDLE] = "tx_comp_ring_0_handle",
  2918. [CNSS_HOST_DP_TCL_DATA_1] = "tcl_data_ring_1",
  2919. [CNSS_HOST_DP_TCL_DATA_1_HANDLE] = "tcl_data_ring_1_handle",
  2920. [CNSS_HOST_DP_TX_COMP_1] = "tx_comp_ring_1",
  2921. [CNSS_HOST_DP_TX_COMP_1_HANDLE] = "tx_comp_ring_1_handle",
  2922. [CNSS_HOST_DP_TCL_DATA_2] = "tcl_data_ring_2",
  2923. [CNSS_HOST_DP_TCL_DATA_2_HANDLE] = "tcl_data_ring_2_handle",
  2924. [CNSS_HOST_DP_TX_COMP_2] = "tx_comp_ring_2",
  2925. [CNSS_HOST_DP_TX_COMP_2_HANDLE] = "tx_comp_ring_2_handle",
  2926. [CNSS_HOST_DP_REO_DST_0] = "reo_dest_ring_0",
  2927. [CNSS_HOST_DP_REO_DST_0_HANDLE] = "reo_dest_ring_0_handle",
  2928. [CNSS_HOST_DP_REO_DST_1] = "reo_dest_ring_1",
  2929. [CNSS_HOST_DP_REO_DST_1_HANDLE] = "reo_dest_ring_1_handle",
  2930. [CNSS_HOST_DP_REO_DST_2] = "reo_dest_ring_2",
  2931. [CNSS_HOST_DP_REO_DST_2_HANDLE] = "reo_dest_ring_2_handle",
  2932. [CNSS_HOST_DP_REO_DST_3] = "reo_dest_ring_3",
  2933. [CNSS_HOST_DP_REO_DST_3_HANDLE] = "reo_dest_ring_3_handle",
  2934. [CNSS_HOST_DP_REO_DST_4] = "reo_dest_ring_4",
  2935. [CNSS_HOST_DP_REO_DST_4_HANDLE] = "reo_dest_ring_4_handle",
  2936. [CNSS_HOST_DP_REO_DST_5] = "reo_dest_ring_5",
  2937. [CNSS_HOST_DP_REO_DST_5_HANDLE] = "reo_dest_ring_5_handle",
  2938. [CNSS_HOST_DP_REO_DST_6] = "reo_dest_ring_6",
  2939. [CNSS_HOST_DP_REO_DST_6_HANDLE] = "reo_dest_ring_6_handle",
  2940. [CNSS_HOST_DP_REO_DST_7] = "reo_dest_ring_7",
  2941. [CNSS_HOST_DP_REO_DST_7_HANDLE] = "reo_dest_ring_7_handle",
  2942. [CNSS_HOST_DP_PDEV_0] = "dp_pdev_0",
  2943. [CNSS_HOST_DP_WLAN_CFG_CTX] = "wlan_cfg_ctx",
  2944. [CNSS_HOST_DP_SOC] = "dp_soc",
  2945. [CNSS_HOST_HAL_RX_FST] = "hal_rx_fst",
  2946. [CNSS_HOST_DP_FISA] = "dp_fisa",
  2947. [CNSS_HOST_DP_FISA_HW_FSE_TABLE] = "dp_fisa_hw_fse_table",
  2948. [CNSS_HOST_DP_FISA_SW_FSE_TABLE] = "dp_fisa_sw_fse_table",
  2949. [CNSS_HOST_HIF] = "hif",
  2950. [CNSS_HOST_QDF_NBUF_HIST] = "qdf_nbuf_history",
  2951. [CNSS_HOST_TCL_WBM_MAP] = "tcl_wbm_map_array",
  2952. [CNSS_HOST_RX_MAC_BUF_RING_0] = "rx_mac_buf_ring_0",
  2953. [CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE] = "rx_mac_buf_ring_0_handle",
  2954. [CNSS_HOST_RX_MAC_BUF_RING_1] = "rx_mac_buf_ring_1",
  2955. [CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE] = "rx_mac_buf_ring_1_handle",
  2956. [CNSS_HOST_RX_REFILL_0] = "rx_refill_buf_ring_0",
  2957. [CNSS_HOST_RX_REFILL_0_HANDLE] = "rx_refill_buf_ring_0_handle",
  2958. [CNSS_HOST_CE_0] = "ce_0",
  2959. [CNSS_HOST_CE_0_SRC_RING] = "ce_0_src_ring",
  2960. [CNSS_HOST_CE_0_SRC_RING_CTX] = "ce_0_src_ring_ctx",
  2961. [CNSS_HOST_CE_1] = "ce_1",
  2962. [CNSS_HOST_CE_1_STATUS_RING] = "ce_1_status_ring",
  2963. [CNSS_HOST_CE_1_STATUS_RING_CTX] = "ce_1_status_ring_ctx",
  2964. [CNSS_HOST_CE_1_DEST_RING] = "ce_1_dest_ring",
  2965. [CNSS_HOST_CE_1_DEST_RING_CTX] = "ce_1_dest_ring_ctx",
  2966. [CNSS_HOST_CE_2] = "ce_2",
  2967. [CNSS_HOST_CE_2_STATUS_RING] = "ce_2_status_ring",
  2968. [CNSS_HOST_CE_2_STATUS_RING_CTX] = "ce_2_status_ring_ctx",
  2969. [CNSS_HOST_CE_2_DEST_RING] = "ce_2_dest_ring",
  2970. [CNSS_HOST_CE_2_DEST_RING_CTX] = "ce_2_dest_ring_ctx",
  2971. [CNSS_HOST_CE_3] = "ce_3",
  2972. [CNSS_HOST_CE_3_SRC_RING] = "ce_3_src_ring",
  2973. [CNSS_HOST_CE_3_SRC_RING_CTX] = "ce_3_src_ring_ctx",
  2974. [CNSS_HOST_CE_4] = "ce_4",
  2975. [CNSS_HOST_CE_4_SRC_RING] = "ce_4_src_ring",
  2976. [CNSS_HOST_CE_4_SRC_RING_CTX] = "ce_4_src_ring_ctx",
  2977. [CNSS_HOST_CE_5] = "ce_5",
  2978. [CNSS_HOST_CE_6] = "ce_6",
  2979. [CNSS_HOST_CE_7] = "ce_7",
  2980. [CNSS_HOST_CE_7_STATUS_RING] = "ce_7_status_ring",
  2981. [CNSS_HOST_CE_7_STATUS_RING_CTX] = "ce_7_status_ring_ctx",
  2982. [CNSS_HOST_CE_7_DEST_RING] = "ce_7_dest_ring",
  2983. [CNSS_HOST_CE_7_DEST_RING_CTX] = "ce_7_dest_ring_ctx",
  2984. [CNSS_HOST_CE_8] = "ce_8",
  2985. [CNSS_HOST_DP_TCL_DATA_3] = "tcl_data_ring_3",
  2986. [CNSS_HOST_DP_TCL_DATA_3_HANDLE] = "tcl_data_ring_3_handle",
  2987. [CNSS_HOST_DP_TX_COMP_3] = "tx_comp_ring_3",
  2988. [CNSS_HOST_DP_TX_COMP_3_HANDLE] = "tx_comp_ring_3_handle"
  2989. };
  2990. int i;
  2991. int ret = 0;
  2992. enum cnss_host_dump_type j;
  2993. if (!dump_enabled()) {
  2994. cnss_pr_info("Dump collection is not enabled\n");
  2995. return ret;
  2996. }
  2997. new_device = kcalloc(1, sizeof(*new_device), GFP_KERNEL);
  2998. if (!new_device) {
  2999. cnss_pr_err("Failed to alloc device mem\n");
  3000. return -ENOMEM;
  3001. }
  3002. new_device->release = cnss_host_ramdump_dev_release;
  3003. device_initialize(new_device);
  3004. dev_set_name(new_device, "wlan_driver");
  3005. dev_ret = device_add(new_device);
  3006. if (dev_ret) {
  3007. cnss_pr_err("Failed to add new device\n");
  3008. goto put_device;
  3009. }
  3010. INIT_LIST_HEAD(&head);
  3011. for (i = 0; i < num_entries_loaded; i++) {
  3012. /* If region name registered by driver is not present in
  3013. * wlan_str. type for that entry will not be set, but entry will
  3014. * be added. Which will result in entry type being 0. Currently
  3015. * entry type 0 is for wlan_logs, which will result in parsing
  3016. * issue for wlan_logs as parsing is done based upon type field.
  3017. * So initialize type with -1(Invalid) to avoid such issues.
  3018. */
  3019. meta_info.entry[i].type = -1;
  3020. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  3021. if (!seg) {
  3022. cnss_pr_err("Failed to alloc seg entry %d\n", i);
  3023. continue;
  3024. }
  3025. seg->va = ssr_entry[i].buffer_pointer;
  3026. seg->da = (dma_addr_t)ssr_entry[i].buffer_pointer;
  3027. seg->size = ssr_entry[i].buffer_size;
  3028. for (j = 0; j < CNSS_HOST_DUMP_TYPE_MAX; j++) {
  3029. if (strcmp(ssr_entry[i].region_name, wlan_str[j]) == 0) {
  3030. meta_info.entry[i].type = j;
  3031. }
  3032. }
  3033. meta_info.entry[i].entry_start = i + 1;
  3034. meta_info.entry[i].entry_num++;
  3035. list_add_tail(&seg->node, &head);
  3036. }
  3037. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  3038. if (!seg) {
  3039. cnss_pr_err("%s: Failed to allocate mem for host dump seg\n",
  3040. __func__);
  3041. goto skip_host_dump;
  3042. }
  3043. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  3044. meta_info.version = CNSS_RAMDUMP_VERSION;
  3045. meta_info.chipset = plat_priv->device_id;
  3046. meta_info.total_entries = num_entries_loaded;
  3047. seg->va = &meta_info;
  3048. seg->da = (dma_addr_t)&meta_info;
  3049. seg->size = sizeof(meta_info);
  3050. list_add(&seg->node, &head);
  3051. ret = qcom_elf_dump(&head, new_device, ELF_CLASS);
  3052. skip_host_dump:
  3053. while (!list_empty(&head)) {
  3054. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  3055. list_del(&seg->node);
  3056. kfree(seg);
  3057. }
  3058. device_del(new_device);
  3059. put_device:
  3060. put_device(new_device);
  3061. cnss_pr_dbg("host ramdump result %d\n", ret);
  3062. return ret;
  3063. }
  3064. #endif
  3065. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  3066. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  3067. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  3068. {
  3069. struct cnss_ramdump_info *ramdump_info;
  3070. struct msm_dump_entry dump_entry;
  3071. ramdump_info = &plat_priv->ramdump_info;
  3072. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  3073. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  3074. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  3075. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  3076. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  3077. sizeof(ramdump_info->dump_data.name));
  3078. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3079. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  3080. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  3081. &dump_entry);
  3082. }
  3083. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  3084. {
  3085. int ret = 0;
  3086. struct device *dev;
  3087. struct cnss_ramdump_info *ramdump_info;
  3088. u32 ramdump_size = 0;
  3089. dev = &plat_priv->plat_dev->dev;
  3090. ramdump_info = &plat_priv->ramdump_info;
  3091. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  3092. /* dt type: legacy or converged */
  3093. ret = of_property_read_u32(dev->of_node,
  3094. "qcom,wlan-ramdump-dynamic",
  3095. &ramdump_size);
  3096. } else {
  3097. ret = of_property_read_u32(plat_priv->dev_node,
  3098. "qcom,wlan-ramdump-dynamic",
  3099. &ramdump_size);
  3100. }
  3101. if (ret == 0) {
  3102. ramdump_info->ramdump_va =
  3103. dma_alloc_coherent(dev, ramdump_size,
  3104. &ramdump_info->ramdump_pa,
  3105. GFP_KERNEL);
  3106. if (ramdump_info->ramdump_va)
  3107. ramdump_info->ramdump_size = ramdump_size;
  3108. }
  3109. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  3110. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  3111. if (ramdump_info->ramdump_size == 0) {
  3112. cnss_pr_info("Ramdump will not be collected");
  3113. goto out;
  3114. }
  3115. ret = cnss_init_dump_entry(plat_priv);
  3116. if (ret) {
  3117. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  3118. goto free_ramdump;
  3119. }
  3120. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  3121. if (!ramdump_info->ramdump_dev) {
  3122. cnss_pr_err("Failed to create ramdump device!");
  3123. ret = -ENOMEM;
  3124. goto free_ramdump;
  3125. }
  3126. return 0;
  3127. free_ramdump:
  3128. dma_free_coherent(dev, ramdump_info->ramdump_size,
  3129. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  3130. out:
  3131. return ret;
  3132. }
  3133. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  3134. {
  3135. struct device *dev;
  3136. struct cnss_ramdump_info *ramdump_info;
  3137. dev = &plat_priv->plat_dev->dev;
  3138. ramdump_info = &plat_priv->ramdump_info;
  3139. if (ramdump_info->ramdump_dev)
  3140. cnss_destroy_ramdump_device(plat_priv,
  3141. ramdump_info->ramdump_dev);
  3142. if (ramdump_info->ramdump_va)
  3143. dma_free_coherent(dev, ramdump_info->ramdump_size,
  3144. ramdump_info->ramdump_va,
  3145. ramdump_info->ramdump_pa);
  3146. }
  3147. /**
  3148. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  3149. * @ret: Error returned by msm_dump_data_register_nominidump
  3150. *
  3151. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  3152. * ignore failure.
  3153. *
  3154. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  3155. */
  3156. static int cnss_ignore_dump_data_reg_fail(int ret)
  3157. {
  3158. return ret;
  3159. }
  3160. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  3161. {
  3162. int ret = 0;
  3163. struct cnss_ramdump_info_v2 *info_v2;
  3164. struct cnss_dump_data *dump_data;
  3165. struct msm_dump_entry dump_entry;
  3166. struct device *dev = &plat_priv->plat_dev->dev;
  3167. u32 ramdump_size = 0;
  3168. info_v2 = &plat_priv->ramdump_info_v2;
  3169. dump_data = &info_v2->dump_data;
  3170. if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG) {
  3171. /* dt type: legacy or converged */
  3172. ret = of_property_read_u32(dev->of_node,
  3173. "qcom,wlan-ramdump-dynamic",
  3174. &ramdump_size);
  3175. } else {
  3176. ret = of_property_read_u32(plat_priv->dev_node,
  3177. "qcom,wlan-ramdump-dynamic",
  3178. &ramdump_size);
  3179. }
  3180. if (ret == 0)
  3181. info_v2->ramdump_size = ramdump_size;
  3182. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  3183. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  3184. if (!info_v2->dump_data_vaddr)
  3185. return -ENOMEM;
  3186. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  3187. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  3188. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  3189. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  3190. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  3191. sizeof(dump_data->name));
  3192. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3193. dump_entry.addr = virt_to_phys(dump_data);
  3194. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  3195. &dump_entry);
  3196. if (ret) {
  3197. ret = cnss_ignore_dump_data_reg_fail(ret);
  3198. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  3199. ret ? "Error" : "Ignoring", ret);
  3200. goto free_ramdump;
  3201. }
  3202. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  3203. if (!info_v2->ramdump_dev) {
  3204. cnss_pr_err("Failed to create ramdump device!\n");
  3205. ret = -ENOMEM;
  3206. goto free_ramdump;
  3207. }
  3208. return 0;
  3209. free_ramdump:
  3210. kfree(info_v2->dump_data_vaddr);
  3211. info_v2->dump_data_vaddr = NULL;
  3212. return ret;
  3213. }
  3214. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  3215. {
  3216. struct cnss_ramdump_info_v2 *info_v2;
  3217. info_v2 = &plat_priv->ramdump_info_v2;
  3218. if (info_v2->ramdump_dev)
  3219. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  3220. kfree(info_v2->dump_data_vaddr);
  3221. info_v2->dump_data_vaddr = NULL;
  3222. info_v2->dump_data_valid = false;
  3223. }
  3224. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  3225. {
  3226. int ret = 0;
  3227. switch (plat_priv->device_id) {
  3228. case QCA6174_DEVICE_ID:
  3229. ret = cnss_register_ramdump_v1(plat_priv);
  3230. break;
  3231. case QCA6290_DEVICE_ID:
  3232. case QCA6390_DEVICE_ID:
  3233. case QCN7605_DEVICE_ID:
  3234. case QCA6490_DEVICE_ID:
  3235. case KIWI_DEVICE_ID:
  3236. case MANGO_DEVICE_ID:
  3237. case PEACH_DEVICE_ID:
  3238. ret = cnss_register_ramdump_v2(plat_priv);
  3239. break;
  3240. default:
  3241. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  3242. ret = -ENODEV;
  3243. break;
  3244. }
  3245. return ret;
  3246. }
  3247. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  3248. {
  3249. switch (plat_priv->device_id) {
  3250. case QCA6174_DEVICE_ID:
  3251. cnss_unregister_ramdump_v1(plat_priv);
  3252. break;
  3253. case QCA6290_DEVICE_ID:
  3254. case QCA6390_DEVICE_ID:
  3255. case QCN7605_DEVICE_ID:
  3256. case QCA6490_DEVICE_ID:
  3257. case KIWI_DEVICE_ID:
  3258. case MANGO_DEVICE_ID:
  3259. case PEACH_DEVICE_ID:
  3260. cnss_unregister_ramdump_v2(plat_priv);
  3261. break;
  3262. default:
  3263. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  3264. break;
  3265. }
  3266. }
  3267. #else
  3268. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  3269. {
  3270. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  3271. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  3272. struct device *dev = &plat_priv->plat_dev->dev;
  3273. u32 ramdump_size = 0;
  3274. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  3275. &ramdump_size) == 0)
  3276. info_v2->ramdump_size = ramdump_size;
  3277. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  3278. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  3279. if (!info_v2->dump_data_vaddr)
  3280. return -ENOMEM;
  3281. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  3282. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  3283. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  3284. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  3285. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  3286. sizeof(dump_data->name));
  3287. info_v2->ramdump_dev = dev;
  3288. return 0;
  3289. }
  3290. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  3291. {
  3292. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  3293. info_v2->ramdump_dev = NULL;
  3294. kfree(info_v2->dump_data_vaddr);
  3295. info_v2->dump_data_vaddr = NULL;
  3296. info_v2->dump_data_valid = false;
  3297. }
  3298. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  3299. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  3300. phys_addr_t *pa, unsigned long attrs)
  3301. {
  3302. struct sg_table sgt;
  3303. int ret;
  3304. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  3305. if (ret) {
  3306. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  3307. va, &dma, size, attrs);
  3308. return -EINVAL;
  3309. }
  3310. *pa = page_to_phys(sg_page(sgt.sgl));
  3311. sg_free_table(&sgt);
  3312. return 0;
  3313. }
  3314. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  3315. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  3316. enum cnss_fw_dump_type type, int seg_no,
  3317. void *va, phys_addr_t pa, size_t size)
  3318. {
  3319. struct md_region md_entry;
  3320. int ret;
  3321. switch (type) {
  3322. case CNSS_FW_IMAGE:
  3323. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  3324. seg_no);
  3325. break;
  3326. case CNSS_FW_RDDM:
  3327. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  3328. seg_no);
  3329. break;
  3330. case CNSS_FW_REMOTE_HEAP:
  3331. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  3332. seg_no);
  3333. break;
  3334. default:
  3335. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3336. return -EINVAL;
  3337. }
  3338. md_entry.phys_addr = pa;
  3339. md_entry.virt_addr = (uintptr_t)va;
  3340. md_entry.size = size;
  3341. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3342. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3343. md_entry.name, va, &pa, size);
  3344. ret = msm_minidump_add_region(&md_entry);
  3345. if (ret < 0)
  3346. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  3347. return ret;
  3348. }
  3349. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  3350. enum cnss_fw_dump_type type, int seg_no,
  3351. void *va, phys_addr_t pa, size_t size)
  3352. {
  3353. struct md_region md_entry;
  3354. int ret;
  3355. switch (type) {
  3356. case CNSS_FW_IMAGE:
  3357. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  3358. seg_no);
  3359. break;
  3360. case CNSS_FW_RDDM:
  3361. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  3362. seg_no);
  3363. break;
  3364. case CNSS_FW_REMOTE_HEAP:
  3365. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  3366. seg_no);
  3367. break;
  3368. default:
  3369. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3370. return -EINVAL;
  3371. }
  3372. md_entry.phys_addr = pa;
  3373. md_entry.virt_addr = (uintptr_t)va;
  3374. md_entry.size = size;
  3375. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  3376. cnss_pr_vdbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3377. md_entry.name, va, &pa, size);
  3378. ret = msm_minidump_remove_region(&md_entry);
  3379. if (ret)
  3380. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  3381. ret);
  3382. return ret;
  3383. }
  3384. #else
  3385. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  3386. enum cnss_fw_dump_type type, int seg_no,
  3387. void *va, phys_addr_t pa, size_t size)
  3388. {
  3389. char name[MAX_NAME_LEN];
  3390. switch (type) {
  3391. case CNSS_FW_IMAGE:
  3392. snprintf(name, MAX_NAME_LEN, "FBC_%X", seg_no);
  3393. break;
  3394. case CNSS_FW_RDDM:
  3395. snprintf(name, MAX_NAME_LEN, "RDDM_%X", seg_no);
  3396. break;
  3397. case CNSS_FW_REMOTE_HEAP:
  3398. snprintf(name, MAX_NAME_LEN, "RHEAP_%X", seg_no);
  3399. break;
  3400. default:
  3401. cnss_pr_err("Unknown dump type ID: %d\n", type);
  3402. return -EINVAL;
  3403. }
  3404. cnss_pr_dbg("Dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  3405. name, va, &pa, size);
  3406. return 0;
  3407. }
  3408. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  3409. enum cnss_fw_dump_type type, int seg_no,
  3410. void *va, phys_addr_t pa, size_t size)
  3411. {
  3412. return 0;
  3413. }
  3414. #endif /* CONFIG_QCOM_MINIDUMP */
  3415. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  3416. const struct firmware **fw_entry,
  3417. const char *filename)
  3418. {
  3419. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  3420. return request_firmware_direct(fw_entry, filename,
  3421. &plat_priv->plat_dev->dev);
  3422. else
  3423. return firmware_request_nowarn(fw_entry, filename,
  3424. &plat_priv->plat_dev->dev);
  3425. }
  3426. #if IS_ENABLED(CONFIG_INTERCONNECT)
  3427. /**
  3428. * cnss_register_bus_scale() - Setup interconnect voting data
  3429. * @plat_priv: Platform data structure
  3430. *
  3431. * For different interconnect path configured in device tree setup voting data
  3432. * for list of bandwidth requirements.
  3433. *
  3434. * Result: 0 for success. -EINVAL if not configured
  3435. */
  3436. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3437. {
  3438. int ret = -EINVAL;
  3439. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  3440. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3441. struct device *dev = &plat_priv->plat_dev->dev;
  3442. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  3443. ret = of_property_read_u32(dev->of_node,
  3444. "qcom,icc-path-count",
  3445. &plat_priv->icc.path_count);
  3446. if (ret) {
  3447. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  3448. return 0;
  3449. }
  3450. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  3451. "qcom,bus-bw-cfg-count",
  3452. &plat_priv->icc.bus_bw_cfg_count);
  3453. if (ret) {
  3454. cnss_pr_err("Failed to get Bus BW Config table size\n");
  3455. goto cleanup;
  3456. }
  3457. cfg_arr_size = plat_priv->icc.path_count *
  3458. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  3459. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  3460. if (!cfg_arr) {
  3461. cnss_pr_err("Failed to alloc cfg table mem\n");
  3462. ret = -ENOMEM;
  3463. goto cleanup;
  3464. }
  3465. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  3466. "qcom,bus-bw-cfg", cfg_arr,
  3467. cfg_arr_size);
  3468. if (ret) {
  3469. cnss_pr_err("Invalid Bus BW Config Table\n");
  3470. goto cleanup;
  3471. }
  3472. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  3473. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  3474. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  3475. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  3476. GFP_KERNEL);
  3477. if (!bus_bw_info) {
  3478. ret = -ENOMEM;
  3479. goto out;
  3480. }
  3481. ret = of_property_read_string_index(dev->of_node,
  3482. "interconnect-names", idx,
  3483. &bus_bw_info->icc_name);
  3484. if (ret)
  3485. goto out;
  3486. bus_bw_info->icc_path =
  3487. of_icc_get(&plat_priv->plat_dev->dev,
  3488. bus_bw_info->icc_name);
  3489. if (IS_ERR(bus_bw_info->icc_path)) {
  3490. ret = PTR_ERR(bus_bw_info->icc_path);
  3491. if (ret != -EPROBE_DEFER) {
  3492. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  3493. bus_bw_info->icc_name, ret);
  3494. goto out;
  3495. }
  3496. }
  3497. bus_bw_info->cfg_table =
  3498. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  3499. sizeof(*bus_bw_info->cfg_table),
  3500. GFP_KERNEL);
  3501. if (!bus_bw_info->cfg_table) {
  3502. ret = -ENOMEM;
  3503. goto out;
  3504. }
  3505. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  3506. bus_bw_info->icc_name);
  3507. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  3508. CNSS_ICC_VOTE_MAX);
  3509. i < plat_priv->icc.bus_bw_cfg_count;
  3510. i++, j += 2) {
  3511. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  3512. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  3513. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  3514. i, bus_bw_info->cfg_table[i].avg_bw,
  3515. bus_bw_info->cfg_table[i].peak_bw);
  3516. }
  3517. list_add_tail(&bus_bw_info->list,
  3518. &plat_priv->icc.list_head);
  3519. }
  3520. kfree(cfg_arr);
  3521. return 0;
  3522. out:
  3523. list_for_each_entry_safe(bus_bw_info, tmp,
  3524. &plat_priv->icc.list_head, list) {
  3525. list_del(&bus_bw_info->list);
  3526. }
  3527. cleanup:
  3528. kfree(cfg_arr);
  3529. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3530. return ret;
  3531. }
  3532. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  3533. {
  3534. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  3535. list_for_each_entry_safe(bus_bw_info, tmp,
  3536. &plat_priv->icc.list_head, list) {
  3537. list_del(&bus_bw_info->list);
  3538. if (bus_bw_info->icc_path)
  3539. icc_put(bus_bw_info->icc_path);
  3540. }
  3541. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  3542. }
  3543. #else
  3544. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  3545. {
  3546. return 0;
  3547. }
  3548. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  3549. #endif /* CONFIG_INTERCONNECT */
  3550. static void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  3551. {
  3552. struct cnss_plat_data *plat_priv = cb_ctx;
  3553. if (!plat_priv) {
  3554. cnss_pr_err("%s: Invalid context\n", __func__);
  3555. return;
  3556. }
  3557. if (status) {
  3558. cnss_pr_info("CNSS Daemon connected\n");
  3559. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3560. complete(&plat_priv->daemon_connected);
  3561. } else {
  3562. cnss_pr_info("CNSS Daemon disconnected\n");
  3563. reinit_completion(&plat_priv->daemon_connected);
  3564. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  3565. }
  3566. }
  3567. static ssize_t enable_hds_store(struct device *dev,
  3568. struct device_attribute *attr,
  3569. const char *buf, size_t count)
  3570. {
  3571. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3572. unsigned int enable_hds = 0;
  3573. if (!plat_priv)
  3574. return -ENODEV;
  3575. if (sscanf(buf, "%du", &enable_hds) != 1) {
  3576. cnss_pr_err("Invalid enable_hds sysfs command\n");
  3577. return -EINVAL;
  3578. }
  3579. if (enable_hds)
  3580. plat_priv->hds_enabled = true;
  3581. else
  3582. plat_priv->hds_enabled = false;
  3583. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  3584. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  3585. return count;
  3586. }
  3587. static ssize_t recovery_show(struct device *dev,
  3588. struct device_attribute *attr,
  3589. char *buf)
  3590. {
  3591. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3592. u32 buf_size = PAGE_SIZE;
  3593. u32 curr_len = 0;
  3594. u32 buf_written = 0;
  3595. if (!plat_priv)
  3596. return -ENODEV;
  3597. buf_written = scnprintf(buf, buf_size,
  3598. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  3599. "BIT0 -- wlan fw recovery\n"
  3600. "BIT1 -- wlan pcss recovery\n"
  3601. "---------------------------------\n");
  3602. curr_len += buf_written;
  3603. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3604. "WLAN recovery %s[%d]\n",
  3605. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  3606. plat_priv->recovery_enabled);
  3607. curr_len += buf_written;
  3608. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  3609. "WLAN PCSS recovery %s[%d]\n",
  3610. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  3611. plat_priv->recovery_pcss_enabled);
  3612. curr_len += buf_written;
  3613. /*
  3614. * Now size of curr_len is not over page size for sure,
  3615. * later if new item or none-fixed size item added, need
  3616. * add check to make sure curr_len is not over page size.
  3617. */
  3618. return curr_len;
  3619. }
  3620. static ssize_t tme_opt_file_download_show(struct device *dev,
  3621. struct device_attribute *attr, char *buf)
  3622. {
  3623. u32 buf_size = PAGE_SIZE;
  3624. u32 curr_len = 0;
  3625. u32 buf_written = 0;
  3626. buf_written = scnprintf(buf, buf_size,
  3627. "Usage: echo [file_type] > /sys/kernel/cnss/tme_opt_file_download\n"
  3628. "file_type = sec -- For OEM_FUSE file\n"
  3629. "file_type = rpr -- For RPR file\n"
  3630. "file_type = dpr -- For DPR file\n");
  3631. curr_len += buf_written;
  3632. return curr_len;
  3633. }
  3634. static ssize_t time_sync_period_show(struct device *dev,
  3635. struct device_attribute *attr,
  3636. char *buf)
  3637. {
  3638. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3639. return scnprintf(buf, PAGE_SIZE, "%u ms\n",
  3640. plat_priv->ctrl_params.time_sync_period);
  3641. }
  3642. /**
  3643. * cnss_get_min_time_sync_period_by_vote() - Get minimum time sync period
  3644. * @plat_priv: Platform data structure
  3645. *
  3646. * Result: return minimum time sync period present in vote from wlan and sys
  3647. */
  3648. static uint32_t cnss_get_min_time_sync_period_by_vote(struct cnss_plat_data *plat_priv)
  3649. {
  3650. unsigned int i, min_time_sync_period = CNSS_TIME_SYNC_PERIOD_INVALID;
  3651. unsigned int time_sync_period;
  3652. for (i = 0; i < TIME_SYNC_VOTE_MAX; i++) {
  3653. time_sync_period = plat_priv->ctrl_params.time_sync_period_vote[i];
  3654. if (min_time_sync_period > time_sync_period)
  3655. min_time_sync_period = time_sync_period;
  3656. }
  3657. return min_time_sync_period;
  3658. }
  3659. static ssize_t time_sync_period_store(struct device *dev,
  3660. struct device_attribute *attr,
  3661. const char *buf, size_t count)
  3662. {
  3663. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3664. unsigned int time_sync_period = 0;
  3665. if (!plat_priv)
  3666. return -ENODEV;
  3667. if (sscanf(buf, "%du", &time_sync_period) != 1) {
  3668. cnss_pr_err("Invalid time sync sysfs command\n");
  3669. return -EINVAL;
  3670. }
  3671. if (time_sync_period < CNSS_MIN_TIME_SYNC_PERIOD) {
  3672. cnss_pr_err("Invalid time sync value\n");
  3673. return -EINVAL;
  3674. }
  3675. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_CNSS] =
  3676. time_sync_period;
  3677. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3678. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3679. cnss_pr_err("Invalid min time sync value\n");
  3680. return -EINVAL;
  3681. }
  3682. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3683. return count;
  3684. }
  3685. /**
  3686. * cnss_update_time_sync_period() - Set time sync period given by driver
  3687. * @dev: device structure
  3688. * @time_sync_period: time sync period value
  3689. *
  3690. * Update time sync period vote of driver and set minimum of time sync period
  3691. * from stored vote through wlan and sys config
  3692. * Result: return 0 for success, error in case of invalid value and no dev
  3693. */
  3694. int cnss_update_time_sync_period(struct device *dev, uint32_t time_sync_period)
  3695. {
  3696. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3697. if (!plat_priv)
  3698. return -ENODEV;
  3699. if (time_sync_period < CNSS_MIN_TIME_SYNC_PERIOD) {
  3700. cnss_pr_err("Invalid time sync value\n");
  3701. return -EINVAL;
  3702. }
  3703. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  3704. time_sync_period;
  3705. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3706. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3707. cnss_pr_err("Invalid min time sync value\n");
  3708. return -EINVAL;
  3709. }
  3710. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3711. return 0;
  3712. }
  3713. EXPORT_SYMBOL(cnss_update_time_sync_period);
  3714. /**
  3715. * cnss_reset_time_sync_period() - Reset time sync period
  3716. * @dev: device structure
  3717. *
  3718. * Update time sync period vote of driver as invalid
  3719. * and reset minimum of time sync period from
  3720. * stored vote through wlan and sys config
  3721. * Result: return 0 for success, error in case of no dev
  3722. */
  3723. int cnss_reset_time_sync_period(struct device *dev)
  3724. {
  3725. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  3726. unsigned int time_sync_period = 0;
  3727. if (!plat_priv)
  3728. return -ENODEV;
  3729. /* Driver vote is set to invalid in case of reset
  3730. * In this case, only vote valid to check is sys config
  3731. */
  3732. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  3733. CNSS_TIME_SYNC_PERIOD_INVALID;
  3734. time_sync_period = cnss_get_min_time_sync_period_by_vote(plat_priv);
  3735. if (time_sync_period == CNSS_TIME_SYNC_PERIOD_INVALID) {
  3736. cnss_pr_err("Invalid min time sync value\n");
  3737. return -EINVAL;
  3738. }
  3739. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  3740. return 0;
  3741. }
  3742. EXPORT_SYMBOL(cnss_reset_time_sync_period);
  3743. static ssize_t recovery_store(struct device *dev,
  3744. struct device_attribute *attr,
  3745. const char *buf, size_t count)
  3746. {
  3747. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3748. unsigned int recovery = 0;
  3749. if (!plat_priv)
  3750. return -ENODEV;
  3751. if (sscanf(buf, "%du", &recovery) != 1) {
  3752. cnss_pr_err("Invalid recovery sysfs command\n");
  3753. return -EINVAL;
  3754. }
  3755. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  3756. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  3757. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  3758. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  3759. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  3760. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  3761. cnss_send_subsys_restart_level_msg(plat_priv);
  3762. return count;
  3763. }
  3764. static ssize_t shutdown_store(struct device *dev,
  3765. struct device_attribute *attr,
  3766. const char *buf, size_t count)
  3767. {
  3768. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3769. cnss_pr_dbg("Received shutdown notification\n");
  3770. if (plat_priv) {
  3771. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3772. cnss_bus_update_status(plat_priv, CNSS_SYS_REBOOT);
  3773. del_timer(&plat_priv->fw_boot_timer);
  3774. complete_all(&plat_priv->power_up_complete);
  3775. complete_all(&plat_priv->cal_complete);
  3776. cnss_pr_dbg("Shutdown notification handled\n");
  3777. }
  3778. return count;
  3779. }
  3780. static ssize_t fs_ready_store(struct device *dev,
  3781. struct device_attribute *attr,
  3782. const char *buf, size_t count)
  3783. {
  3784. int fs_ready = 0;
  3785. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3786. if (sscanf(buf, "%du", &fs_ready) != 1)
  3787. return -EINVAL;
  3788. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  3789. fs_ready, count);
  3790. if (!plat_priv) {
  3791. cnss_pr_err("plat_priv is NULL\n");
  3792. return count;
  3793. }
  3794. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  3795. cnss_pr_dbg("QMI is bypassed\n");
  3796. return count;
  3797. }
  3798. set_bit(CNSS_FS_READY, &plat_priv->driver_state);
  3799. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  3800. cnss_driver_event_post(plat_priv,
  3801. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3802. 0, NULL);
  3803. }
  3804. return count;
  3805. }
  3806. static ssize_t qdss_trace_start_store(struct device *dev,
  3807. struct device_attribute *attr,
  3808. const char *buf, size_t count)
  3809. {
  3810. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3811. wlfw_qdss_trace_start(plat_priv);
  3812. cnss_pr_dbg("Received QDSS start command\n");
  3813. return count;
  3814. }
  3815. static ssize_t qdss_trace_stop_store(struct device *dev,
  3816. struct device_attribute *attr,
  3817. const char *buf, size_t count)
  3818. {
  3819. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3820. u32 option = 0;
  3821. if (sscanf(buf, "%du", &option) != 1)
  3822. return -EINVAL;
  3823. wlfw_qdss_trace_stop(plat_priv, option);
  3824. cnss_pr_dbg("Received QDSS stop command\n");
  3825. return count;
  3826. }
  3827. static ssize_t qdss_conf_download_store(struct device *dev,
  3828. struct device_attribute *attr,
  3829. const char *buf, size_t count)
  3830. {
  3831. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3832. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  3833. cnss_pr_dbg("Received QDSS download config command\n");
  3834. return count;
  3835. }
  3836. static ssize_t tme_opt_file_download_store(struct device *dev,
  3837. struct device_attribute *attr,
  3838. const char *buf, size_t count)
  3839. {
  3840. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3841. char cmd[5];
  3842. if (sscanf(buf, "%s", cmd) != 1)
  3843. return -EINVAL;
  3844. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3845. cnss_pr_err("Firmware is not ready yet\n");
  3846. return 0;
  3847. }
  3848. if (plat_priv->device_id == PEACH_DEVICE_ID &&
  3849. cnss_bus_runtime_pm_get_sync(plat_priv) < 0)
  3850. goto runtime_pm_put;
  3851. if (strcmp(cmd, "sec") == 0) {
  3852. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_OEM_FUSE_FILE_V01);
  3853. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_OEM_FUSE_FILE_V01);
  3854. } else if (strcmp(cmd, "rpr") == 0) {
  3855. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_RPR_FILE_V01);
  3856. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_RPR_FILE_V01);
  3857. } else if (strcmp(cmd, "dpr") == 0) {
  3858. cnss_bus_load_tme_opt_file(plat_priv, WLFW_TME_LITE_DPR_FILE_V01);
  3859. cnss_wlfw_tme_opt_file_dnld_send_sync(plat_priv, WLFW_TME_LITE_DPR_FILE_V01);
  3860. }
  3861. cnss_pr_dbg("Received tme_opt_file_download indication cmd: %s\n", cmd);
  3862. runtime_pm_put:
  3863. if (plat_priv->device_id == PEACH_DEVICE_ID)
  3864. cnss_bus_runtime_pm_put(plat_priv);
  3865. return count;
  3866. }
  3867. static ssize_t hw_trace_override_store(struct device *dev,
  3868. struct device_attribute *attr,
  3869. const char *buf, size_t count)
  3870. {
  3871. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3872. int tmp = 0;
  3873. if (sscanf(buf, "%du", &tmp) != 1)
  3874. return -EINVAL;
  3875. plat_priv->hw_trc_override = tmp;
  3876. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  3877. return count;
  3878. }
  3879. static ssize_t charger_mode_store(struct device *dev,
  3880. struct device_attribute *attr,
  3881. const char *buf, size_t count)
  3882. {
  3883. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  3884. int tmp = 0;
  3885. if (sscanf(buf, "%du", &tmp) != 1)
  3886. return -EINVAL;
  3887. plat_priv->charger_mode = tmp;
  3888. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  3889. return count;
  3890. }
  3891. static DEVICE_ATTR_WO(fs_ready);
  3892. static DEVICE_ATTR_WO(shutdown);
  3893. static DEVICE_ATTR_RW(recovery);
  3894. static DEVICE_ATTR_WO(enable_hds);
  3895. static DEVICE_ATTR_WO(qdss_trace_start);
  3896. static DEVICE_ATTR_WO(qdss_trace_stop);
  3897. static DEVICE_ATTR_WO(qdss_conf_download);
  3898. static DEVICE_ATTR_RW(tme_opt_file_download);
  3899. static DEVICE_ATTR_WO(hw_trace_override);
  3900. static DEVICE_ATTR_WO(charger_mode);
  3901. static DEVICE_ATTR_RW(time_sync_period);
  3902. static struct attribute *cnss_attrs[] = {
  3903. &dev_attr_fs_ready.attr,
  3904. &dev_attr_shutdown.attr,
  3905. &dev_attr_recovery.attr,
  3906. &dev_attr_enable_hds.attr,
  3907. &dev_attr_qdss_trace_start.attr,
  3908. &dev_attr_qdss_trace_stop.attr,
  3909. &dev_attr_qdss_conf_download.attr,
  3910. &dev_attr_tme_opt_file_download.attr,
  3911. &dev_attr_hw_trace_override.attr,
  3912. &dev_attr_charger_mode.attr,
  3913. &dev_attr_time_sync_period.attr,
  3914. NULL,
  3915. };
  3916. static struct attribute_group cnss_attr_group = {
  3917. .attrs = cnss_attrs,
  3918. };
  3919. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  3920. {
  3921. struct device *dev = &plat_priv->plat_dev->dev;
  3922. int ret;
  3923. char cnss_name[CNSS_FS_NAME_SIZE];
  3924. char shutdown_name[32];
  3925. if (cnss_is_dual_wlan_enabled()) {
  3926. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3927. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3928. snprintf(shutdown_name, sizeof(shutdown_name),
  3929. "shutdown_wlan_%d", plat_priv->plat_idx);
  3930. } else {
  3931. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3932. snprintf(shutdown_name, sizeof(shutdown_name),
  3933. "shutdown_wlan");
  3934. }
  3935. ret = sysfs_create_link(kernel_kobj, &dev->kobj, cnss_name);
  3936. if (ret) {
  3937. cnss_pr_err("Failed to create cnss link, err = %d\n",
  3938. ret);
  3939. goto out;
  3940. }
  3941. /* This is only for backward compatibility. */
  3942. ret = sysfs_create_link(kernel_kobj, &dev->kobj, shutdown_name);
  3943. if (ret) {
  3944. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  3945. ret);
  3946. goto rm_cnss_link;
  3947. }
  3948. return 0;
  3949. rm_cnss_link:
  3950. sysfs_remove_link(kernel_kobj, cnss_name);
  3951. out:
  3952. return ret;
  3953. }
  3954. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  3955. {
  3956. char cnss_name[CNSS_FS_NAME_SIZE];
  3957. char shutdown_name[32];
  3958. if (cnss_is_dual_wlan_enabled()) {
  3959. snprintf(cnss_name, CNSS_FS_NAME_SIZE,
  3960. CNSS_FS_NAME "_%d", plat_priv->plat_idx);
  3961. snprintf(shutdown_name, sizeof(shutdown_name),
  3962. "shutdown_wlan_%d", plat_priv->plat_idx);
  3963. } else {
  3964. snprintf(cnss_name, CNSS_FS_NAME_SIZE, CNSS_FS_NAME);
  3965. snprintf(shutdown_name, sizeof(shutdown_name),
  3966. "shutdown_wlan");
  3967. }
  3968. sysfs_remove_link(kernel_kobj, shutdown_name);
  3969. sysfs_remove_link(kernel_kobj, cnss_name);
  3970. }
  3971. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  3972. {
  3973. int ret = 0;
  3974. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  3975. &cnss_attr_group);
  3976. if (ret) {
  3977. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  3978. ret);
  3979. goto out;
  3980. }
  3981. cnss_create_sysfs_link(plat_priv);
  3982. return 0;
  3983. out:
  3984. return ret;
  3985. }
  3986. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0))
  3987. union cnss_device_group_devres {
  3988. const struct attribute_group *group;
  3989. };
  3990. static void devm_cnss_group_remove(struct device *dev, void *res)
  3991. {
  3992. union cnss_device_group_devres *devres = res;
  3993. const struct attribute_group *group = devres->group;
  3994. cnss_pr_dbg("%s: removing group %p\n", __func__, group);
  3995. sysfs_remove_group(&dev->kobj, group);
  3996. }
  3997. static int devm_cnss_group_match(struct device *dev, void *res, void *data)
  3998. {
  3999. return ((union cnss_device_group_devres *)res) == data;
  4000. }
  4001. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  4002. {
  4003. cnss_remove_sysfs_link(plat_priv);
  4004. WARN_ON(devres_release(&plat_priv->plat_dev->dev,
  4005. devm_cnss_group_remove, devm_cnss_group_match,
  4006. (void *)&cnss_attr_group));
  4007. }
  4008. #else
  4009. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  4010. {
  4011. cnss_remove_sysfs_link(plat_priv);
  4012. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  4013. }
  4014. #endif
  4015. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  4016. {
  4017. spin_lock_init(&plat_priv->event_lock);
  4018. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  4019. WQ_UNBOUND, 1);
  4020. if (!plat_priv->event_wq) {
  4021. cnss_pr_err("Failed to create event workqueue!\n");
  4022. return -EFAULT;
  4023. }
  4024. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  4025. INIT_LIST_HEAD(&plat_priv->event_list);
  4026. return 0;
  4027. }
  4028. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  4029. {
  4030. destroy_workqueue(plat_priv->event_wq);
  4031. }
  4032. static int cnss_reboot_notifier(struct notifier_block *nb,
  4033. unsigned long action,
  4034. void *data)
  4035. {
  4036. struct cnss_plat_data *plat_priv =
  4037. container_of(nb, struct cnss_plat_data, reboot_nb);
  4038. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  4039. cnss_bus_update_status(plat_priv, CNSS_SYS_REBOOT);
  4040. del_timer(&plat_priv->fw_boot_timer);
  4041. complete_all(&plat_priv->power_up_complete);
  4042. complete_all(&plat_priv->cal_complete);
  4043. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  4044. return NOTIFY_DONE;
  4045. }
  4046. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  4047. #ifdef CONFIG_CNSS_HW_SECURE_SMEM
  4048. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  4049. {
  4050. uint32_t *peripheralStateInfo = NULL;
  4051. size_t size = 0;
  4052. /* Once this flag is set, secure peripheral feature
  4053. * will not be supported till next reboot
  4054. */
  4055. if (plat_priv->sec_peri_feature_disable)
  4056. return 0;
  4057. peripheralStateInfo = qcom_smem_get(QCOM_SMEM_HOST_ANY, PERISEC_SMEM_ID, &size);
  4058. if (IS_ERR_OR_NULL(peripheralStateInfo)) {
  4059. if (PTR_ERR(peripheralStateInfo) != -ENOENT &&
  4060. PTR_ERR(peripheralStateInfo) != -ENODEV)
  4061. CNSS_ASSERT(0);
  4062. cnss_pr_dbg("Secure HW feature not enabled. ret = %d\n",
  4063. PTR_ERR(peripheralStateInfo));
  4064. plat_priv->sec_peri_feature_disable = true;
  4065. return 0;
  4066. }
  4067. cnss_pr_dbg("Secure HW state: %d\n", *peripheralStateInfo);
  4068. if ((*peripheralStateInfo >> (HW_WIFI_UID - 0x500)) & 0x1)
  4069. set_bit(CNSS_WLAN_HW_DISABLED,
  4070. &plat_priv->driver_state);
  4071. else
  4072. clear_bit(CNSS_WLAN_HW_DISABLED,
  4073. &plat_priv->driver_state);
  4074. return 0;
  4075. }
  4076. #else
  4077. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  4078. {
  4079. struct Object client_env;
  4080. struct Object app_object;
  4081. u32 wifi_uid = HW_WIFI_UID;
  4082. union ObjectArg obj_arg[2] = {{{0, 0}}};
  4083. int ret;
  4084. u8 state = 0;
  4085. /* Once this flag is set, secure peripheral feature
  4086. * will not be supported till next reboot
  4087. */
  4088. if (plat_priv->sec_peri_feature_disable)
  4089. return 0;
  4090. /* get rootObj */
  4091. ret = get_client_env_object(&client_env);
  4092. if (ret) {
  4093. cnss_pr_dbg("Failed to get client_env_object, ret: %d\n", ret);
  4094. goto end;
  4095. }
  4096. ret = IClientEnv_open(client_env, HW_STATE_UID, &app_object);
  4097. if (ret) {
  4098. cnss_pr_dbg("Failed to get app_object, ret: %d\n", ret);
  4099. if (ret == FEATURE_NOT_SUPPORTED) {
  4100. ret = 0; /* Do not Assert */
  4101. plat_priv->sec_peri_feature_disable = true;
  4102. cnss_pr_dbg("Secure HW feature not supported\n");
  4103. }
  4104. goto exit_release_clientenv;
  4105. }
  4106. obj_arg[0].b = (struct ObjectBuf) {&wifi_uid, sizeof(u32)};
  4107. obj_arg[1].b = (struct ObjectBuf) {&state, sizeof(u8)};
  4108. ret = Object_invoke(app_object, HW_OP_GET_STATE, obj_arg,
  4109. ObjectCounts_pack(1, 1, 0, 0));
  4110. cnss_pr_dbg("SMC invoke ret: %d state: %d\n", ret, state);
  4111. if (ret) {
  4112. if (ret == PERIPHERAL_NOT_FOUND) {
  4113. ret = 0; /* Do not Assert */
  4114. plat_priv->sec_peri_feature_disable = true;
  4115. cnss_pr_dbg("Secure HW mode is not updated. Peripheral not found\n");
  4116. }
  4117. goto exit_release_app_obj;
  4118. }
  4119. if (state == 1)
  4120. set_bit(CNSS_WLAN_HW_DISABLED,
  4121. &plat_priv->driver_state);
  4122. else
  4123. clear_bit(CNSS_WLAN_HW_DISABLED,
  4124. &plat_priv->driver_state);
  4125. exit_release_app_obj:
  4126. Object_release(app_object);
  4127. exit_release_clientenv:
  4128. Object_release(client_env);
  4129. end:
  4130. if (ret) {
  4131. cnss_pr_err("Unable to get HW disable status\n");
  4132. CNSS_ASSERT(0);
  4133. }
  4134. return ret;
  4135. }
  4136. #endif
  4137. #else
  4138. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  4139. {
  4140. return 0;
  4141. }
  4142. #endif
  4143. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  4144. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  4145. {
  4146. }
  4147. #else
  4148. static void cnss_sram_dump_init(struct cnss_plat_data *plat_priv)
  4149. {
  4150. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  4151. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  4152. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  4153. }
  4154. #endif
  4155. #if IS_ENABLED(CONFIG_WCNSS_MEM_PRE_ALLOC)
  4156. static void cnss_initialize_mem_pool(unsigned long device_id)
  4157. {
  4158. cnss_initialize_prealloc_pool(device_id);
  4159. }
  4160. static void cnss_deinitialize_mem_pool(void)
  4161. {
  4162. cnss_deinitialize_prealloc_pool();
  4163. }
  4164. #else
  4165. static void cnss_initialize_mem_pool(unsigned long device_id)
  4166. {
  4167. }
  4168. static void cnss_deinitialize_mem_pool(void)
  4169. {
  4170. }
  4171. #endif
  4172. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  4173. {
  4174. int ret;
  4175. ret = cnss_init_sol_gpio(plat_priv);
  4176. if (ret)
  4177. return ret;
  4178. timer_setup(&plat_priv->fw_boot_timer,
  4179. cnss_bus_fw_boot_timeout_hdlr, 0);
  4180. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  4181. if (ret)
  4182. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  4183. ret);
  4184. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  4185. init_completion(&plat_priv->power_up_complete);
  4186. init_completion(&plat_priv->cal_complete);
  4187. init_completion(&plat_priv->rddm_complete);
  4188. init_completion(&plat_priv->recovery_complete);
  4189. init_completion(&plat_priv->daemon_connected);
  4190. mutex_init(&plat_priv->dev_lock);
  4191. mutex_init(&plat_priv->driver_ops_lock);
  4192. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  4193. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  4194. if (ret)
  4195. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  4196. ret);
  4197. plat_priv->recovery_ws =
  4198. wakeup_source_register(&plat_priv->plat_dev->dev,
  4199. "CNSS_FW_RECOVERY");
  4200. if (!plat_priv->recovery_ws)
  4201. cnss_pr_err("Failed to setup FW recovery wake source\n");
  4202. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  4203. cnss_daemon_connection_update_cb,
  4204. plat_priv);
  4205. if (ret)
  4206. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  4207. ret);
  4208. cnss_sram_dump_init(plat_priv);
  4209. if (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4210. "qcom,rc-ep-short-channel"))
  4211. cnss_set_feature_list(plat_priv, CNSS_RC_EP_ULTRASHORT_CHANNEL_V01);
  4212. if (plat_priv->device_id == PEACH_DEVICE_ID)
  4213. cnss_set_feature_list(plat_priv, CNSS_AUX_UC_SUPPORT_V01);
  4214. return 0;
  4215. }
  4216. #ifdef CONFIG_DISABLE_CNSS_SRAM_DUMP
  4217. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  4218. {
  4219. }
  4220. #else
  4221. static void cnss_sram_dump_deinit(struct cnss_plat_data *plat_priv)
  4222. {
  4223. if (plat_priv->device_id == QCA6490_DEVICE_ID &&
  4224. cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01)
  4225. kfree(plat_priv->sram_dump);
  4226. }
  4227. #endif
  4228. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  4229. {
  4230. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  4231. plat_priv);
  4232. complete_all(&plat_priv->recovery_complete);
  4233. complete_all(&plat_priv->rddm_complete);
  4234. complete_all(&plat_priv->cal_complete);
  4235. complete_all(&plat_priv->power_up_complete);
  4236. complete_all(&plat_priv->daemon_connected);
  4237. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  4238. unregister_reboot_notifier(&plat_priv->reboot_nb);
  4239. del_timer(&plat_priv->fw_boot_timer);
  4240. wakeup_source_unregister(plat_priv->recovery_ws);
  4241. cnss_deinit_sol_gpio(plat_priv);
  4242. cnss_sram_dump_deinit(plat_priv);
  4243. kfree(plat_priv->on_chip_pmic_board_ids);
  4244. }
  4245. static void cnss_init_time_sync_period_default(struct cnss_plat_data *plat_priv)
  4246. {
  4247. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_WLAN] =
  4248. CNSS_TIME_SYNC_PERIOD_INVALID;
  4249. plat_priv->ctrl_params.time_sync_period_vote[TIME_SYNC_VOTE_CNSS] =
  4250. CNSS_TIME_SYNC_PERIOD_DEFAULT;
  4251. }
  4252. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  4253. {
  4254. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  4255. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  4256. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4257. "qcom,wlan-cbc-enabled");
  4258. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  4259. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  4260. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  4261. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  4262. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  4263. cnss_init_time_sync_period_default(plat_priv);
  4264. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  4265. * enabled by default
  4266. */
  4267. plat_priv->adsp_pc_enabled = true;
  4268. }
  4269. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  4270. {
  4271. struct device *dev = &plat_priv->plat_dev->dev;
  4272. plat_priv->use_pm_domain =
  4273. of_property_read_bool(dev->of_node, "use-pm-domain");
  4274. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  4275. }
  4276. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  4277. {
  4278. struct device *dev = &plat_priv->plat_dev->dev;
  4279. plat_priv->set_wlaon_pwr_ctrl =
  4280. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  4281. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  4282. plat_priv->set_wlaon_pwr_ctrl);
  4283. }
  4284. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  4285. {
  4286. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4287. "qcom,converged-dt") ||
  4288. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4289. "qcom,same-dt-multi-dev") ||
  4290. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4291. "qcom,multi-wlan-exchg"));
  4292. }
  4293. static const struct platform_device_id cnss_platform_id_table[] = {
  4294. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  4295. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  4296. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  4297. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  4298. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  4299. { .name = "mango", .driver_data = MANGO_DEVICE_ID, },
  4300. { .name = "peach", .driver_data = PEACH_DEVICE_ID, },
  4301. { .name = "qcaconv", .driver_data = 0, },
  4302. { },
  4303. };
  4304. static const struct of_device_id cnss_of_match_table[] = {
  4305. {
  4306. .compatible = "qcom,cnss",
  4307. .data = (void *)&cnss_platform_id_table[0]},
  4308. {
  4309. .compatible = "qcom,cnss-qca6290",
  4310. .data = (void *)&cnss_platform_id_table[1]},
  4311. {
  4312. .compatible = "qcom,cnss-qca6390",
  4313. .data = (void *)&cnss_platform_id_table[2]},
  4314. {
  4315. .compatible = "qcom,cnss-qca6490",
  4316. .data = (void *)&cnss_platform_id_table[3]},
  4317. {
  4318. .compatible = "qcom,cnss-kiwi",
  4319. .data = (void *)&cnss_platform_id_table[4]},
  4320. {
  4321. .compatible = "qcom,cnss-mango",
  4322. .data = (void *)&cnss_platform_id_table[5]},
  4323. {
  4324. .compatible = "qcom,cnss-peach",
  4325. .data = (void *)&cnss_platform_id_table[6]},
  4326. {
  4327. .compatible = "qcom,cnss-qca-converged",
  4328. .data = (void *)&cnss_platform_id_table[7]},
  4329. { },
  4330. };
  4331. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  4332. static inline bool
  4333. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  4334. {
  4335. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  4336. "use-nv-mac");
  4337. }
  4338. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  4339. {
  4340. struct device_node *child;
  4341. u32 id, i;
  4342. int id_n, device_identifier_gpio, ret;
  4343. u8 gpio_value;
  4344. if (plat_priv->dt_type != CNSS_DTT_CONVERGED)
  4345. return 0;
  4346. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  4347. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  4348. if (ret) {
  4349. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  4350. return ret;
  4351. }
  4352. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  4353. gpio_value = gpio_get_value(device_identifier_gpio);
  4354. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  4355. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  4356. child) {
  4357. if (strcmp(child->name, "chip_cfg"))
  4358. continue;
  4359. id_n = of_property_count_u32_elems(child, "supported-ids");
  4360. if (id_n <= 0) {
  4361. cnss_pr_err("Device id is NOT set\n");
  4362. return -EINVAL;
  4363. }
  4364. for (i = 0; i < id_n; i++) {
  4365. ret = of_property_read_u32_index(child,
  4366. "supported-ids",
  4367. i, &id);
  4368. if (ret) {
  4369. cnss_pr_err("Failed to read supported ids\n");
  4370. return -EINVAL;
  4371. }
  4372. if (gpio_value && id == QCA6490_DEVICE_ID) {
  4373. plat_priv->plat_dev->dev.of_node = child;
  4374. plat_priv->device_id = QCA6490_DEVICE_ID;
  4375. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  4376. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  4377. child->name, i, id);
  4378. return 0;
  4379. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  4380. plat_priv->plat_dev->dev.of_node = child;
  4381. plat_priv->device_id = KIWI_DEVICE_ID;
  4382. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  4383. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  4384. child->name, i, id);
  4385. return 0;
  4386. }
  4387. }
  4388. }
  4389. return -EINVAL;
  4390. }
  4391. static inline u32
  4392. cnss_dt_type(struct cnss_plat_data *plat_priv)
  4393. {
  4394. bool is_converged_dt = of_property_read_bool(
  4395. plat_priv->plat_dev->dev.of_node, "qcom,converged-dt");
  4396. bool is_multi_wlan_xchg;
  4397. if (is_converged_dt)
  4398. return CNSS_DTT_CONVERGED;
  4399. is_multi_wlan_xchg = of_property_read_bool(
  4400. plat_priv->plat_dev->dev.of_node, "qcom,multi-wlan-exchg");
  4401. if (is_multi_wlan_xchg)
  4402. return CNSS_DTT_MULTIEXCHG;
  4403. return CNSS_DTT_LEGACY;
  4404. }
  4405. static int cnss_wlan_device_init(struct cnss_plat_data *plat_priv)
  4406. {
  4407. int ret = 0;
  4408. int retry = 0;
  4409. if (test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  4410. return 0;
  4411. retry:
  4412. ret = cnss_power_on_device(plat_priv, true);
  4413. if (ret)
  4414. goto end;
  4415. ret = cnss_bus_init(plat_priv);
  4416. if (ret) {
  4417. if ((ret != -EPROBE_DEFER) &&
  4418. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  4419. cnss_power_off_device(plat_priv);
  4420. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  4421. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  4422. goto retry;
  4423. }
  4424. goto power_off;
  4425. }
  4426. return 0;
  4427. power_off:
  4428. cnss_power_off_device(plat_priv);
  4429. end:
  4430. return ret;
  4431. }
  4432. int cnss_wlan_hw_enable(void)
  4433. {
  4434. struct cnss_plat_data *plat_priv;
  4435. int ret = 0;
  4436. if (cnss_is_dual_wlan_enabled())
  4437. plat_priv = cnss_get_first_plat_priv(NULL);
  4438. else
  4439. plat_priv = cnss_get_plat_priv(NULL);
  4440. if (!plat_priv)
  4441. return -ENODEV;
  4442. clear_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state);
  4443. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  4444. goto register_driver;
  4445. ret = cnss_wlan_device_init(plat_priv);
  4446. if (ret) {
  4447. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state))
  4448. CNSS_ASSERT(0);
  4449. return ret;
  4450. }
  4451. if (test_bit(CNSS_FS_READY, &plat_priv->driver_state))
  4452. cnss_driver_event_post(plat_priv,
  4453. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  4454. 0, NULL);
  4455. register_driver:
  4456. if (plat_priv->driver_ops)
  4457. ret = cnss_wlan_register_driver(plat_priv->driver_ops);
  4458. return ret;
  4459. }
  4460. EXPORT_SYMBOL(cnss_wlan_hw_enable);
  4461. int cnss_set_wfc_mode(struct device *dev, struct cnss_wfc_cfg cfg)
  4462. {
  4463. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  4464. int ret = 0;
  4465. if (!plat_priv)
  4466. return -ENODEV;
  4467. /* If IMS server is connected, return success without QMI send */
  4468. if (test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  4469. cnss_pr_dbg("Ignore host request as IMS server is connected");
  4470. return ret;
  4471. }
  4472. ret = cnss_wlfw_send_host_wfc_call_status(plat_priv, cfg);
  4473. return ret;
  4474. }
  4475. EXPORT_SYMBOL(cnss_set_wfc_mode);
  4476. static int cnss_tcdev_get_max_state(struct thermal_cooling_device *tcdev,
  4477. unsigned long *thermal_state)
  4478. {
  4479. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4480. if (!tcdev || !tcdev->devdata) {
  4481. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4482. return -EINVAL;
  4483. }
  4484. cnss_tcdev = tcdev->devdata;
  4485. *thermal_state = cnss_tcdev->max_thermal_state;
  4486. return 0;
  4487. }
  4488. static int cnss_tcdev_get_cur_state(struct thermal_cooling_device *tcdev,
  4489. unsigned long *thermal_state)
  4490. {
  4491. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4492. if (!tcdev || !tcdev->devdata) {
  4493. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4494. return -EINVAL;
  4495. }
  4496. cnss_tcdev = tcdev->devdata;
  4497. *thermal_state = cnss_tcdev->curr_thermal_state;
  4498. return 0;
  4499. }
  4500. static int cnss_tcdev_set_cur_state(struct thermal_cooling_device *tcdev,
  4501. unsigned long thermal_state)
  4502. {
  4503. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4504. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  4505. int ret = 0;
  4506. if (!tcdev || !tcdev->devdata) {
  4507. cnss_pr_err("tcdev or tcdev->devdata is null!\n");
  4508. return -EINVAL;
  4509. }
  4510. cnss_tcdev = tcdev->devdata;
  4511. if (thermal_state > cnss_tcdev->max_thermal_state)
  4512. return -EINVAL;
  4513. cnss_pr_vdbg("Cooling device set current state: %ld,for cdev id %d",
  4514. thermal_state, cnss_tcdev->tcdev_id);
  4515. mutex_lock(&plat_priv->tcdev_lock);
  4516. ret = cnss_bus_set_therm_cdev_state(plat_priv,
  4517. thermal_state,
  4518. cnss_tcdev->tcdev_id);
  4519. if (!ret)
  4520. cnss_tcdev->curr_thermal_state = thermal_state;
  4521. mutex_unlock(&plat_priv->tcdev_lock);
  4522. if (ret) {
  4523. cnss_pr_err("Setting Current Thermal State Failed: %d,for cdev id %d",
  4524. ret, cnss_tcdev->tcdev_id);
  4525. return ret;
  4526. }
  4527. return 0;
  4528. }
  4529. static struct thermal_cooling_device_ops cnss_cooling_ops = {
  4530. .get_max_state = cnss_tcdev_get_max_state,
  4531. .get_cur_state = cnss_tcdev_get_cur_state,
  4532. .set_cur_state = cnss_tcdev_set_cur_state,
  4533. };
  4534. int cnss_thermal_cdev_register(struct device *dev, unsigned long max_state,
  4535. int tcdev_id)
  4536. {
  4537. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4538. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4539. char cdev_node_name[THERMAL_NAME_LENGTH] = "";
  4540. struct device_node *dev_node;
  4541. int ret = 0;
  4542. if (!priv) {
  4543. cnss_pr_err("Platform driver is not initialized!\n");
  4544. return -ENODEV;
  4545. }
  4546. cnss_tcdev = kzalloc(sizeof(*cnss_tcdev), GFP_KERNEL);
  4547. if (!cnss_tcdev) {
  4548. cnss_pr_err("Failed to allocate cnss_tcdev object!\n");
  4549. return -ENOMEM;
  4550. }
  4551. cnss_tcdev->tcdev_id = tcdev_id;
  4552. cnss_tcdev->max_thermal_state = max_state;
  4553. snprintf(cdev_node_name, THERMAL_NAME_LENGTH,
  4554. "qcom,cnss_cdev%d", tcdev_id);
  4555. dev_node = of_find_node_by_name(NULL, cdev_node_name);
  4556. if (!dev_node) {
  4557. cnss_pr_err("Failed to get cooling device node\n");
  4558. kfree(cnss_tcdev);
  4559. return -EINVAL;
  4560. }
  4561. cnss_pr_dbg("tcdev node->name=%s\n", dev_node->name);
  4562. if (of_find_property(dev_node, "#cooling-cells", NULL)) {
  4563. cnss_tcdev->tcdev = thermal_of_cooling_device_register(dev_node,
  4564. cdev_node_name,
  4565. cnss_tcdev,
  4566. &cnss_cooling_ops);
  4567. if (IS_ERR_OR_NULL(cnss_tcdev->tcdev)) {
  4568. ret = PTR_ERR(cnss_tcdev->tcdev);
  4569. cnss_pr_err("Cooling device register failed: %d, for cdev id %d\n",
  4570. ret, cnss_tcdev->tcdev_id);
  4571. kfree(cnss_tcdev);
  4572. } else {
  4573. cnss_pr_dbg("Cooling device registered for cdev id %d",
  4574. cnss_tcdev->tcdev_id);
  4575. mutex_lock(&priv->tcdev_lock);
  4576. list_add(&cnss_tcdev->tcdev_list,
  4577. &priv->cnss_tcdev_list);
  4578. mutex_unlock(&priv->tcdev_lock);
  4579. }
  4580. } else {
  4581. cnss_pr_dbg("Cooling device registration not supported");
  4582. kfree(cnss_tcdev);
  4583. ret = -EOPNOTSUPP;
  4584. }
  4585. return ret;
  4586. }
  4587. EXPORT_SYMBOL(cnss_thermal_cdev_register);
  4588. void cnss_thermal_cdev_unregister(struct device *dev, int tcdev_id)
  4589. {
  4590. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4591. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4592. if (!priv) {
  4593. cnss_pr_err("Platform driver is not initialized!\n");
  4594. return;
  4595. }
  4596. mutex_lock(&priv->tcdev_lock);
  4597. while (!list_empty(&priv->cnss_tcdev_list)) {
  4598. cnss_tcdev = list_first_entry(&priv->cnss_tcdev_list,
  4599. struct cnss_thermal_cdev,
  4600. tcdev_list);
  4601. thermal_cooling_device_unregister(cnss_tcdev->tcdev);
  4602. list_del(&cnss_tcdev->tcdev_list);
  4603. kfree(cnss_tcdev);
  4604. }
  4605. mutex_unlock(&priv->tcdev_lock);
  4606. }
  4607. EXPORT_SYMBOL(cnss_thermal_cdev_unregister);
  4608. int cnss_get_curr_therm_cdev_state(struct device *dev,
  4609. unsigned long *thermal_state,
  4610. int tcdev_id)
  4611. {
  4612. struct cnss_plat_data *priv = cnss_get_plat_priv(NULL);
  4613. struct cnss_thermal_cdev *cnss_tcdev = NULL;
  4614. if (!priv) {
  4615. cnss_pr_err("Platform driver is not initialized!\n");
  4616. return -ENODEV;
  4617. }
  4618. mutex_lock(&priv->tcdev_lock);
  4619. list_for_each_entry(cnss_tcdev, &priv->cnss_tcdev_list, tcdev_list) {
  4620. if (cnss_tcdev->tcdev_id != tcdev_id)
  4621. continue;
  4622. *thermal_state = cnss_tcdev->curr_thermal_state;
  4623. mutex_unlock(&priv->tcdev_lock);
  4624. cnss_pr_dbg("Cooling device current state: %ld, for cdev id %d",
  4625. cnss_tcdev->curr_thermal_state, tcdev_id);
  4626. return 0;
  4627. }
  4628. mutex_unlock(&priv->tcdev_lock);
  4629. cnss_pr_dbg("Cooling device ID not found: %d", tcdev_id);
  4630. return -EINVAL;
  4631. }
  4632. EXPORT_SYMBOL(cnss_get_curr_therm_cdev_state);
  4633. static int cnss_probe(struct platform_device *plat_dev)
  4634. {
  4635. int ret = 0;
  4636. struct cnss_plat_data *plat_priv;
  4637. const struct of_device_id *of_id;
  4638. const struct platform_device_id *device_id;
  4639. if (cnss_get_plat_priv(plat_dev)) {
  4640. cnss_pr_err("Driver is already initialized!\n");
  4641. ret = -EEXIST;
  4642. goto out;
  4643. }
  4644. ret = cnss_plat_env_available();
  4645. if (ret)
  4646. goto out;
  4647. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  4648. if (!of_id || !of_id->data) {
  4649. cnss_pr_err("Failed to find of match device!\n");
  4650. ret = -ENODEV;
  4651. goto out;
  4652. }
  4653. device_id = of_id->data;
  4654. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  4655. GFP_KERNEL);
  4656. if (!plat_priv) {
  4657. ret = -ENOMEM;
  4658. goto out;
  4659. }
  4660. plat_priv->plat_dev = plat_dev;
  4661. plat_priv->dev_node = NULL;
  4662. plat_priv->device_id = device_id->driver_data;
  4663. plat_priv->dt_type = cnss_dt_type(plat_priv);
  4664. cnss_pr_dbg("Probing platform driver from dt type: %d\n",
  4665. plat_priv->dt_type);
  4666. plat_priv->use_fw_path_with_prefix =
  4667. cnss_use_fw_path_with_prefix(plat_priv);
  4668. ret = cnss_get_dev_cfg_node(plat_priv);
  4669. if (ret) {
  4670. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  4671. goto reset_plat_dev;
  4672. }
  4673. cnss_initialize_mem_pool(plat_priv->device_id);
  4674. ret = cnss_get_pld_bus_ops_name(plat_priv);
  4675. if (ret)
  4676. cnss_pr_vdbg("Failed to find bus ops name, err = %d\n",
  4677. ret);
  4678. ret = cnss_get_rc_num(plat_priv);
  4679. if (ret)
  4680. cnss_pr_err("Failed to find PCIe RC number, err = %d\n", ret);
  4681. cnss_pr_dbg("rc_num=%d\n", plat_priv->rc_num);
  4682. plat_priv->bus_type = cnss_get_bus_type(plat_priv);
  4683. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  4684. cnss_set_plat_priv(plat_dev, plat_priv);
  4685. cnss_set_device_name(plat_priv);
  4686. platform_set_drvdata(plat_dev, plat_priv);
  4687. INIT_LIST_HEAD(&plat_priv->vreg_list);
  4688. INIT_LIST_HEAD(&plat_priv->clk_list);
  4689. cnss_get_pm_domain_info(plat_priv);
  4690. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  4691. cnss_power_misc_params_init(plat_priv);
  4692. cnss_pci_of_switch_type_init(plat_priv);
  4693. cnss_get_tcs_info(plat_priv);
  4694. cnss_get_cpr_info(plat_priv);
  4695. cnss_aop_interface_init(plat_priv);
  4696. cnss_init_control_params(plat_priv);
  4697. ret = cnss_get_resources(plat_priv);
  4698. if (ret)
  4699. goto reset_ctx;
  4700. ret = cnss_register_esoc(plat_priv);
  4701. if (ret)
  4702. goto free_res;
  4703. ret = cnss_register_bus_scale(plat_priv);
  4704. if (ret)
  4705. goto unreg_esoc;
  4706. ret = cnss_create_sysfs(plat_priv);
  4707. if (ret)
  4708. goto unreg_bus_scale;
  4709. ret = cnss_event_work_init(plat_priv);
  4710. if (ret)
  4711. goto remove_sysfs;
  4712. ret = cnss_dms_init(plat_priv);
  4713. if (ret)
  4714. goto deinit_event_work;
  4715. ret = cnss_debugfs_create(plat_priv);
  4716. if (ret)
  4717. goto deinit_dms;
  4718. ret = cnss_misc_init(plat_priv);
  4719. if (ret)
  4720. goto destroy_debugfs;
  4721. ret = cnss_wlan_hw_disable_check(plat_priv);
  4722. if (ret)
  4723. goto deinit_misc;
  4724. /* Make sure all platform related init are done before
  4725. * device power on and bus init.
  4726. */
  4727. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  4728. ret = cnss_wlan_device_init(plat_priv);
  4729. if (ret)
  4730. goto deinit_misc;
  4731. } else {
  4732. cnss_pr_info("WLAN HW Disabled. Defer PCI enumeration\n");
  4733. }
  4734. cnss_register_coex_service(plat_priv);
  4735. cnss_register_ims_service(plat_priv);
  4736. mutex_init(&plat_priv->tcdev_lock);
  4737. INIT_LIST_HEAD(&plat_priv->cnss_tcdev_list);
  4738. cnss_pr_info("Platform driver probed successfully.\n");
  4739. return 0;
  4740. deinit_misc:
  4741. cnss_misc_deinit(plat_priv);
  4742. destroy_debugfs:
  4743. cnss_debugfs_destroy(plat_priv);
  4744. deinit_dms:
  4745. cnss_cancel_dms_work();
  4746. cnss_dms_deinit(plat_priv);
  4747. deinit_event_work:
  4748. cnss_event_work_deinit(plat_priv);
  4749. remove_sysfs:
  4750. cnss_remove_sysfs(plat_priv);
  4751. unreg_bus_scale:
  4752. cnss_unregister_bus_scale(plat_priv);
  4753. unreg_esoc:
  4754. cnss_unregister_esoc(plat_priv);
  4755. free_res:
  4756. cnss_put_resources(plat_priv);
  4757. reset_ctx:
  4758. cnss_aop_interface_deinit(plat_priv);
  4759. platform_set_drvdata(plat_dev, NULL);
  4760. cnss_deinitialize_mem_pool();
  4761. reset_plat_dev:
  4762. cnss_clear_plat_priv(plat_priv);
  4763. out:
  4764. return ret;
  4765. }
  4766. static int cnss_remove(struct platform_device *plat_dev)
  4767. {
  4768. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  4769. plat_priv->audio_iommu_domain = NULL;
  4770. cnss_genl_exit();
  4771. cnss_unregister_ims_service(plat_priv);
  4772. cnss_unregister_coex_service(plat_priv);
  4773. cnss_bus_deinit(plat_priv);
  4774. cnss_misc_deinit(plat_priv);
  4775. cnss_debugfs_destroy(plat_priv);
  4776. cnss_cancel_dms_work();
  4777. cnss_dms_deinit(plat_priv);
  4778. cnss_qmi_deinit(plat_priv);
  4779. cnss_event_work_deinit(plat_priv);
  4780. cnss_remove_sysfs(plat_priv);
  4781. cnss_unregister_bus_scale(plat_priv);
  4782. cnss_unregister_esoc(plat_priv);
  4783. cnss_put_resources(plat_priv);
  4784. cnss_aop_interface_deinit(plat_priv);
  4785. cnss_deinitialize_mem_pool();
  4786. platform_set_drvdata(plat_dev, NULL);
  4787. cnss_clear_plat_priv(plat_priv);
  4788. return 0;
  4789. }
  4790. static struct platform_driver cnss_platform_driver = {
  4791. .probe = cnss_probe,
  4792. .remove = cnss_remove,
  4793. .driver = {
  4794. .name = "cnss2",
  4795. .of_match_table = cnss_of_match_table,
  4796. #ifdef CONFIG_CNSS_ASYNC
  4797. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  4798. #endif
  4799. },
  4800. };
  4801. static bool cnss_check_compatible_node(void)
  4802. {
  4803. struct device_node *dn = NULL;
  4804. for_each_matching_node(dn, cnss_of_match_table) {
  4805. if (of_device_is_available(dn)) {
  4806. cnss_allow_driver_loading = true;
  4807. return true;
  4808. }
  4809. }
  4810. return false;
  4811. }
  4812. /**
  4813. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  4814. *
  4815. * Valid device tree node means a node with "compatible" property from the
  4816. * device match table and "status" property is not disabled.
  4817. *
  4818. * Return: true if valid device tree node found, false if not found
  4819. */
  4820. static bool cnss_is_valid_dt_node_found(void)
  4821. {
  4822. struct device_node *dn = NULL;
  4823. for_each_matching_node(dn, cnss_of_match_table) {
  4824. if (of_device_is_available(dn))
  4825. break;
  4826. }
  4827. if (dn)
  4828. return true;
  4829. return false;
  4830. }
  4831. static int __init cnss_initialize(void)
  4832. {
  4833. int ret = 0;
  4834. if (!cnss_is_valid_dt_node_found())
  4835. return -ENODEV;
  4836. if (!cnss_check_compatible_node())
  4837. return ret;
  4838. cnss_debug_init();
  4839. ret = platform_driver_register(&cnss_platform_driver);
  4840. if (ret)
  4841. cnss_debug_deinit();
  4842. ret = cnss_genl_init();
  4843. if (ret < 0)
  4844. cnss_pr_err("CNSS genl init failed %d\n", ret);
  4845. cnss_init_plat_env_count();
  4846. return ret;
  4847. }
  4848. static void __exit cnss_exit(void)
  4849. {
  4850. cnss_genl_exit();
  4851. platform_driver_unregister(&cnss_platform_driver);
  4852. cnss_debug_deinit();
  4853. }
  4854. module_init(cnss_initialize);
  4855. module_exit(cnss_exit);
  4856. MODULE_LICENSE("GPL v2");
  4857. MODULE_DESCRIPTION("CNSS2 Platform Driver");