bus.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "bus.h"
  7. #include "debug.h"
  8. #include "pci.h"
  9. #include "pci_platform.h"
  10. enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev)
  11. {
  12. if (!dev)
  13. return CNSS_BUS_NONE;
  14. if (!dev->bus)
  15. return CNSS_BUS_NONE;
  16. if (memcmp(dev->bus->name, "pci", 3) == 0)
  17. return CNSS_BUS_PCI;
  18. else
  19. return CNSS_BUS_NONE;
  20. }
  21. enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv)
  22. {
  23. int ret;
  24. struct device *dev;
  25. u32 bus_type_dt = CNSS_BUS_NONE;
  26. if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) {
  27. dev = &plat_priv->plat_dev->dev;
  28. ret = of_property_read_u32(dev->of_node, "qcom,bus-type",
  29. &bus_type_dt);
  30. if (!ret)
  31. if (bus_type_dt < CNSS_BUS_MAX)
  32. cnss_pr_dbg("Got bus type[%u] from dt\n",
  33. bus_type_dt);
  34. else
  35. bus_type_dt = CNSS_BUS_NONE;
  36. else
  37. cnss_pr_err("No bus type for multi-exchg dt\n");
  38. return bus_type_dt;
  39. }
  40. switch (plat_priv->device_id) {
  41. case QCA6174_DEVICE_ID:
  42. case QCA6290_DEVICE_ID:
  43. case QCA6390_DEVICE_ID:
  44. case QCN7605_DEVICE_ID:
  45. case QCA6490_DEVICE_ID:
  46. case KIWI_DEVICE_ID:
  47. case MANGO_DEVICE_ID:
  48. case PEACH_DEVICE_ID:
  49. return CNSS_BUS_PCI;
  50. default:
  51. cnss_pr_err("Unknown device_id: 0x%lx\n", plat_priv->device_id);
  52. return CNSS_BUS_NONE;
  53. }
  54. }
  55. void *cnss_bus_dev_to_bus_priv(struct device *dev)
  56. {
  57. if (!dev)
  58. return NULL;
  59. switch (cnss_get_dev_bus_type(dev)) {
  60. case CNSS_BUS_PCI:
  61. return cnss_get_pci_priv(to_pci_dev(dev));
  62. default:
  63. return NULL;
  64. }
  65. }
  66. struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev)
  67. {
  68. void *bus_priv;
  69. if (!dev)
  70. return cnss_get_plat_priv(NULL);
  71. bus_priv = cnss_bus_dev_to_bus_priv(dev);
  72. if (!bus_priv)
  73. return NULL;
  74. switch (cnss_get_dev_bus_type(dev)) {
  75. case CNSS_BUS_PCI:
  76. return cnss_pci_priv_to_plat_priv(bus_priv);
  77. default:
  78. return NULL;
  79. }
  80. }
  81. int cnss_bus_init(struct cnss_plat_data *plat_priv)
  82. {
  83. if (!plat_priv)
  84. return -ENODEV;
  85. switch (plat_priv->bus_type) {
  86. case CNSS_BUS_PCI:
  87. return cnss_pci_init(plat_priv);
  88. default:
  89. cnss_pr_err("Unsupported bus type: %d\n",
  90. plat_priv->bus_type);
  91. return -EINVAL;
  92. }
  93. }
  94. void cnss_bus_deinit(struct cnss_plat_data *plat_priv)
  95. {
  96. if (!plat_priv)
  97. return;
  98. switch (plat_priv->bus_type) {
  99. case CNSS_BUS_PCI:
  100. return cnss_pci_deinit(plat_priv);
  101. default:
  102. cnss_pr_err("Unsupported bus type: %d\n",
  103. plat_priv->bus_type);
  104. return;
  105. }
  106. }
  107. void cnss_bus_add_fw_prefix_name(struct cnss_plat_data *plat_priv,
  108. char *prefix_name, char *name)
  109. {
  110. if (!plat_priv)
  111. return;
  112. switch (plat_priv->bus_type) {
  113. case CNSS_BUS_PCI:
  114. return cnss_pci_add_fw_prefix_name(plat_priv->bus_priv,
  115. prefix_name, name);
  116. default:
  117. cnss_pr_err("Unsupported bus type: %d\n",
  118. plat_priv->bus_type);
  119. return;
  120. }
  121. }
  122. int cnss_bus_load_tme_patch(struct cnss_plat_data *plat_priv)
  123. {
  124. if (!plat_priv)
  125. return -ENODEV;
  126. switch (plat_priv->bus_type) {
  127. case CNSS_BUS_PCI:
  128. return cnss_pci_load_tme_patch(plat_priv->bus_priv);
  129. default:
  130. cnss_pr_err("Unsupported bus type: %d\n",
  131. plat_priv->bus_type);
  132. return -EINVAL;
  133. }
  134. }
  135. int cnss_bus_load_tme_opt_file(struct cnss_plat_data *plat_priv,
  136. enum wlfw_tme_lite_file_type_v01 file)
  137. {
  138. if (!plat_priv)
  139. return -ENODEV;
  140. switch (plat_priv->bus_type) {
  141. case CNSS_BUS_PCI:
  142. return cnss_pci_load_tme_opt_file(plat_priv->bus_priv, file);
  143. default:
  144. cnss_pr_err("Unsupported bus type: %d\n",
  145. plat_priv->bus_type);
  146. return -EINVAL;
  147. }
  148. }
  149. int cnss_bus_load_m3(struct cnss_plat_data *plat_priv)
  150. {
  151. if (!plat_priv)
  152. return -ENODEV;
  153. switch (plat_priv->bus_type) {
  154. case CNSS_BUS_PCI:
  155. return cnss_pci_load_m3(plat_priv->bus_priv);
  156. default:
  157. cnss_pr_err("Unsupported bus type: %d\n",
  158. plat_priv->bus_type);
  159. return -EINVAL;
  160. }
  161. }
  162. int cnss_bus_load_aux(struct cnss_plat_data *plat_priv)
  163. {
  164. if (!plat_priv)
  165. return -ENODEV;
  166. switch (plat_priv->bus_type) {
  167. case CNSS_BUS_PCI:
  168. return cnss_pci_load_aux(plat_priv->bus_priv);
  169. default:
  170. cnss_pr_err("Unsupported bus type: %d\n",
  171. plat_priv->bus_type);
  172. return -EINVAL;
  173. }
  174. }
  175. int cnss_bus_handle_dev_sol_irq(struct cnss_plat_data *plat_priv)
  176. {
  177. if (!plat_priv)
  178. return -ENODEV;
  179. switch (plat_priv->bus_type) {
  180. case CNSS_BUS_PCI:
  181. return cnss_pci_handle_dev_sol_irq(plat_priv->bus_priv);
  182. default:
  183. cnss_pr_err("Unsupported bus type: %d\n",
  184. plat_priv->bus_type);
  185. return -EINVAL;
  186. }
  187. }
  188. int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv)
  189. {
  190. if (!plat_priv)
  191. return -ENODEV;
  192. switch (plat_priv->bus_type) {
  193. case CNSS_BUS_PCI:
  194. return cnss_pci_alloc_fw_mem(plat_priv->bus_priv);
  195. default:
  196. cnss_pr_err("Unsupported bus type: %d\n",
  197. plat_priv->bus_type);
  198. return -EINVAL;
  199. }
  200. }
  201. int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv)
  202. {
  203. if (!plat_priv)
  204. return -ENODEV;
  205. switch (plat_priv->bus_type) {
  206. case CNSS_BUS_PCI:
  207. return cnss_pci_alloc_qdss_mem(plat_priv->bus_priv);
  208. default:
  209. cnss_pr_err("Unsupported bus type: %d\n",
  210. plat_priv->bus_type);
  211. return -EINVAL;
  212. }
  213. }
  214. void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv)
  215. {
  216. if (!plat_priv)
  217. return;
  218. switch (plat_priv->bus_type) {
  219. case CNSS_BUS_PCI:
  220. cnss_pci_free_qdss_mem(plat_priv->bus_priv);
  221. return;
  222. default:
  223. cnss_pr_err("Unsupported bus type: %d\n",
  224. plat_priv->bus_type);
  225. return;
  226. }
  227. }
  228. u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv)
  229. {
  230. if (!plat_priv)
  231. return -ENODEV;
  232. switch (plat_priv->bus_type) {
  233. case CNSS_BUS_PCI:
  234. return cnss_pci_get_wake_msi(plat_priv->bus_priv);
  235. default:
  236. cnss_pr_err("Unsupported bus type: %d\n",
  237. plat_priv->bus_type);
  238. return -EINVAL;
  239. }
  240. }
  241. int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv)
  242. {
  243. if (!plat_priv)
  244. return -ENODEV;
  245. switch (plat_priv->bus_type) {
  246. case CNSS_BUS_PCI:
  247. return cnss_pci_force_fw_assert_hdlr(plat_priv->bus_priv);
  248. default:
  249. cnss_pr_err("Unsupported bus type: %d\n",
  250. plat_priv->bus_type);
  251. return -EINVAL;
  252. }
  253. }
  254. int cnss_bus_qmi_send_get(struct cnss_plat_data *plat_priv)
  255. {
  256. if (!plat_priv)
  257. return -ENODEV;
  258. switch (plat_priv->bus_type) {
  259. case CNSS_BUS_PCI:
  260. return cnss_pci_qmi_send_get(plat_priv->bus_priv);
  261. default:
  262. cnss_pr_err("Unsupported bus type: %d\n",
  263. plat_priv->bus_type);
  264. return -EINVAL;
  265. }
  266. }
  267. int cnss_bus_qmi_send_put(struct cnss_plat_data *plat_priv)
  268. {
  269. if (!plat_priv)
  270. return -ENODEV;
  271. switch (plat_priv->bus_type) {
  272. case CNSS_BUS_PCI:
  273. return cnss_pci_qmi_send_put(plat_priv->bus_priv);
  274. default:
  275. cnss_pr_err("Unsupported bus type: %d\n",
  276. plat_priv->bus_type);
  277. return -EINVAL;
  278. }
  279. }
  280. void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t)
  281. {
  282. struct cnss_plat_data *plat_priv =
  283. from_timer(plat_priv, t, fw_boot_timer);
  284. if (!plat_priv)
  285. return;
  286. switch (plat_priv->bus_type) {
  287. case CNSS_BUS_PCI:
  288. return cnss_pci_fw_boot_timeout_hdlr(plat_priv->bus_priv);
  289. default:
  290. cnss_pr_err("Unsupported bus type: %d\n",
  291. plat_priv->bus_type);
  292. return;
  293. }
  294. }
  295. void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, bool in_panic)
  296. {
  297. if (!plat_priv)
  298. return;
  299. switch (plat_priv->bus_type) {
  300. case CNSS_BUS_PCI:
  301. return cnss_pci_collect_dump_info(plat_priv->bus_priv,
  302. in_panic);
  303. default:
  304. cnss_pr_err("Unsupported bus type: %d\n",
  305. plat_priv->bus_type);
  306. return;
  307. }
  308. }
  309. void cnss_bus_device_crashed(struct cnss_plat_data *plat_priv)
  310. {
  311. if (!plat_priv)
  312. return;
  313. switch (plat_priv->bus_type) {
  314. case CNSS_BUS_PCI:
  315. return cnss_pci_device_crashed(plat_priv->bus_priv);
  316. default:
  317. cnss_pr_err("Unsupported bus type: %d\n",
  318. plat_priv->bus_type);
  319. return;
  320. }
  321. }
  322. int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv)
  323. {
  324. if (!plat_priv)
  325. return -ENODEV;
  326. switch (plat_priv->bus_type) {
  327. case CNSS_BUS_PCI:
  328. return cnss_pci_call_driver_probe(plat_priv->bus_priv);
  329. default:
  330. cnss_pr_err("Unsupported bus type: %d\n",
  331. plat_priv->bus_type);
  332. return -EINVAL;
  333. }
  334. }
  335. int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv)
  336. {
  337. if (!plat_priv)
  338. return -ENODEV;
  339. switch (plat_priv->bus_type) {
  340. case CNSS_BUS_PCI:
  341. return cnss_pci_call_driver_remove(plat_priv->bus_priv);
  342. default:
  343. cnss_pr_err("Unsupported bus type: %d\n",
  344. plat_priv->bus_type);
  345. return -EINVAL;
  346. }
  347. }
  348. int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv)
  349. {
  350. if (!plat_priv)
  351. return -ENODEV;
  352. switch (plat_priv->bus_type) {
  353. case CNSS_BUS_PCI:
  354. return cnss_pci_dev_powerup(plat_priv->bus_priv);
  355. default:
  356. cnss_pr_err("Unsupported bus type: %d\n",
  357. plat_priv->bus_type);
  358. return -EINVAL;
  359. }
  360. }
  361. int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv)
  362. {
  363. if (!plat_priv)
  364. return -ENODEV;
  365. switch (plat_priv->bus_type) {
  366. case CNSS_BUS_PCI:
  367. return cnss_pci_dev_shutdown(plat_priv->bus_priv);
  368. default:
  369. cnss_pr_err("Unsupported bus type: %d\n",
  370. plat_priv->bus_type);
  371. return -EINVAL;
  372. }
  373. }
  374. int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv)
  375. {
  376. if (!plat_priv)
  377. return -ENODEV;
  378. switch (plat_priv->bus_type) {
  379. case CNSS_BUS_PCI:
  380. return cnss_pci_dev_crash_shutdown(plat_priv->bus_priv);
  381. default:
  382. cnss_pr_err("Unsupported bus type: %d\n",
  383. plat_priv->bus_type);
  384. return -EINVAL;
  385. }
  386. }
  387. int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv)
  388. {
  389. if (!plat_priv)
  390. return -ENODEV;
  391. switch (plat_priv->bus_type) {
  392. case CNSS_BUS_PCI:
  393. return cnss_pci_dev_ramdump(plat_priv->bus_priv);
  394. default:
  395. cnss_pr_err("Unsupported bus type: %d\n",
  396. plat_priv->bus_type);
  397. return -EINVAL;
  398. }
  399. }
  400. int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data)
  401. {
  402. if (!plat_priv)
  403. return -ENODEV;
  404. switch (plat_priv->bus_type) {
  405. case CNSS_BUS_PCI:
  406. return cnss_pci_register_driver_hdlr(plat_priv->bus_priv, data);
  407. default:
  408. cnss_pr_err("Unsupported bus type: %d\n",
  409. plat_priv->bus_type);
  410. return -EINVAL;
  411. }
  412. }
  413. int cnss_bus_runtime_pm_get_sync(struct cnss_plat_data *plat_priv)
  414. {
  415. if (!plat_priv)
  416. return -ENODEV;
  417. switch (plat_priv->bus_type) {
  418. case CNSS_BUS_PCI:
  419. return cnss_pci_pm_runtime_get_sync(plat_priv->bus_priv, RTPM_ID_CNSS);
  420. default:
  421. cnss_pr_err("Unsupported bus type: %d\n",
  422. plat_priv->bus_type);
  423. return -EINVAL;
  424. }
  425. }
  426. void cnss_bus_runtime_pm_put(struct cnss_plat_data *plat_priv)
  427. {
  428. if (!plat_priv)
  429. return;
  430. switch (plat_priv->bus_type) {
  431. case CNSS_BUS_PCI:
  432. cnss_pci_pm_runtime_mark_last_busy(plat_priv->bus_priv);
  433. cnss_pci_pm_runtime_put_autosuspend(plat_priv->bus_priv, RTPM_ID_CNSS);
  434. break;
  435. default:
  436. cnss_pr_err("Unsupported bus type: %d\n",
  437. plat_priv->bus_type);
  438. }
  439. }
  440. int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv)
  441. {
  442. if (!plat_priv)
  443. return -ENODEV;
  444. switch (plat_priv->bus_type) {
  445. case CNSS_BUS_PCI:
  446. return cnss_pci_unregister_driver_hdlr(plat_priv->bus_priv);
  447. default:
  448. cnss_pr_err("Unsupported bus type: %d\n",
  449. plat_priv->bus_type);
  450. return -EINVAL;
  451. }
  452. }
  453. int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv,
  454. int modem_current_status)
  455. {
  456. if (!plat_priv)
  457. return -ENODEV;
  458. switch (plat_priv->bus_type) {
  459. case CNSS_BUS_PCI:
  460. return cnss_pci_call_driver_modem_status(plat_priv->bus_priv,
  461. modem_current_status);
  462. default:
  463. cnss_pr_err("Unsupported bus type: %d\n",
  464. plat_priv->bus_type);
  465. return -EINVAL;
  466. }
  467. }
  468. int cnss_bus_update_status(struct cnss_plat_data *plat_priv,
  469. enum cnss_driver_status status)
  470. {
  471. if (!plat_priv)
  472. return -ENODEV;
  473. switch (plat_priv->bus_type) {
  474. case CNSS_BUS_PCI:
  475. return cnss_pci_update_status(plat_priv->bus_priv, status);
  476. default:
  477. cnss_pr_err("Unsupported bus type: %d\n",
  478. plat_priv->bus_type);
  479. return -EINVAL;
  480. }
  481. }
  482. int cnss_bus_update_uevent(struct cnss_plat_data *plat_priv,
  483. enum cnss_driver_status status, void *data)
  484. {
  485. if (!plat_priv)
  486. return -ENODEV;
  487. switch (plat_priv->bus_type) {
  488. case CNSS_BUS_PCI:
  489. return cnss_pci_call_driver_uevent(plat_priv->bus_priv,
  490. status, data);
  491. default:
  492. cnss_pr_err("Unsupported bus type: %d\n",
  493. plat_priv->bus_type);
  494. return -EINVAL;
  495. }
  496. }
  497. int cnss_bus_is_device_down(struct cnss_plat_data *plat_priv)
  498. {
  499. if (!plat_priv)
  500. return -ENODEV;
  501. switch (plat_priv->bus_type) {
  502. case CNSS_BUS_PCI:
  503. return cnss_pcie_is_device_down(plat_priv->bus_priv);
  504. default:
  505. cnss_pr_dbg("Unsupported bus type: %d\n",
  506. plat_priv->bus_type);
  507. return 0;
  508. }
  509. }
  510. int cnss_bus_shutdown_cleanup(struct cnss_plat_data *plat_priv)
  511. {
  512. if (!plat_priv)
  513. return -ENODEV;
  514. switch (plat_priv->bus_type) {
  515. case CNSS_BUS_PCI:
  516. return cnss_pci_shutdown_cleanup(plat_priv->bus_priv);
  517. default:
  518. cnss_pr_dbg("Unsupported bus type: %d\n",
  519. plat_priv->bus_type);
  520. return 0;
  521. }
  522. }
  523. int cnss_bus_check_link_status(struct cnss_plat_data *plat_priv)
  524. {
  525. if (!plat_priv)
  526. return -ENODEV;
  527. switch (plat_priv->bus_type) {
  528. case CNSS_BUS_PCI:
  529. return cnss_pci_check_link_status(plat_priv->bus_priv);
  530. default:
  531. cnss_pr_dbg("Unsupported bus type: %d\n",
  532. plat_priv->bus_type);
  533. return 0;
  534. }
  535. }
  536. int cnss_bus_recover_link_down(struct cnss_plat_data *plat_priv)
  537. {
  538. if (!plat_priv)
  539. return -ENODEV;
  540. switch (plat_priv->bus_type) {
  541. case CNSS_BUS_PCI:
  542. return cnss_pci_recover_link_down(plat_priv->bus_priv);
  543. default:
  544. cnss_pr_dbg("Unsupported bus type: %d\n",
  545. plat_priv->bus_type);
  546. return -EINVAL;
  547. }
  548. }
  549. int cnss_bus_debug_reg_read(struct cnss_plat_data *plat_priv, u32 offset,
  550. u32 *val, bool raw_access)
  551. {
  552. if (!plat_priv)
  553. return -ENODEV;
  554. switch (plat_priv->bus_type) {
  555. case CNSS_BUS_PCI:
  556. return cnss_pci_debug_reg_read(plat_priv->bus_priv, offset,
  557. val, raw_access);
  558. default:
  559. cnss_pr_dbg("Unsupported bus type: %d\n",
  560. plat_priv->bus_type);
  561. return 0;
  562. }
  563. }
  564. int cnss_bus_debug_reg_write(struct cnss_plat_data *plat_priv, u32 offset,
  565. u32 val, bool raw_access)
  566. {
  567. if (!plat_priv)
  568. return -ENODEV;
  569. switch (plat_priv->bus_type) {
  570. case CNSS_BUS_PCI:
  571. return cnss_pci_debug_reg_write(plat_priv->bus_priv, offset,
  572. val, raw_access);
  573. default:
  574. cnss_pr_dbg("Unsupported bus type: %d\n",
  575. plat_priv->bus_type);
  576. return 0;
  577. }
  578. }
  579. int cnss_bus_get_iova(struct cnss_plat_data *plat_priv, u64 *addr, u64 *size)
  580. {
  581. if (!plat_priv)
  582. return -ENODEV;
  583. switch (plat_priv->bus_type) {
  584. case CNSS_BUS_PCI:
  585. return cnss_pci_get_iova(plat_priv->bus_priv, addr, size);
  586. default:
  587. cnss_pr_err("Unsupported bus type: %d\n",
  588. plat_priv->bus_type);
  589. return -EINVAL;
  590. }
  591. }
  592. int cnss_bus_get_iova_ipa(struct cnss_plat_data *plat_priv, u64 *addr,
  593. u64 *size)
  594. {
  595. if (!plat_priv)
  596. return -ENODEV;
  597. switch (plat_priv->bus_type) {
  598. case CNSS_BUS_PCI:
  599. return cnss_pci_get_iova_ipa(plat_priv->bus_priv, addr, size);
  600. default:
  601. cnss_pr_err("Unsupported bus type: %d\n",
  602. plat_priv->bus_type);
  603. return -EINVAL;
  604. }
  605. }
  606. bool cnss_bus_is_smmu_s1_enabled(struct cnss_plat_data *plat_priv)
  607. {
  608. if (!plat_priv)
  609. return false;
  610. switch (plat_priv->bus_type) {
  611. case CNSS_BUS_PCI:
  612. return cnss_pci_is_smmu_s1_enabled(plat_priv->bus_priv);
  613. default:
  614. cnss_pr_err("Unsupported bus type: %d\n",
  615. plat_priv->bus_type);
  616. return false;
  617. }
  618. }
  619. int cnss_bus_dsp_link_control(struct cnss_plat_data *plat_priv,
  620. bool link_enable)
  621. {
  622. if (!plat_priv || plat_priv->pcie_switch_type != PCIE_SWITCH_NTN3)
  623. return -ENODEV;
  624. switch (plat_priv->bus_type) {
  625. case CNSS_BUS_PCI:
  626. return cnss_pci_dsp_link_control(plat_priv->bus_priv, link_enable);
  627. default:
  628. cnss_pr_err("Unsupported bus type: %d\n",
  629. plat_priv->bus_type);
  630. return -EINVAL;
  631. }
  632. }
  633. int cnss_bus_set_dsp_link_status(struct cnss_plat_data *plat_priv,
  634. bool link_enable)
  635. {
  636. if (!plat_priv || plat_priv->pcie_switch_type != PCIE_SWITCH_NTN3)
  637. return -ENODEV;
  638. switch (plat_priv->bus_type) {
  639. case CNSS_BUS_PCI:
  640. return cnss_pci_set_dsp_link_status(plat_priv->bus_priv, link_enable);
  641. default:
  642. cnss_pr_err("Unsupported bus type: %d\n",
  643. plat_priv->bus_type);
  644. return -EINVAL;
  645. }
  646. }
  647. int cnss_bus_get_dsp_link_status(struct cnss_plat_data *plat_priv)
  648. {
  649. if (!plat_priv || plat_priv->pcie_switch_type != PCIE_SWITCH_NTN3)
  650. return -ENODEV;
  651. switch (plat_priv->bus_type) {
  652. case CNSS_BUS_PCI:
  653. return cnss_pci_get_dsp_link_status(plat_priv->bus_priv);
  654. default:
  655. cnss_pr_err("Unsupported bus type: %d\n",
  656. plat_priv->bus_type);
  657. return -EINVAL;
  658. }
  659. }
  660. int cnss_bus_dsp_link_enable(struct cnss_plat_data *plat_priv)
  661. {
  662. if (!plat_priv || plat_priv->pcie_switch_type != PCIE_SWITCH_NTN3)
  663. return -ENODEV;
  664. switch (plat_priv->bus_type) {
  665. case CNSS_BUS_PCI:
  666. return cnss_pci_dsp_link_enable(plat_priv->bus_priv);
  667. default:
  668. cnss_pr_err("Unsupported bus type: %d\n",
  669. plat_priv->bus_type);
  670. return -EINVAL;
  671. }
  672. }
  673. int cnss_bus_update_time_sync_period(struct cnss_plat_data *plat_priv,
  674. unsigned int time_sync_period)
  675. {
  676. if (!plat_priv)
  677. return -ENODEV;
  678. switch (plat_priv->bus_type) {
  679. case CNSS_BUS_PCI:
  680. return cnss_pci_update_time_sync_period(plat_priv->bus_priv,
  681. time_sync_period);
  682. default:
  683. cnss_pr_err("Unsupported bus type: %d\n",
  684. plat_priv->bus_type);
  685. return -EINVAL;
  686. }
  687. }
  688. int cnss_bus_set_therm_cdev_state(struct cnss_plat_data *plat_priv,
  689. unsigned long thermal_state,
  690. int tcdev_id)
  691. {
  692. if (!plat_priv)
  693. return -ENODEV;
  694. switch (plat_priv->bus_type) {
  695. case CNSS_BUS_PCI:
  696. return cnss_pci_set_therm_cdev_state(plat_priv->bus_priv,
  697. thermal_state,
  698. tcdev_id);
  699. default:
  700. cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type);
  701. return -EINVAL;
  702. }
  703. }
  704. int cnss_bus_get_msi_assignment(struct cnss_plat_data *plat_priv,
  705. char *msi_name,
  706. int *num_vectors,
  707. u32 *user_base_data,
  708. u32 *base_vector)
  709. {
  710. if (!plat_priv)
  711. return -ENODEV;
  712. switch (plat_priv->bus_type) {
  713. case CNSS_BUS_PCI:
  714. return cnss_pci_get_user_msi_assignment(plat_priv->bus_priv,
  715. msi_name,
  716. num_vectors,
  717. user_base_data,
  718. base_vector);
  719. default:
  720. cnss_pr_err("Unsupported bus type: %d\n", plat_priv->bus_type);
  721. return -EINVAL;
  722. }
  723. }
  724. #if IS_ENABLED(CONFIG_MHI_BUS_MISC)
  725. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *plat_priv)
  726. {
  727. struct cnss_pci_data *pci_priv;
  728. pci_priv = plat_priv->bus_priv;
  729. if (!pci_priv) {
  730. cnss_pr_err("mhi satellite could not be disabled since pci_priv is NULL\n");
  731. return;
  732. }
  733. switch (plat_priv->bus_type) {
  734. case CNSS_BUS_PCI:
  735. /* MHI satellite configuration is only for KIWI V2 and
  736. * that too only in DRV mode.
  737. */
  738. if (plat_priv->device_id == KIWI_DEVICE_ID &&
  739. plat_priv->device_version.major_version == FW_V2_NUMBER) {
  740. cnss_pr_dbg("Remove MHI satellite configuration\n");
  741. return cnss_mhi_controller_set_base(pci_priv, 0);
  742. }
  743. break;
  744. default:
  745. cnss_pr_dbg("Unsupported bus type: %d, ignore disable mhi satellite cfg\n",
  746. plat_priv->bus_type);
  747. return;
  748. }
  749. return;
  750. }
  751. #else
  752. void cnss_bus_disable_mhi_satellite_cfg(struct cnss_plat_data *pci_priv)
  753. {
  754. }
  755. #endif