qcedev.c 74 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * QTI CE device driver.
  4. *
  5. * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
  6. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  7. */
  8. #include <linux/mman.h>
  9. #include <linux/module.h>
  10. #include <linux/device.h>
  11. #include <linux/types.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/kernel.h>
  15. #include <linux/dmapool.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/fs.h>
  21. #include <linux/uaccess.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/scatterlist.h>
  24. #include <linux/crypto.h>
  25. #include "linux/qcedev.h"
  26. #include <linux/interconnect.h>
  27. #include <linux/delay.h>
  28. #include <linux/version.h>
  29. #include <crypto/hash.h>
  30. #include "qcedevi.h"
  31. #include "qce.h"
  32. #include "qcedev_smmu.h"
  33. #include "qcom_crypto_device.h"
  34. #define CACHE_LINE_SIZE 64
  35. #define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
  36. #define MAX_CEHW_REQ_TRANSFER_SIZE (128*32*1024)
  37. /*
  38. * Max wait time once a crypto request is submitted.
  39. */
  40. #define MAX_CRYPTO_WAIT_TIME 1500
  41. /*
  42. * Max wait time once a offload crypto request is submitted.
  43. * This is low due to expected timeout and key pause errors.
  44. * This is temporary, and we can use the 1500 value once the
  45. * core irqs are enabled.
  46. */
  47. #define MAX_OFFLOAD_CRYPTO_WAIT_TIME 50
  48. #define MAX_REQUEST_TIME 5000
  49. enum qcedev_req_status {
  50. QCEDEV_REQ_CURRENT = 0,
  51. QCEDEV_REQ_WAITING = 1,
  52. QCEDEV_REQ_SUBMITTED = 2,
  53. QCEDEV_REQ_DONE = 3,
  54. };
  55. static uint8_t _std_init_vector_sha1_uint8[] = {
  56. 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
  57. 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
  58. 0xC3, 0xD2, 0xE1, 0xF0
  59. };
  60. /* standard initialization vector for SHA-256, source: FIPS 180-2 */
  61. static uint8_t _std_init_vector_sha256_uint8[] = {
  62. 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
  63. 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
  64. 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
  65. 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
  66. };
  67. #define QCEDEV_CTX_KEY_MASK 0x000000ff
  68. #define QCEDEV_CTX_USE_HW_KEY 0x00000001
  69. #define QCEDEV_CTX_USE_PIPE_KEY 0x00000002
  70. static DEFINE_MUTEX(send_cmd_lock);
  71. static DEFINE_MUTEX(qcedev_sent_bw_req);
  72. static DEFINE_MUTEX(hash_access_lock);
  73. static dev_t qcedev_device_no;
  74. static struct class *driver_class;
  75. static struct device *class_dev;
  76. static const struct of_device_id qcedev_match[] = {
  77. { .compatible = "qcom,qcedev"},
  78. { .compatible = "qcom,qcedev,context-bank"},
  79. {}
  80. };
  81. MODULE_DEVICE_TABLE(of, qcedev_match);
  82. static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
  83. {
  84. unsigned int control_flag;
  85. int ret = 0;
  86. if (podev->ce_support.req_bw_before_clk) {
  87. if (enable)
  88. control_flag = QCE_BW_REQUEST_FIRST;
  89. else
  90. control_flag = QCE_CLK_DISABLE_FIRST;
  91. } else {
  92. if (enable)
  93. control_flag = QCE_CLK_ENABLE_FIRST;
  94. else
  95. control_flag = QCE_BW_REQUEST_RESET_FIRST;
  96. }
  97. switch (control_flag) {
  98. case QCE_CLK_ENABLE_FIRST:
  99. ret = qce_enable_clk(podev->qce);
  100. if (ret) {
  101. pr_err("%s Unable enable clk\n", __func__);
  102. return ret;
  103. }
  104. ret = icc_set_bw(podev->icc_path,
  105. podev->icc_avg_bw, podev->icc_peak_bw);
  106. if (ret) {
  107. pr_err("%s Unable to set high bw\n", __func__);
  108. ret = qce_disable_clk(podev->qce);
  109. if (ret)
  110. pr_err("%s Unable disable clk\n", __func__);
  111. return ret;
  112. }
  113. break;
  114. case QCE_BW_REQUEST_FIRST:
  115. ret = icc_set_bw(podev->icc_path,
  116. podev->icc_avg_bw, podev->icc_peak_bw);
  117. if (ret) {
  118. pr_err("%s Unable to set high bw\n", __func__);
  119. return ret;
  120. }
  121. ret = qce_enable_clk(podev->qce);
  122. if (ret) {
  123. pr_err("%s Unable enable clk\n", __func__);
  124. ret = icc_set_bw(podev->icc_path, 0, 0);
  125. if (ret)
  126. pr_err("%s Unable to set low bw\n", __func__);
  127. return ret;
  128. }
  129. break;
  130. case QCE_CLK_DISABLE_FIRST:
  131. ret = qce_disable_clk(podev->qce);
  132. if (ret) {
  133. pr_err("%s Unable to disable clk\n", __func__);
  134. return ret;
  135. }
  136. ret = icc_set_bw(podev->icc_path, 0, 0);
  137. if (ret) {
  138. pr_err("%s Unable to set low bw\n", __func__);
  139. ret = qce_enable_clk(podev->qce);
  140. if (ret)
  141. pr_err("%s Unable enable clk\n", __func__);
  142. return ret;
  143. }
  144. break;
  145. case QCE_BW_REQUEST_RESET_FIRST:
  146. ret = icc_set_bw(podev->icc_path, 0, 0);
  147. if (ret) {
  148. pr_err("%s Unable to set low bw\n", __func__);
  149. return ret;
  150. }
  151. ret = qce_disable_clk(podev->qce);
  152. if (ret) {
  153. pr_err("%s Unable to disable clk\n", __func__);
  154. ret = icc_set_bw(podev->icc_path,
  155. podev->icc_avg_bw, podev->icc_peak_bw);
  156. if (ret)
  157. pr_err("%s Unable to set high bw\n", __func__);
  158. return ret;
  159. }
  160. break;
  161. default:
  162. return -ENOENT;
  163. }
  164. return 0;
  165. }
  166. static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
  167. bool high_bw_req)
  168. {
  169. int ret = 0;
  170. if(podev == NULL) return;
  171. mutex_lock(&qcedev_sent_bw_req);
  172. if (high_bw_req) {
  173. if (podev->high_bw_req_count == 0) {
  174. ret = qcedev_control_clocks(podev, true);
  175. if (ret)
  176. goto exit_unlock_mutex;
  177. ret = qce_set_irqs(podev->qce, true);
  178. if (ret) {
  179. pr_err("%s: could not enable bam irqs, ret = %d",
  180. __func__, ret);
  181. qcedev_control_clocks(podev, false);
  182. goto exit_unlock_mutex;
  183. }
  184. }
  185. podev->high_bw_req_count++;
  186. } else {
  187. if (podev->high_bw_req_count == 1) {
  188. ret = qce_set_irqs(podev->qce, false);
  189. if (ret) {
  190. pr_err("%s: could not disable bam irqs, ret = %d",
  191. __func__, ret);
  192. goto exit_unlock_mutex;
  193. }
  194. ret = qcedev_control_clocks(podev, false);
  195. if (ret)
  196. goto exit_unlock_mutex;
  197. }
  198. podev->high_bw_req_count--;
  199. }
  200. exit_unlock_mutex:
  201. mutex_unlock(&qcedev_sent_bw_req);
  202. }
  203. #define QCEDEV_MAGIC 0x56434544 /* "qced" */
  204. static int qcedev_open(struct inode *inode, struct file *file);
  205. static int qcedev_release(struct inode *inode, struct file *file);
  206. static int start_cipher_req(struct qcedev_control *podev,
  207. int *current_req_info);
  208. static int start_offload_cipher_req(struct qcedev_control *podev,
  209. int *current_req_info);
  210. static int start_sha_req(struct qcedev_control *podev,
  211. int *current_req_info);
  212. static const struct file_operations qcedev_fops = {
  213. .owner = THIS_MODULE,
  214. .unlocked_ioctl = qcedev_ioctl,
  215. .open = qcedev_open,
  216. .release = qcedev_release,
  217. };
  218. static struct qcedev_control qce_dev[] = {
  219. {
  220. .magic = QCEDEV_MAGIC,
  221. },
  222. };
  223. #define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
  224. #define DEBUG_MAX_FNAME 16
  225. #define DEBUG_MAX_RW_BUF 1024
  226. struct qcedev_stat {
  227. u32 qcedev_dec_success;
  228. u32 qcedev_dec_fail;
  229. u32 qcedev_enc_success;
  230. u32 qcedev_enc_fail;
  231. u32 qcedev_sha_success;
  232. u32 qcedev_sha_fail;
  233. };
  234. static struct qcedev_stat _qcedev_stat;
  235. static struct dentry *_debug_dent;
  236. static char _debug_read_buf[DEBUG_MAX_RW_BUF];
  237. static int _debug_qcedev;
  238. static struct qcedev_control *qcedev_minor_to_control(unsigned int n)
  239. {
  240. int i;
  241. for (i = 0; i < MAX_QCE_DEVICE; i++) {
  242. if (qce_dev[i].minor == n)
  243. return &qce_dev[n];
  244. }
  245. return NULL;
  246. }
  247. static int qcedev_open(struct inode *inode, struct file *file)
  248. {
  249. struct qcedev_handle *handle;
  250. struct qcedev_control *podev;
  251. podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
  252. if (podev == NULL) {
  253. pr_err("%s: no such device %d\n", __func__,
  254. MINOR(inode->i_rdev));
  255. return -ENOENT;
  256. }
  257. handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
  258. if (handle == NULL)
  259. return -ENOMEM;
  260. handle->cntl = podev;
  261. file->private_data = handle;
  262. qcedev_ce_high_bw_req(podev, true);
  263. mutex_init(&handle->registeredbufs.lock);
  264. INIT_LIST_HEAD(&handle->registeredbufs.list);
  265. return 0;
  266. }
  267. static int qcedev_release(struct inode *inode, struct file *file)
  268. {
  269. struct qcedev_control *podev;
  270. struct qcedev_handle *handle;
  271. handle = file->private_data;
  272. podev = handle->cntl;
  273. if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
  274. pr_err("%s: invalid handle %pK\n",
  275. __func__, podev);
  276. }
  277. if (podev)
  278. qcedev_ce_high_bw_req(podev, false);
  279. if (qcedev_unmap_all_buffers(handle))
  280. pr_err("%s: failed to unmap all ion buffers\n", __func__);
  281. kfree_sensitive(handle);
  282. file->private_data = NULL;
  283. return 0;
  284. }
  285. static void req_done(unsigned long data)
  286. {
  287. struct qcedev_control *podev = (struct qcedev_control *)data;
  288. struct qcedev_async_req *areq;
  289. unsigned long flags = 0;
  290. struct qcedev_async_req *new_req = NULL;
  291. spin_lock_irqsave(&podev->lock, flags);
  292. areq = podev->active_command;
  293. podev->active_command = NULL;
  294. if (areq) {
  295. areq->state = QCEDEV_REQ_DONE;
  296. if (!areq->timed_out)
  297. complete(&areq->complete);
  298. }
  299. /* Look through queued requests and wake up the corresponding thread */
  300. if (!list_empty(&podev->ready_commands)) {
  301. new_req = container_of(podev->ready_commands.next,
  302. struct qcedev_async_req, list);
  303. list_del(&new_req->list);
  304. new_req->state = QCEDEV_REQ_CURRENT;
  305. wake_up_interruptible(&new_req->wait_q);
  306. }
  307. spin_unlock_irqrestore(&podev->lock, flags);
  308. }
  309. void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
  310. unsigned char *authdata, int ret)
  311. {
  312. struct qcedev_sha_req *areq;
  313. struct qcedev_control *pdev;
  314. struct qcedev_handle *handle;
  315. uint32_t *auth32 = (uint32_t *)authdata;
  316. areq = (struct qcedev_sha_req *) cookie;
  317. if (!areq || !areq->cookie)
  318. return;
  319. handle = (struct qcedev_handle *) areq->cookie;
  320. pdev = handle->cntl;
  321. if (!pdev)
  322. return;
  323. if (digest)
  324. memcpy(&handle->sha_ctxt.digest[0], digest, 32);
  325. if (authdata) {
  326. handle->sha_ctxt.auth_data[0] = auth32[0];
  327. handle->sha_ctxt.auth_data[1] = auth32[1];
  328. }
  329. tasklet_schedule(&pdev->done_tasklet);
  330. };
  331. void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
  332. unsigned char *iv, int ret)
  333. {
  334. struct qcedev_cipher_req *areq;
  335. struct qcedev_handle *handle;
  336. struct qcedev_control *podev;
  337. struct qcedev_async_req *qcedev_areq;
  338. areq = (struct qcedev_cipher_req *) cookie;
  339. if (!areq || !areq->cookie)
  340. return;
  341. handle = (struct qcedev_handle *) areq->cookie;
  342. podev = handle->cntl;
  343. if (!podev)
  344. return;
  345. qcedev_areq = podev->active_command;
  346. if (iv && qcedev_areq)
  347. memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
  348. qcedev_areq->cipher_op_req.ivlen);
  349. tasklet_schedule(&podev->done_tasklet);
  350. };
  351. static int start_cipher_req(struct qcedev_control *podev,
  352. int *current_req_info)
  353. {
  354. struct qcedev_async_req *qcedev_areq;
  355. struct qce_req creq;
  356. int ret = 0;
  357. memset(&creq, 0, sizeof(creq));
  358. /* start the command on the podev->active_command */
  359. qcedev_areq = podev->active_command;
  360. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  361. if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
  362. pr_err("%s: Use of PMEM is not supported\n", __func__);
  363. goto unsupported;
  364. }
  365. creq.pmem = NULL;
  366. switch (qcedev_areq->cipher_op_req.alg) {
  367. case QCEDEV_ALG_DES:
  368. creq.alg = CIPHER_ALG_DES;
  369. break;
  370. case QCEDEV_ALG_3DES:
  371. creq.alg = CIPHER_ALG_3DES;
  372. break;
  373. case QCEDEV_ALG_AES:
  374. creq.alg = CIPHER_ALG_AES;
  375. break;
  376. default:
  377. return -EINVAL;
  378. }
  379. switch (qcedev_areq->cipher_op_req.mode) {
  380. case QCEDEV_AES_MODE_CBC:
  381. case QCEDEV_DES_MODE_CBC:
  382. creq.mode = QCE_MODE_CBC;
  383. break;
  384. case QCEDEV_AES_MODE_ECB:
  385. case QCEDEV_DES_MODE_ECB:
  386. creq.mode = QCE_MODE_ECB;
  387. break;
  388. case QCEDEV_AES_MODE_CTR:
  389. creq.mode = QCE_MODE_CTR;
  390. break;
  391. case QCEDEV_AES_MODE_XTS:
  392. creq.mode = QCE_MODE_XTS;
  393. break;
  394. default:
  395. return -EINVAL;
  396. }
  397. if ((creq.alg == CIPHER_ALG_AES) &&
  398. (creq.mode == QCE_MODE_CTR)) {
  399. creq.dir = QCE_ENCRYPT;
  400. } else {
  401. if (qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC)
  402. creq.dir = QCE_ENCRYPT;
  403. else
  404. creq.dir = QCE_DECRYPT;
  405. }
  406. creq.iv = &qcedev_areq->cipher_op_req.iv[0];
  407. creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
  408. creq.iv_ctr_size = 0;
  409. creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
  410. creq.encklen = qcedev_areq->cipher_op_req.encklen;
  411. creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
  412. if (qcedev_areq->cipher_op_req.encklen == 0) {
  413. if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
  414. || (qcedev_areq->cipher_op_req.op ==
  415. QCEDEV_OPER_DEC_NO_KEY))
  416. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  417. else {
  418. int i;
  419. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  420. if (qcedev_areq->cipher_op_req.enckey[i] != 0)
  421. break;
  422. }
  423. if ((podev->platform_support.hw_key_support == 1) &&
  424. (i == QCEDEV_MAX_KEY_SIZE))
  425. creq.op = QCE_REQ_ABLK_CIPHER;
  426. else {
  427. ret = -EINVAL;
  428. goto unsupported;
  429. }
  430. }
  431. } else {
  432. creq.op = QCE_REQ_ABLK_CIPHER;
  433. }
  434. creq.qce_cb = qcedev_cipher_req_cb;
  435. creq.areq = (void *)&qcedev_areq->cipher_req;
  436. creq.flags = 0;
  437. creq.offload_op = QCE_OFFLOAD_NONE;
  438. ret = qce_ablk_cipher_req(podev->qce, &creq);
  439. *current_req_info = creq.current_req_info;
  440. unsupported:
  441. qcedev_areq->err = ret ? -ENXIO : 0;
  442. return ret;
  443. };
  444. void qcedev_offload_cipher_req_cb(void *cookie, unsigned char *icv,
  445. unsigned char *iv, int ret)
  446. {
  447. struct qcedev_cipher_req *areq;
  448. struct qcedev_handle *handle;
  449. struct qcedev_control *podev;
  450. struct qcedev_async_req *qcedev_areq;
  451. areq = (struct qcedev_cipher_req *) cookie;
  452. if (!areq || !areq->cookie)
  453. return;
  454. handle = (struct qcedev_handle *) areq->cookie;
  455. podev = handle->cntl;
  456. if (!podev)
  457. return;
  458. qcedev_areq = podev->active_command;
  459. if (iv && qcedev_areq)
  460. memcpy(&qcedev_areq->offload_cipher_op_req.iv[0], iv,
  461. qcedev_areq->offload_cipher_op_req.ivlen);
  462. tasklet_schedule(&podev->done_tasklet);
  463. }
  464. static int start_offload_cipher_req(struct qcedev_control *podev,
  465. int *current_req_info)
  466. {
  467. struct qcedev_async_req *qcedev_areq;
  468. struct qce_req creq;
  469. u8 patt_sz = 0, proc_data_sz = 0;
  470. int ret = 0;
  471. memset(&creq, 0, sizeof(creq));
  472. /* Start the command on the podev->active_command */
  473. qcedev_areq = podev->active_command;
  474. qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
  475. switch (qcedev_areq->offload_cipher_op_req.alg) {
  476. case QCEDEV_ALG_AES:
  477. creq.alg = CIPHER_ALG_AES;
  478. break;
  479. default:
  480. return -EINVAL;
  481. }
  482. switch (qcedev_areq->offload_cipher_op_req.mode) {
  483. case QCEDEV_AES_MODE_CBC:
  484. creq.mode = QCE_MODE_CBC;
  485. break;
  486. case QCEDEV_AES_MODE_CTR:
  487. creq.mode = QCE_MODE_CTR;
  488. break;
  489. default:
  490. return -EINVAL;
  491. }
  492. if (qcedev_areq->offload_cipher_op_req.is_copy_op ||
  493. qcedev_areq->offload_cipher_op_req.encrypt) {
  494. creq.dir = QCE_ENCRYPT;
  495. } else {
  496. switch(qcedev_areq->offload_cipher_op_req.op) {
  497. case QCEDEV_OFFLOAD_HLOS_HLOS:
  498. case QCEDEV_OFFLOAD_HLOS_HLOS_1:
  499. case QCEDEV_OFFLOAD_HLOS_CPB:
  500. case QCEDEV_OFFLOAD_HLOS_CPB_1:
  501. creq.dir = QCE_DECRYPT;
  502. break;
  503. case QCEDEV_OFFLOAD_CPB_HLOS:
  504. creq.dir = QCE_ENCRYPT;
  505. break;
  506. default:
  507. return -EINVAL;
  508. }
  509. }
  510. creq.iv = &qcedev_areq->offload_cipher_op_req.iv[0];
  511. creq.ivsize = qcedev_areq->offload_cipher_op_req.ivlen;
  512. creq.iv_ctr_size = qcedev_areq->offload_cipher_op_req.iv_ctr_size;
  513. creq.encklen = qcedev_areq->offload_cipher_op_req.encklen;
  514. /* OFFLOAD use cases use PIPE keys so no need to set keys */
  515. creq.flags = QCEDEV_CTX_USE_PIPE_KEY;
  516. creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
  517. creq.offload_op = (int)qcedev_areq->offload_cipher_op_req.op;
  518. if (qcedev_areq->offload_cipher_op_req.is_copy_op)
  519. creq.is_copy_op = true;
  520. creq.cryptlen = qcedev_areq->offload_cipher_op_req.data_len;
  521. creq.qce_cb = qcedev_offload_cipher_req_cb;
  522. creq.areq = (void *)&qcedev_areq->cipher_req;
  523. patt_sz = qcedev_areq->offload_cipher_op_req.pattern_info.patt_sz;
  524. proc_data_sz =
  525. qcedev_areq->offload_cipher_op_req.pattern_info.proc_data_sz;
  526. creq.is_pattern_valid =
  527. qcedev_areq->offload_cipher_op_req.is_pattern_valid;
  528. if (creq.is_pattern_valid) {
  529. creq.pattern_info = 0x1;
  530. if (patt_sz)
  531. creq.pattern_info |= (patt_sz - 1) << 4;
  532. if (proc_data_sz)
  533. creq.pattern_info |= (proc_data_sz - 1) << 8;
  534. creq.pattern_info |=
  535. qcedev_areq->offload_cipher_op_req.pattern_info.patt_offset << 12;
  536. }
  537. creq.block_offset = qcedev_areq->offload_cipher_op_req.block_offset;
  538. ret = qce_ablk_cipher_req(podev->qce, &creq);
  539. *current_req_info = creq.current_req_info;
  540. qcedev_areq->err = ret ? -ENXIO : 0;
  541. return ret;
  542. }
  543. static int start_sha_req(struct qcedev_control *podev,
  544. int *current_req_info)
  545. {
  546. struct qcedev_async_req *qcedev_areq;
  547. struct qce_sha_req sreq;
  548. int ret = 0;
  549. struct qcedev_handle *handle;
  550. /* start the command on the podev->active_command */
  551. qcedev_areq = podev->active_command;
  552. handle = qcedev_areq->handle;
  553. switch (qcedev_areq->sha_op_req.alg) {
  554. case QCEDEV_ALG_SHA1:
  555. sreq.alg = QCE_HASH_SHA1;
  556. break;
  557. case QCEDEV_ALG_SHA256:
  558. sreq.alg = QCE_HASH_SHA256;
  559. break;
  560. case QCEDEV_ALG_SHA1_HMAC:
  561. if (podev->ce_support.sha_hmac) {
  562. sreq.alg = QCE_HASH_SHA1_HMAC;
  563. sreq.authkey = &handle->sha_ctxt.authkey[0];
  564. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  565. } else {
  566. sreq.alg = QCE_HASH_SHA1;
  567. sreq.authkey = NULL;
  568. }
  569. break;
  570. case QCEDEV_ALG_SHA256_HMAC:
  571. if (podev->ce_support.sha_hmac) {
  572. sreq.alg = QCE_HASH_SHA256_HMAC;
  573. sreq.authkey = &handle->sha_ctxt.authkey[0];
  574. sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
  575. } else {
  576. sreq.alg = QCE_HASH_SHA256;
  577. sreq.authkey = NULL;
  578. }
  579. break;
  580. case QCEDEV_ALG_AES_CMAC:
  581. sreq.alg = QCE_HASH_AES_CMAC;
  582. sreq.authkey = &handle->sha_ctxt.authkey[0];
  583. sreq.authklen = qcedev_areq->sha_op_req.authklen;
  584. break;
  585. default:
  586. pr_err("Algorithm %d not supported, exiting\n",
  587. qcedev_areq->sha_op_req.alg);
  588. return -EINVAL;
  589. }
  590. qcedev_areq->sha_req.cookie = handle;
  591. sreq.qce_cb = qcedev_sha_req_cb;
  592. if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
  593. sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
  594. sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
  595. sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
  596. sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
  597. sreq.digest = &handle->sha_ctxt.digest[0];
  598. sreq.first_blk = handle->sha_ctxt.first_blk;
  599. sreq.last_blk = handle->sha_ctxt.last_blk;
  600. }
  601. sreq.size = qcedev_areq->sha_req.sreq.nbytes;
  602. sreq.src = qcedev_areq->sha_req.sreq.src;
  603. sreq.areq = (void *)&qcedev_areq->sha_req;
  604. sreq.flags = 0;
  605. ret = qce_process_sha_req(podev->qce, &sreq);
  606. *current_req_info = sreq.current_req_info;
  607. qcedev_areq->err = ret ? -ENXIO : 0;
  608. return ret;
  609. };
  610. static void qcedev_check_crypto_status(
  611. struct qcedev_async_req *qcedev_areq, void *handle)
  612. {
  613. struct qce_error error = {0};
  614. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  615. qce_get_crypto_status(handle, &error);
  616. if (error.timer_error) {
  617. qcedev_areq->offload_cipher_op_req.err =
  618. QCEDEV_OFFLOAD_KEY_TIMER_EXPIRED_ERROR;
  619. } else if (error.key_paused) {
  620. qcedev_areq->offload_cipher_op_req.err =
  621. QCEDEV_OFFLOAD_KEY_PAUSE_ERROR;
  622. } else if (error.generic_error) {
  623. qcedev_areq->offload_cipher_op_req.err =
  624. QCEDEV_OFFLOAD_GENERIC_ERROR;
  625. }
  626. return;
  627. }
  628. #define MAX_RETRIES 333
  629. static int submit_req(struct qcedev_async_req *qcedev_areq,
  630. struct qcedev_handle *handle)
  631. {
  632. struct qcedev_control *podev;
  633. unsigned long flags = 0;
  634. int ret = 0;
  635. struct qcedev_stat *pstat;
  636. int current_req_info = 0;
  637. int wait = MAX_CRYPTO_WAIT_TIME;
  638. struct qcedev_async_req *new_req = NULL;
  639. int retries = 0;
  640. int req_wait = MAX_REQUEST_TIME;
  641. unsigned int crypto_wait = 0;
  642. qcedev_areq->err = 0;
  643. podev = handle->cntl;
  644. init_waitqueue_head(&qcedev_areq->wait_q);
  645. spin_lock_irqsave(&podev->lock, flags);
  646. /*
  647. * Service only one crypto request at a time.
  648. * Any other new requests are queued in ready_commands and woken up
  649. * only when the active command has finished successfully or when the
  650. * request times out or when the command failed when setting up.
  651. */
  652. do {
  653. if (podev->active_command == NULL) {
  654. podev->active_command = qcedev_areq;
  655. qcedev_areq->state = QCEDEV_REQ_SUBMITTED;
  656. switch (qcedev_areq->op_type) {
  657. case QCEDEV_CRYPTO_OPER_CIPHER:
  658. ret = start_cipher_req(podev,
  659. &current_req_info);
  660. crypto_wait = MAX_CRYPTO_WAIT_TIME;
  661. break;
  662. case QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER:
  663. ret = start_offload_cipher_req(podev,
  664. &current_req_info);
  665. crypto_wait = MAX_OFFLOAD_CRYPTO_WAIT_TIME;
  666. break;
  667. default:
  668. crypto_wait = MAX_CRYPTO_WAIT_TIME;
  669. ret = start_sha_req(podev,
  670. &current_req_info);
  671. break;
  672. }
  673. } else {
  674. list_add_tail(&qcedev_areq->list,
  675. &podev->ready_commands);
  676. qcedev_areq->state = QCEDEV_REQ_WAITING;
  677. req_wait = wait_event_interruptible_lock_irq_timeout(
  678. qcedev_areq->wait_q,
  679. (qcedev_areq->state == QCEDEV_REQ_CURRENT),
  680. podev->lock,
  681. msecs_to_jiffies(MAX_REQUEST_TIME));
  682. if ((req_wait == 0) || (req_wait == -ERESTARTSYS)) {
  683. pr_err("%s: request timed out, req_wait = %d\n",
  684. __func__, req_wait);
  685. list_del(&qcedev_areq->list);
  686. podev->active_command = NULL;
  687. spin_unlock_irqrestore(&podev->lock, flags);
  688. return qcedev_areq->err;
  689. }
  690. }
  691. } while (qcedev_areq->state != QCEDEV_REQ_SUBMITTED);
  692. if (ret != 0) {
  693. podev->active_command = NULL;
  694. /*
  695. * Look through queued requests and wake up the corresponding
  696. * thread.
  697. */
  698. if (!list_empty(&podev->ready_commands)) {
  699. new_req = container_of(podev->ready_commands.next,
  700. struct qcedev_async_req, list);
  701. list_del(&new_req->list);
  702. new_req->state = QCEDEV_REQ_CURRENT;
  703. wake_up_interruptible(&new_req->wait_q);
  704. }
  705. }
  706. spin_unlock_irqrestore(&podev->lock, flags);
  707. qcedev_areq->timed_out = false;
  708. if (ret == 0)
  709. wait = wait_for_completion_timeout(&qcedev_areq->complete,
  710. msecs_to_jiffies(crypto_wait));
  711. if (!wait) {
  712. /*
  713. * This means wait timed out, and the callback routine was not
  714. * exercised. The callback sequence does some housekeeping which
  715. * would be missed here, hence having a call to qce here to do
  716. * that.
  717. */
  718. pr_err("%s: wait timed out, req info = %d\n", __func__,
  719. current_req_info);
  720. spin_lock_irqsave(&podev->lock, flags);
  721. qcedev_areq->timed_out = true;
  722. spin_unlock_irqrestore(&podev->lock, flags);
  723. qcedev_check_crypto_status(qcedev_areq, podev->qce);
  724. if (qcedev_areq->offload_cipher_op_req.err ==
  725. QCEDEV_OFFLOAD_NO_ERROR) {
  726. pr_err("%s: no error, wait for request to be done", __func__);
  727. while (qcedev_areq->state != QCEDEV_REQ_DONE &&
  728. retries < MAX_RETRIES) {
  729. usleep_range(3000, 5000);
  730. retries++;
  731. pr_err("%s: waiting for req state to be done, retries = %d",
  732. __func__, retries);
  733. }
  734. return 0;
  735. }
  736. ret = qce_manage_timeout(podev->qce, current_req_info);
  737. if (ret)
  738. pr_err("%s: error during manage timeout", __func__);
  739. req_done((unsigned long) podev);
  740. if (qcedev_areq->offload_cipher_op_req.err !=
  741. QCEDEV_OFFLOAD_NO_ERROR)
  742. return 0;
  743. }
  744. if (ret)
  745. qcedev_areq->err = -EIO;
  746. pstat = &_qcedev_stat;
  747. if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
  748. switch (qcedev_areq->cipher_op_req.op) {
  749. case QCEDEV_OPER_DEC:
  750. if (qcedev_areq->err)
  751. pstat->qcedev_dec_fail++;
  752. else
  753. pstat->qcedev_dec_success++;
  754. break;
  755. case QCEDEV_OPER_ENC:
  756. if (qcedev_areq->err)
  757. pstat->qcedev_enc_fail++;
  758. else
  759. pstat->qcedev_enc_success++;
  760. break;
  761. default:
  762. break;
  763. }
  764. } else if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER) {
  765. //Do nothing
  766. } else {
  767. if (qcedev_areq->err)
  768. pstat->qcedev_sha_fail++;
  769. else
  770. pstat->qcedev_sha_success++;
  771. }
  772. return qcedev_areq->err;
  773. }
  774. static int qcedev_sha_init(struct qcedev_async_req *areq,
  775. struct qcedev_handle *handle)
  776. {
  777. struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
  778. memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
  779. sha_ctxt->first_blk = 1;
  780. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  781. (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
  782. memcpy(&sha_ctxt->digest[0],
  783. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  784. sha_ctxt->diglen = SHA1_DIGEST_SIZE;
  785. } else {
  786. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
  787. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
  788. memcpy(&sha_ctxt->digest[0],
  789. &_std_init_vector_sha256_uint8[0],
  790. SHA256_DIGEST_SIZE);
  791. sha_ctxt->diglen = SHA256_DIGEST_SIZE;
  792. }
  793. }
  794. sha_ctxt->init_done = true;
  795. return 0;
  796. }
  797. static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
  798. struct qcedev_handle *handle,
  799. struct scatterlist *sg_src)
  800. {
  801. int err = 0;
  802. int i = 0;
  803. uint32_t total;
  804. uint8_t *user_src = NULL;
  805. uint8_t *k_src = NULL;
  806. uint8_t *k_buf_src = NULL;
  807. uint32_t buf_size = 0;
  808. uint8_t *k_align_src = NULL;
  809. uint32_t sha_pad_len = 0;
  810. uint32_t trailing_buf_len = 0;
  811. uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
  812. uint32_t sha_block_size;
  813. total = qcedev_areq->sha_op_req.data_len + t_buf;
  814. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
  815. sha_block_size = SHA1_BLOCK_SIZE;
  816. else
  817. sha_block_size = SHA256_BLOCK_SIZE;
  818. if (total <= sha_block_size) {
  819. uint32_t len = qcedev_areq->sha_op_req.data_len;
  820. i = 0;
  821. k_src = &handle->sha_ctxt.trailing_buf[t_buf];
  822. /* Copy data from user src(s) */
  823. while (len > 0) {
  824. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  825. if (user_src && copy_from_user(k_src,
  826. (void __user *)user_src,
  827. qcedev_areq->sha_op_req.data[i].len))
  828. return -EFAULT;
  829. len -= qcedev_areq->sha_op_req.data[i].len;
  830. k_src += qcedev_areq->sha_op_req.data[i].len;
  831. i++;
  832. }
  833. handle->sha_ctxt.trailing_buf_len = total;
  834. return 0;
  835. }
  836. buf_size = total + CACHE_LINE_SIZE * 2;
  837. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  838. if (k_buf_src == NULL)
  839. return -ENOMEM;
  840. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  841. CACHE_LINE_SIZE);
  842. k_src = k_align_src;
  843. /* check for trailing buffer from previous updates and append it */
  844. if (t_buf > 0) {
  845. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  846. t_buf);
  847. k_src += t_buf;
  848. }
  849. /* Copy data from user src(s) */
  850. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  851. if (user_src && copy_from_user(k_src,
  852. (void __user *)user_src,
  853. qcedev_areq->sha_op_req.data[0].len)) {
  854. memset(k_buf_src, 0, buf_size);
  855. kfree(k_buf_src);
  856. return -EFAULT;
  857. }
  858. k_src += qcedev_areq->sha_op_req.data[0].len;
  859. for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
  860. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  861. if (user_src && copy_from_user(k_src,
  862. (void __user *)user_src,
  863. qcedev_areq->sha_op_req.data[i].len)) {
  864. memset(k_buf_src, 0, buf_size);
  865. kfree(k_buf_src);
  866. return -EFAULT;
  867. }
  868. k_src += qcedev_areq->sha_op_req.data[i].len;
  869. }
  870. /* get new trailing buffer */
  871. sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
  872. trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
  873. qcedev_areq->sha_req.sreq.src = sg_src;
  874. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src,
  875. total-trailing_buf_len);
  876. qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
  877. /* update sha_ctxt trailing buf content to new trailing buf */
  878. if (trailing_buf_len > 0) {
  879. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  880. memcpy(&handle->sha_ctxt.trailing_buf[0],
  881. (k_src - trailing_buf_len),
  882. trailing_buf_len);
  883. }
  884. handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
  885. err = submit_req(qcedev_areq, handle);
  886. handle->sha_ctxt.last_blk = 0;
  887. handle->sha_ctxt.first_blk = 0;
  888. memset(k_buf_src, 0, buf_size);
  889. kfree(k_buf_src);
  890. return err;
  891. }
  892. static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
  893. struct qcedev_handle *handle,
  894. struct scatterlist *sg_src)
  895. {
  896. int err = 0;
  897. int i = 0;
  898. int j = 0;
  899. int k = 0;
  900. int num_entries = 0;
  901. uint32_t total = 0;
  902. if (!handle->sha_ctxt.init_done) {
  903. pr_err("%s Init was not called\n", __func__);
  904. return -EINVAL;
  905. }
  906. if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
  907. struct qcedev_sha_op_req *saved_req;
  908. struct qcedev_sha_op_req req;
  909. struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
  910. uint32_t req_size = 0;
  911. req_size = sizeof(struct qcedev_sha_op_req);
  912. /* save the original req structure */
  913. saved_req =
  914. kmalloc(req_size, GFP_KERNEL);
  915. if (saved_req == NULL) {
  916. pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n",
  917. __func__, (uintptr_t)saved_req);
  918. return -ENOMEM;
  919. }
  920. memcpy(&req, sreq, sizeof(*sreq));
  921. memcpy(saved_req, sreq, sizeof(*sreq));
  922. i = 0;
  923. /* Address 32 KB at a time */
  924. while ((i < req.entries) && (err == 0)) {
  925. if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
  926. sreq->data[0].len = QCE_MAX_OPER_DATA;
  927. if (i > 0) {
  928. sreq->data[0].vaddr =
  929. sreq->data[i].vaddr;
  930. }
  931. sreq->data_len = QCE_MAX_OPER_DATA;
  932. sreq->entries = 1;
  933. err = qcedev_sha_update_max_xfer(qcedev_areq,
  934. handle, sg_src);
  935. sreq->data[i].len = req.data[i].len -
  936. QCE_MAX_OPER_DATA;
  937. sreq->data[i].vaddr = req.data[i].vaddr +
  938. QCE_MAX_OPER_DATA;
  939. req.data[i].vaddr = sreq->data[i].vaddr;
  940. req.data[i].len = sreq->data[i].len;
  941. } else {
  942. total = 0;
  943. for (j = i; j < req.entries; j++) {
  944. num_entries++;
  945. if ((total + sreq->data[j].len) >=
  946. QCE_MAX_OPER_DATA) {
  947. sreq->data[j].len =
  948. (QCE_MAX_OPER_DATA - total);
  949. total = QCE_MAX_OPER_DATA;
  950. break;
  951. }
  952. total += sreq->data[j].len;
  953. }
  954. sreq->data_len = total;
  955. if (i > 0)
  956. for (k = 0; k < num_entries; k++) {
  957. sreq->data[k].len =
  958. sreq->data[i+k].len;
  959. sreq->data[k].vaddr =
  960. sreq->data[i+k].vaddr;
  961. }
  962. sreq->entries = num_entries;
  963. i = j;
  964. err = qcedev_sha_update_max_xfer(qcedev_areq,
  965. handle, sg_src);
  966. num_entries = 0;
  967. sreq->data[i].vaddr = req.data[i].vaddr +
  968. sreq->data[i].len;
  969. sreq->data[i].len = req.data[i].len -
  970. sreq->data[i].len;
  971. req.data[i].vaddr = sreq->data[i].vaddr;
  972. req.data[i].len = sreq->data[i].len;
  973. if (sreq->data[i].len == 0)
  974. i++;
  975. }
  976. } /* end of while ((i < req.entries) && (err == 0)) */
  977. /* Restore the original req structure */
  978. for (i = 0; i < saved_req->entries; i++) {
  979. sreq->data[i].len = saved_req->data[i].len;
  980. sreq->data[i].vaddr = saved_req->data[i].vaddr;
  981. }
  982. sreq->entries = saved_req->entries;
  983. sreq->data_len = saved_req->data_len;
  984. memset(saved_req, 0, req_size);
  985. kfree(saved_req);
  986. } else
  987. err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
  988. return err;
  989. }
  990. static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
  991. struct qcedev_handle *handle)
  992. {
  993. int err = 0;
  994. struct scatterlist sg_src;
  995. uint32_t total;
  996. uint8_t *k_buf_src = NULL;
  997. uint32_t buf_size = 0;
  998. uint8_t *k_align_src = NULL;
  999. if (!handle->sha_ctxt.init_done) {
  1000. pr_err("%s Init was not called\n", __func__);
  1001. return -EINVAL;
  1002. }
  1003. handle->sha_ctxt.last_blk = 1;
  1004. total = handle->sha_ctxt.trailing_buf_len;
  1005. buf_size = total + CACHE_LINE_SIZE * 2;
  1006. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1007. if (k_buf_src == NULL)
  1008. return -ENOMEM;
  1009. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1010. CACHE_LINE_SIZE);
  1011. memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
  1012. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1013. sg_init_one(qcedev_areq->sha_req.sreq.src, k_align_src, total);
  1014. qcedev_areq->sha_req.sreq.nbytes = total;
  1015. err = submit_req(qcedev_areq, handle);
  1016. handle->sha_ctxt.first_blk = 0;
  1017. handle->sha_ctxt.last_blk = 0;
  1018. handle->sha_ctxt.auth_data[0] = 0;
  1019. handle->sha_ctxt.auth_data[1] = 0;
  1020. handle->sha_ctxt.trailing_buf_len = 0;
  1021. handle->sha_ctxt.init_done = false;
  1022. memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
  1023. memset(k_buf_src, 0, buf_size);
  1024. kfree(k_buf_src);
  1025. qcedev_areq->sha_req.sreq.src = NULL;
  1026. return err;
  1027. }
  1028. static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
  1029. struct qcedev_handle *handle,
  1030. struct scatterlist *sg_src)
  1031. {
  1032. int err = 0;
  1033. int i = 0;
  1034. uint32_t total;
  1035. uint8_t *user_src = NULL;
  1036. uint8_t *k_src = NULL;
  1037. uint8_t *k_buf_src = NULL;
  1038. uint32_t buf_size = 0;
  1039. total = qcedev_areq->sha_op_req.data_len;
  1040. if ((qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_128) &&
  1041. (qcedev_areq->sha_op_req.authklen != QCEDEV_AES_KEY_256)) {
  1042. pr_err("%s: unsupported key length\n", __func__);
  1043. return -EINVAL;
  1044. }
  1045. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1046. (void __user *)qcedev_areq->sha_op_req.authkey,
  1047. qcedev_areq->sha_op_req.authklen))
  1048. return -EFAULT;
  1049. if (total > U32_MAX - CACHE_LINE_SIZE * 2)
  1050. return -EINVAL;
  1051. buf_size = total + CACHE_LINE_SIZE * 2;
  1052. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1053. if (k_buf_src == NULL)
  1054. return -ENOMEM;
  1055. k_src = k_buf_src;
  1056. /* Copy data from user src(s) */
  1057. user_src = qcedev_areq->sha_op_req.data[0].vaddr;
  1058. for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
  1059. user_src = qcedev_areq->sha_op_req.data[i].vaddr;
  1060. if (user_src && copy_from_user(k_src, (void __user *)user_src,
  1061. qcedev_areq->sha_op_req.data[i].len)) {
  1062. memset(k_buf_src, 0, buf_size);
  1063. kfree(k_buf_src);
  1064. return -EFAULT;
  1065. }
  1066. k_src += qcedev_areq->sha_op_req.data[i].len;
  1067. }
  1068. qcedev_areq->sha_req.sreq.src = sg_src;
  1069. sg_init_one(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
  1070. qcedev_areq->sha_req.sreq.nbytes = total;
  1071. handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
  1072. err = submit_req(qcedev_areq, handle);
  1073. memset(k_buf_src, 0, buf_size);
  1074. kfree(k_buf_src);
  1075. return err;
  1076. }
  1077. static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
  1078. struct qcedev_handle *handle,
  1079. struct scatterlist *sg_src)
  1080. {
  1081. int err = 0;
  1082. if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
  1083. qcedev_sha_init(areq, handle);
  1084. if (copy_from_user(&handle->sha_ctxt.authkey[0],
  1085. (void __user *)areq->sha_op_req.authkey,
  1086. areq->sha_op_req.authklen))
  1087. return -EFAULT;
  1088. } else {
  1089. struct qcedev_async_req authkey_areq;
  1090. uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
  1091. init_completion(&authkey_areq.complete);
  1092. authkey_areq.sha_op_req.entries = 1;
  1093. authkey_areq.sha_op_req.data[0].vaddr =
  1094. areq->sha_op_req.authkey;
  1095. authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
  1096. authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
  1097. authkey_areq.sha_op_req.diglen = 0;
  1098. authkey_areq.handle = handle;
  1099. memset(&authkey_areq.sha_op_req.digest[0], 0,
  1100. QCEDEV_MAX_SHA_DIGEST);
  1101. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1102. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
  1103. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
  1104. authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
  1105. authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
  1106. qcedev_sha_init(&authkey_areq, handle);
  1107. err = qcedev_sha_update(&authkey_areq, handle, sg_src);
  1108. if (!err)
  1109. err = qcedev_sha_final(&authkey_areq, handle);
  1110. else
  1111. return err;
  1112. memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
  1113. handle->sha_ctxt.diglen);
  1114. qcedev_sha_init(areq, handle);
  1115. memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
  1116. handle->sha_ctxt.diglen);
  1117. }
  1118. return err;
  1119. }
  1120. static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
  1121. struct qcedev_handle *handle)
  1122. {
  1123. int err = 0;
  1124. struct scatterlist sg_src;
  1125. uint8_t *k_src = NULL;
  1126. uint32_t sha_block_size = 0;
  1127. uint32_t sha_digest_size = 0;
  1128. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1129. sha_digest_size = SHA1_DIGEST_SIZE;
  1130. sha_block_size = SHA1_BLOCK_SIZE;
  1131. } else {
  1132. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1133. sha_digest_size = SHA256_DIGEST_SIZE;
  1134. sha_block_size = SHA256_BLOCK_SIZE;
  1135. }
  1136. }
  1137. k_src = kmalloc(sha_block_size, GFP_KERNEL);
  1138. if (k_src == NULL)
  1139. return -ENOMEM;
  1140. /* check for trailing buffer from previous updates and append it */
  1141. memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
  1142. handle->sha_ctxt.trailing_buf_len);
  1143. qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
  1144. sg_init_one(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
  1145. qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
  1146. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1147. memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
  1148. sha_digest_size);
  1149. handle->sha_ctxt.trailing_buf_len = sha_digest_size;
  1150. handle->sha_ctxt.first_blk = 1;
  1151. handle->sha_ctxt.last_blk = 0;
  1152. handle->sha_ctxt.auth_data[0] = 0;
  1153. handle->sha_ctxt.auth_data[1] = 0;
  1154. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
  1155. memcpy(&handle->sha_ctxt.digest[0],
  1156. &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
  1157. handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
  1158. }
  1159. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
  1160. memcpy(&handle->sha_ctxt.digest[0],
  1161. &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
  1162. handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
  1163. }
  1164. err = submit_req(qcedev_areq, handle);
  1165. handle->sha_ctxt.last_blk = 0;
  1166. handle->sha_ctxt.first_blk = 0;
  1167. memset(k_src, 0, sha_block_size);
  1168. kfree(k_src);
  1169. qcedev_areq->sha_req.sreq.src = NULL;
  1170. return err;
  1171. }
  1172. static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
  1173. struct qcedev_handle *handle, bool ikey)
  1174. {
  1175. int i;
  1176. uint32_t constant;
  1177. uint32_t sha_block_size;
  1178. if (ikey)
  1179. constant = 0x36;
  1180. else
  1181. constant = 0x5c;
  1182. if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
  1183. sha_block_size = SHA1_BLOCK_SIZE;
  1184. else
  1185. sha_block_size = SHA256_BLOCK_SIZE;
  1186. memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
  1187. for (i = 0; i < sha_block_size; i++)
  1188. handle->sha_ctxt.trailing_buf[i] =
  1189. (handle->sha_ctxt.authkey[i] ^ constant);
  1190. handle->sha_ctxt.trailing_buf_len = sha_block_size;
  1191. return 0;
  1192. }
  1193. static int qcedev_hmac_init(struct qcedev_async_req *areq,
  1194. struct qcedev_handle *handle,
  1195. struct scatterlist *sg_src)
  1196. {
  1197. int err;
  1198. struct qcedev_control *podev = handle->cntl;
  1199. err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
  1200. if (err)
  1201. return err;
  1202. if (!podev->ce_support.sha_hmac)
  1203. qcedev_hmac_update_iokey(areq, handle, true);
  1204. return 0;
  1205. }
  1206. static int qcedev_hmac_final(struct qcedev_async_req *areq,
  1207. struct qcedev_handle *handle)
  1208. {
  1209. int err;
  1210. struct qcedev_control *podev = handle->cntl;
  1211. err = qcedev_sha_final(areq, handle);
  1212. if (podev->ce_support.sha_hmac)
  1213. return err;
  1214. qcedev_hmac_update_iokey(areq, handle, false);
  1215. err = qcedev_hmac_get_ohash(areq, handle);
  1216. if (err)
  1217. return err;
  1218. err = qcedev_sha_final(areq, handle);
  1219. return err;
  1220. }
  1221. static int qcedev_hash_init(struct qcedev_async_req *areq,
  1222. struct qcedev_handle *handle,
  1223. struct scatterlist *sg_src)
  1224. {
  1225. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1226. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1227. return qcedev_sha_init(areq, handle);
  1228. else
  1229. return qcedev_hmac_init(areq, handle, sg_src);
  1230. }
  1231. static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
  1232. struct qcedev_handle *handle,
  1233. struct scatterlist *sg_src)
  1234. {
  1235. return qcedev_sha_update(qcedev_areq, handle, sg_src);
  1236. }
  1237. static int qcedev_hash_final(struct qcedev_async_req *areq,
  1238. struct qcedev_handle *handle)
  1239. {
  1240. if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
  1241. (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
  1242. return qcedev_sha_final(areq, handle);
  1243. else
  1244. return qcedev_hmac_final(areq, handle);
  1245. }
  1246. static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
  1247. int *di, struct qcedev_handle *handle,
  1248. uint8_t *k_align_src)
  1249. {
  1250. int err = 0;
  1251. int i = 0;
  1252. int dst_i = *di;
  1253. struct scatterlist sg_src;
  1254. uint32_t byteoffset = 0;
  1255. uint8_t *user_src = NULL;
  1256. uint8_t *k_align_dst = k_align_src;
  1257. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1258. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1259. byteoffset = areq->cipher_op_req.byteoffset;
  1260. user_src = areq->cipher_op_req.vbuf.src[0].vaddr;
  1261. if (user_src && copy_from_user((k_align_src + byteoffset),
  1262. (void __user *)user_src,
  1263. areq->cipher_op_req.vbuf.src[0].len))
  1264. return -EFAULT;
  1265. k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
  1266. for (i = 1; i < areq->cipher_op_req.entries; i++) {
  1267. user_src = areq->cipher_op_req.vbuf.src[i].vaddr;
  1268. if (user_src && copy_from_user(k_align_src,
  1269. (void __user *)user_src,
  1270. areq->cipher_op_req.vbuf.src[i].len)) {
  1271. return -EFAULT;
  1272. }
  1273. k_align_src += areq->cipher_op_req.vbuf.src[i].len;
  1274. }
  1275. /* restore src beginning */
  1276. k_align_src = k_align_dst;
  1277. areq->cipher_op_req.data_len += byteoffset;
  1278. areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
  1279. areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
  1280. /* In place encryption/decryption */
  1281. sg_init_one(areq->cipher_req.creq.src,
  1282. k_align_dst,
  1283. areq->cipher_op_req.data_len);
  1284. areq->cipher_req.creq.cryptlen = areq->cipher_op_req.data_len;
  1285. areq->cipher_req.creq.iv = areq->cipher_op_req.iv;
  1286. areq->cipher_op_req.entries = 1;
  1287. err = submit_req(areq, handle);
  1288. /* copy data to destination buffer*/
  1289. creq->data_len -= byteoffset;
  1290. while (creq->data_len > 0) {
  1291. if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
  1292. if (err == 0 && copy_to_user(
  1293. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1294. (k_align_dst + byteoffset),
  1295. creq->vbuf.dst[dst_i].len)) {
  1296. err = -EFAULT;
  1297. goto exit;
  1298. }
  1299. k_align_dst += creq->vbuf.dst[dst_i].len;
  1300. creq->data_len -= creq->vbuf.dst[dst_i].len;
  1301. dst_i++;
  1302. } else {
  1303. if (err == 0 && copy_to_user(
  1304. (void __user *)creq->vbuf.dst[dst_i].vaddr,
  1305. (k_align_dst + byteoffset),
  1306. creq->data_len)) {
  1307. err = -EFAULT;
  1308. goto exit;
  1309. }
  1310. k_align_dst += creq->data_len;
  1311. creq->vbuf.dst[dst_i].len -= creq->data_len;
  1312. creq->vbuf.dst[dst_i].vaddr += creq->data_len;
  1313. creq->data_len = 0;
  1314. }
  1315. }
  1316. *di = dst_i;
  1317. exit:
  1318. areq->cipher_req.creq.src = NULL;
  1319. areq->cipher_req.creq.dst = NULL;
  1320. return err;
  1321. };
  1322. static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
  1323. struct qcedev_handle *handle)
  1324. {
  1325. int err = 0;
  1326. int di = 0;
  1327. int i = 0;
  1328. int j = 0;
  1329. int k = 0;
  1330. uint32_t byteoffset = 0;
  1331. int num_entries = 0;
  1332. uint32_t total = 0;
  1333. uint32_t len;
  1334. uint8_t *k_buf_src = NULL;
  1335. uint32_t buf_size = 0;
  1336. uint8_t *k_align_src = NULL;
  1337. uint32_t max_data_xfer;
  1338. struct qcedev_cipher_op_req *saved_req;
  1339. uint32_t req_size = 0;
  1340. struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
  1341. total = 0;
  1342. if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1343. byteoffset = areq->cipher_op_req.byteoffset;
  1344. buf_size = QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2;
  1345. k_buf_src = kmalloc(buf_size, GFP_KERNEL);
  1346. if (k_buf_src == NULL)
  1347. return -ENOMEM;
  1348. k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
  1349. CACHE_LINE_SIZE);
  1350. max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
  1351. req_size = sizeof(struct qcedev_cipher_op_req);
  1352. saved_req = kmemdup(creq, req_size, GFP_KERNEL);
  1353. if (saved_req == NULL) {
  1354. memset(k_buf_src, 0, buf_size);
  1355. kfree(k_buf_src);
  1356. return -ENOMEM;
  1357. }
  1358. if (areq->cipher_op_req.data_len > max_data_xfer) {
  1359. struct qcedev_cipher_op_req req;
  1360. /* save the original req structure */
  1361. memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
  1362. i = 0;
  1363. /* Address 32 KB at a time */
  1364. while ((i < req.entries) && (err == 0)) {
  1365. if (creq->vbuf.src[i].len > max_data_xfer) {
  1366. creq->vbuf.src[0].len = max_data_xfer;
  1367. if (i > 0) {
  1368. creq->vbuf.src[0].vaddr =
  1369. creq->vbuf.src[i].vaddr;
  1370. }
  1371. creq->data_len = max_data_xfer;
  1372. creq->entries = 1;
  1373. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1374. &di, handle, k_align_src);
  1375. if (err < 0) {
  1376. memset(saved_req, 0, req_size);
  1377. memset(k_buf_src, 0, buf_size);
  1378. kfree(k_buf_src);
  1379. kfree(saved_req);
  1380. return err;
  1381. }
  1382. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1383. max_data_xfer;
  1384. creq->vbuf.src[i].vaddr =
  1385. req.vbuf.src[i].vaddr +
  1386. max_data_xfer;
  1387. req.vbuf.src[i].vaddr =
  1388. creq->vbuf.src[i].vaddr;
  1389. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1390. } else {
  1391. total = areq->cipher_op_req.byteoffset;
  1392. for (j = i; j < req.entries; j++) {
  1393. num_entries++;
  1394. if ((total + creq->vbuf.src[j].len)
  1395. >= max_data_xfer) {
  1396. creq->vbuf.src[j].len =
  1397. max_data_xfer - total;
  1398. total = max_data_xfer;
  1399. break;
  1400. }
  1401. total += creq->vbuf.src[j].len;
  1402. }
  1403. creq->data_len = total;
  1404. if (i > 0)
  1405. for (k = 0; k < num_entries; k++) {
  1406. creq->vbuf.src[k].len =
  1407. creq->vbuf.src[i+k].len;
  1408. creq->vbuf.src[k].vaddr =
  1409. creq->vbuf.src[i+k].vaddr;
  1410. }
  1411. creq->entries = num_entries;
  1412. i = j;
  1413. err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
  1414. &di, handle, k_align_src);
  1415. if (err < 0) {
  1416. memset(saved_req, 0, req_size);
  1417. memset(k_buf_src, 0, buf_size);
  1418. kfree(k_buf_src);
  1419. kfree(saved_req);
  1420. return err;
  1421. }
  1422. num_entries = 0;
  1423. areq->cipher_op_req.byteoffset = 0;
  1424. creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
  1425. + creq->vbuf.src[i].len;
  1426. creq->vbuf.src[i].len = req.vbuf.src[i].len -
  1427. creq->vbuf.src[i].len;
  1428. req.vbuf.src[i].vaddr =
  1429. creq->vbuf.src[i].vaddr;
  1430. req.vbuf.src[i].len = creq->vbuf.src[i].len;
  1431. if (creq->vbuf.src[i].len == 0)
  1432. i++;
  1433. }
  1434. areq->cipher_op_req.byteoffset = 0;
  1435. max_data_xfer = QCE_MAX_OPER_DATA;
  1436. byteoffset = 0;
  1437. } /* end of while ((i < req.entries) && (err == 0)) */
  1438. } else
  1439. err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
  1440. k_align_src);
  1441. /* Restore the original req structure */
  1442. for (i = 0; i < saved_req->entries; i++) {
  1443. creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
  1444. creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
  1445. }
  1446. for (len = 0, i = 0; len < saved_req->data_len; i++) {
  1447. creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
  1448. creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
  1449. len += saved_req->vbuf.dst[i].len;
  1450. }
  1451. creq->entries = saved_req->entries;
  1452. creq->data_len = saved_req->data_len;
  1453. creq->byteoffset = saved_req->byteoffset;
  1454. memset(saved_req, 0, req_size);
  1455. memset(k_buf_src, 0, buf_size);
  1456. kfree(saved_req);
  1457. kfree(k_buf_src);
  1458. return err;
  1459. }
  1460. static int qcedev_smmu_ablk_offload_cipher(struct qcedev_async_req *areq,
  1461. struct qcedev_handle *handle)
  1462. {
  1463. int i = 0;
  1464. int err = 0;
  1465. size_t byteoffset = 0;
  1466. size_t transfer_data_len = 0;
  1467. size_t pending_data_len = 0;
  1468. size_t max_data_xfer = MAX_CEHW_REQ_TRANSFER_SIZE - byteoffset;
  1469. uint8_t *user_src = NULL;
  1470. uint8_t *user_dst = NULL;
  1471. struct scatterlist sg_src;
  1472. struct scatterlist sg_dst;
  1473. if (areq->offload_cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
  1474. byteoffset = areq->offload_cipher_op_req.byteoffset;
  1475. /*
  1476. * areq has two components:
  1477. * a) Request that comes from userspace i.e. offload_cipher_op_req
  1478. * b) Request that QCE understands - skcipher i.e. cipher_req.creq
  1479. * skcipher has sglist pointers src and dest that would carry
  1480. * data to/from CE.
  1481. */
  1482. areq->cipher_req.creq.src = &sg_src;
  1483. areq->cipher_req.creq.dst = &sg_dst;
  1484. sg_init_table(&sg_src, 1);
  1485. sg_init_table(&sg_dst, 1);
  1486. for (i = 0; i < areq->offload_cipher_op_req.entries; i++) {
  1487. transfer_data_len = 0;
  1488. pending_data_len = areq->offload_cipher_op_req.vbuf.src[i].len;
  1489. user_src = areq->offload_cipher_op_req.vbuf.src[i].vaddr;
  1490. user_src += byteoffset;
  1491. user_dst = areq->offload_cipher_op_req.vbuf.dst[i].vaddr;
  1492. user_dst += byteoffset;
  1493. areq->cipher_req.creq.iv = areq->offload_cipher_op_req.iv;
  1494. while (pending_data_len) {
  1495. transfer_data_len = min(max_data_xfer,
  1496. pending_data_len);
  1497. sg_src.dma_address = (dma_addr_t)user_src;
  1498. sg_dst.dma_address = (dma_addr_t)user_dst;
  1499. areq->cipher_req.creq.cryptlen = transfer_data_len;
  1500. sg_src.length = transfer_data_len;
  1501. sg_dst.length = transfer_data_len;
  1502. err = submit_req(areq, handle);
  1503. if (err) {
  1504. pr_err("%s: Error processing req, err = %d\n",
  1505. __func__, err);
  1506. goto exit;
  1507. }
  1508. /* update data len to be processed */
  1509. pending_data_len -= transfer_data_len;
  1510. user_src += transfer_data_len;
  1511. user_dst += transfer_data_len;
  1512. }
  1513. }
  1514. exit:
  1515. areq->cipher_req.creq.src = NULL;
  1516. areq->cipher_req.creq.dst = NULL;
  1517. return err;
  1518. }
  1519. static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
  1520. struct qcedev_control *podev)
  1521. {
  1522. /* if intending to use HW key make sure key fields are set
  1523. * correctly and HW key is indeed supported in target
  1524. */
  1525. if (req->encklen == 0) {
  1526. int i;
  1527. for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
  1528. if (req->enckey[i]) {
  1529. pr_err("%s: Invalid key: non-zero key input\n",
  1530. __func__);
  1531. goto error;
  1532. }
  1533. }
  1534. if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
  1535. (req->op != QCEDEV_OPER_DEC_NO_KEY))
  1536. if (!podev->platform_support.hw_key_support) {
  1537. pr_err("%s: Invalid op %d\n", __func__,
  1538. (uint32_t)req->op);
  1539. goto error;
  1540. }
  1541. } else {
  1542. if (req->encklen == QCEDEV_AES_KEY_192) {
  1543. if (!podev->ce_support.aes_key_192) {
  1544. pr_err("%s: AES-192 not supported\n", __func__);
  1545. goto error;
  1546. }
  1547. } else {
  1548. /* if not using HW key make sure key
  1549. * length is valid
  1550. */
  1551. if (req->mode == QCEDEV_AES_MODE_XTS) {
  1552. if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
  1553. (req->encklen != QCEDEV_AES_KEY_256*2)) {
  1554. pr_err("%s: unsupported key size: %d\n",
  1555. __func__, req->encklen);
  1556. goto error;
  1557. }
  1558. } else {
  1559. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1560. (req->encklen != QCEDEV_AES_KEY_256)) {
  1561. pr_err("%s: unsupported key size %d\n",
  1562. __func__, req->encklen);
  1563. goto error;
  1564. }
  1565. }
  1566. }
  1567. }
  1568. return 0;
  1569. error:
  1570. return -EINVAL;
  1571. }
  1572. static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
  1573. struct qcedev_control *podev)
  1574. {
  1575. uint32_t total = 0;
  1576. uint32_t i;
  1577. if (req->use_pmem) {
  1578. pr_err("%s: Use of PMEM is not supported\n", __func__);
  1579. goto error;
  1580. }
  1581. if ((req->entries == 0) || (req->data_len == 0) ||
  1582. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1583. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1584. goto error;
  1585. }
  1586. if ((req->alg >= QCEDEV_ALG_LAST) ||
  1587. (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
  1588. pr_err("%s: Invalid algorithm %d\n", __func__,
  1589. (uint32_t)req->alg);
  1590. goto error;
  1591. }
  1592. if ((req->mode == QCEDEV_AES_MODE_XTS) &&
  1593. (!podev->ce_support.aes_xts)) {
  1594. pr_err("%s: XTS algorithm is not supported\n", __func__);
  1595. goto error;
  1596. }
  1597. if (req->alg == QCEDEV_ALG_AES) {
  1598. if (qcedev_check_cipher_key(req, podev))
  1599. goto error;
  1600. }
  1601. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1602. if (req->byteoffset) {
  1603. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1604. pr_err("%s: Operation on byte offset not supported\n",
  1605. __func__);
  1606. goto error;
  1607. }
  1608. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1609. pr_err("%s: Invalid byte offset\n", __func__);
  1610. goto error;
  1611. }
  1612. total = req->byteoffset;
  1613. for (i = 0; i < req->entries; i++) {
  1614. if (total > U32_MAX - req->vbuf.src[i].len) {
  1615. pr_err("%s:Integer overflow on total src len\n",
  1616. __func__);
  1617. goto error;
  1618. }
  1619. total += req->vbuf.src[i].len;
  1620. }
  1621. }
  1622. if (req->data_len < req->byteoffset) {
  1623. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1624. __func__, req->data_len, req->byteoffset);
  1625. goto error;
  1626. }
  1627. /* Ensure IV size */
  1628. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1629. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1630. goto error;
  1631. }
  1632. /* Ensure Key size */
  1633. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1634. pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
  1635. goto error;
  1636. }
  1637. /* Ensure zer ivlen for ECB mode */
  1638. if (req->ivlen > 0) {
  1639. if ((req->mode == QCEDEV_AES_MODE_ECB) ||
  1640. (req->mode == QCEDEV_DES_MODE_ECB)) {
  1641. pr_err("%s: Expecting a zero length IV\n", __func__);
  1642. goto error;
  1643. }
  1644. } else {
  1645. if ((req->mode != QCEDEV_AES_MODE_ECB) &&
  1646. (req->mode != QCEDEV_DES_MODE_ECB)) {
  1647. pr_err("%s: Expecting a non-zero ength IV\n", __func__);
  1648. goto error;
  1649. }
  1650. }
  1651. /* Check for sum of all dst length is equal to data_len */
  1652. for (i = 0, total = 0; i < req->entries; i++) {
  1653. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1654. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1655. __func__, i, req->vbuf.dst[i].len);
  1656. goto error;
  1657. }
  1658. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1659. pr_err("%s: Integer overflow on total req dst vbuf length\n",
  1660. __func__);
  1661. goto error;
  1662. }
  1663. total += req->vbuf.dst[i].len;
  1664. }
  1665. if (total != req->data_len) {
  1666. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1667. __func__, i, total, req->data_len);
  1668. goto error;
  1669. }
  1670. /* Check for sum of all src length is equal to data_len */
  1671. for (i = 0, total = 0; i < req->entries; i++) {
  1672. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1673. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1674. __func__, i, req->vbuf.src[i].len);
  1675. goto error;
  1676. }
  1677. if (req->vbuf.src[i].len > U32_MAX - total) {
  1678. pr_err("%s: Integer overflow on total req src vbuf length\n",
  1679. __func__);
  1680. goto error;
  1681. }
  1682. total += req->vbuf.src[i].len;
  1683. }
  1684. if (total != req->data_len) {
  1685. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1686. __func__, total, req->data_len);
  1687. goto error;
  1688. }
  1689. return 0;
  1690. error:
  1691. return -EINVAL;
  1692. }
  1693. static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
  1694. struct qcedev_control *podev)
  1695. {
  1696. uint32_t total = 0;
  1697. uint32_t i;
  1698. if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
  1699. (!podev->ce_support.cmac)) {
  1700. pr_err("%s: CMAC not supported\n", __func__);
  1701. goto sha_error;
  1702. }
  1703. if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
  1704. pr_err("%s: Invalid num entries (%d)\n",
  1705. __func__, req->entries);
  1706. goto sha_error;
  1707. }
  1708. if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
  1709. pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
  1710. goto sha_error;
  1711. }
  1712. if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
  1713. (req->alg == QCEDEV_ALG_SHA256_HMAC)) {
  1714. if (req->authkey == NULL) {
  1715. pr_err("%s: Invalid authkey pointer\n", __func__);
  1716. goto sha_error;
  1717. }
  1718. if (req->authklen <= 0) {
  1719. pr_err("%s: Invalid authkey length (%d)\n",
  1720. __func__, req->authklen);
  1721. goto sha_error;
  1722. }
  1723. }
  1724. if (req->alg == QCEDEV_ALG_AES_CMAC) {
  1725. if ((req->authklen != QCEDEV_AES_KEY_128) &&
  1726. (req->authklen != QCEDEV_AES_KEY_256)) {
  1727. pr_err("%s: unsupported key length\n", __func__);
  1728. goto sha_error;
  1729. }
  1730. }
  1731. /* Check for sum of all src length is equal to data_len */
  1732. for (i = 0, total = 0; i < req->entries; i++) {
  1733. if (req->data[i].len > U32_MAX - total) {
  1734. pr_err("%s: Integer overflow on total req buf length\n",
  1735. __func__);
  1736. goto sha_error;
  1737. }
  1738. total += req->data[i].len;
  1739. }
  1740. if (total != req->data_len) {
  1741. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1742. __func__, total, req->data_len);
  1743. goto sha_error;
  1744. }
  1745. return 0;
  1746. sha_error:
  1747. return -EINVAL;
  1748. }
  1749. static int qcedev_check_offload_cipher_key(struct qcedev_offload_cipher_op_req *req,
  1750. struct qcedev_control *podev)
  1751. {
  1752. if (req->encklen == 0)
  1753. return -EINVAL;
  1754. /* AES-192 is not a valid option for OFFLOAD use case */
  1755. if ((req->encklen != QCEDEV_AES_KEY_128) &&
  1756. (req->encklen != QCEDEV_AES_KEY_256)) {
  1757. pr_err("%s: unsupported key size %d\n",
  1758. __func__, req->encklen);
  1759. goto error;
  1760. }
  1761. return 0;
  1762. error:
  1763. return -EINVAL;
  1764. }
  1765. static int qcedev_check_offload_cipher_params(struct qcedev_offload_cipher_op_req *req,
  1766. struct qcedev_control *podev)
  1767. {
  1768. uint32_t total = 0;
  1769. int i = 0;
  1770. if ((req->entries == 0) || (req->data_len == 0) ||
  1771. (req->entries > QCEDEV_MAX_BUFFERS)) {
  1772. pr_err("%s: Invalid cipher length/entries\n", __func__);
  1773. goto error;
  1774. }
  1775. if ((req->alg != QCEDEV_ALG_AES) ||
  1776. (req->mode > QCEDEV_AES_MODE_CTR)) {
  1777. pr_err("%s: Invalid algorithm %d\n", __func__,
  1778. (uint32_t)req->alg);
  1779. goto error;
  1780. }
  1781. if (qcedev_check_offload_cipher_key(req, podev))
  1782. goto error;
  1783. if (req->block_offset >= AES_CE_BLOCK_SIZE)
  1784. goto error;
  1785. /* if using a byteoffset, make sure it is CTR mode using vbuf */
  1786. if (req->byteoffset) {
  1787. if (req->mode != QCEDEV_AES_MODE_CTR) {
  1788. pr_err("%s: Operation on byte offset not supported\n",
  1789. __func__);
  1790. goto error;
  1791. }
  1792. if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
  1793. pr_err("%s: Invalid byte offset\n", __func__);
  1794. goto error;
  1795. }
  1796. total = req->byteoffset;
  1797. for (i = 0; i < req->entries; i++) {
  1798. if (total > U32_MAX - req->vbuf.src[i].len) {
  1799. pr_err("%s:Int overflow on total src len\n",
  1800. __func__);
  1801. goto error;
  1802. }
  1803. total += req->vbuf.src[i].len;
  1804. }
  1805. }
  1806. if (req->data_len < req->byteoffset) {
  1807. pr_err("%s: req data length %u is less than byteoffset %u\n",
  1808. __func__, req->data_len, req->byteoffset);
  1809. goto error;
  1810. }
  1811. /* Ensure IV size */
  1812. if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
  1813. pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
  1814. goto error;
  1815. }
  1816. /* Ensure Key size */
  1817. if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
  1818. pr_err("%s: Klen is not correct: %u\n", __func__,
  1819. req->encklen);
  1820. goto error;
  1821. }
  1822. /* Check for sum of all dst length is equal to data_len */
  1823. for (i = 0, total = 0; i < req->entries; i++) {
  1824. if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
  1825. pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
  1826. __func__, i, req->vbuf.dst[i].len);
  1827. goto error;
  1828. }
  1829. if (req->vbuf.dst[i].len >= U32_MAX - total) {
  1830. pr_err("%s: Int overflow on total req dst vbuf len\n",
  1831. __func__);
  1832. goto error;
  1833. }
  1834. total += req->vbuf.dst[i].len;
  1835. }
  1836. if (total != req->data_len) {
  1837. pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
  1838. __func__, i, total, req->data_len);
  1839. goto error;
  1840. }
  1841. /* Check for sum of all src length is equal to data_len */
  1842. for (i = 0, total = 0; i < req->entries; i++) {
  1843. if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
  1844. pr_err("%s: NULL req src vbuf[%d] with length %d\n",
  1845. __func__, i, req->vbuf.src[i].len);
  1846. goto error;
  1847. }
  1848. if (req->vbuf.src[i].len > U32_MAX - total) {
  1849. pr_err("%s: Int overflow on total req src vbuf len\n",
  1850. __func__);
  1851. goto error;
  1852. }
  1853. total += req->vbuf.src[i].len;
  1854. }
  1855. if (total != req->data_len) {
  1856. pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
  1857. __func__, total, req->data_len);
  1858. goto error;
  1859. }
  1860. return 0;
  1861. error:
  1862. return -EINVAL;
  1863. }
  1864. long qcedev_ioctl(struct file *file,
  1865. unsigned int cmd, unsigned long arg)
  1866. {
  1867. int err = 0;
  1868. struct qcedev_handle *handle;
  1869. struct qcedev_control *podev;
  1870. struct qcedev_async_req *qcedev_areq;
  1871. struct qcedev_stat *pstat;
  1872. qcedev_areq = kzalloc(sizeof(struct qcedev_async_req), GFP_KERNEL);
  1873. if (!qcedev_areq)
  1874. return -ENOMEM;
  1875. handle = file->private_data;
  1876. podev = handle->cntl;
  1877. qcedev_areq->handle = handle;
  1878. if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
  1879. pr_err("%s: invalid handle %pK\n",
  1880. __func__, podev);
  1881. err = -ENOENT;
  1882. goto exit_free_qcedev_areq;
  1883. }
  1884. /* Verify user arguments. */
  1885. if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC) {
  1886. err = -ENOTTY;
  1887. goto exit_free_qcedev_areq;
  1888. }
  1889. init_completion(&qcedev_areq->complete);
  1890. pstat = &_qcedev_stat;
  1891. switch (cmd) {
  1892. case QCEDEV_IOCTL_ENC_REQ:
  1893. case QCEDEV_IOCTL_DEC_REQ:
  1894. if (copy_from_user(&qcedev_areq->cipher_op_req,
  1895. (void __user *)arg,
  1896. sizeof(struct qcedev_cipher_op_req))) {
  1897. err = -EFAULT;
  1898. goto exit_free_qcedev_areq;
  1899. }
  1900. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_CIPHER;
  1901. if (qcedev_check_cipher_params(&qcedev_areq->cipher_op_req,
  1902. podev)) {
  1903. err = -EINVAL;
  1904. goto exit_free_qcedev_areq;
  1905. }
  1906. err = qcedev_vbuf_ablk_cipher(qcedev_areq, handle);
  1907. if (err)
  1908. goto exit_free_qcedev_areq;
  1909. if (copy_to_user((void __user *)arg,
  1910. &qcedev_areq->cipher_op_req,
  1911. sizeof(struct qcedev_cipher_op_req))) {
  1912. err = -EFAULT;
  1913. goto exit_free_qcedev_areq;
  1914. }
  1915. break;
  1916. case QCEDEV_IOCTL_OFFLOAD_OP_REQ:
  1917. if (copy_from_user(&qcedev_areq->offload_cipher_op_req,
  1918. (void __user *)arg,
  1919. sizeof(struct qcedev_offload_cipher_op_req))) {
  1920. err = -EFAULT;
  1921. goto exit_free_qcedev_areq;
  1922. }
  1923. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER;
  1924. if (qcedev_check_offload_cipher_params(
  1925. &qcedev_areq->offload_cipher_op_req, podev)) {
  1926. err = -EINVAL;
  1927. goto exit_free_qcedev_areq;
  1928. }
  1929. qcedev_areq->offload_cipher_op_req.err = QCEDEV_OFFLOAD_NO_ERROR;
  1930. err = qcedev_smmu_ablk_offload_cipher(qcedev_areq, handle);
  1931. if (err)
  1932. goto exit_free_qcedev_areq;
  1933. if (copy_to_user((void __user *)arg,
  1934. &qcedev_areq->offload_cipher_op_req,
  1935. sizeof(struct qcedev_offload_cipher_op_req))) {
  1936. err = -EFAULT;
  1937. goto exit_free_qcedev_areq;
  1938. }
  1939. break;
  1940. case QCEDEV_IOCTL_SHA_INIT_REQ:
  1941. {
  1942. struct scatterlist sg_src;
  1943. if (copy_from_user(&qcedev_areq->sha_op_req,
  1944. (void __user *)arg,
  1945. sizeof(struct qcedev_sha_op_req))) {
  1946. err = -EFAULT;
  1947. goto exit_free_qcedev_areq;
  1948. }
  1949. mutex_lock(&hash_access_lock);
  1950. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1951. mutex_unlock(&hash_access_lock);
  1952. err = -EINVAL;
  1953. goto exit_free_qcedev_areq;
  1954. }
  1955. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1956. err = qcedev_hash_init(qcedev_areq, handle, &sg_src);
  1957. if (err) {
  1958. mutex_unlock(&hash_access_lock);
  1959. goto exit_free_qcedev_areq;
  1960. }
  1961. mutex_unlock(&hash_access_lock);
  1962. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  1963. sizeof(struct qcedev_sha_op_req))) {
  1964. err = -EFAULT;
  1965. goto exit_free_qcedev_areq;
  1966. }
  1967. handle->sha_ctxt.init_done = true;
  1968. }
  1969. break;
  1970. case QCEDEV_IOCTL_GET_CMAC_REQ:
  1971. if (!podev->ce_support.cmac) {
  1972. err = -ENOTTY;
  1973. goto exit_free_qcedev_areq;
  1974. }
  1975. fallthrough;
  1976. case QCEDEV_IOCTL_SHA_UPDATE_REQ:
  1977. {
  1978. struct scatterlist sg_src;
  1979. if (copy_from_user(&qcedev_areq->sha_op_req,
  1980. (void __user *)arg,
  1981. sizeof(struct qcedev_sha_op_req))) {
  1982. err = -EFAULT;
  1983. goto exit_free_qcedev_areq;
  1984. }
  1985. mutex_lock(&hash_access_lock);
  1986. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  1987. mutex_unlock(&hash_access_lock);
  1988. err = -EINVAL;
  1989. goto exit_free_qcedev_areq;
  1990. }
  1991. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  1992. if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
  1993. err = qcedev_hash_cmac(qcedev_areq, handle, &sg_src);
  1994. if (err) {
  1995. mutex_unlock(&hash_access_lock);
  1996. goto exit_free_qcedev_areq;
  1997. }
  1998. } else {
  1999. if (!handle->sha_ctxt.init_done) {
  2000. pr_err("%s Init was not called\n", __func__);
  2001. mutex_unlock(&hash_access_lock);
  2002. err = -EINVAL;
  2003. goto exit_free_qcedev_areq;
  2004. }
  2005. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2006. if (err) {
  2007. mutex_unlock(&hash_access_lock);
  2008. goto exit_free_qcedev_areq;
  2009. }
  2010. }
  2011. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2012. pr_err("Invalid sha_ctxt.diglen %d\n",
  2013. handle->sha_ctxt.diglen);
  2014. mutex_unlock(&hash_access_lock);
  2015. err = -EINVAL;
  2016. goto exit_free_qcedev_areq;
  2017. }
  2018. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2019. &handle->sha_ctxt.digest[0],
  2020. handle->sha_ctxt.diglen);
  2021. mutex_unlock(&hash_access_lock);
  2022. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2023. sizeof(struct qcedev_sha_op_req))) {
  2024. err = -EFAULT;
  2025. goto exit_free_qcedev_areq;
  2026. }
  2027. }
  2028. break;
  2029. case QCEDEV_IOCTL_SHA_FINAL_REQ:
  2030. if (!handle->sha_ctxt.init_done) {
  2031. pr_err("%s Init was not called\n", __func__);
  2032. err = -EINVAL;
  2033. goto exit_free_qcedev_areq;
  2034. }
  2035. if (copy_from_user(&qcedev_areq->sha_op_req,
  2036. (void __user *)arg,
  2037. sizeof(struct qcedev_sha_op_req))) {
  2038. err = -EFAULT;
  2039. goto exit_free_qcedev_areq;
  2040. }
  2041. mutex_lock(&hash_access_lock);
  2042. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2043. mutex_unlock(&hash_access_lock);
  2044. err = -EINVAL;
  2045. goto exit_free_qcedev_areq;
  2046. }
  2047. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2048. err = qcedev_hash_final(qcedev_areq, handle);
  2049. if (err) {
  2050. mutex_unlock(&hash_access_lock);
  2051. goto exit_free_qcedev_areq;
  2052. }
  2053. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2054. pr_err("Invalid sha_ctxt.diglen %d\n",
  2055. handle->sha_ctxt.diglen);
  2056. mutex_unlock(&hash_access_lock);
  2057. err = -EINVAL;
  2058. goto exit_free_qcedev_areq;
  2059. }
  2060. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2061. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2062. &handle->sha_ctxt.digest[0],
  2063. handle->sha_ctxt.diglen);
  2064. mutex_unlock(&hash_access_lock);
  2065. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2066. sizeof(struct qcedev_sha_op_req))) {
  2067. err = -EFAULT;
  2068. goto exit_free_qcedev_areq;
  2069. }
  2070. handle->sha_ctxt.init_done = false;
  2071. break;
  2072. case QCEDEV_IOCTL_GET_SHA_REQ:
  2073. {
  2074. struct scatterlist sg_src;
  2075. if (copy_from_user(&qcedev_areq->sha_op_req,
  2076. (void __user *)arg,
  2077. sizeof(struct qcedev_sha_op_req))) {
  2078. err = -EFAULT;
  2079. goto exit_free_qcedev_areq;
  2080. }
  2081. mutex_lock(&hash_access_lock);
  2082. if (qcedev_check_sha_params(&qcedev_areq->sha_op_req, podev)) {
  2083. mutex_unlock(&hash_access_lock);
  2084. err = -EINVAL;
  2085. goto exit_free_qcedev_areq;
  2086. }
  2087. qcedev_areq->op_type = QCEDEV_CRYPTO_OPER_SHA;
  2088. qcedev_hash_init(qcedev_areq, handle, &sg_src);
  2089. err = qcedev_hash_update(qcedev_areq, handle, &sg_src);
  2090. if (err) {
  2091. mutex_unlock(&hash_access_lock);
  2092. goto exit_free_qcedev_areq;
  2093. }
  2094. err = qcedev_hash_final(qcedev_areq, handle);
  2095. if (err) {
  2096. mutex_unlock(&hash_access_lock);
  2097. goto exit_free_qcedev_areq;
  2098. }
  2099. if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
  2100. pr_err("Invalid sha_ctxt.diglen %d\n",
  2101. handle->sha_ctxt.diglen);
  2102. mutex_unlock(&hash_access_lock);
  2103. err = -EINVAL;
  2104. goto exit_free_qcedev_areq;
  2105. }
  2106. qcedev_areq->sha_op_req.diglen = handle->sha_ctxt.diglen;
  2107. memcpy(&qcedev_areq->sha_op_req.digest[0],
  2108. &handle->sha_ctxt.digest[0],
  2109. handle->sha_ctxt.diglen);
  2110. mutex_unlock(&hash_access_lock);
  2111. if (copy_to_user((void __user *)arg, &qcedev_areq->sha_op_req,
  2112. sizeof(struct qcedev_sha_op_req))) {
  2113. err = -EFAULT;
  2114. goto exit_free_qcedev_areq;
  2115. }
  2116. }
  2117. break;
  2118. case QCEDEV_IOCTL_MAP_BUF_REQ:
  2119. {
  2120. unsigned long long vaddr = 0;
  2121. struct qcedev_map_buf_req map_buf = { {0} };
  2122. int i = 0;
  2123. if (copy_from_user(&map_buf,
  2124. (void __user *)arg, sizeof(map_buf))) {
  2125. err = -EFAULT;
  2126. goto exit_free_qcedev_areq;
  2127. }
  2128. if (map_buf.num_fds > ARRAY_SIZE(map_buf.fd)) {
  2129. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2130. __func__, map_buf.num_fds);
  2131. err = -EINVAL;
  2132. goto exit_free_qcedev_areq;
  2133. }
  2134. for (i = 0; i < map_buf.num_fds; i++) {
  2135. err = qcedev_check_and_map_buffer(handle,
  2136. map_buf.fd[i],
  2137. map_buf.fd_offset[i],
  2138. map_buf.fd_size[i],
  2139. &vaddr);
  2140. if (err) {
  2141. pr_err(
  2142. "%s: err: failed to map fd(%d) - %d\n",
  2143. __func__, map_buf.fd[i], err);
  2144. goto exit_free_qcedev_areq;
  2145. }
  2146. map_buf.buf_vaddr[i] = vaddr;
  2147. pr_info("%s: info: vaddr = %llx\n, fd = %d",
  2148. __func__, vaddr, map_buf.fd[i]);
  2149. }
  2150. if (copy_to_user((void __user *)arg, &map_buf,
  2151. sizeof(map_buf))) {
  2152. err = -EFAULT;
  2153. goto exit_free_qcedev_areq;
  2154. }
  2155. break;
  2156. }
  2157. case QCEDEV_IOCTL_UNMAP_BUF_REQ:
  2158. {
  2159. struct qcedev_unmap_buf_req unmap_buf = { { 0 } };
  2160. int i = 0;
  2161. if (copy_from_user(&unmap_buf,
  2162. (void __user *)arg, sizeof(unmap_buf))) {
  2163. err = -EFAULT;
  2164. goto exit_free_qcedev_areq;
  2165. }
  2166. if (unmap_buf.num_fds > ARRAY_SIZE(unmap_buf.fd)) {
  2167. pr_err("%s: err: num_fds = %d exceeds max value\n",
  2168. __func__, unmap_buf.num_fds);
  2169. err = -EINVAL;
  2170. goto exit_free_qcedev_areq;
  2171. }
  2172. for (i = 0; i < unmap_buf.num_fds; i++) {
  2173. err = qcedev_check_and_unmap_buffer(handle,
  2174. unmap_buf.fd[i]);
  2175. if (err) {
  2176. pr_err(
  2177. "%s: err: failed to unmap fd(%d) - %d\n",
  2178. __func__,
  2179. unmap_buf.fd[i], err);
  2180. goto exit_free_qcedev_areq;
  2181. }
  2182. }
  2183. break;
  2184. }
  2185. default:
  2186. err = -ENOTTY;
  2187. goto exit_free_qcedev_areq;
  2188. }
  2189. exit_free_qcedev_areq:
  2190. kfree(qcedev_areq);
  2191. return err;
  2192. }
  2193. static int qcedev_probe_device(struct platform_device *pdev)
  2194. {
  2195. void *handle = NULL;
  2196. int rc = 0;
  2197. struct qcedev_control *podev;
  2198. struct msm_ce_hw_support *platform_support;
  2199. podev = &qce_dev[0];
  2200. rc = alloc_chrdev_region(&qcedev_device_no, 0, 1, QCEDEV_DEV);
  2201. if (rc < 0) {
  2202. pr_err("alloc_chrdev_region failed %d\n", rc);
  2203. return rc;
  2204. }
  2205. #if (KERNEL_VERSION(6, 3, 0) <= LINUX_VERSION_CODE)
  2206. driver_class = class_create(QCEDEV_DEV);
  2207. #else
  2208. driver_class = class_create(THIS_MODULE, QCEDEV_DEV);
  2209. #endif
  2210. if (IS_ERR(driver_class)) {
  2211. rc = -ENOMEM;
  2212. pr_err("class_create failed %d\n", rc);
  2213. goto exit_unreg_chrdev_region;
  2214. }
  2215. class_dev = device_create(driver_class, NULL, qcedev_device_no, NULL,
  2216. QCEDEV_DEV);
  2217. if (IS_ERR(class_dev)) {
  2218. pr_err("class_device_create failed %d\n", rc);
  2219. rc = -ENOMEM;
  2220. goto exit_destroy_class;
  2221. }
  2222. cdev_init(&podev->cdev, &qcedev_fops);
  2223. podev->cdev.owner = THIS_MODULE;
  2224. rc = cdev_add(&podev->cdev, MKDEV(MAJOR(qcedev_device_no), 0), 1);
  2225. if (rc < 0) {
  2226. pr_err("cdev_add failed %d\n", rc);
  2227. goto exit_destroy_device;
  2228. }
  2229. podev->minor = 0;
  2230. podev->high_bw_req_count = 0;
  2231. INIT_LIST_HEAD(&podev->ready_commands);
  2232. podev->active_command = NULL;
  2233. INIT_LIST_HEAD(&podev->context_banks);
  2234. spin_lock_init(&podev->lock);
  2235. tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
  2236. podev->icc_path = of_icc_get(&pdev->dev, "data_path");
  2237. if (IS_ERR(podev->icc_path)) {
  2238. rc = PTR_ERR(podev->icc_path);
  2239. pr_err("%s Failed to get icc path with error %d\n",
  2240. __func__, rc);
  2241. goto exit_del_cdev;
  2242. }
  2243. /*
  2244. * HLOS crypto vote values from DTSI. If no values specified, use
  2245. * nominal values.
  2246. */
  2247. if (of_property_read_u32((&pdev->dev)->of_node,
  2248. "qcom,icc_avg_bw",
  2249. &podev->icc_avg_bw)) {
  2250. pr_warn("%s: No icc avg BW set, using default\n", __func__);
  2251. podev->icc_avg_bw = CRYPTO_AVG_BW;
  2252. }
  2253. if (of_property_read_u32((&pdev->dev)->of_node,
  2254. "qcom,icc_peak_bw",
  2255. &podev->icc_peak_bw)) {
  2256. pr_warn("%s: No icc peak BW set, using default\n", __func__);
  2257. podev->icc_peak_bw = CRYPTO_PEAK_BW;
  2258. }
  2259. rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
  2260. podev->icc_peak_bw);
  2261. if (rc) {
  2262. pr_err("%s Unable to set high bandwidth\n", __func__);
  2263. goto exit_unregister_bus_scale;
  2264. }
  2265. handle = qce_open(pdev, &rc);
  2266. if (handle == NULL) {
  2267. rc = -ENODEV;
  2268. goto exit_scale_busbandwidth;
  2269. }
  2270. podev->qce = handle;
  2271. rc = qce_set_irqs(podev->qce, false);
  2272. if (rc) {
  2273. pr_err("%s: could not disable bam irqs, ret = %d",
  2274. __func__, rc);
  2275. goto exit_scale_busbandwidth;
  2276. }
  2277. rc = icc_set_bw(podev->icc_path, 0, 0);
  2278. if (rc) {
  2279. pr_err("%s Unable to set to low bandwidth\n", __func__);
  2280. goto exit_qce_close;
  2281. }
  2282. podev->pdev = pdev;
  2283. platform_set_drvdata(pdev, podev);
  2284. qce_hw_support(podev->qce, &podev->ce_support);
  2285. if (podev->ce_support.bam) {
  2286. podev->platform_support.ce_shared = 0;
  2287. podev->platform_support.shared_ce_resource = 0;
  2288. podev->platform_support.hw_key_support =
  2289. podev->ce_support.hw_key;
  2290. podev->platform_support.sha_hmac = 1;
  2291. } else {
  2292. platform_support =
  2293. (struct msm_ce_hw_support *)pdev->dev.platform_data;
  2294. podev->platform_support.ce_shared = platform_support->ce_shared;
  2295. podev->platform_support.shared_ce_resource =
  2296. platform_support->shared_ce_resource;
  2297. podev->platform_support.hw_key_support =
  2298. platform_support->hw_key_support;
  2299. podev->platform_support.sha_hmac = platform_support->sha_hmac;
  2300. }
  2301. podev->mem_client = qcedev_mem_new_client(MEM_ION);
  2302. if (!podev->mem_client) {
  2303. pr_err("%s: err: qcedev_mem_new_client failed\n", __func__);
  2304. goto exit_qce_close;
  2305. }
  2306. rc = of_platform_populate(pdev->dev.of_node, qcedev_match,
  2307. NULL, &pdev->dev);
  2308. if (rc) {
  2309. pr_err("%s: err: of_platform_populate failed: %d\n",
  2310. __func__, rc);
  2311. goto exit_mem_new_client;
  2312. }
  2313. return 0;
  2314. exit_mem_new_client:
  2315. if (podev->mem_client)
  2316. qcedev_mem_delete_client(podev->mem_client);
  2317. podev->mem_client = NULL;
  2318. exit_qce_close:
  2319. if (handle)
  2320. qce_close(handle);
  2321. exit_scale_busbandwidth:
  2322. icc_set_bw(podev->icc_path, 0, 0);
  2323. exit_unregister_bus_scale:
  2324. if (podev->icc_path)
  2325. icc_put(podev->icc_path);
  2326. exit_del_cdev:
  2327. cdev_del(&podev->cdev);
  2328. exit_destroy_device:
  2329. device_destroy(driver_class, qcedev_device_no);
  2330. exit_destroy_class:
  2331. class_destroy(driver_class);
  2332. exit_unreg_chrdev_region:
  2333. unregister_chrdev_region(qcedev_device_no, 1);
  2334. podev->icc_path = NULL;
  2335. platform_set_drvdata(pdev, NULL);
  2336. podev->pdev = NULL;
  2337. podev->qce = NULL;
  2338. return rc;
  2339. }
  2340. static int qcedev_probe(struct platform_device *pdev)
  2341. {
  2342. if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcedev"))
  2343. return qcedev_probe_device(pdev);
  2344. else if (of_device_is_compatible(pdev->dev.of_node,
  2345. "qcom,qcedev,context-bank"))
  2346. return qcedev_parse_context_bank(pdev);
  2347. return -EINVAL;
  2348. };
  2349. static int qcedev_remove(struct platform_device *pdev)
  2350. {
  2351. struct qcedev_control *podev;
  2352. podev = platform_get_drvdata(pdev);
  2353. if (!podev)
  2354. return 0;
  2355. qcedev_ce_high_bw_req(podev, true);
  2356. if (podev->qce)
  2357. qce_close(podev->qce);
  2358. qcedev_ce_high_bw_req(podev, false);
  2359. if (podev->icc_path)
  2360. icc_put(podev->icc_path);
  2361. tasklet_kill(&podev->done_tasklet);
  2362. cdev_del(&podev->cdev);
  2363. device_destroy(driver_class, qcedev_device_no);
  2364. class_destroy(driver_class);
  2365. unregister_chrdev_region(qcedev_device_no, 1);
  2366. return 0;
  2367. };
  2368. static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
  2369. {
  2370. struct qcedev_control *podev;
  2371. int ret;
  2372. podev = platform_get_drvdata(pdev);
  2373. if (!podev)
  2374. return 0;
  2375. mutex_lock(&qcedev_sent_bw_req);
  2376. if (podev->high_bw_req_count) {
  2377. ret = qce_set_irqs(podev->qce, false);
  2378. if (ret) {
  2379. pr_err("%s: could not disable bam irqs, ret = %d",
  2380. __func__, ret);
  2381. goto suspend_exit;
  2382. }
  2383. ret = qcedev_control_clocks(podev, false);
  2384. if (ret)
  2385. goto suspend_exit;
  2386. }
  2387. suspend_exit:
  2388. mutex_unlock(&qcedev_sent_bw_req);
  2389. return 0;
  2390. }
  2391. static int qcedev_resume(struct platform_device *pdev)
  2392. {
  2393. struct qcedev_control *podev;
  2394. int ret;
  2395. podev = platform_get_drvdata(pdev);
  2396. if (!podev)
  2397. return 0;
  2398. mutex_lock(&qcedev_sent_bw_req);
  2399. if (podev->high_bw_req_count) {
  2400. ret = qcedev_control_clocks(podev, true);
  2401. if (ret)
  2402. goto resume_exit;
  2403. ret = qce_set_irqs(podev->qce, true);
  2404. if (ret) {
  2405. pr_err("%s: could not enable bam irqs, ret = %d",
  2406. __func__, ret);
  2407. qcedev_control_clocks(podev, false);
  2408. }
  2409. }
  2410. resume_exit:
  2411. mutex_unlock(&qcedev_sent_bw_req);
  2412. return 0;
  2413. }
  2414. static struct platform_driver qcedev_plat_driver = {
  2415. .probe = qcedev_probe,
  2416. .remove = qcedev_remove,
  2417. .suspend = qcedev_suspend,
  2418. .resume = qcedev_resume,
  2419. .driver = {
  2420. .name = "qce",
  2421. .of_match_table = qcedev_match,
  2422. },
  2423. };
  2424. static int _disp_stats(int id)
  2425. {
  2426. struct qcedev_stat *pstat;
  2427. int len = 0;
  2428. pstat = &_qcedev_stat;
  2429. len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
  2430. "\nQTI QCE dev driver %d Statistics:\n",
  2431. id + 1);
  2432. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2433. " Encryption operation success : %d\n",
  2434. pstat->qcedev_enc_success);
  2435. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2436. " Encryption operation fail : %d\n",
  2437. pstat->qcedev_enc_fail);
  2438. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2439. " Decryption operation success : %d\n",
  2440. pstat->qcedev_dec_success);
  2441. len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
  2442. " Encryption operation fail : %d\n",
  2443. pstat->qcedev_dec_fail);
  2444. return len;
  2445. }
  2446. static ssize_t _debug_stats_read(struct file *file, char __user *buf,
  2447. size_t count, loff_t *ppos)
  2448. {
  2449. ssize_t rc = -EINVAL;
  2450. int qcedev = *((int *) file->private_data);
  2451. int len;
  2452. len = _disp_stats(qcedev);
  2453. if (len <= count)
  2454. rc = simple_read_from_buffer((void __user *) buf, len,
  2455. ppos, (void *) _debug_read_buf, len);
  2456. return rc;
  2457. }
  2458. static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
  2459. size_t count, loff_t *ppos)
  2460. {
  2461. memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
  2462. return count;
  2463. };
  2464. static const struct file_operations _debug_stats_ops = {
  2465. .open = simple_open,
  2466. .read = _debug_stats_read,
  2467. .write = _debug_stats_write,
  2468. };
  2469. static int _qcedev_debug_init(void)
  2470. {
  2471. int rc;
  2472. char name[DEBUG_MAX_FNAME];
  2473. struct dentry *dent;
  2474. _debug_dent = debugfs_create_dir("qcedev", NULL);
  2475. if (IS_ERR(_debug_dent)) {
  2476. pr_debug("qcedev debugfs_create_dir fail, error %ld\n",
  2477. PTR_ERR(_debug_dent));
  2478. return PTR_ERR(_debug_dent);
  2479. }
  2480. snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
  2481. _debug_qcedev = 0;
  2482. dent = debugfs_create_file(name, 0644, _debug_dent,
  2483. &_debug_qcedev, &_debug_stats_ops);
  2484. if (dent == NULL) {
  2485. pr_debug("qcedev debugfs_create_file fail, error %ld\n",
  2486. PTR_ERR(dent));
  2487. rc = PTR_ERR(dent);
  2488. goto err;
  2489. }
  2490. return 0;
  2491. err:
  2492. debugfs_remove_recursive(_debug_dent);
  2493. return rc;
  2494. }
  2495. static int qcedev_init(void)
  2496. {
  2497. _qcedev_debug_init();
  2498. return platform_driver_register(&qcedev_plat_driver);
  2499. }
  2500. static void qcedev_exit(void)
  2501. {
  2502. debugfs_remove_recursive(_debug_dent);
  2503. platform_driver_unregister(&qcedev_plat_driver);
  2504. }
  2505. MODULE_LICENSE("GPL v2");
  2506. MODULE_DESCRIPTION("QTI DEV Crypto driver");
  2507. MODULE_IMPORT_NS(DMA_BUF);
  2508. module_init(qcedev_init);
  2509. module_exit(qcedev_exit);