samsung-sm8650
/
android_kernel_samsung_sm8650-modules


			
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							/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _GEN8_REG_H
#define _GEN8_REG_H

/* GEN8 interrupt bits */
#define GEN8_INT_GPUIDLE                0
#define GEN8_INT_AHBERROR               1
#define GEN8_INT_CPIPCINT0              4
#define GEN8_INT_CPIPCINT1              5
#define GEN8_INT_ATBASYNCFIFOOVERFLOW   6
#define GEN8_INT_GPCERROR               7
#define GEN8_INT_SWINTERRUPT            8
#define GEN8_INT_HWERROR                9
#define GEN8_INT_CCU_CLEAN_DEPTH_TS     10
#define GEN8_INT_CCU_CLEAN_COLOR_TS     11
#define GEN8_INT_CCU_RESOLVE_CLEAN_TS   12
#define GEN8_INT_PM4CPINTERRUPT         15
#define GEN8_INT_PM4CPINTERRUPTLPAC     16
#define GEN8_INT_RB_DONE_TS             17
#define GEN8_INT_CACHE_CLEAN_TS         20
#define GEN8_INT_CACHE_CLEAN_TS_LPAC    21
#define GEN8_INT_ATBBUSOVERFLOW         22
#define GEN8_INT_HANGDETECTINTERRUPT    23
#define GEN8_INT_OUTOFBOUNDACCESS       24
#define GEN8_INT_UCHETRAPINTERRUPT      25
#define GEN8_INT_DEBUGBUSINTERRUPT0     26
#define GEN8_INT_DEBUGBUSINTERRUPT1     27
#define GEN8_INT_TSBWRITEERROR          28
#define GEN8_INT_SWFUSEVIOLATION        29
#define GEN8_INT_ISDBCPUIRQ             30
#define GEN8_INT_ISDBUNDERDEBUG         31

/* RBBM registers */
#define GEN8_RBBM_GBIF_CLIENT_QOS_CNTL           0x008
#define GEN8_RBBM_GBIF_HALT                      0x00a
#define GEN8_RBBM_GBIF_HALT_ACK                  0x00b
#define GEN8_RBBM_WAIT_IDLE_CLOCKS_CNTL          0x010
#define GEN8_RBBM_WAIT_IDLE_CLOCKS_CNTL2         0x011
#define GEN8_RBBM_STATUS                         0x012
#define GEN8_RBBM_STATUS1                        0x013
#define GEN8_RBBM_GFX_STATUS                     0x015
#define GEN8_RBBM_GFX_STATUS1                    0x016
#define GEN8_RBBM_LPAC_STATUS                    0x018
#define GEN8_RBBM_GFX_BR_STATUS                  0x01a
#define GEN8_RBBM_GFX_BV_STATUS                  0x01c
#define GEN8_RBBM_ISDB_CNT                       0x02d
#define GEN8_RBBM_SNAPSHOT_STATUS                0x02e
#define GEN8_RBBM_INTERFACE_HANG_INT_CNTL        0x02f
#define GEN8_RBBM_INT_CLEAR_CMD                  0x061
#define GEN8_RBBM_INT_0_MASK                     0x062
#define GEN8_RBBM_INT_2_MASK                     0x064
#define GEN8_RBBM_INT_0_STATUS                   0x06a
#define GEN8_RBBM_SW_FUSE_INT_STATUS             0x071
#define GEN8_RBBM_SW_FUSE_INT_MASK               0x072
#define GEN8_RBBM_SW_RESET_CMD                   0x073
#define GEN8_RBBM_CLOCK_CNTL_GLOBAL              0x09a
#define GEN8_RBBM_CGC_GLOBAL_LOAD_CMD            0x09b
#define GEN8_RBBM_CGC_P2S_TRIG_CMD               0x09c
#define GEN8_RBBM_CGC_P2S_CNTL                   0x09d
#define GEN8_RBBM_CGC_P2S_STATUS                 0x09f

#define GEN8_RBBM_CGC_0_PC                       0x10b
#define GEN8_RBBM_PERFCTR_GPU_BUSY_MASKED        0x19e
#define GEN8_RBBM_PERFCTR_SRAM_INIT_STATUS       0x19f
#define GEN8_RBBM_PERFCTR_FLUSH_HOST_STATUS      0x1a1
#define GEN8_RBBM_PERFCTR_CP_0_LO                0x1b0
#define GEN8_RBBM_PERFCTR_CP_0_HI                0x1b1
#define GEN8_RBBM_PERFCTR_CP_1_LO                0x1b2
#define GEN8_RBBM_PERFCTR_CP_1_HI                0x1b3
#define GEN8_RBBM_PERFCTR_CP_2_LO                0x1b4
#define GEN8_RBBM_PERFCTR_CP_2_HI                0x1b5
#define GEN8_RBBM_PERFCTR_CP_3_LO                0x1b6
#define GEN8_RBBM_PERFCTR_CP_3_HI                0x1b7
#define GEN8_RBBM_PERFCTR_CP_4_LO                0x1b8
#define GEN8_RBBM_PERFCTR_CP_4_HI                0x1b9
#define GEN8_RBBM_PERFCTR_CP_5_LO                0x1ba
#define GEN8_RBBM_PERFCTR_CP_5_HI                0x1bb
#define GEN8_RBBM_PERFCTR_CP_6_LO                0x1bc
#define GEN8_RBBM_PERFCTR_CP_6_HI                0x1bd
#define GEN8_RBBM_PERFCTR_CP_7_LO                0x1be
#define GEN8_RBBM_PERFCTR_CP_7_HI                0x1bf
#define GEN8_RBBM_PERFCTR_CP_8_LO                0x1c0
#define GEN8_RBBM_PERFCTR_CP_8_HI                0x1c1
#define GEN8_RBBM_PERFCTR_CP_9_LO                0x1c2
#define GEN8_RBBM_PERFCTR_CP_9_HI                0x1c3
#define GEN8_RBBM_PERFCTR_CP_10_LO               0x1c4
#define GEN8_RBBM_PERFCTR_CP_10_HI               0x1c5
#define GEN8_RBBM_PERFCTR_CP_11_LO               0x1c6
#define GEN8_RBBM_PERFCTR_CP_11_HI               0x1c7
#define GEN8_RBBM_PERFCTR_CP_12_LO               0x1c8
#define GEN8_RBBM_PERFCTR_CP_12_HI               0x1c9
#define GEN8_RBBM_PERFCTR_CP_13_LO               0x1ca
#define GEN8_RBBM_PERFCTR_CP_13_HI               0x1cb
#define GEN8_RBBM_PERFCTR_RBBM_0_LO              0x1cc
#define GEN8_RBBM_PERFCTR_RBBM_0_HI              0x1cd
#define GEN8_RBBM_PERFCTR_RBBM_1_LO              0x1ce
#define GEN8_RBBM_PERFCTR_RBBM_1_HI              0x1cf
#define GEN8_RBBM_PERFCTR_RBBM_2_LO              0x1d0
#define GEN8_RBBM_PERFCTR_RBBM_2_HI              0x1d1
#define GEN8_RBBM_PERFCTR_RBBM_3_LO              0x1d2
#define GEN8_RBBM_PERFCTR_RBBM_3_HI              0x1d3
#define GEN8_RBBM_PERFCTR_PC_0_LO                0x1d4
#define GEN8_RBBM_PERFCTR_PC_0_HI                0x1d5
#define GEN8_RBBM_PERFCTR_PC_1_LO                0x1d6
#define GEN8_RBBM_PERFCTR_PC_1_HI                0x1d7
#define GEN8_RBBM_PERFCTR_PC_2_LO                0x1d8
#define GEN8_RBBM_PERFCTR_PC_2_HI                0x1d9
#define GEN8_RBBM_PERFCTR_PC_3_LO                0x1da
#define GEN8_RBBM_PERFCTR_PC_3_HI                0x1db
#define GEN8_RBBM_PERFCTR_PC_4_LO                0x1dc
#define GEN8_RBBM_PERFCTR_PC_4_HI                0x1dd
#define GEN8_RBBM_PERFCTR_PC_5_LO                0x1de
#define GEN8_RBBM_PERFCTR_PC_5_HI                0x1df
#define GEN8_RBBM_PERFCTR_PC_6_LO                0x1e0
#define GEN8_RBBM_PERFCTR_PC_6_HI                0x1e1
#define GEN8_RBBM_PERFCTR_PC_7_LO                0x1e2
#define GEN8_RBBM_PERFCTR_PC_7_HI                0x1e3
#define GEN8_RBBM_PERFCTR_VFD_0_LO               0x1e4
#define GEN8_RBBM_PERFCTR_VFD_0_HI               0x1e5
#define GEN8_RBBM_PERFCTR_VFD_1_LO               0x1e6
#define GEN8_RBBM_PERFCTR_VFD_1_HI               0x1e7
#define GEN8_RBBM_PERFCTR_VFD_2_LO               0x1e8
#define GEN8_RBBM_PERFCTR_VFD_2_HI               0x1e9
#define GEN8_RBBM_PERFCTR_VFD_3_LO               0x1ea
#define GEN8_RBBM_PERFCTR_VFD_3_HI               0x1eb
#define GEN8_RBBM_PERFCTR_VFD_4_LO               0x1ec
#define GEN8_RBBM_PERFCTR_VFD_4_HI               0x1ed
#define GEN8_RBBM_PERFCTR_VFD_5_LO               0x1ee
#define GEN8_RBBM_PERFCTR_VFD_5_HI               0x1ef
#define GEN8_RBBM_PERFCTR_VFD_6_LO               0x1f0
#define GEN8_RBBM_PERFCTR_VFD_6_HI               0x1f1
#define GEN8_RBBM_PERFCTR_VFD_7_LO               0x1f2
#define GEN8_RBBM_PERFCTR_VFD_7_HI               0x1f3
#define GEN8_RBBM_PERFCTR_HLSQ_0_LO              0x1f4
#define GEN8_RBBM_PERFCTR_HLSQ_0_HI              0x1f5
#define GEN8_RBBM_PERFCTR_HLSQ_1_LO              0x1f6
#define GEN8_RBBM_PERFCTR_HLSQ_1_HI              0x1f7
#define GEN8_RBBM_PERFCTR_HLSQ_2_LO              0x1f8
#define GEN8_RBBM_PERFCTR_HLSQ_2_HI              0x1f9
#define GEN8_RBBM_PERFCTR_HLSQ_3_LO              0x1fa
#define GEN8_RBBM_PERFCTR_HLSQ_3_HI              0x1fb
#define GEN8_RBBM_PERFCTR_HLSQ_4_LO              0x1fc
#define GEN8_RBBM_PERFCTR_HLSQ_4_HI              0x1fd
#define GEN8_RBBM_PERFCTR_HLSQ_5_LO              0x1fe
#define GEN8_RBBM_PERFCTR_HLSQ_5_HI              0x1ff
#define GEN8_RBBM_PERFCTR_VPC_0_LO               0x200
#define GEN8_RBBM_PERFCTR_VPC_0_HI               0x201
#define GEN8_RBBM_PERFCTR_VPC_1_LO               0x202
#define GEN8_RBBM_PERFCTR_VPC_1_HI               0x203
#define GEN8_RBBM_PERFCTR_VPC_2_LO               0x204
#define GEN8_RBBM_PERFCTR_VPC_2_HI               0x205
#define GEN8_RBBM_PERFCTR_VPC_3_LO               0x206
#define GEN8_RBBM_PERFCTR_VPC_3_HI               0x207
#define GEN8_RBBM_PERFCTR_VPC_4_LO               0x208
#define GEN8_RBBM_PERFCTR_VPC_4_HI               0x209
#define GEN8_RBBM_PERFCTR_VPC_5_LO               0x20a
#define GEN8_RBBM_PERFCTR_VPC_5_HI               0x20b
#define GEN8_RBBM_PERFCTR_CCU_0_LO               0x20c
#define GEN8_RBBM_PERFCTR_CCU_0_HI               0x20d
#define GEN8_RBBM_PERFCTR_CCU_1_LO               0x20e
#define GEN8_RBBM_PERFCTR_CCU_1_HI               0x20f
#define GEN8_RBBM_PERFCTR_CCU_2_LO               0x210
#define GEN8_RBBM_PERFCTR_CCU_2_HI               0x211
#define GEN8_RBBM_PERFCTR_CCU_3_LO               0x212
#define GEN8_RBBM_PERFCTR_CCU_3_HI               0x213
#define GEN8_RBBM_PERFCTR_CCU_4_LO               0x214
#define GEN8_RBBM_PERFCTR_CCU_4_HI               0x215
#define GEN8_RBBM_PERFCTR_TSE_0_LO               0x216
#define GEN8_RBBM_PERFCTR_TSE_0_HI               0x217
#define GEN8_RBBM_PERFCTR_TSE_1_LO               0x218
#define GEN8_RBBM_PERFCTR_TSE_1_HI               0x219
#define GEN8_RBBM_PERFCTR_TSE_2_LO               0x21a
#define GEN8_RBBM_PERFCTR_TSE_2_HI               0x21b
#define GEN8_RBBM_PERFCTR_TSE_3_LO               0x21c
#define GEN8_RBBM_PERFCTR_TSE_3_HI               0x21d
#define GEN8_RBBM_PERFCTR_RAS_0_LO               0x21e
#define GEN8_RBBM_PERFCTR_RAS_0_HI               0x21f
#define GEN8_RBBM_PERFCTR_RAS_1_LO               0x220
#define GEN8_RBBM_PERFCTR_RAS_1_HI               0x221
#define GEN8_RBBM_PERFCTR_RAS_2_LO               0x222
#define GEN8_RBBM_PERFCTR_RAS_2_HI               0x223
#define GEN8_RBBM_PERFCTR_RAS_3_LO               0x224
#define GEN8_RBBM_PERFCTR_RAS_3_HI               0x225
#define GEN8_RBBM_PERFCTR_UCHE_0_LO              0x226
#define GEN8_RBBM_PERFCTR_UCHE_0_HI              0x227
#define GEN8_RBBM_PERFCTR_UCHE_1_LO              0x228
#define GEN8_RBBM_PERFCTR_UCHE_1_HI              0x229
#define GEN8_RBBM_PERFCTR_UCHE_2_LO              0x22a
#define GEN8_RBBM_PERFCTR_UCHE_2_HI              0x22b
#define GEN8_RBBM_PERFCTR_UCHE_3_LO              0x22c
#define GEN8_RBBM_PERFCTR_UCHE_3_HI              0x22d
#define GEN8_RBBM_PERFCTR_UCHE_4_LO              0x22e
#define GEN8_RBBM_PERFCTR_UCHE_4_HI              0x22f
#define GEN8_RBBM_PERFCTR_UCHE_5_LO              0x230
#define GEN8_RBBM_PERFCTR_UCHE_5_HI              0x231
#define GEN8_RBBM_PERFCTR_UCHE_6_LO              0x232
#define GEN8_RBBM_PERFCTR_UCHE_6_HI              0x233
#define GEN8_RBBM_PERFCTR_UCHE_7_LO              0x234
#define GEN8_RBBM_PERFCTR_UCHE_7_HI              0x235
#define GEN8_RBBM_PERFCTR_UCHE_8_LO              0x236
#define GEN8_RBBM_PERFCTR_UCHE_8_HI              0x237
#define GEN8_RBBM_PERFCTR_UCHE_9_LO              0x238
#define GEN8_RBBM_PERFCTR_UCHE_9_HI              0x239
#define GEN8_RBBM_PERFCTR_UCHE_10_LO             0x23a
#define GEN8_RBBM_PERFCTR_UCHE_10_HI             0x23b
#define GEN8_RBBM_PERFCTR_UCHE_11_LO             0x23c
#define GEN8_RBBM_PERFCTR_UCHE_11_HI             0x23d
#define GEN8_RBBM_PERFCTR_UCHE_12_LO             0x23e
#define GEN8_RBBM_PERFCTR_UCHE_12_HI             0x23f
#define GEN8_RBBM_PERFCTR_UCHE_13_LO             0x240
#define GEN8_RBBM_PERFCTR_UCHE_13_HI             0x241
#define GEN8_RBBM_PERFCTR_UCHE_14_LO             0x242
#define GEN8_RBBM_PERFCTR_UCHE_14_HI             0x243
#define GEN8_RBBM_PERFCTR_UCHE_15_LO             0x244
#define GEN8_RBBM_PERFCTR_UCHE_15_HI             0x245
#define GEN8_RBBM_PERFCTR_UCHE_16_LO             0x246
#define GEN8_RBBM_PERFCTR_UCHE_16_HI             0x247
#define GEN8_RBBM_PERFCTR_UCHE_17_LO             0x248
#define GEN8_RBBM_PERFCTR_UCHE_17_HI             0x249
#define GEN8_RBBM_PERFCTR_UCHE_18_LO             0x24a
#define GEN8_RBBM_PERFCTR_UCHE_18_HI             0x24b
#define GEN8_RBBM_PERFCTR_UCHE_19_LO             0x24c
#define GEN8_RBBM_PERFCTR_UCHE_19_HI             0x24d
#define GEN8_RBBM_PERFCTR_UCHE_20_LO             0x24e
#define GEN8_RBBM_PERFCTR_UCHE_20_HI             0x24f
#define GEN8_RBBM_PERFCTR_UCHE_21_LO             0x250
#define GEN8_RBBM_PERFCTR_UCHE_21_HI             0x251
#define GEN8_RBBM_PERFCTR_UCHE_22_LO             0x252
#define GEN8_RBBM_PERFCTR_UCHE_22_HI             0x253
#define GEN8_RBBM_PERFCTR_UCHE_23_LO             0x254
#define GEN8_RBBM_PERFCTR_UCHE_23_HI             0x255
#define GEN8_RBBM_PERFCTR_TP_0_LO                0x256
#define GEN8_RBBM_PERFCTR_TP_0_HI                0x257
#define GEN8_RBBM_PERFCTR_TP_1_LO                0x258
#define GEN8_RBBM_PERFCTR_TP_1_HI                0x259
#define GEN8_RBBM_PERFCTR_TP_2_LO                0x25a
#define GEN8_RBBM_PERFCTR_TP_2_HI                0x25b
#define GEN8_RBBM_PERFCTR_TP_3_LO                0x25c
#define GEN8_RBBM_PERFCTR_TP_3_HI                0x25d
#define GEN8_RBBM_PERFCTR_TP_4_LO                0x25e
#define GEN8_RBBM_PERFCTR_TP_4_HI                0x25f
#define GEN8_RBBM_PERFCTR_TP_5_LO                0x260
#define GEN8_RBBM_PERFCTR_TP_5_HI                0x261
#define GEN8_RBBM_PERFCTR_TP_6_LO                0x262
#define GEN8_RBBM_PERFCTR_TP_6_HI                0x263
#define GEN8_RBBM_PERFCTR_TP_7_LO                0x264
#define GEN8_RBBM_PERFCTR_TP_7_HI                0x265
#define GEN8_RBBM_PERFCTR_TP_8_LO                0x266
#define GEN8_RBBM_PERFCTR_TP_8_HI                0x267
#define GEN8_RBBM_PERFCTR_TP_9_LO                0x268
#define GEN8_RBBM_PERFCTR_TP_9_HI                0x269
#define GEN8_RBBM_PERFCTR_TP_10_LO               0x26a
#define GEN8_RBBM_PERFCTR_TP_10_HI               0x26b
#define GEN8_RBBM_PERFCTR_TP_11_LO               0x26c
#define GEN8_RBBM_PERFCTR_TP_11_HI               0x26d
#define GEN8_RBBM_PERFCTR_SP_0_LO                0x26e
#define GEN8_RBBM_PERFCTR_SP_0_HI                0x26f
#define GEN8_RBBM_PERFCTR_SP_1_LO                0x270
#define GEN8_RBBM_PERFCTR_SP_1_HI                0x271
#define GEN8_RBBM_PERFCTR_SP_2_LO                0x272
#define GEN8_RBBM_PERFCTR_SP_2_HI                0x273
#define GEN8_RBBM_PERFCTR_SP_3_LO                0x274
#define GEN8_RBBM_PERFCTR_SP_3_HI                0x275
#define GEN8_RBBM_PERFCTR_SP_4_LO                0x276
#define GEN8_RBBM_PERFCTR_SP_4_HI                0x277
#define GEN8_RBBM_PERFCTR_SP_5_LO                0x278
#define GEN8_RBBM_PERFCTR_SP_5_HI                0x279
#define GEN8_RBBM_PERFCTR_SP_6_LO                0x27a
#define GEN8_RBBM_PERFCTR_SP_6_HI                0x27b
#define GEN8_RBBM_PERFCTR_SP_7_LO                0x27c
#define GEN8_RBBM_PERFCTR_SP_7_HI                0x27d
#define GEN8_RBBM_PERFCTR_SP_8_LO                0x27e
#define GEN8_RBBM_PERFCTR_SP_8_HI                0x27f
#define GEN8_RBBM_PERFCTR_SP_9_LO                0x280
#define GEN8_RBBM_PERFCTR_SP_9_HI                0x281
#define GEN8_RBBM_PERFCTR_SP_10_LO               0x282
#define GEN8_RBBM_PERFCTR_SP_10_HI               0x283
#define GEN8_RBBM_PERFCTR_SP_11_LO               0x284
#define GEN8_RBBM_PERFCTR_SP_11_HI               0x285
#define GEN8_RBBM_PERFCTR_SP_12_LO               0x286
#define GEN8_RBBM_PERFCTR_SP_12_HI               0x287
#define GEN8_RBBM_PERFCTR_SP_13_LO               0x288
#define GEN8_RBBM_PERFCTR_SP_13_HI               0x289
#define GEN8_RBBM_PERFCTR_SP_14_LO               0x28a
#define GEN8_RBBM_PERFCTR_SP_14_HI               0x28b
#define GEN8_RBBM_PERFCTR_SP_15_LO               0x28c
#define GEN8_RBBM_PERFCTR_SP_15_HI               0x28d
#define GEN8_RBBM_PERFCTR_SP_16_LO               0x28e
#define GEN8_RBBM_PERFCTR_SP_16_HI               0x28f
#define GEN8_RBBM_PERFCTR_SP_17_LO               0x290
#define GEN8_RBBM_PERFCTR_SP_17_HI               0x291
#define GEN8_RBBM_PERFCTR_SP_18_LO               0x292
#define GEN8_RBBM_PERFCTR_SP_18_HI               0x293
#define GEN8_RBBM_PERFCTR_SP_19_LO               0x294
#define GEN8_RBBM_PERFCTR_SP_19_HI               0x295
#define GEN8_RBBM_PERFCTR_SP_20_LO               0x296
#define GEN8_RBBM_PERFCTR_SP_20_HI               0x297
#define GEN8_RBBM_PERFCTR_SP_21_LO               0x298
#define GEN8_RBBM_PERFCTR_SP_21_HI               0x299
#define GEN8_RBBM_PERFCTR_SP_22_LO               0x29a
#define GEN8_RBBM_PERFCTR_SP_22_HI               0x29b
#define GEN8_RBBM_PERFCTR_SP_23_LO               0x29c
#define GEN8_RBBM_PERFCTR_SP_23_HI               0x29d
#define GEN8_RBBM_PERFCTR_RB_0_LO                0x29e
#define GEN8_RBBM_PERFCTR_RB_0_HI                0x29f
#define GEN8_RBBM_PERFCTR_RB_1_LO                0x2a0
#define GEN8_RBBM_PERFCTR_RB_1_HI                0x2a1
#define GEN8_RBBM_PERFCTR_RB_2_LO                0x2a2
#define GEN8_RBBM_PERFCTR_RB_2_HI                0x2a3
#define GEN8_RBBM_PERFCTR_RB_3_LO                0x2a4
#define GEN8_RBBM_PERFCTR_RB_3_HI                0x2a5
#define GEN8_RBBM_PERFCTR_RB_4_LO                0x2a6
#define GEN8_RBBM_PERFCTR_RB_4_HI                0x2a7
#define GEN8_RBBM_PERFCTR_RB_5_LO                0x2a8
#define GEN8_RBBM_PERFCTR_RB_5_HI                0x2a9
#define GEN8_RBBM_PERFCTR_RB_6_LO                0x2aa
#define GEN8_RBBM_PERFCTR_RB_6_HI                0x2ab
#define GEN8_RBBM_PERFCTR_RB_7_LO                0x2ac
#define GEN8_RBBM_PERFCTR_RB_7_HI                0x2ad
#define GEN8_RBBM_PERFCTR_VSC_0_LO               0x2ae
#define GEN8_RBBM_PERFCTR_VSC_0_HI               0x2af
#define GEN8_RBBM_PERFCTR_VSC_1_LO               0x2b0
#define GEN8_RBBM_PERFCTR_VSC_1_HI               0x2b1
#define GEN8_RBBM_PERFCTR_LRZ_0_LO               0x2b2
#define GEN8_RBBM_PERFCTR_LRZ_0_HI               0x2b3
#define GEN8_RBBM_PERFCTR_LRZ_1_LO               0x2b4
#define GEN8_RBBM_PERFCTR_LRZ_1_HI               0x2b5
#define GEN8_RBBM_PERFCTR_LRZ_2_LO               0x2b6
#define GEN8_RBBM_PERFCTR_LRZ_2_HI               0x2b7
#define GEN8_RBBM_PERFCTR_LRZ_3_LO               0x2b8
#define GEN8_RBBM_PERFCTR_LRZ_3_HI               0x2b9
#define GEN8_RBBM_PERFCTR_CMP_0_LO               0x2ba
#define GEN8_RBBM_PERFCTR_CMP_0_HI               0x2bb
#define GEN8_RBBM_PERFCTR_CMP_1_LO               0x2bc
#define GEN8_RBBM_PERFCTR_CMP_1_HI               0x2bd
#define GEN8_RBBM_PERFCTR_CMP_2_LO               0x2be
#define GEN8_RBBM_PERFCTR_CMP_2_HI               0x2bf
#define GEN8_RBBM_PERFCTR_CMP_3_LO               0x2c0
#define GEN8_RBBM_PERFCTR_CMP_3_HI               0x2c1
#define GEN8_RBBM_PERFCTR_UFC_0_LO               0x2c2
#define GEN8_RBBM_PERFCTR_UFC_0_HI               0x2c3
#define GEN8_RBBM_PERFCTR_UFC_1_LO               0x2c4
#define GEN8_RBBM_PERFCTR_UFC_1_HI               0x2c5
#define GEN8_RBBM_PERFCTR_UFC_2_LO               0x2c6
#define GEN8_RBBM_PERFCTR_UFC_2_HI               0x2c7
#define GEN8_RBBM_PERFCTR_UFC_3_LO               0x2c8
#define GEN8_RBBM_PERFCTR_UFC_3_HI               0x2c9

#define GEN8_RBBM_PERFCTR2_HLSQ_0_LO             0x2e2
#define GEN8_RBBM_PERFCTR2_HLSQ_0_HI             0x2e3
#define GEN8_RBBM_PERFCTR2_HLSQ_1_LO             0x2e4
#define GEN8_RBBM_PERFCTR2_HLSQ_1_HI             0x2e5
#define GEN8_RBBM_PERFCTR2_HLSQ_2_LO             0x2e6
#define GEN8_RBBM_PERFCTR2_HLSQ_2_HI             0x2e7
#define GEN8_RBBM_PERFCTR2_HLSQ_3_LO             0x2e8
#define GEN8_RBBM_PERFCTR2_HLSQ_3_HI             0x2e9
#define GEN8_RBBM_PERFCTR2_HLSQ_4_LO             0x2ea
#define GEN8_RBBM_PERFCTR2_HLSQ_4_HI             0x2eb
#define GEN8_RBBM_PERFCTR2_HLSQ_5_LO             0x2ec
#define GEN8_RBBM_PERFCTR2_HLSQ_5_HI             0x2ed
#define GEN8_RBBM_PERFCTR2_CP_0_LO               0x2ee
#define GEN8_RBBM_PERFCTR2_CP_0_HI               0x2ef
#define GEN8_RBBM_PERFCTR2_CP_1_LO               0x2f0
#define GEN8_RBBM_PERFCTR2_CP_1_HI               0x2f1
#define GEN8_RBBM_PERFCTR2_CP_2_LO               0x2f2
#define GEN8_RBBM_PERFCTR2_CP_2_HI               0x2f3
#define GEN8_RBBM_PERFCTR2_CP_3_LO               0x2f4
#define GEN8_RBBM_PERFCTR2_CP_3_HI               0x2f5
#define GEN8_RBBM_PERFCTR2_CP_4_LO               0x2f6
#define GEN8_RBBM_PERFCTR2_CP_4_HI               0x2f7
#define GEN8_RBBM_PERFCTR2_CP_5_LO               0x2f8
#define GEN8_RBBM_PERFCTR2_CP_5_HI               0x2f9
#define GEN8_RBBM_PERFCTR2_CP_6_LO               0x2fa
#define GEN8_RBBM_PERFCTR2_CP_6_HI               0x2fb
#define GEN8_RBBM_PERFCTR2_SP_0_LO               0x2fc
#define GEN8_RBBM_PERFCTR2_SP_0_HI               0x2fd
#define GEN8_RBBM_PERFCTR2_SP_1_LO               0x2fe
#define GEN8_RBBM_PERFCTR2_SP_1_HI               0x2ff
#define GEN8_RBBM_PERFCTR2_SP_2_LO               0x300
#define GEN8_RBBM_PERFCTR2_SP_2_HI               0x301
#define GEN8_RBBM_PERFCTR2_SP_3_LO               0x302
#define GEN8_RBBM_PERFCTR2_SP_3_HI               0x303
#define GEN8_RBBM_PERFCTR2_SP_4_LO               0x304
#define GEN8_RBBM_PERFCTR2_SP_4_HI               0x305
#define GEN8_RBBM_PERFCTR2_SP_5_LO               0x306
#define GEN8_RBBM_PERFCTR2_SP_5_HI               0x307
#define GEN8_RBBM_PERFCTR2_SP_6_LO               0x308
#define GEN8_RBBM_PERFCTR2_SP_6_HI               0x309
#define GEN8_RBBM_PERFCTR2_SP_7_LO               0x30a
#define GEN8_RBBM_PERFCTR2_SP_7_HI               0x30b
#define GEN8_RBBM_PERFCTR2_SP_8_LO               0x30c
#define GEN8_RBBM_PERFCTR2_SP_8_HI               0x30d
#define GEN8_RBBM_PERFCTR2_SP_9_LO               0x30e
#define GEN8_RBBM_PERFCTR2_SP_9_HI               0x30f
#define GEN8_RBBM_PERFCTR2_SP_10_LO              0x310
#define GEN8_RBBM_PERFCTR2_SP_10_HI              0x311
#define GEN8_RBBM_PERFCTR2_SP_11_LO              0x312
#define GEN8_RBBM_PERFCTR2_SP_11_HI              0x313
#define GEN8_RBBM_PERFCTR2_TP_0_LO               0x314
#define GEN8_RBBM_PERFCTR2_TP_0_HI               0x315
#define GEN8_RBBM_PERFCTR2_TP_1_LO               0x316
#define GEN8_RBBM_PERFCTR2_TP_1_HI               0x317
#define GEN8_RBBM_PERFCTR2_TP_2_LO               0x318
#define GEN8_RBBM_PERFCTR2_TP_2_HI               0x319
#define GEN8_RBBM_PERFCTR2_TP_3_LO               0x31a
#define GEN8_RBBM_PERFCTR2_TP_3_HI               0x31b
#define GEN8_RBBM_PERFCTR2_TP_4_LO               0x31c
#define GEN8_RBBM_PERFCTR2_TP_4_HI               0x31d
#define GEN8_RBBM_PERFCTR2_TP_5_LO               0x31e
#define GEN8_RBBM_PERFCTR2_TP_5_HI               0x31f
#define GEN8_RBBM_PERFCTR2_TP_6_LO               0x320
#define GEN8_RBBM_PERFCTR2_TP_6_HI               0x321
#define GEN8_RBBM_PERFCTR2_TP_7_LO               0x322
#define GEN8_RBBM_PERFCTR2_TP_7_HI               0x323
#define GEN8_RBBM_PERFCTR2_UFC_0_LO              0x324
#define GEN8_RBBM_PERFCTR2_UFC_0_HI              0x325
#define GEN8_RBBM_PERFCTR2_UFC_1_LO              0x326
#define GEN8_RBBM_PERFCTR2_UFC_1_HI              0x327
#define GEN8_RBBM_PERFCTR_BV_PC_0_LO             0x328
#define GEN8_RBBM_PERFCTR_BV_PC_0_HI             0x329
#define GEN8_RBBM_PERFCTR_BV_PC_1_LO             0x32a
#define GEN8_RBBM_PERFCTR_BV_PC_1_HI             0x32b
#define GEN8_RBBM_PERFCTR_BV_PC_2_LO             0x32c
#define GEN8_RBBM_PERFCTR_BV_PC_2_HI             0x32d
#define GEN8_RBBM_PERFCTR_BV_PC_3_LO             0x32e
#define GEN8_RBBM_PERFCTR_BV_PC_3_HI             0x32f
#define GEN8_RBBM_PERFCTR_BV_PC_4_LO             0x330
#define GEN8_RBBM_PERFCTR_BV_PC_4_HI             0x331
#define GEN8_RBBM_PERFCTR_BV_PC_5_LO             0x332
#define GEN8_RBBM_PERFCTR_BV_PC_5_HI             0x333
#define GEN8_RBBM_PERFCTR_BV_PC_6_LO             0x334
#define GEN8_RBBM_PERFCTR_BV_PC_6_HI             0x335
#define GEN8_RBBM_PERFCTR_BV_PC_7_LO             0x336
#define GEN8_RBBM_PERFCTR_BV_PC_7_HI             0x337
#define GEN8_RBBM_PERFCTR_BV_VFD_0_LO            0x338
#define GEN8_RBBM_PERFCTR_BV_VFD_0_HI            0x339
#define GEN8_RBBM_PERFCTR_BV_VFD_1_LO            0x33a
#define GEN8_RBBM_PERFCTR_BV_VFD_1_HI            0x33b
#define GEN8_RBBM_PERFCTR_BV_VFD_2_LO            0x33c
#define GEN8_RBBM_PERFCTR_BV_VFD_2_HI            0x33d
#define GEN8_RBBM_PERFCTR_BV_VFD_3_LO            0x33e
#define GEN8_RBBM_PERFCTR_BV_VFD_3_HI            0x33f
#define GEN8_RBBM_PERFCTR_BV_VFD_4_LO            0x340
#define GEN8_RBBM_PERFCTR_BV_VFD_4_HI            0x341
#define GEN8_RBBM_PERFCTR_BV_VFD_5_LO            0x342
#define GEN8_RBBM_PERFCTR_BV_VFD_5_HI            0x343
#define GEN8_RBBM_PERFCTR_BV_VFD_6_LO            0x344
#define GEN8_RBBM_PERFCTR_BV_VFD_6_HI            0x345
#define GEN8_RBBM_PERFCTR_BV_VFD_7_LO            0x346
#define GEN8_RBBM_PERFCTR_BV_VFD_7_HI            0x347
#define GEN8_RBBM_PERFCTR_BV_VPC_0_LO            0x348
#define GEN8_RBBM_PERFCTR_BV_VPC_0_HI            0x349
#define GEN8_RBBM_PERFCTR_BV_VPC_1_LO            0x34a
#define GEN8_RBBM_PERFCTR_BV_VPC_1_HI            0x34b
#define GEN8_RBBM_PERFCTR_BV_VPC_2_LO            0x34c
#define GEN8_RBBM_PERFCTR_BV_VPC_2_HI            0x34d
#define GEN8_RBBM_PERFCTR_BV_VPC_3_LO            0x34e
#define GEN8_RBBM_PERFCTR_BV_VPC_3_HI            0x34f
#define GEN8_RBBM_PERFCTR_BV_VPC_4_LO            0x350
#define GEN8_RBBM_PERFCTR_BV_VPC_4_HI            0x351
#define GEN8_RBBM_PERFCTR_BV_VPC_5_LO            0x352
#define GEN8_RBBM_PERFCTR_BV_VPC_5_HI            0x353
#define GEN8_RBBM_PERFCTR_BV_TSE_0_LO            0x354
#define GEN8_RBBM_PERFCTR_BV_TSE_0_HI            0x355
#define GEN8_RBBM_PERFCTR_BV_TSE_1_LO            0x356
#define GEN8_RBBM_PERFCTR_BV_TSE_1_HI            0x357
#define GEN8_RBBM_PERFCTR_BV_TSE_2_LO            0x358
#define GEN8_RBBM_PERFCTR_BV_TSE_2_HI            0x359
#define GEN8_RBBM_PERFCTR_BV_TSE_3_LO            0x35a
#define GEN8_RBBM_PERFCTR_BV_TSE_3_HI            0x35b
#define GEN8_RBBM_PERFCTR_BV_RAS_0_LO            0x35c
#define GEN8_RBBM_PERFCTR_BV_RAS_0_HI            0x35d
#define GEN8_RBBM_PERFCTR_BV_RAS_1_LO            0x35e
#define GEN8_RBBM_PERFCTR_BV_RAS_1_HI            0x35f
#define GEN8_RBBM_PERFCTR_BV_RAS_2_LO            0x360
#define GEN8_RBBM_PERFCTR_BV_RAS_2_HI            0x361
#define GEN8_RBBM_PERFCTR_BV_RAS_3_LO            0x362
#define GEN8_RBBM_PERFCTR_BV_RAS_3_HI            0x363
#define GEN8_RBBM_PERFCTR_BV_LRZ_0_LO            0x364
#define GEN8_RBBM_PERFCTR_BV_LRZ_0_HI            0x365
#define GEN8_RBBM_PERFCTR_BV_LRZ_1_LO            0x366
#define GEN8_RBBM_PERFCTR_BV_LRZ_1_HI            0x367
#define GEN8_RBBM_PERFCTR_BV_LRZ_2_LO            0x368
#define GEN8_RBBM_PERFCTR_BV_LRZ_2_HI            0x369
#define GEN8_RBBM_PERFCTR_BV_LRZ_3_LO            0x36a
#define GEN8_RBBM_PERFCTR_BV_LRZ_3_HI            0x36b

#define GEN8_RBBM_NC_MODE_CNTL                   0x440
#define GEN8_RBBM_PERFCTR_RBBM_SEL_0             0x441
#define GEN8_RBBM_PERFCTR_RBBM_SEL_1             0x442
#define GEN8_RBBM_PERFCTR_RBBM_SEL_2             0x443
#define GEN8_RBBM_PERFCTR_RBBM_SEL_3             0x444

#define GEN8_RBBM_PERFCTR_SRAM_INIT_CMD          0x449
#define GEN8_RBBM_PERFCTR_FLUSH_HOST_CMD         0x44c
#define GEN8_RBBM_PERFCTR_CNTL                   0x460

/* GPU Slice registers */
#define GEN8_RBBM_SLICE_PERFCTR_CNTL              0x500
#define GEN8_RBBM_SLICE_INTERFACE_HANG_INT_CNTL   0x58f
#define GEN8_RBBM_SLICE_PERFCTR_RBBM_SEL_0        0x5e0
#define GEN8_RBBM_SLICE_PERFCTR_RBBM_SEL_1        0x5e1
#define GEN8_RBBM_SLICE_PERFCTR_RBBM_SEL_2        0x5e2
#define GEN8_RBBM_SLICE_PERFCTR_RBBM_SEL_3        0x5e3
#define GEN8_RBBM_SLICE_PERFCTR_SRAM_INIT_CMD     0x5e8
#define GEN8_RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD    0x5eb
#define GEN8_RBBM_SLICE_NC_MODE_CNTL              0x5ec
#define GEN8_VSC_BIN_SIZE                         0xc02
#define GEN8_VSC_KMD_DBG_ECO_CNTL                 0xdf0

/* DBGC_CFG registers */
#define GEN8_DBGC_CFG_DBGBUS_SEL_A               0x600
#define GEN8_DBGC_CFG_DBGBUS_SEL_B               0x601
#define GEN8_DBGC_CFG_DBGBUS_SEL_C               0x602
#define GEN8_DBGC_CFG_DBGBUS_SEL_D               0x603
#define GEN8_DBGC_CFG_DBGBUS_CNTLT               0x604
#define GEN8_DBGC_CFG_DBGBUS_CNTLM               0x605
#define GEN8_DBGC_CFG_DBGBUS_OPL                 0x606
#define GEN8_DBGC_CFG_DBGBUS_OPE                 0x607
#define GEN8_DBGC_CFG_DBGBUS_IVTL_0              0x608
#define GEN8_DBGC_CFG_DBGBUS_IVTL_1              0x609
#define GEN8_DBGC_CFG_DBGBUS_IVTL_2              0x60a
#define GEN8_DBGC_CFG_DBGBUS_IVTL_3              0x60b
#define GEN8_DBGC_CFG_DBGBUS_MASKL_0             0x60c
#define GEN8_DBGC_CFG_DBGBUS_MASKL_1             0x60d
#define GEN8_DBGC_CFG_DBGBUS_MASKL_2             0x60e
#define GEN8_DBGC_CFG_DBGBUS_MASKL_3             0x60f
#define GEN8_DBGC_CFG_DBGBUS_BYTEL_0             0x610
#define GEN8_DBGC_CFG_DBGBUS_BYTEL_1             0x611
#define GEN8_DBGC_CFG_DBGBUS_IVTE_0              0x612
#define GEN8_DBGC_CFG_DBGBUS_IVTE_1              0x613
#define GEN8_DBGC_CFG_DBGBUS_IVTE_2              0x614
#define GEN8_DBGC_CFG_DBGBUS_IVTE_3              0x615
#define GEN8_DBGC_CFG_DBGBUS_MASKE_0             0x616
#define GEN8_DBGC_CFG_DBGBUS_MASKE_1             0x617
#define GEN8_DBGC_CFG_DBGBUS_MASKE_2             0x618
#define GEN8_DBGC_CFG_DBGBUS_MASKE_3             0x619
#define GEN8_DBGC_CFG_DBGBUS_NIBBLEE             0x61a
#define GEN8_DBGC_CFG_DBGBUS_PTRC0               0x61b
#define GEN8_DBGC_CFG_DBGBUS_PTRC1               0x61c
#define GEN8_DBGC_CFG_DBGBUS_LOADREG             0x61d
#define GEN8_DBGC_CFG_DBGBUS_IDX                 0x61e
#define GEN8_DBGC_CFG_DBGBUS_CLRC                0x61f
#define GEN8_DBGC_CFG_DBGBUS_LOADIVT             0x620
#define GEN8_DBGC_VBIF_DBG_CNTL                  0x621
#define GEN8_DBGC_DBG_LO_HI_GPIO                 0x622
#define GEN8_DBGC_EXT_TRACE_BUS_CNTL             0x623
#define GEN8_DBGC_READ_AHB_THROUGH_DBG           0x624
#define GEN8_DBGC_CFG_DBGBUS_EVENT_LOGIC         0x625
#define GEN8_DBGC_CFG_DBGBUS_OVER                0x626
#define GEN8_DBGC_CFG_DBGBUS_COUNT0              0x627
#define GEN8_DBGC_CFG_DBGBUS_COUNT1              0x628
#define GEN8_DBGC_CFG_DBGBUS_COUNT2              0x629
#define GEN8_DBGC_CFG_DBGBUS_COUNT3              0x62a
#define GEN8_DBGC_CFG_DBGBUS_COUNT4              0x62b
#define GEN8_DBGC_CFG_DBGBUS_COUNT5              0x62c
#define GEN8_DBGC_CFG_DBGBUS_TRACE_ADDR          0x62d
#define GEN8_DBGC_CFG_DBGBUS_TRACE_BUF0          0x62e
#define GEN8_DBGC_CFG_DBGBUS_TRACE_BUF1          0x62f
#define GEN8_DBGC_CFG_DBGBUS_TRACE_BUF2          0x630
#define GEN8_DBGC_CFG_DBGBUS_TRACE_BUF3          0x631
#define GEN8_DBGC_CFG_DBGBUS_TRACE_BUF4          0x632
#define GEN8_DBGC_CFG_DBGBUS_MISR0               0x633
#define GEN8_DBGC_CFG_DBGBUS_MISR1               0x634
#define GEN8_DBGC_EVT_CFG                        0x635
#define GEN8_DBGC_EVT_INTF_SEL_0                 0x636 /* Indexed Register */
#define GEN8_DBGC_EVT_INTF_SEL_1                 0x637 /* Indexed Register */
#define GEN8_DBGC_EVT_SLICE_CFG                  0x638
#define GEN8_DBGC_QDSS_TIMESTAMP_0               0x639 /* Indexed Register */
#define GEN8_DBGC_QDSS_TIMESTAMP_1               0x63a /* Indexed Register */
#define GEN8_DBGC_ECO_CNTL                       0x63b
#define GEN8_DBGC_AHB_DBG_CNTL                   0x63c
#define GEN8_DBGC_EVT_INTF_SEL_2                 0x63d
#define GEN8_DBGC_CFG_DBGBUS_PONG_SEL_A          0x640
#define GEN8_DBGC_CFG_DBGBUS_PONG_SEL_B          0x641
#define GEN8_DBGC_CFG_DBGBUS_PONG_SEL_C          0x642
#define GEN8_DBGC_CFG_DBGBUS_PONG_SEL_D          0x643
#define GEN8_DBGC_CFG_DBGBUS_MISC_MODE           0x644
#define GEN8_DBGC_EVT_INTF_SEL_3_0               0x650 /* Indexed Register */
#define GEN8_DBGC_EVT_INTF_SEL_3_1               0x651 /* Indexed Register */
#define GEN8_DBGC_EVT_INTF_SEL_3_2               0x652 /* Indexed Register */
#define GEN8_DBGC_EVT_INTF_SEL_3_3               0x653 /* Indexed Register */
#define GEN8_DBGC_EVT_INTF_SEL_3_4               0x654 /* Indexed Register */
#define GEN8_DBGC_EVT_INTF_SEL_3_5               0x655 /* Indexed Register */
#define GEN8_DBGC_TRACE_BUFFER_STATUS            0x660
#define GEN8_DBGC_TRACE_BUFFER_CMD               0x661
#define GEN8_DBGC_DBG_TRACE_BUFFER_RD_ADDR       0x662
#define GEN8_DBGC_DBG_TRACE_BUFFER_RD_DATA       0x663
#define GEN8_DBGC_TRACE_BUFFER_ATB_RD_STATUS     0x664
#define GEN8_DBGC_SMMU_FAULT_BLOCK_HALT_CFG      0x665
#define GEN8_DBGC_DBG_LOPC_SB_RD_ADDR            0x666
#define GEN8_DBGC_DBG_LOPC_SB_RD_DATA            0x667
#define GEN8_DBGC_DBG_LOPC_SB_WR_ADDR            0x668
#define GEN8_DBGC_DBG_LOPC_SB_WR_DATA            0x669
#define GEN8_DBGC_INTERRUPT_STATUS               0x66a
#define GEN8_DBGC_GBIF_DBG_BASE_LO               0x680
#define GEN8_DBGC_GBIF_DBG_BASE_HI               0x681
#define GEN8_DBGC_GBIF_DBG_BUFF_SIZE             0x682
#define GEN8_DBGC_GBIF_DBG_CNTL                  0x683
#define GEN8_DBGC_GBIF_DBG_CMD                   0x684
#define GEN8_DBGC_GBIF_DBG_STATUS                0x685
#define GEN8_DBGC_SCOPE_PERF_COUNTER_CFG_US      0x700
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_FE_US    0x701
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_VPC_US   0x702
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS_US 0x703
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS_US 0x704
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_NONE_US  0x707
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_US 0x708
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_US 0x709
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS_US 0x70a
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_NONE_US 0x70f
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_FE_US     0x710
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_FE_US_1   0x711
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_FE_US_2   0x712
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_VPC_US    0x713
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_VPC_US_1  0x714
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_VS_US  0x715
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_PS_US  0x716
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_NONE_US   0x720
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_NONE_US_1 0x721
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US  0x722
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_1 0x723
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_2 0x724
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US 0x730
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US_1 0x731
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_US 0x732
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_NONE_US 0x740
#define GEN8_DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_US 0x742
#define GEN8_DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_US 0x743
#define GEN8_DBGC_CFG_GBIF_BR_PERF_CNTR_BASE_LO  0x744
#define GEN8_DBGC_CFG_GBIF_BR_PERF_CNTR_BASE_HI  0x745
#define GEN8_DBGC_CFG_GBIF_BR_BUFFER_SIZE        0x746
#define GEN8_DBGC_CFG_GBIF_BV_PERF_CNTR_BASE_LO  0x747
#define GEN8_DBGC_CFG_GBIF_BV_PERF_CNTR_BASE_HI  0x748
#define GEN8_DBGC_CFG_GBIF_BV_BUFFER_SIZE        0x749
#define GEN8_DBGC_CFG_GBIF_QOS_CTRL              0x74a
#define GEN8_DBGC_GBIF_BR_PERF_CNTR_WRITE_POINTER 0x750
#define GEN8_DBGC_GBIF_BV_PERF_CNTR_WRITE_POINTER 0x751
#define GEN8_DBGC_PERF_COUNTER_FE_LOCAL_BATCH_ID 0x752
#define GEN8_DBGC_CFG_PERF_WAIT_IDLE_CLOCKS_CNTL 0x753
#define GEN8_DBGC_PERF_COUNTER_SCOPING_CMD_US    0x754
#define GEN8_DBGC_PERF_SKEW_BUFFER_INIT_CMD      0x755
#define GEN8_DBGC_LOPC_INTERRUPT_STATUS          0x759
#define GEN8_DBGC_LOPC_BUFFER_PTR_STATUS         0x75a
#define GEN8_DBGC_PERF_SCOPING_STATUS            0x75b
#define GEN8_DBGC_PERF_COUNTER_PKT_STATUS        0x75c
#define GEN8_DBGC_GC_LIVE_MBX_PKT_STATUS         0x760
#define GEN8_DBGC_GC_ALW_MBX_PKT_STATUS          0x761
#define GEN8_DBGC_AO_CNTR_LO_STATUS              0x762
#define GEN8_DBGC_AO_CNTR_HI_STATUS              0x763
#define GEN8_DBGC_LOPC_GC_SB_DEPTH_STATUS        0x770
#define GEN8_DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_US 0x780
#define GEN8_DBGC_CFG_PERF_TRIG_LPAC_US          0x781
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_LPAC_US   0x782
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_1 0x783
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_2 0x784
#define GEN8_DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_US 0x785
#define GEN8_DBGC_CFG_GBIF_LPAC_PERF_CNTR_BASE_LO 0x786
#define GEN8_DBGC_CFG_GBIF_LPAC_PERF_CNTR_BASE_HI 0x787
#define GEN8_DBGC_CFG_GBIF_LPAC_BUFFER_SIZE      0x788
#define GEN8_DBGC_GBIF_LPAC_PERF_CNTR_WRITE_POINTER 0x789
#define GEN8_DBGC_CFG_LPAC_PERF_WAIT_IDLE_CLOCKS_CNTL 0x78a
#define GEN8_DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_US 0x78b
#define GEN8_DBGC_LPAC_MBX_PKT_STATUS            0x78c
#define GEN8_DBGC_LPAC_PERF_SCOPING_STATUS       0x78d
#define GEN8_DBGC_LOPC_LPAC_SB_DEPTH_STATUS      0x790
#define GEN8_DBGC_SCOPE_PERF_COUNTER_CFG_S       0x7a0
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_FE_S     0x7a1
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS    0x7a2
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_VPC_VS   0x7a3
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_GRAS     0x7a4
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS    0x7a5
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_VPC_PS   0x7a6
#define GEN8_DBGC_CFG_PERF_TRIG_CLUSTER_PS       0x7a7
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_S  0x7a8
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS 0x7a9
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_VS 0x7aa
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_GRAS  0x7ab
#define GEN8_DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_PS 0x7ac
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_FE_S      0x7ad
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_FE_S_1    0x7ae
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_FE_S_2    0x7af
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_FE_S_3    0x7b0
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_VS     0x7b1
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_VS_1   0x7b2
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_VS_2   0x7b3
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_VS_3   0x7b4
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_VPC_VS    0x7b5
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_VPC_VS_1  0x7b6
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_GRAS      0x7b7
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_GRAS_1    0x7b8
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_GRAS_2    0x7b9
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_PS     0x7ba
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_PS_1   0x7bb
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_PS_2   0x7bc
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_SP_PS_3   0x7bd
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_VPC_PS    0x7be
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_VPC_PS_1  0x7bf
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_PS        0x7c0
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_PS_1      0x7c1
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_PS_2      0x7c2
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_PS_3      0x7c3
#define GEN8_DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_S  0x7c4
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S   0x7c5
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_1 0x7c6
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_2 0x7c7
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_3 0x7c8
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS  0x7c9
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_1 0x7ca
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_2 0x7cb
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_3 0x7cc
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS 0x7cd
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS_1 0x7ce
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS   0x7cf
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_1 0x7d0
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_2 0x7d1
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS 0x7d2
#define GEN8_DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS_1 0x7d3
#define GEN8_DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_S 0x7d4
#define GEN8_DBGC_PERF_COUNTER_SCOPING_CMD_S     0x7d5
#define GEN8_DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_S  0x7e0
#define GEN8_DBGC_CFG_PERF_TRIG_LPAC_S           0x7e1
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_LPAC_S    0x7e2
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_1  0x7e3
#define GEN8_DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_2  0x7e4
#define GEN8_DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_S 0x7e5
#define GEN8_DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_S 0x7e6

/* VSC registers */
#define GEN8_VSC_PERFCTR_VSC_SEL_0          0xcd8
#define GEN8_VSC_PERFCTR_VSC_SEL_1          0xcd9

/* CP registers */
#define GEN8_CP_RB_BASE_LO_GC                                  0x800
#define GEN8_CP_RB_BASE_HI_GC                                  0x801
#define GEN8_CP_RB_CNTL_GC                                     0x802
#define GEN8_CP_RB_RPTR_WR_GC                                  0x803
#define GEN8_CP_RB_RPTR_ADDR_LO_BR                             0x804
#define GEN8_CP_RB_RPTR_ADDR_HI_BR                             0x805
#define GEN8_CP_RB_RPTR_BR                                     0x806
#define GEN8_CP_RB_WPTR_GC                                     0x807
#define GEN8_CP_RB_RPTR_ADDR_LO_BV                             0x808
#define GEN8_CP_RB_RPTR_ADDR_HI_BV                             0x809
#define GEN8_CP_RB_RPTR_BV                                     0x80a
#define GEN8_CP_RB_BASE_LO_LPAC                                0x80b
#define GEN8_CP_RB_BASE_HI_LPAC                                0x80c
#define GEN8_CP_RB_CNTL_LPAC                                   0x80d
#define GEN8_CP_RB_RPTR_WR_LPAC                                0x80e
#define GEN8_CP_RB_RPTR_ADDR_LO_LPAC                           0x80f
#define GEN8_CP_RB_RPTR_ADDR_HI_LPAC                           0x810
#define GEN8_CP_RB_RPTR_LPAC                                   0x811
#define GEN8_CP_RB_WPTR_LPAC                                   0x812
#define GEN8_CP_SMMU_STREAM_ID_LPAC                            0x814
#define GEN8_CP_SQE_CNTL                                       0x815
#define GEN8_CP_SQE_INSTR_BASE_LO                              0x816
#define GEN8_CP_SQE_INSTR_BASE_HI                              0x817
#define GEN8_CP_AQE_INSTR_BASE_LO_0                            0x818
#define GEN8_CP_AQE_INSTR_BASE_HI_0                            0x819
#define GEN8_CP_AQE_INSTR_BASE_LO_1                            0x81a
#define GEN8_CP_AQE_INSTR_BASE_HI_1                            0x81b
#define GEN8_CP_APERTURE_CNTL_HOST                             0x81c
#define GEN8_CP_APERTURE_CNTL_GMU                              0x81d
#define GEN8_CP_APERTURE_CNTL_CD                               0x81e
#define GEN8_CP_CP2GMU_STATUS                                  0x822
#define GEN8_CP_RL_ERROR_DETAILS_0                             0x840
#define GEN8_CP_RL_ERROR_DETAILS_1                             0x841
#define GEN8_CP_CRASH_DUMP_SCRIPT_BASE_LO                      0x842
#define GEN8_CP_CRASH_DUMP_SCRIPT_BASE_HI                      0x843
#define GEN8_CP_CRASH_DUMP_CNTL                                0x844
#define GEN8_CP_CRASH_DUMP_STATUS                              0x845
#define GEN8_CP_DBG_ECO_CNTL                                   0x84b
#define GEN8_CP_MISC_CNTL                                      0x84c
#define GEN8_CP_APRIV_CNTL_PIPE                                0x84d
#define GEN8_CP_PROTECT_CNTL_PIPE                              0x84e
#define GEN8_CP_PROTECT_STATUS_PIPE                            0x84f
#define GEN8_CP_PROTECT_REG_GLOBAL                             0x850
#define GEN8_CP_PROTECT_REG_PIPE                               0x8a0

#define GEN8_CP_SQE_ICACHE_CNTL_PIPE                           0x8b0
#define GEN8_CP_SQE_DCACHE_CNTL_PIPE                           0x8b1
#define GEN8_CP_CHICKEN_DBG_PIPE                               0x8b2
#define GEN8_CP_HW_FAULT_STATUS_PIPE                           0x8b3
#define GEN8_CP_HW_FAULT_STATUS_MASK_PIPE                      0x8b4
#define GEN8_CP_INTERRUPT_STATUS_GLOBAL                        0x8b5
#define GEN8_CP_INTERRUPT_STATUS_MASK_GLOBAL                   0x8b6
#define GEN8_CP_INTERRUPT_STATUS_PIPE                          0x8b7
#define GEN8_CP_INTERRUPT_STATUS_MASK_PIPE                     0x8b8
#define GEN8_CP_PIPE_STATUS_PIPE                               0x8b9
#define GEN8_CP_GPU_BATCH_ID_PIPE                              0x8ba
#define GEN8_CP_SQE_STATUS_PIPE                                0x8bb
#define GEN8_CP_CONTEXT_SWITCH_CNTL                            0x8c0
#define GEN8_CP_CONTEXT_SWITCH_SMMU_INFO_LO                    0x8c1
#define GEN8_CP_CONTEXT_SWITCH_SMMU_INFO_HI                    0x8c2
#define GEN8_CP_CONTEXT_SWITCH_PNSR_ADDR_LO                    0x8c3
#define GEN8_CP_CONTEXT_SWITCH_PNSR_ADDR_HI                    0x8c4
#define GEN8_CP_CONTEXT_SWITCH_PSR_ADDR_LO                     0x8c5
#define GEN8_CP_CONTEXT_SWITCH_PSR_ADDR_HI                     0x8c6
#define GEN8_CP_CONTEXT_SWITCH_NPR_ADDR_LO                     0x8c7
#define GEN8_CP_CONTEXT_SWITCH_NPR_ADDR_HI                     0x8c8
#define GEN8_CP_CONTEXT_SWITCH_LEVEL_STATUS                    0x8cb
#define GEN8_CP_PERFCTR_CP_SEL_0                               0x8d0
#define GEN8_CP_PERFCTR_CP_SEL_1                               0x8d1
#define GEN8_CP_PERFCTR_CP_SEL_2                               0x8d2
#define GEN8_CP_PERFCTR_CP_SEL_3                               0x8d3
#define GEN8_CP_PERFCTR_CP_SEL_4                               0x8d4
#define GEN8_CP_PERFCTR_CP_SEL_5                               0x8d5
#define GEN8_CP_PERFCTR_CP_SEL_6                               0x8d6
#define GEN8_CP_PERFCTR_CP_SEL_7                               0x8d7
#define GEN8_CP_PERFCTR_CP_SEL_8                               0x8d8
#define GEN8_CP_PERFCTR_CP_SEL_9                               0x8d9
#define GEN8_CP_PERFCTR_CP_SEL_10                              0x8da
#define GEN8_CP_PERFCTR_CP_SEL_11                              0x8db
#define GEN8_CP_PERFCTR_CP_SEL_12                              0x8dc
#define GEN8_CP_PERFCTR_CP_SEL_13                              0x8dd
#define GEN8_CP_PERFCTR_CP_SEL_14                              0x8de
#define GEN8_CP_PERFCTR_CP_SEL_15                              0x8df
#define GEN8_CP_PERFCTR_CP_SEL_16                              0x8e0
#define GEN8_CP_PERFCTR_CP_SEL_17                              0x8e1
#define GEN8_CP_PERFCTR_CP_SEL_18                              0x8e2
#define GEN8_CP_PERFCTR_CP_SEL_19                              0x8e3
#define GEN8_CP_PERFCTR_CP_SEL_20                              0x8e4
#define GEN8_CP_ALWAYS_ON_COUNTER_LO                           0x8e7
#define GEN8_CP_ALWAYS_ON_COUNTER_HI                           0x8e8
#define GEN8_CP_ALWAYS_ON_CONTEXT_LO                           0x8e9
#define GEN8_CP_ALWAYS_ON_CONTEXT_HI                           0x8ea
#define GEN8_CP_SQE_STAT_ADDR_PIPE                             0x8f0
#define GEN8_CP_SQE_STAT_DATA_PIPE                             0x8f1
#define GEN8_CP_DRAW_STATE_ADDR_PIPE                           0x8f2
#define GEN8_CP_DRAW_STATE_DATA_PIPE                           0x8f3
#define GEN8_CP_ROQ_DBG_ADDR_PIPE                              0x8f4
#define GEN8_CP_ROQ_DBG_DATA_PIPE                              0x8f5
#define GEN8_CP_MEM_POOL_DBG_ADDR_PIPE                         0x8f6
#define GEN8_CP_MEM_POOL_DBG_DATA_PIPE                         0x8f7
#define GEN8_CP_SQE_UCODE_DBG_ADDR_PIPE                        0x8f8
#define GEN8_CP_SQE_UCODE_DBG_DATA_PIPE                        0x8f9
#define GEN8_CP_RESOURCE_TABLE_DBG_ADDR_BV                     0x8fa
#define GEN8_CP_RESOURCE_TABLE_DBG_DATA_BV                     0x8fb
#define GEN8_CP_FIFO_DBG_ADDR_LPAC                             0x8fc
#define GEN8_CP_FIFO_DBG_DATA_LPAC                             0x8fd
#define GEN8_CP_FIFO_DBG_ADDR_DDE_PIPE                         0x8fe
#define GEN8_CP_FIFO_DBG_DATA_DDE_PIPE                         0x8ff
#define GEN8_CP_IB1_BASE_LO_PIPE                               0x900
#define GEN8_CP_IB1_BASE_HI_PIPE                               0x901
#define GEN8_CP_IB1_REM_SIZE_PIPE                              0x902
#define GEN8_CP_IB1_INIT_SIZE_PIPE                             0x903
#define GEN8_CP_IB2_BASE_LO_PIPE                               0x904
#define GEN8_CP_IB2_BASE_HI_PIPE                               0x905
#define GEN8_CP_IB2_REM_SIZE_PIPE                              0x906
#define GEN8_CP_IB2_INIT_SIZE_PIPE                             0x907
#define GEN8_CP_IB3_BASE_LO_PIPE                               0x908
#define GEN8_CP_IB3_BASE_HI_PIPE                               0x909
#define GEN8_CP_IB3_REM_SIZE_PIPE                              0x90a
#define GEN8_CP_IB3_INIT_SIZE_PIPE                             0x90b
#define GEN8_CP_SDS_BASE_LO_PIPE                               0x90c
#define GEN8_CP_SDS_BASE_HI_PIPE                               0x90d
#define GEN8_CP_SDS_REM_SIZE_PIPE                              0x90e
#define GEN8_CP_SDS_INIT_SIZE_PIPE                             0x90f
#define GEN8_CP_MRB_BASE_LO_PIPE                               0x910
#define GEN8_CP_MRB_BASE_HI_PIPE                               0x911
#define GEN8_CP_MRB_REM_SIZE_PIPE                              0x912
#define GEN8_CP_MRB_INIT_SIZE_PIPE                             0x913
#define GEN8_CP_VSD_BASE_LO_PIPE                               0x914
#define GEN8_CP_VSD_BASE_HI_PIPE                               0x915
#define GEN8_CP_VSD_REM_SIZE_PIPE                              0x916
#define GEN8_CP_VSD_INIT_SIZE_PIPE                             0x917
#define GEN8_CP_ROQ_AVAIL_RB_PIPE                              0x918
#define GEN8_CP_ROQ_AVAIL_IB1_PIPE                             0x919
#define GEN8_CP_ROQ_AVAIL_IB2_PIPE                             0x91a
#define GEN8_CP_ROQ_AVAIL_IB3_PIPE                             0x91b
#define GEN8_CP_ROQ_AVAIL_SDS_PIPE                             0x91c
#define GEN8_CP_ROQ_AVAIL_MRB_PIPE                             0x91d
#define GEN8_CP_ROQ_AVAIL_VSD_PIPE                             0x91e
#define GEN8_CP_ROQ_RB_STATUS_PIPE                             0x920
#define GEN8_CP_ROQ_IB1_STATUS_PIPE                            0x921
#define GEN8_CP_ROQ_IB2_STATUS_PIPE                            0x922
#define GEN8_CP_ROQ_IB3_STATUS_PIPE                            0x923
#define GEN8_CP_ROQ_SDS_STATUS_PIPE                            0x924
#define GEN8_CP_ROQ_MRB_STATUS_PIPE                            0x925
#define GEN8_CP_ROQ_VSD_STATUS_PIPE                            0x926
#define GEN8_CP_SLICE_MEM_POOL_DBG_ADDR_PIPE                   0xb00
#define GEN8_CP_SLICE_MEM_POOL_DBG_DATA_PIPE                   0xb01
#define GEN8_CP_SLICE_CHICKEN_DBG_PIPE                         0xb93

/* UCHE registers */
#define GEN8_UCHE_MODE_CNTL                 0xe01
#define GEN8_UCHE_CACHE_WAYS                0xe04
#define GEN8_UCHE_WRITE_THRU_BASE_LO        0xe06
#define GEN8_UCHE_WRITE_THRU_BASE_HI        0xe07
#define GEN8_UCHE_TRAP_BASE_LO              0xe08
#define GEN8_UCHE_TRAP_BASE_HI              0xe09
#define GEN8_UCHE_VARB_IDLE_TIMEOUT         0xe10
#define GEN8_UCHE_CLIENT_PF                 0xe11
#define GEN8_UCHE_GBIF_GX_CONFIG            0xe12
#define GEN8_UCHE_DBG_ECO_CNTL_0            0xe15
#define GEN8_UCHE_HW_DBG_CNTL               0xe16
#define GEN8_UCHE_PERFCTR_UCHE_SEL_0        0xe20
#define GEN8_UCHE_PERFCTR_UCHE_SEL_1        0xe21
#define GEN8_UCHE_PERFCTR_UCHE_SEL_2        0xe22
#define GEN8_UCHE_PERFCTR_UCHE_SEL_3        0xe23
#define GEN8_UCHE_PERFCTR_UCHE_SEL_4        0xe24
#define GEN8_UCHE_PERFCTR_UCHE_SEL_5        0xe25
#define GEN8_UCHE_PERFCTR_UCHE_SEL_6        0xe26
#define GEN8_UCHE_PERFCTR_UCHE_SEL_7        0xe27
#define GEN8_UCHE_PERFCTR_UCHE_SEL_8        0xe28
#define GEN8_UCHE_PERFCTR_UCHE_SEL_9        0xe29
#define GEN8_UCHE_PERFCTR_UCHE_SEL_10       0xe2a
#define GEN8_UCHE_PERFCTR_UCHE_SEL_11       0xe2b
#define GEN8_UCHE_PERFCTR_UCHE_SEL_12       0xe2c
#define GEN8_UCHE_PERFCTR_UCHE_SEL_13       0xe2d
#define GEN8_UCHE_PERFCTR_UCHE_SEL_14       0xe2e
#define GEN8_UCHE_PERFCTR_UCHE_SEL_15       0xe2f
#define GEN8_UCHE_PERFCTR_UCHE_SEL_16       0xe30
#define GEN8_UCHE_PERFCTR_UCHE_SEL_17       0xe31
#define GEN8_UCHE_PERFCTR_UCHE_SEL_18       0xe32
#define GEN8_UCHE_PERFCTR_UCHE_SEL_19       0xe33
#define GEN8_UCHE_PERFCTR_UCHE_SEL_20       0xe34
#define GEN8_UCHE_PERFCTR_UCHE_SEL_21       0xe35
#define GEN8_UCHE_PERFCTR_UCHE_SEL_22       0xe36
#define GEN8_UCHE_PERFCTR_UCHE_SEL_23       0xe37

/* UCHE CCHE registers */
#define GEN8_UCHE_CCHE_MODE_CNTL                 0xf01
#define GEN8_UCHE_CCHE_CACHE_WAYS                0xf02
#define GEN8_UCHE_CCHE_WRITE_THRU_BASE_LO        0xf04
#define GEN8_UCHE_CCHE_WRITE_THRU_BASE_HI        0xf05
#define GEN8_UCHE_CCHE_TRAP_BASE_LO              0xf06
#define GEN8_UCHE_CCHE_TRAP_BASE_HI              0xf07
#define GEN8_UCHE_CCHE_GC_GMEM_RANGE_MIN_LO      0xf08
#define GEN8_UCHE_CCHE_GC_GMEM_RANGE_MIN_HI      0xf09
#define GEN8_UCHE_CCHE_LPAC_GMEM_RANGE_MIN_LO    0xf0a
#define GEN8_UCHE_CCHE_LPAC_GMEM_RANGE_MIN_HI    0xf0b
#define GEN8_UCHE_CCHE_HW_DBG_CNTL               0xf0c

#define GEN8_GBIF_CX_CONFIG                 0x3c00

/* GRAS registers */
#define GEN8_GRAS_TSEFE_DBG_ECO_CNTL        0x8600
#define GEN8_GRAS_PERFCTR_TSEFE_SEL_0       0x8610
#define GEN8_GRAS_PERFCTR_TSEFE_SEL_1       0x8611
#define GEN8_GRAS_PERFCTR_TSEFE_SEL_2       0x8612
#define GEN8_GRAS_PERFCTR_TSEFE_SEL_3       0x8613
#define GEN8_GRAS_NC_MODE_CNTL              0x8700
#define GEN8_GRAS_DBG_ECO_CNTL              0x8702
#define GEN8_GRAS_PERFCTR_TSE_SEL_0         0x8710
#define GEN8_GRAS_PERFCTR_TSE_SEL_1         0x8711
#define GEN8_GRAS_PERFCTR_TSE_SEL_2         0x8712
#define GEN8_GRAS_PERFCTR_TSE_SEL_3         0x8713
#define GEN8_GRAS_PERFCTR_RAS_SEL_0         0x8720
#define GEN8_GRAS_PERFCTR_RAS_SEL_1         0x8721
#define GEN8_GRAS_PERFCTR_RAS_SEL_2         0x8722
#define GEN8_GRAS_PERFCTR_RAS_SEL_3         0x8723
#define GEN8_GRAS_PERFCTR_LRZ_SEL_0         0x8730
#define GEN8_GRAS_PERFCTR_LRZ_SEL_1         0x8731
#define GEN8_GRAS_PERFCTR_LRZ_SEL_2         0x8732
#define GEN8_GRAS_PERFCTR_LRZ_SEL_3         0x8733

/* RB registers */
#define GEN8_RB_DBG_ECO_CNTL                0x8e04
#define GEN8_RB_CCU_DBG_ECO_CNTL            0x8e06
#define GEN8_RB_CCU_CNTL                    0x8e07
#define GEN8_RB_CCU_NC_MODE_CNTL            0x8e08
#define GEN8_RB_GC_GMEM_PROTECT             0x8e09
#define GEN8_RB_LPAC_GMEM_PROTECT           0x8e0a
#define GEN8_RB_PERFCTR_RB_SEL_0            0x8e10
#define GEN8_RB_PERFCTR_RB_SEL_1            0x8e11
#define GEN8_RB_PERFCTR_RB_SEL_2            0x8e12
#define GEN8_RB_PERFCTR_RB_SEL_3            0x8e13
#define GEN8_RB_PERFCTR_RB_SEL_4            0x8e14
#define GEN8_RB_PERFCTR_RB_SEL_5            0x8e15
#define GEN8_RB_PERFCTR_RB_SEL_6            0x8e16
#define GEN8_RB_PERFCTR_RB_SEL_7            0x8e17
#define GEN8_RB_PERFCTR_CCU_SEL_0           0x8e18
#define GEN8_RB_PERFCTR_CCU_SEL_1           0x8e19
#define GEN8_RB_PERFCTR_CCU_SEL_2           0x8e1a
#define GEN8_RB_PERFCTR_CCU_SEL_3           0x8e1b
#define GEN8_RB_PERFCTR_CCU_SEL_4           0x8e1c
#define GEN8_RB_SUB_BLOCK_SEL_CNTL_HOST     0x8e3b
#define GEN8_RB_SUB_BLOCK_SEL_CNTL_CD       0x8e3d
#define GEN8_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x8e50
#define GEN8_RB_SLICE_UFC_PREFETCH_CNTL     0x8e77
#define GEN8_RB_SLICE_UFC_DBG_CNTL          0x8e78
#define GEN8_RB_CMP_NC_MODE_CNTL            0x8f00
#define GEN8_RB_RESOLVE_PREFETCH_CNTL       0x8f01
#define GEN8_RB_CMP_DBG_ECO_CNTL            0x8f02
#define GEN8_RB_UNSLICE_STATUS              0x8f03
#define GEN8_RB_PERFCTR_CMP_SEL_0           0x8f04
#define GEN8_RB_PERFCTR_CMP_SEL_1           0x8f05
#define GEN8_RB_PERFCTR_CMP_SEL_2           0x8f06
#define GEN8_RB_PERFCTR_CMP_SEL_3           0x8f07
#define GEN8_RB_PERFCTR_UFC_SEL_0           0x8f10
#define GEN8_RB_PERFCTR_UFC_SEL_1           0x8f11
#define GEN8_RB_PERFCTR_UFC_SEL_2           0x8f12
#define GEN8_RB_PERFCTR_UFC_SEL_3           0x8f13
#define GEN8_RB_PERFCTR_UFC_SEL_4           0x8f14
#define GEN8_RB_PERFCTR_UFC_SEL_5           0x8f15
#define GEN8_RB_UFC_DBG_CNTL                0x8f29

/* VPC registers */
#define GEN8_VPC_DBG_ECO_CNTL_2                  0x9604
#define GEN8_VPC_PERFCTR_VPC_SEL_2_0             0x9670
#define GEN8_VPC_PERFCTR_VPC_SEL_2_1             0x9671
#define GEN8_VPC_PERFCTR_VPC_SEL_2_2             0x9672
#define GEN8_VPC_PERFCTR_VPC_SEL_2_3             0x9673
#define GEN8_VPC_PERFCTR_VPC_SEL_2_4             0x9674
#define GEN8_VPC_PERFCTR_VPC_SEL_2_5             0x9675
#define GEN8_VPC_PERFCTR_VPC_SEL_2_6             0x9676
#define GEN8_VPC_PERFCTR_VPC_SEL_2_7             0x9677
#define GEN8_VPC_PERFCTR_VPC_SEL_2_8             0x9678
#define GEN8_VPC_PERFCTR_VPC_SEL_2_9             0x9679
#define GEN8_VPC_PERFCTR_VPC_SEL_2_10            0x967a
#define GEN8_VPC_PERFCTR_VPC_SEL_2_11            0x967b
#define GEN8_VPC_DBG_ECO_CNTL                    0x9680
#define GEN8_VPC_PERFCTR_VPC_SEL_0               0x9690 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_1               0x9691 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_2               0x9692 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_3               0x9693 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_4               0x9694 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_5               0x9695 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_6               0x9696 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_7               0x9697 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_8               0x9698 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_9               0x9699 /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_10              0x969a /* Indexed Register */
#define GEN8_VPC_PERFCTR_VPC_SEL_11              0x969b /* Indexed Register */
#define GEN8_VPC_LB_MODE_CNTL                    0x9740
#define GEN8_VPC_FLATSHADE_MODE_CNTL             0x9741
#define GEN8_VPC_DBG_ECO_CNTL_1                  0x9742
#define GEN8_VPC_DBG_ECO_CNTL_3                  0x9745
#define GEN8_VPC_PERFCTR_VPC_SEL_1_0             0x9750
#define GEN8_VPC_PERFCTR_VPC_SEL_1_1             0x9751
#define GEN8_VPC_PERFCTR_VPC_SEL_1_2             0x9752
#define GEN8_VPC_PERFCTR_VPC_SEL_1_3             0x9753
#define GEN8_VPC_PERFCTR_VPC_SEL_1_4             0x9754
#define GEN8_VPC_PERFCTR_VPC_SEL_1_5             0x9755
#define GEN8_VPC_PERFCTR_VPC_SEL_1_6             0x9756
#define GEN8_VPC_PERFCTR_VPC_SEL_1_7             0x9757
#define GEN8_VPC_PERFCTR_VPC_SEL_1_8             0x9758
#define GEN8_VPC_PERFCTR_VPC_SEL_1_9             0x9759
#define GEN8_VPC_PERFCTR_VPC_SEL_1_10            0x975a
#define GEN8_VPC_PERFCTR_VPC_SEL_1_11            0x975b

/* PC registers:*/
#define GEN8_PC_AUTO_VERTEX_STRIDE          0x9e0a
#define GEN8_PC_VIS_STREAM_CNTL             0x9e0d
#define GEN8_PC_CHICKEN_BITS_3              0x9e22
#define GEN8_PC_CHICKEN_BITS_4              0x9e23
#define GEN8_PC_PERFCTR_PC_SEL_0            0x9e30
#define GEN8_PC_PERFCTR_PC_SEL_1            0x9e31
#define GEN8_PC_PERFCTR_PC_SEL_2            0x9e32
#define GEN8_PC_PERFCTR_PC_SEL_3            0x9e33
#define GEN8_PC_PERFCTR_PC_SEL_4            0x9e34
#define GEN8_PC_PERFCTR_PC_SEL_5            0x9e35
#define GEN8_PC_PERFCTR_PC_SEL_6            0x9e36
#define GEN8_PC_PERFCTR_PC_SEL_7            0x9e37
#define GEN8_PC_PERFCTR_PC_SEL_8            0x9e38
#define GEN8_PC_PERFCTR_PC_SEL_9            0x9e39
#define GEN8_PC_PERFCTR_PC_SEL_10           0x9e3a
#define GEN8_PC_PERFCTR_PC_SEL_11           0x9e3b
#define GEN8_PC_PERFCTR_PC_SEL_12           0x9e3c
#define GEN8_PC_PERFCTR_PC_SEL_13           0x9e3d
#define GEN8_PC_PERFCTR_PC_SEL_14           0x9e3e
#define GEN8_PC_PERFCTR_PC_SEL_15           0x9e3f
#define GEN8_PC_CHICKEN_BITS_1              0x9e50
#define GEN8_PC_DBG_ECO_CNTL                0x9e53
#define GEN8_PC_CHICKEN_BITS_2              0x9f20
#define GEN8_PC_CHICKEN_BITS_5              0x9f23

#define GEN8_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1 0x9e64
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_0      0x9f00
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_1      0x9f01
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_2      0x9f02
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_3      0x9f03
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_4      0x9f04
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_5      0x9f05
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_6      0x9f06
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_7      0x9f07
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_8      0x9f08
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_9      0x9f09
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_10     0x9f0a
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_11     0x9f0b
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_12     0x9f0c
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_13     0x9f0d
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_14     0x9f0e
#define GEN8_PC_SLICE_PERFCTR_PC_SEL_15     0x9f0f


/* VFD registers */
#define GEN8_VFD_DBG_ECO_CNTL               0xa600
#define GEN8_VFD_PERFCTR_VFD_SEL_0          0xa610
#define GEN8_VFD_PERFCTR_VFD_SEL_1          0xa611
#define GEN8_VFD_PERFCTR_VFD_SEL_2          0xa612
#define GEN8_VFD_PERFCTR_VFD_SEL_3          0xa613
#define GEN8_VFD_PERFCTR_VFD_SEL_4          0xa614
#define GEN8_VFD_PERFCTR_VFD_SEL_5          0xa615
#define GEN8_VFD_PERFCTR_VFD_SEL_6          0xa616
#define GEN8_VFD_PERFCTR_VFD_SEL_7          0xa617
#define GEN8_VFD_PERFCTR_VFD_SEL_8          0xa618
#define GEN8_VFD_PERFCTR_VFD_SEL_9          0xa619
#define GEN8_VFD_PERFCTR_VFD_SEL_10         0xa61a
#define GEN8_VFD_PERFCTR_VFD_SEL_11         0xa61b
#define GEN8_VFD_PERFCTR_VFD_SEL_12         0xa61c
#define GEN8_VFD_PERFCTR_VFD_SEL_13         0xa61d
#define GEN8_VFD_PERFCTR_VFD_SEL_14         0xa61e
#define GEN8_VFD_PERFCTR_VFD_SEL_15         0xa61f
#define GEN8_VFD_CB_BV_THRESHOLD            0xa639
#define GEN8_VFD_CB_BR_THRESHOLD            0xa63a
#define GEN8_VFD_CB_BUSY_REQ_CNT            0xa63b
#define GEN8_VFD_CB_LP_REQ_CNT              0xa63c

/* SP registers */
#define GEN8_SP_DBG_ECO_CNTL                     0xae00
#define GEN8_SP_SHADER_PROFILING                 0xae01
#define GEN8_SP_NC_MODE_CNTL                     0xae02
#define GEN8_SP_CHICKEN_BITS                     0xae03
#define GEN8_SP_NC_MODE_CNTL_2                   0xae04
#define GEN8_SP_SS_CHICKEN_BITS_0                0xae05
#define GEN8_SP_ISDB_CNTL                        0xae06
#define GEN8_SP_PERFCTR_CNTL                     0xae07
#define GEN8_SP_CHICKEN_BITS_1                   0xae08
#define GEN8_SP_CHICKEN_BITS_2                   0xae09
#define GEN8_SP_CHICKEN_BITS_3                   0xae0a
#define GEN8_SP_CHICKEN_BITS_4                   0xae0b
#define GEN8_SP_STATUS                           0xae0c
#define GEN8_SP_PERFCTR_SHADER_MASK              0xae0f
#define GEN8_SP_HLSQ_GC_GMEM_RANGE_MIN_LO        0xae10
#define GEN8_SP_HLSQ_GC_GMEM_RANGE_MIN_HI        0xae11
#define GEN8_SP_HLSQ_LPAC_GMEM_RANGE_MIN_LO      0xae12
#define GEN8_SP_HLSQ_LPAC_GMEM_RANGE_MIN_HI      0xae13
#define GEN8_SP_LPAC_CPI_STATUS                  0xae15
#define GEN8_SP_LPAC_DBG_STATUS                  0xae16
#define GEN8_SP_LPAC_ISDB_BATCH_COUNT            0xae17
#define GEN8_SP_LPAC_ISDB_BATCH_COUNT_INCR_EN    0xae18
#define GEN8_SP_LPAC_ISDB_BATCH_COUNT_SHADERS    0xae19
#define GEN8_SP_ISDB_BATCH_COUNT                 0xae30
#define GEN8_SP_ISDB_BATCH_COUNT_INCR_EN         0xae31
#define GEN8_SP_ISDB_BATCH_COUNT_SHADERS         0xae32
#define GEN8_SP_ISDB_DEBUG_CONFIG                0xae35
#define GEN8_SP_SELF_THROTTLE_CONTROL            0xae3a
#define GEN8_SP_DISPATCH_CNTL                    0xae3b
#define GEN8_SP_SW_DEBUG_ADDR_LO                 0xae3c
#define GEN8_SP_SW_DEBUG_ADDR_HI                 0xae3d
#define GEN8_SP_ISDB_DEBUG_ADDR_LO               0xae3e
#define GEN8_SP_ISDB_DEBUG_ADDR_HI               0xae3f
#define GEN8_SP_HLSQ_TIMEOUT_THRESHOLD_DP        0xae6b
#define GEN8_SP_HLSQ_DBG_ECO_CNTL                0xae6c
#define GEN8_SP_READ_SEL                         0xae6d
#define GEN8_SP_DBG_CNTL                         0xae71

#define GEN8_SP_PERFCTR_HLSQ_SEL_0          0xae60
#define GEN8_SP_PERFCTR_HLSQ_SEL_1          0xae61
#define GEN8_SP_PERFCTR_HLSQ_SEL_2          0xae62
#define GEN8_SP_PERFCTR_HLSQ_SEL_3          0xae63
#define GEN8_SP_PERFCTR_HLSQ_SEL_4          0xae64
#define GEN8_SP_PERFCTR_HLSQ_SEL_5          0xae65
#define GEN8_SP_PERFCTR_SP_SEL_0            0xae80
#define GEN8_SP_PERFCTR_SP_SEL_1            0xae81
#define GEN8_SP_PERFCTR_SP_SEL_2            0xae82
#define GEN8_SP_PERFCTR_SP_SEL_3            0xae83
#define GEN8_SP_PERFCTR_SP_SEL_4            0xae84
#define GEN8_SP_PERFCTR_SP_SEL_5            0xae85
#define GEN8_SP_PERFCTR_SP_SEL_6            0xae86
#define GEN8_SP_PERFCTR_SP_SEL_7            0xae87
#define GEN8_SP_PERFCTR_SP_SEL_8            0xae88
#define GEN8_SP_PERFCTR_SP_SEL_9            0xae89
#define GEN8_SP_PERFCTR_SP_SEL_10           0xae8a
#define GEN8_SP_PERFCTR_SP_SEL_11           0xae8b
#define GEN8_SP_PERFCTR_SP_SEL_12           0xae8c
#define GEN8_SP_PERFCTR_SP_SEL_13           0xae8d
#define GEN8_SP_PERFCTR_SP_SEL_14           0xae8e
#define GEN8_SP_PERFCTR_SP_SEL_15           0xae8f
#define GEN8_SP_PERFCTR_SP_SEL_16           0xae90
#define GEN8_SP_PERFCTR_SP_SEL_17           0xae91
#define GEN8_SP_PERFCTR_SP_SEL_18           0xae92
#define GEN8_SP_PERFCTR_SP_SEL_19           0xae93
#define GEN8_SP_PERFCTR_SP_SEL_20           0xae94
#define GEN8_SP_PERFCTR_SP_SEL_21           0xae95
#define GEN8_SP_PERFCTR_SP_SEL_22           0xae96
#define GEN8_SP_PERFCTR_SP_SEL_23           0xae97
#define GEN8_SP_PERFCTR_SP_SEL_24           0xae98
#define GEN8_SP_PERFCTR_SP_SEL_25           0xae99
#define GEN8_SP_PERFCTR_SP_SEL_26           0xae9a
#define GEN8_SP_PERFCTR_SP_SEL_27           0xae9b
#define GEN8_SP_PERFCTR_SP_SEL_28           0xae9c
#define GEN8_SP_PERFCTR_SP_SEL_29           0xae9d
#define GEN8_SP_PERFCTR_SP_SEL_30           0xae9e
#define GEN8_SP_PERFCTR_SP_SEL_31           0xae9f
#define GEN8_SP_PERFCTR_SP_SEL_32           0xaea0
#define GEN8_SP_PERFCTR_SP_SEL_33           0xaea1
#define GEN8_SP_PERFCTR_SP_SEL_34           0xaea2
#define GEN8_SP_PERFCTR_SP_SEL_35           0xaea3
#define GEN8_SP_PERFCTR_HLSQ_SEL_2_0        0xaec0
#define GEN8_SP_PERFCTR_HLSQ_SEL_2_1        0xaec1
#define GEN8_SP_PERFCTR_HLSQ_SEL_2_2        0xaec2
#define GEN8_SP_PERFCTR_HLSQ_SEL_2_3        0xaec3
#define GEN8_SP_PERFCTR_HLSQ_SEL_2_4        0xaec4
#define GEN8_SP_PERFCTR_HLSQ_SEL_2_5        0xaec5

/* TP registers */
#define GEN8_TPL1_DBG_ECO_CNTL              0xb600
#define GEN8_TPL1_DBG_ECO_CNTL1             0xb602
#define GEN8_TPL1_NC_MODE_CNTL              0xb604
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_0   0xb606
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_1   0xb607
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_2   0xb608
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_3   0xb609
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_4   0xb60a
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_5   0xb60b
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_6   0xb60c
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_7   0xb60d
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_8   0xb60e
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_9   0xb60f
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_10   0xb610
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_11   0xb611
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_12   0xb612
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_13   0xb613
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_14   0xb614
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_15   0xb615
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_16   0xb616
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_17   0xb617
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_18   0xb618
#define GEN8_TPL1_BICUBIC_WEIGHTS_TABLE_19   0xb619

#define GEN8_TPL1_PERFCTR_TP_SEL_0          0xb620
#define GEN8_TPL1_PERFCTR_TP_SEL_1          0xb621
#define GEN8_TPL1_PERFCTR_TP_SEL_2          0xb622
#define GEN8_TPL1_PERFCTR_TP_SEL_3          0xb623
#define GEN8_TPL1_PERFCTR_TP_SEL_4          0xb624
#define GEN8_TPL1_PERFCTR_TP_SEL_5          0xb625
#define GEN8_TPL1_PERFCTR_TP_SEL_6          0xb626
#define GEN8_TPL1_PERFCTR_TP_SEL_7          0xb627
#define GEN8_TPL1_PERFCTR_TP_SEL_8          0xb628
#define GEN8_TPL1_PERFCTR_TP_SEL_9          0xb629
#define GEN8_TPL1_PERFCTR_TP_SEL_10         0xb62a
#define GEN8_TPL1_PERFCTR_TP_SEL_11         0xb62b
#define GEN8_TPL1_PERFCTR_TP_SEL_12         0xb62c
#define GEN8_TPL1_PERFCTR_TP_SEL_13         0xb62d
#define GEN8_TPL1_PERFCTR_TP_SEL_14         0xb62e
#define GEN8_TPL1_PERFCTR_TP_SEL_15         0xb62f
#define GEN8_TPL1_PERFCTR_TP_SEL_16         0xb630
#define GEN8_TPL1_PERFCTR_TP_SEL_17         0xb631
#define GEN8_TPL1_PERFCTR_TP_SEL_18         0xb632
#define GEN8_TPL1_PERFCTR_TP_SEL_19         0xb633


#define GEN8_SP_AHB_READ_APERTURE           0xc000

#define GEN8_RBBM_SECVID_TRUST_CNTL              0xf400
#define GEN8_RBBM_SECVID_TSB_TRUSTED_BASE_LO     0xf800
#define GEN8_RBBM_SECVID_TSB_TRUSTED_BASE_HI     0xf801
#define GEN8_RBBM_SECVID_TSB_TRUSTED_SIZE        0xf802
#define GEN8_RBBM_SECVID_TSB_CNTL                0xf803
#define GEN8_RBBM_SECVID_TSB_STATUS_LO           0xfc00
#define GEN8_RBBM_SECVID_TSB_STATUS_HI           0xfc01

/* GBIF countables */
#define GBIF_AXI0_READ_DATA_TOTAL_BEATS    34
#define GBIF_AXI1_READ_DATA_TOTAL_BEATS    35
#define GBIF_AXI0_WRITE_DATA_TOTAL_BEATS   46
#define GBIF_AXI1_WRITE_DATA_TOTAL_BEATS   47

/* GBIF registers */
#define GEN8_GBIF_SCACHE_CNTL0            0x3c01
#define GEN8_GBIF_SCACHE_CNTL1            0x3c02
#define GEN8_GBIF_QSB_SIDE0               0x3c03
#define GEN8_GBIF_QSB_SIDE1               0x3c04
#define GEN8_GBIF_QSB_SIDE2               0x3c05
#define GEN8_GBIF_QSB_SIDE3               0x3c06
#define GEN8_GBIF_HALT                    0x3c45
#define GEN8_GBIF_HALT_ACK                0x3c46

#define GEN8_GBIF_CLIENT_HALT_MASK        BIT(0)
#define GEN8_GBIF_ARB_HALT_MASK           BIT(1)
#define GEN8_GBIF_GX_HALT_MASK            BIT(0)

#define GEN8_GBIF_PERF_PWR_CNT_EN                0x3cc0
#define GEN8_GBIF_PERF_PWR_CNT_CLR               0x3cc1
#define GEN8_GBIF_PERF_CNT_SEL_0                 0x3cc2
#define GEN8_GBIF_PERF_CNT_SEL_1                 0x3cc3
#define GEN8_GBIF_PWR_CNT_SEL                    0x3cc4
#define GEN8_GBIF_PERF_CNT_LO_0                  0x3cc6
#define GEN8_GBIF_PERF_CNT_HI_0                  0x3cc7
#define GEN8_GBIF_PERF_CNT_LO_1                  0x3cc8
#define GEN8_GBIF_PERF_CNT_HI_1                  0x3cc9
#define GEN8_GBIF_PERF_CNT_LO_2                  0x3cca
#define GEN8_GBIF_PERF_CNT_HI_2                  0x3ccb
#define GEN8_GBIF_PERF_CNT_LO_3                  0x3ccc
#define GEN8_GBIF_PERF_CNT_HI_3                  0x3ccd
#define GEN8_GBIF_PERF_CNT_LO_4                  0x3cce
#define GEN8_GBIF_PERF_CNT_HI_4                  0x3ccf
#define GEN8_GBIF_PERF_CNT_LO_5                  0x3cd0
#define GEN8_GBIF_PERF_CNT_HI_5                  0x3cd1
#define GEN8_GBIF_PERF_CNT_LO_6                  0x3cd2
#define GEN8_GBIF_PERF_CNT_HI_6                  0x3cd3
#define GEN8_GBIF_PERF_CNT_LO_7                  0x3cd4
#define GEN8_GBIF_PERF_CNT_HI_7                  0x3cd5
#define GEN8_GBIF_PWR_CNT_LO_0                   0x3ce0 /* Indexed Register */
#define GEN8_GBIF_PWR_CNT_LO_1                   0x3ce1 /* Indexed Register */
#define GEN8_GBIF_PWR_CNT_LO_2                   0x3ce2 /* Indexed Register */
#define GEN8_GBIF_PWR_CNT_HI_0                   0x3ce3 /* Indexed Register */
#define GEN8_GBIF_PWR_CNT_HI_1                   0x3ce4 /* Indexed Register */
#define GEN8_GBIF_PWR_CNT_HI_2                   0x3ce5 /* Indexed Register */

/* CX_DBGC_CFG registers: Fixme for Snapshot */
#define GEN8_CX_DBGC_CFG_DBGBUS_SEL_A                   0x18400
#define GEN8_CX_DBGC_CFG_DBGBUS_SEL_B                   0x18401
#define GEN8_CX_DBGC_CFG_DBGBUS_SEL_C                   0x18402
#define GEN8_CX_DBGC_CFG_DBGBUS_SEL_D                   0x18403
#define GEN8_CX_DBGC_CFG_DBGBUS_CNTLT                   0x18404
#define GEN8_CX_DBGC_CFG_DBGBUS_CNTLM                   0x18405
#define GEN8_CX_DBGC_CFG_DBGBUS_OPL                     0x18406
#define GEN8_CX_DBGC_CFG_DBGBUS_OPE                     0x18407
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTL_0                  0x18408
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTL_1                  0x18409
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTL_2                  0x1840a
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTL_3                  0x1840b
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKL_0                 0x1840c
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKL_1                 0x1840d
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKL_2                 0x1840e
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKL_3                 0x1840f
#define GEN8_CX_DBGC_CFG_DBGBUS_BYTEL_0                 0x18410
#define GEN8_CX_DBGC_CFG_DBGBUS_BYTEL_1                 0x18411
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTE_0                  0x18412
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTE_1                  0x18413
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTE_2                  0x18414
#define GEN8_CX_DBGC_CFG_DBGBUS_IVTE_3                  0x18415
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKE_0                 0x18416
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKE_1                 0x18417
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKE_2                 0x18418
#define GEN8_CX_DBGC_CFG_DBGBUS_MASKE_3                 0x18419
#define GEN8_CX_DBGC_CFG_DBGBUS_NIBBLEE                 0x1841a
#define GEN8_CX_DBGC_CFG_DBGBUS_PTRC0                   0x1841b
#define GEN8_CX_DBGC_CFG_DBGBUS_PTRC1                   0x1841c
#define GEN8_CX_DBGC_CFG_DBGBUS_LOADREG                 0x1841d
#define GEN8_CX_DBGC_CFG_DBGBUS_IDX                     0x1841e
#define GEN8_CX_DBGC_CFG_DBGBUS_CLRC                    0x1841f
#define GEN8_CX_DBGC_CFG_DBGBUS_LOADIVT                 0x18420
#define GEN8_CX_DBGC_VBIF_DBG_CNTL                      0x18421
#define GEN8_CX_DBGC_DBG_LO_HI_GPIO                     0x18422
#define GEN8_CX_DBGC_EXT_TRACE_BUS_CNTL                 0x18423
#define GEN8_CX_DBGC_READ_AHB_THROUGH_DBG               0x18424
#define GEN8_CX_DBGC_CFG_DBGBUS_OVER                    0x18426
#define GEN8_CX_DBGC_CFG_DBGBUS_TRACE_BUF1              0x1842f
#define GEN8_CX_DBGC_CFG_DBGBUS_TRACE_BUF2              0x18430
#define GEN8_CX_DBGC_EVT_CFG                            0x18435
#define GEN8_CX_DBGC_EVT_INTF_SEL_0                     0x18436
#define GEN8_CX_DBGC_EVT_INTF_SEL_1                     0x18437
#define GEN8_CX_DBGC_PERF_ATB_CFG                       0x18438
#define GEN8_CX_DBGC_ECO_CNTL                           0x1843b
#define GEN8_CX_DBGC_AHB_DBG_CNTL                       0x1843c
#define GEN8_CX_DBGC_TCM_DBG_ADDR                       0x18580
#define GEN8_CX_DBGC_TCM_DBG_DATA                       0x18581

/* GMU control registers */
#define GEN8_GMU_CM3_ITCM_START			0x1b400
#define GEN8_GMU_CM3_DTCM_START			0x1c400
#define GEN8_GMUCX_ICACHE_CONFIG		0x1f400
#define GEN8_GMUCX_DCACHE_CONFIG		0x1f401
#define GEN8_GMUCX_SYS_BUS_CONFIG		0x1f40f
#define GEN8_GMUCX_MRC_GBIF_QOS_CTRL		0x1f50b
#define GEN8_GMUCX_PWR_COL_KEEPALIVE		0x1f7e4
#define GEN8_GMUCX_PWR_COL_PREEMPTION_KEEPALIVE	0x1f7e5
#define GEN8_GMUCX_GFX_PWR_CLK_STATUS		0x1f7e8
#define GEN8_GMUCX_RPMH_POWER_STATE			0x1f7e9
/* FAL10 veto register */
#define GEN8_GMUCX_CX_FAL_INTF				0x1f7ec
#define GEN8_GMUCX_CX_FALNEXT_INTF			0x1f7ed
#define GEN8_GMUCX_CM3_SYSRESET			0x1f800
#define GEN8_GMUCX_CM3_BOOT_CONFIG		0x1f801
#define GEN8_GMUCX_WFI_CONFIG		0x1f802
#define GEN8_GMUCX_WDOG_CTRL		0x1f813
#define GEN8_GMUCX_CM3_FW_INIT_RESULT		0x1f81c
#define GEN8_GMUCX_CM3_CFG			0x1f82d
#define GEN8_GMUCX_AO_COUNTER_LO	0x1f840
#define GEN8_GMUCX_AO_COUNTER_HI	0x1f841

#define GEN8_GMUCX_PERF_COUNTER_ENABLE             0x1f848
#define GEN8_GMUCX_PERF_COUNTER_SELECT_0           0x1f858
#define GEN8_GMUCX_PERF_COUNTER_SELECT_1           0x1f859
#define GEN8_GMUCX_PERF_COUNTER_SELECT_H_0         0x1f868
#define GEN8_GMUCX_PERF_COUNTER_SELECT_H_1         0x1f869
#define GEN8_GMUCX_PERF_COUNTER_L_0                0x1f878
#define GEN8_GMUCX_PERF_COUNTER_H_0                0x1f879
#define GEN8_GMUCX_PERF_COUNTER_L_1                0x1f87a
#define GEN8_GMUCX_PERF_COUNTER_H_1                0x1f87b
#define GEN8_GMUCX_PERF_COUNTER_L_2                0x1f87c
#define GEN8_GMUCX_PERF_COUNTER_H_2                0x1f87d
#define GEN8_GMUCX_PERF_COUNTER_L_3                0x1f87e
#define GEN8_GMUCX_PERF_COUNTER_H_3                0x1f87f
#define GEN8_GMUCX_PERF_COUNTER_L_4                0x1f880
#define GEN8_GMUCX_PERF_COUNTER_H_4                0x1f881
#define GEN8_GMUCX_PERF_COUNTER_L_5                0x1f882
#define GEN8_GMUCX_PERF_COUNTER_H_5                0x1f883

#define GEN8_GMUCX_POWER_COUNTER_ENABLE            0x1fc10
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_0   0x1fc30
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_1   0x1fc31
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_2   0x1fc32
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_3   0x1fc33
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_H_0 0x1fc38
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_H_1 0x1fc39
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_H_2 0x1fc3a
#define GEN8_GMUCX_POWER_COUNTER_SELECT_GMUCLK_H_3 0x1fc3b
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_0    0x1fc40
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_1    0x1fc41
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_2    0x1fc42
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_3    0x1fc43
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_4    0x1fc44
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_5    0x1fc45
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_6    0x1fc46
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_7    0x1fc47
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_8    0x1fc48
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_9    0x1fc49
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_0  0x1fc50
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_1  0x1fc51
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_2  0x1fc52
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_3  0x1fc53
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_4  0x1fc54
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_5  0x1fc55
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_6  0x1fc56
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_7  0x1fc57
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_8  0x1fc58
#define GEN8_GMUCX_POWER_COUNTER_SELECT_XOCLK_H_9  0x1fc59

#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_0        0x1fc60
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_0        0x1fc61
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_1        0x1fc62
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_1        0x1fc63
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_2        0x1fc64
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_2        0x1fc65
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_3        0x1fc66
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_3        0x1fc67
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_4        0x1fc68
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_4        0x1fc69
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_5        0x1fc6a
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_5        0x1fc6b
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_6        0x1fc6c
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_6        0x1fc6d
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_7        0x1fc6e
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_7        0x1fc6f
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_8        0x1fc70
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_8        0x1fc71
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_9        0x1fc72
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_9        0x1fc73
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_10       0x1fc74
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_10       0x1fc75
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_11       0x1fc76
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_11       0x1fc77
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_12       0x1fc78
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_12       0x1fc79
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_13       0x1fc7a
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_13       0x1fc7b
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_14       0x1fc7c
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_14       0x1fc7d
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_L_15       0x1fc7e
#define GEN8_GMUCX_POWER_COUNTER_GMUCLK_H_15       0x1fc7f

#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_0         0x1fca0
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_0         0x1fca1
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_1         0x1fca2
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_1         0x1fca3
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_2         0x1fca4
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_2         0x1fca5
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_3         0x1fca6
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_3         0x1fca7
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_4         0x1fca8
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_4         0x1fca9
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_5         0x1fcaa
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_5         0x1fcab
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_6         0x1fcac
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_6         0x1fcad
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_7         0x1fcae
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_7         0x1fcaf
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_8         0x1fcb0
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_8         0x1fcb1
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_9         0x1fcb2
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_9         0x1fcb3
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_10        0x1fcb4
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_10        0x1fcb5
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_11        0x1fcb6
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_11        0x1fcb7
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_12        0x1fcb8
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_12        0x1fcb9
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_13        0x1fcba
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_13        0x1fcbb
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_14        0x1fcbc
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_14        0x1fcbd
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_15        0x1fcbe
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_15        0x1fcbf
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_16        0x1fcc0
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_16        0x1fcc1
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_17        0x1fcc2
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_17        0x1fcc3
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_18        0x1fcc4
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_18        0x1fcc5
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_19        0x1fcc6
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_19        0x1fcc7
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_20        0x1fcc8
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_20        0x1fcc9
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_21        0x1fcca
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_21        0x1fccb
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_22        0x1fccc
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_22        0x1fccd
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_23        0x1fcce
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_23        0x1fccf
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_24        0x1fcd0
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_24        0x1fcd1
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_25        0x1fcd2
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_25        0x1fcd3
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_26        0x1fcd4
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_26        0x1fcd5
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_27        0x1fcd6
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_27        0x1fcd7
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_28        0x1fcd8
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_28        0x1fcd9
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_29        0x1fcda
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_29        0x1fcdb
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_30        0x1fcdc
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_30        0x1fcdd
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_31        0x1fcde
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_31        0x1fcdf
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_32        0x1fce0
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_32        0x1fce1
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_33        0x1fce2
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_33        0x1fce3
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_34        0x1fce4
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_34        0x1fce5
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_35        0x1fce6
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_35        0x1fce7
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_36        0x1fce8
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_36        0x1fce9
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_37        0x1fcea
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_37        0x1fceb
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_38        0x1fcec
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_38        0x1fced
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_L_39        0x1fcee
#define GEN8_GMUCX_POWER_COUNTER_XOCLK_H_39        0x1fcef

/* HFI registers*/
#define GEN8_GMUCX_HFI_CTRL_STATUS		0x1f980
#define GEN8_GMUCX_HFI_QTBL_INFO			0x1f984
#define GEN8_GMUCX_HFI_QTBL_ADDR			0x1f985
#define GEN8_GMUCX_HFI_CTRL_INIT			0x1f986
#define GEN8_GMUCX_GMU2HOST_INTR_SET		0x1f990
#define GEN8_GMUCX_GMU2HOST_INTR_CLR		0x1f991
#define GEN8_GMUCX_GMU2HOST_INTR_INFO		0x1f992
#define GEN8_GMUCX_GMU2HOST_INTR_MASK		0x1f993
#define GEN8_GMUCX_HOST2GMU_INTR_SET		0x1f994
#define GEN8_GMUCX_HOST2GMU_INTR_CLR		0x1f995
#define GEN8_GMUCX_HOST2GMU_INTR_RAW_INFO		0x1f996
#define GEN8_GMUCX_GENERAL_8			0x1f9c8
#define GEN8_GMUCX_GENERAL_9			0x1f9c9
#define GEN8_GMUCX_GENERAL_10			0x1f9ca
#define GEN8_GMUCX_GENERAL_11			0x1f9cb

/* Always on registers */
#define GEN8_GMUAO_AO_INTERRUPT_EN		0x23b03
#define GEN8_GMUAO_AO_HOST_INTERRUPT_CLR		0x23b04
#define GEN8_GMUAO_AO_HOST_INTERRUPT_STATUS	0x23b05
#define GEN8_GMUAO_AO_HOST_INTERRUPT_MASK		0x23b06

/* GMU RSC control registers */
#define GEN8_GMUAO_RSCC_CONTROL_REQ			0x23b07
#define GEN8_GMUAO_RSCC_CONTROL_ACK			0x23b08

#define GEN8_GMUAO_CGC_MODE_CNTL	0x23b09
#define GEN8_GMUAO_CGC_DELAY_CNTL	0x23b0a
#define GEN8_GMUAO_CGC_HYST_CNTL	0x23b0b
#define GEN8_GMUAO_GPU_CX_BUSY_STATUS	0x23b0c
#define GEN8_GMUAO_GPU_CX_BUSY_STATUS2	0x23b0d
#define GEN8_GMUAO_GPU_CX_BUSY_MASK	0x23b0e

/* FENCE control registers */
#define GEN8_GMUAO_AHB_FENCE_CTRL		0x23b10
#define GEN8_GMUAO_AHB_FENCE_RANGE_0		0x23b11
#define GEN8_GMUAO_AHB_FENCE_STATUS		0x23b13
#define GEN8_GMUAO_AHB_FENCE_STATUS_CLR	0x23b14
#define GEN8_GMUAO_RBBM_INT_UNMASKED_STATUS_SHADOW	0x23b15
#define GEN8_GMUAO_LPAC_BUSY_STATUS		0x23b30

/* GMU countables */
#define GEN8_GMU_CM3_BUSY_CYCLES		0

/* GPUCC registers */
#define GEN8_GPU_CC_CX_CFG_GDSCR		0x26421
#define GEN8_GPU_CC_GX_DOMAIN_MISC3		0x26541

/* GPU RSC sequencer registers */
#define GEN8_GPU_RSCC_RSC_STATUS0_DRV0			0x00004
#define GEN8_RSCC_SEQ_BUSY_DRV0				0x00101
#define GEN8_RSCC_TCS0_DRV0_STATUS			0x0034a
#define GEN8_RSCC_TCS1_DRV0_STATUS			0x003f2
#define GEN8_RSCC_TCS2_DRV0_STATUS			0x0049a
#define GEN8_RSCC_TCS3_DRV0_STATUS			0x00542
#define GEN8_RSCC_TCS4_DRV0_STATUS			0x005ea
#define GEN8_RSCC_TCS5_DRV0_STATUS			0x00692
#define GEN8_RSCC_TCS6_DRV0_STATUS			0x0073a
#define GEN8_RSCC_TCS7_DRV0_STATUS			0x007e2
#define GEN8_RSCC_TCS8_DRV0_STATUS			0x0088a
#define GEN8_RSCC_TCS9_DRV0_STATUS			0x00932

#define GEN8_SMMU_BASE				0x28000

/* GPU CX_MISC registers */
#define GEN8_GPU_CX_MISC_CX_AHB_AON_CNTL	0x10
#define GEN8_GPU_CX_MISC_CX_AHB_GMU_CNTL	0x11
#define GEN8_GPU_CX_MISC_CX_AHB_CP_CNTL		0x12
#define GEN8_GPU_CX_MISC_CX_AHB_VBIF_SMMU_CNTL	0x13
#define GEN8_GPU_CX_MISC_CX_AHB_HOST_CNTL	0x14
#define GEN8_GPU_CX_MISC_INT_CLEAR_CMD		0x31
#define GEN8_GPU_CX_MISC_INT_0_MASK		0x33
#define GEN8_GPU_CX_MISC_INT_0_STATUS		0x34
#define GEN8_GPU_CX_MISC_AO_COUNTER_LO		0x80
#define GEN8_GPU_CX_MISC_AO_COUNTER_HI		0x81
#define GEN8_GPU_CX_MISC_SW_FUSE_VALUE		0x400

/* GPU SW Fuse Feature bit fields */
#define GEN8_FASTBLEND_SW_FUSE		0
#define GEN8_LPAC_SW_FUSE		1
#define GEN8_RAYTRACING_SW_FUSE		2

#define GEN8_SW_FUSE_INT_MASK \
	((1 << GEN8_FASTBLEND_SW_FUSE) |	\
	(1 << GEN8_LPAC_SW_FUSE) |	\
	(1 << GEN8_RAYTRACING_SW_FUSE))

/* QDSS register offsets */
#define QDSS_AOSS_APB_TMC_RSZ 0x04
#define QDSS_AOSS_APB_TMC_RRD 0x10
#define QDSS_AOSS_APB_TMC_RRP 0x14
#define QDSS_AOSS_APB_TMC_RWP 0x18
#define QDSS_AOSS_APB_TMC_CTRL 0x20
#define QDSS_AOSS_APB_TMC_MODE 0x28
#define QDSS_AOSS_APB_TMC_FFCR 0x304
#define QDSS_AOSS_APB_TMC_LAR 0xfb0
#define QDSS_AOSS_APB_ETR_CTRL 0x20
#define QDSS_AOSS_APB_ETR1_CTRL 0x7020

#endif /* _GEN8_REG_H */