cvp_hfi.c 151 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <asm/memory.h>
  7. #include <linux/coresight-stm.h>
  8. #include <linux/delay.h>
  9. #include <linux/devfreq.h>
  10. #include <linux/hash.h>
  11. #include <linux/io.h>
  12. #include <linux/iommu.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/of.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/soc/qcom/llcc-qcom.h>
  21. #include <linux/qcom_scm.h>
  22. #include <linux/soc/qcom/smem.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/reset.h>
  25. #include <linux/pm_wakeup.h>
  26. #include "hfi_packetization.h"
  27. #include "msm_cvp_debug.h"
  28. #include "cvp_core_hfi.h"
  29. #include "cvp_hfi_helper.h"
  30. #include "cvp_hfi_io.h"
  31. #include "msm_cvp_dsp.h"
  32. #include "msm_cvp_clocks.h"
  33. #include "vm/cvp_vm.h"
  34. #include "cvp_dump.h"
  35. // ysi - added for debug
  36. #include <linux/clk/qcom.h>
  37. #include "msm_cvp_common.h"
  38. #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
  39. #define QDSS_IOVA_START 0x80001000
  40. #define MIN_PAYLOAD_SIZE 3
  41. struct cvp_tzbsp_memprot {
  42. u32 cp_start;
  43. u32 cp_size;
  44. u32 cp_nonpixel_start;
  45. u32 cp_nonpixel_size;
  46. };
  47. #define TZBSP_CVP_PAS_ID 26
  48. /* Poll interval in uS */
  49. #define POLL_INTERVAL_US 50
  50. enum tzbsp_subsys_state {
  51. TZ_SUBSYS_STATE_SUSPEND = 0,
  52. TZ_SUBSYS_STATE_RESUME = 1,
  53. TZ_SUBSYS_STATE_RESTORE_THRESHOLD = 2,
  54. };
  55. const struct msm_cvp_gov_data CVP_DEFAULT_BUS_VOTE = {
  56. .data = NULL,
  57. .data_count = 0,
  58. };
  59. const int cvp_max_packets = 32;
  60. static void iris_hfi_pm_handler(struct work_struct *work);
  61. static DECLARE_DELAYED_WORK(iris_hfi_pm_work, iris_hfi_pm_handler);
  62. static inline int __resume(struct iris_hfi_device *device);
  63. static inline int __suspend(struct iris_hfi_device *device);
  64. static int __disable_regulator(struct iris_hfi_device *device,
  65. const char *name);
  66. static int __enable_regulator(struct iris_hfi_device *device,
  67. const char *name);
  68. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet);
  69. static int __initialize_packetization(struct iris_hfi_device *device);
  70. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  71. u32 session_id);
  72. static bool __is_session_valid(struct iris_hfi_device *device,
  73. struct cvp_hal_session *session, const char *func);
  74. static int __iface_cmdq_write(struct iris_hfi_device *device,
  75. void *pkt);
  76. static int __load_fw(struct iris_hfi_device *device);
  77. static int __power_on_init(struct iris_hfi_device *device);
  78. static void __unload_fw(struct iris_hfi_device *device);
  79. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state);
  80. static int __enable_subcaches(struct iris_hfi_device *device);
  81. static int __set_subcaches(struct iris_hfi_device *device);
  82. static int __release_subcaches(struct iris_hfi_device *device);
  83. static int __disable_subcaches(struct iris_hfi_device *device);
  84. static int __power_collapse(struct iris_hfi_device *device, bool force);
  85. static int iris_hfi_noc_error_info(void *dev);
  86. static void interrupt_init_iris2(struct iris_hfi_device *device);
  87. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device);
  88. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device);
  89. static void power_off_iris2(struct iris_hfi_device *device);
  90. static int __set_ubwc_config(struct iris_hfi_device *device);
  91. static void __noc_error_info_iris2(struct iris_hfi_device *device);
  92. static int __enable_hw_power_collapse(struct iris_hfi_device *device);
  93. static int __disable_hw_power_collapse(struct iris_hfi_device *device);
  94. static int __power_off_controller(struct iris_hfi_device *device);
  95. static int __hwfence_regs_map(struct iris_hfi_device *device);
  96. static int __hwfence_regs_unmap(struct iris_hfi_device *device);
  97. static int __reset_control_assert_name(struct iris_hfi_device *device, const char *name);
  98. static int __reset_control_deassert_name(struct iris_hfi_device *device, const char *name);
  99. static int __reset_control_acquire(struct iris_hfi_device *device, const char *name);
  100. static int __reset_control_release(struct iris_hfi_device *device, const char *name);
  101. static bool __is_ctl_power_on(struct iris_hfi_device *device);
  102. static void __print_sidebandmanager_regs(struct iris_hfi_device *device);
  103. static void dump_noc_reg(struct iris_hfi_device *device);
  104. static struct cvp_hal_ops hal_ops = {
  105. .interrupt_init = interrupt_init_iris2,
  106. .setup_dsp_uc_memmap = setup_dsp_uc_memmap_vpu5,
  107. .clock_config_on_enable = clock_config_on_enable_vpu5,
  108. .power_off = power_off_iris2,
  109. .noc_error_info = __noc_error_info_iris2,
  110. .reset_control_assert_name = __reset_control_assert_name,
  111. .reset_control_deassert_name = __reset_control_deassert_name,
  112. .reset_control_acquire_name = __reset_control_acquire,
  113. .reset_control_release_name = __reset_control_release,
  114. };
  115. /**
  116. * Utility function to enforce some of our assumptions. Spam calls to this
  117. * in hotspots in code to double check some of the assumptions that we hold.
  118. */
  119. static inline void __strict_check(struct iris_hfi_device *device)
  120. {
  121. msm_cvp_res_handle_fatal_hw_error(device->res,
  122. !mutex_is_locked(&device->lock));
  123. }
  124. static inline void __set_state(struct iris_hfi_device *device,
  125. enum iris_hfi_state state)
  126. {
  127. device->state = state;
  128. }
  129. static inline bool __core_in_valid_state(struct iris_hfi_device *device)
  130. {
  131. return device->state != IRIS_STATE_DEINIT;
  132. }
  133. static inline bool is_sys_cache_present(struct iris_hfi_device *device)
  134. {
  135. return device->res->sys_cache_present;
  136. }
  137. static int cvp_synx_recover(void)
  138. {
  139. #ifdef CVP_SYNX_ENABLED
  140. return synx_recover(SYNX_CLIENT_EVA_CTX0);
  141. #else
  142. return 0;
  143. #endif /* End of CVP_SYNX_ENABLED */
  144. }
  145. #define ROW_SIZE 32
  146. unsigned long long get_aon_time(void)
  147. {
  148. unsigned long long val;
  149. asm volatile("mrs %0, cntvct_el0" : "=r" (val));
  150. return val;
  151. }
  152. int get_hfi_version(void)
  153. {
  154. struct msm_cvp_core *core;
  155. struct iris_hfi_device *hfi;
  156. core = cvp_driver->cvp_core;
  157. hfi = (struct iris_hfi_device *)core->dev_ops->hfi_device_data;
  158. return hfi->version;
  159. }
  160. unsigned int get_msg_size(struct cvp_hfi_msg_session_hdr *hdr)
  161. {
  162. struct msm_cvp_core *core;
  163. struct iris_hfi_device *device;
  164. u32 minor_ver;
  165. core = cvp_driver->cvp_core;
  166. if (core)
  167. device = core->dev_ops->hfi_device_data;
  168. else
  169. return 0;
  170. if (!device) {
  171. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  172. return 0;
  173. }
  174. minor_ver = (device->version & HFI_VERSION_MINOR_MASK) >>
  175. HFI_VERSION_MINOR_SHIFT;
  176. if (minor_ver < 2)
  177. return sizeof(struct cvp_hfi_msg_session_hdr);
  178. if (hdr->packet_type == HFI_MSG_SESSION_CVP_FD)
  179. return sizeof(struct cvp_hfi_msg_session_hdr_ext);
  180. else
  181. return sizeof(struct cvp_hfi_msg_session_hdr);
  182. }
  183. unsigned int get_msg_session_id(void *msg)
  184. {
  185. struct cvp_hfi_msg_session_hdr *hdr =
  186. (struct cvp_hfi_msg_session_hdr *)msg;
  187. return hdr->session_id;
  188. }
  189. unsigned int get_msg_errorcode(void *msg)
  190. {
  191. struct cvp_hfi_msg_session_hdr *hdr =
  192. (struct cvp_hfi_msg_session_hdr *)msg;
  193. return hdr->error_type;
  194. }
  195. int get_msg_opconfigs(void *msg, unsigned int *session_id,
  196. unsigned int *error_type, unsigned int *config_id)
  197. {
  198. struct cvp_hfi_msg_session_op_cfg_packet *cfg =
  199. (struct cvp_hfi_msg_session_op_cfg_packet *)msg;
  200. *session_id = cfg->session_id;
  201. *error_type = cfg->error_type;
  202. *config_id = cfg->op_conf_id;
  203. return 0;
  204. }
  205. static void __dump_packet(u8 *packet, enum cvp_msg_prio log_level)
  206. {
  207. u32 c = 0, packet_size = *(u32 *)packet;
  208. /*
  209. * row must contain enough for 0xdeadbaad * 8 to be converted into
  210. * "de ad ba ab " * 8 + '\0'
  211. */
  212. char row[3 * ROW_SIZE];
  213. for (c = 0; c * ROW_SIZE < packet_size; ++c) {
  214. int bytes_to_read = ((c + 1) * ROW_SIZE > packet_size) ?
  215. packet_size % ROW_SIZE : ROW_SIZE;
  216. hex_dump_to_buffer(packet + c * ROW_SIZE, bytes_to_read,
  217. ROW_SIZE, 4, row, sizeof(row), false);
  218. dprintk(log_level, "%s\n", row);
  219. }
  220. }
  221. static int __dsp_suspend(struct iris_hfi_device *device, bool force)
  222. {
  223. int rc;
  224. if (msm_cvp_dsp_disable)
  225. return 0;
  226. dprintk(CVP_DSP, "%s: suspend dsp\n", __func__);
  227. rc = cvp_dsp_suspend(force);
  228. if (rc) {
  229. if (rc != -EBUSY)
  230. dprintk(CVP_ERR,
  231. "%s: dsp suspend failed with error %d\n",
  232. __func__, rc);
  233. return rc;
  234. }
  235. dprintk(CVP_DSP, "%s: dsp suspended\n", __func__);
  236. return 0;
  237. }
  238. static int __dsp_resume(struct iris_hfi_device *device)
  239. {
  240. int rc;
  241. if (msm_cvp_dsp_disable)
  242. return 0;
  243. dprintk(CVP_DSP, "%s: resume dsp\n", __func__);
  244. rc = cvp_dsp_resume();
  245. if (rc) {
  246. dprintk(CVP_ERR,
  247. "%s: dsp resume failed with error %d\n",
  248. __func__, rc);
  249. return rc;
  250. }
  251. dprintk(CVP_DSP, "%s: dsp resumed\n", __func__);
  252. return rc;
  253. }
  254. static int __dsp_shutdown(struct iris_hfi_device *device)
  255. {
  256. int rc;
  257. if (msm_cvp_dsp_disable)
  258. return 0;
  259. dprintk(CVP_DSP, "%s: shutdown dsp\n", __func__);
  260. rc = cvp_dsp_shutdown();
  261. if (rc) {
  262. dprintk(CVP_ERR,
  263. "%s: dsp shutdown failed with error %d\n",
  264. __func__, rc);
  265. WARN_ON(1);
  266. }
  267. dprintk(CVP_DSP, "%s: dsp shutdown successful\n", __func__);
  268. return rc;
  269. }
  270. static int __acquire_regulator(struct regulator_info *rinfo,
  271. struct iris_hfi_device *device)
  272. {
  273. int rc = 0;
  274. if (rinfo->has_hw_power_collapse) {
  275. /*Acquire XO_RESET to avoid race condition with video*/
  276. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  277. if (rc) {
  278. dprintk(CVP_ERR,
  279. "XO_RESET could not be acquired: skip acquiring the regulator %s from FW\n",
  280. rinfo->name);
  281. return -EINVAL;
  282. }
  283. rc = regulator_set_mode(rinfo->regulator,
  284. REGULATOR_MODE_NORMAL);
  285. if (rc) {
  286. /*
  287. * This is somewhat fatal, but nothing we can do
  288. * about it. We can't disable the regulator w/o
  289. * getting it back under s/w control
  290. */
  291. dprintk(CVP_WARN,
  292. "Failed to acquire regulator control: %s\n",
  293. rinfo->name);
  294. } else {
  295. dprintk(CVP_PWR,
  296. "Acquire regulator control from HW: %s\n",
  297. rinfo->name);
  298. }
  299. /*Release XO_RESET after regulator is enabled.*/
  300. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  301. }
  302. if (!regulator_is_enabled(rinfo->regulator)) {
  303. dprintk(CVP_WARN, "Regulator is not enabled %s\n",
  304. rinfo->name);
  305. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  306. }
  307. return rc;
  308. }
  309. static int __hand_off_regulator(struct iris_hfi_device *device, struct regulator_info *rinfo)
  310. {
  311. int rc = 0;
  312. if (rinfo->has_hw_power_collapse) {
  313. /*Acquire XO_RESET to avoid race condition with video*/
  314. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  315. if (rc) {
  316. dprintk(CVP_ERR,
  317. "XO_RESET could not be acquired: skip hand off the regulator %s to FW\n",
  318. rinfo->name);
  319. return -EINVAL;
  320. }
  321. rc = regulator_set_mode(rinfo->regulator,
  322. REGULATOR_MODE_FAST);
  323. /*Release XO_RESET after regulator is enabled.*/
  324. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  325. if (rc) {
  326. dprintk(CVP_WARN,
  327. "Failed to hand off regulator control: %s\n",
  328. rinfo->name);
  329. } else {
  330. dprintk(CVP_PWR,
  331. "Hand off regulator control to HW: %s\n",
  332. rinfo->name);
  333. }
  334. }
  335. return rc;
  336. }
  337. static int __hand_off_regulators(struct iris_hfi_device *device)
  338. {
  339. struct regulator_info *rinfo;
  340. int rc = 0, c = 0;
  341. iris_hfi_for_each_regulator(device, rinfo) {
  342. rc = __hand_off_regulator(device, rinfo);
  343. /*
  344. * If one regulator hand off failed, driver should take
  345. * the control for other regulators back.
  346. */
  347. if (rc)
  348. goto err_reg_handoff_failed;
  349. c++;
  350. }
  351. return rc;
  352. err_reg_handoff_failed:
  353. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  354. __acquire_regulator(rinfo, device);
  355. return rc;
  356. }
  357. static int __take_back_regulators(struct iris_hfi_device *device)
  358. {
  359. struct regulator_info *rinfo;
  360. int rc = 0;
  361. iris_hfi_for_each_regulator(device, rinfo) {
  362. rc = __acquire_regulator(rinfo, device);
  363. /*
  364. * if one regulator hand off failed, driver should take
  365. * the control for other regulators back.
  366. */
  367. if (rc)
  368. return rc;
  369. }
  370. return rc;
  371. }
  372. static int __write_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  373. bool *rx_req_is_set)
  374. {
  375. struct cvp_hfi_queue_header *queue;
  376. struct cvp_hfi_cmd_session_hdr *cmd_pkt;
  377. u32 packet_size_in_words, new_write_idx;
  378. u32 empty_space, read_idx, write_idx;
  379. u32 *write_ptr;
  380. if (!qinfo || !packet) {
  381. dprintk(CVP_ERR, "Invalid Params\n");
  382. return -EINVAL;
  383. } else if (!qinfo->q_array.align_virtual_addr) {
  384. dprintk(CVP_WARN, "Queues have already been freed\n");
  385. return -EINVAL;
  386. }
  387. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  388. if (!queue) {
  389. dprintk(CVP_ERR, "queue not present\n");
  390. return -ENOENT;
  391. }
  392. cmd_pkt = (struct cvp_hfi_cmd_session_hdr *)packet;
  393. if (cmd_pkt->size >= sizeof(struct cvp_hfi_cmd_session_hdr))
  394. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  395. __func__, cmd_pkt->packet_type,
  396. cmd_pkt->session_id,
  397. cmd_pkt->client_data.transaction_id,
  398. cmd_pkt->client_data.kdata & (FENCE_BIT - 1));
  399. else if (cmd_pkt->size >= 12)
  400. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x\n", __func__,
  401. cmd_pkt->packet_type, cmd_pkt->session_id);
  402. if (msm_cvp_debug & CVP_PKT) {
  403. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  404. __dump_packet(packet, CVP_PKT);
  405. }
  406. packet_size_in_words = (*(u32 *)packet) >> 2;
  407. if (!packet_size_in_words || packet_size_in_words >
  408. qinfo->q_array.mem_size>>2) {
  409. dprintk(CVP_ERR, "Invalid packet size\n");
  410. return -ENODATA;
  411. }
  412. spin_lock(&qinfo->hfi_lock);
  413. read_idx = queue->qhdr_read_idx;
  414. write_idx = queue->qhdr_write_idx;
  415. empty_space = (write_idx >= read_idx) ?
  416. ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) :
  417. (read_idx - write_idx);
  418. if (empty_space <= packet_size_in_words) {
  419. queue->qhdr_tx_req = 1;
  420. spin_unlock(&qinfo->hfi_lock);
  421. dprintk(CVP_ERR, "Insufficient size (%d) to write (%d)\n",
  422. empty_space, packet_size_in_words);
  423. return -ENOTEMPTY;
  424. }
  425. queue->qhdr_tx_req = 0;
  426. new_write_idx = write_idx + packet_size_in_words;
  427. write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  428. (write_idx << 2));
  429. if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  430. write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  431. qinfo->q_array.mem_size)) {
  432. spin_unlock(&qinfo->hfi_lock);
  433. dprintk(CVP_ERR, "Invalid write index\n");
  434. return -ENODATA;
  435. }
  436. if (new_write_idx < (qinfo->q_array.mem_size >> 2)) {
  437. memcpy(write_ptr, packet, packet_size_in_words << 2);
  438. } else {
  439. new_write_idx -= qinfo->q_array.mem_size >> 2;
  440. memcpy(write_ptr, packet, (packet_size_in_words -
  441. new_write_idx) << 2);
  442. memcpy((void *)qinfo->q_array.align_virtual_addr,
  443. packet + ((packet_size_in_words - new_write_idx) << 2),
  444. new_write_idx << 2);
  445. }
  446. /*
  447. * Memory barrier to make sure packet is written before updating the
  448. * write index
  449. */
  450. mb();
  451. queue->qhdr_write_idx = new_write_idx;
  452. if (rx_req_is_set)
  453. *rx_req_is_set = queue->qhdr_rx_req == 1;
  454. /*
  455. * Memory barrier to make sure write index is updated before an
  456. * interrupt is raised.
  457. */
  458. mb();
  459. spin_unlock(&qinfo->hfi_lock);
  460. return 0;
  461. }
  462. static int __read_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  463. u32 *pb_tx_req_is_set)
  464. {
  465. struct cvp_hfi_queue_header *queue;
  466. struct cvp_hfi_msg_session_hdr *msg_pkt;
  467. u32 packet_size_in_words, new_read_idx;
  468. u32 *read_ptr;
  469. u32 receive_request = 0;
  470. u32 read_idx, write_idx;
  471. int rc = 0;
  472. if (!qinfo || !packet || !pb_tx_req_is_set) {
  473. dprintk(CVP_ERR, "Invalid Params\n");
  474. return -EINVAL;
  475. } else if (!qinfo->q_array.align_virtual_addr) {
  476. dprintk(CVP_WARN, "Queues have already been freed\n");
  477. return -EINVAL;
  478. }
  479. /*
  480. * Memory barrier to make sure data is valid before
  481. *reading it
  482. */
  483. mb();
  484. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  485. if (!queue) {
  486. dprintk(CVP_ERR, "Queue memory is not allocated\n");
  487. return -ENOMEM;
  488. }
  489. /*
  490. * Do not set receive request for debug queue, if set,
  491. * Iris generates interrupt for debug messages even
  492. * when there is no response message available.
  493. * In general debug queue will not become full as it
  494. * is being emptied out for every interrupt from Iris.
  495. * Iris will anyway generates interrupt if it is full.
  496. */
  497. spin_lock(&qinfo->hfi_lock);
  498. if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q)
  499. receive_request = 1;
  500. read_idx = queue->qhdr_read_idx;
  501. write_idx = queue->qhdr_write_idx;
  502. if (read_idx == write_idx) {
  503. queue->qhdr_rx_req = receive_request;
  504. /*
  505. * mb() to ensure qhdr is updated in main memory
  506. * so that iris reads the updated header values
  507. */
  508. mb();
  509. *pb_tx_req_is_set = 0;
  510. if (write_idx != queue->qhdr_write_idx) {
  511. queue->qhdr_rx_req = 0;
  512. } else {
  513. spin_unlock(&qinfo->hfi_lock);
  514. dprintk(CVP_HFI,
  515. "%s queue is empty, rx_req = %u, tx_req = %u, read_idx = %u\n",
  516. receive_request ? "message" : "debug",
  517. queue->qhdr_rx_req, queue->qhdr_tx_req,
  518. queue->qhdr_read_idx);
  519. return -ENODATA;
  520. }
  521. }
  522. read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  523. (read_idx << 2));
  524. if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  525. read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  526. qinfo->q_array.mem_size - sizeof(*read_ptr))) {
  527. spin_unlock(&qinfo->hfi_lock);
  528. dprintk(CVP_ERR, "Invalid read index\n");
  529. return -ENODATA;
  530. }
  531. packet_size_in_words = (*read_ptr) >> 2;
  532. if (!packet_size_in_words) {
  533. spin_unlock(&qinfo->hfi_lock);
  534. dprintk(CVP_ERR, "Zero packet size\n");
  535. return -ENODATA;
  536. }
  537. new_read_idx = read_idx + packet_size_in_words;
  538. if (((packet_size_in_words << 2) <= CVP_IFACEQ_VAR_HUGE_PKT_SIZE)
  539. && read_idx <= (qinfo->q_array.mem_size >> 2)) {
  540. if (new_read_idx < (qinfo->q_array.mem_size >> 2)) {
  541. memcpy(packet, read_ptr,
  542. packet_size_in_words << 2);
  543. } else {
  544. new_read_idx -= (qinfo->q_array.mem_size >> 2);
  545. memcpy(packet, read_ptr,
  546. (packet_size_in_words - new_read_idx) << 2);
  547. memcpy(packet + ((packet_size_in_words -
  548. new_read_idx) << 2),
  549. (u8 *)qinfo->q_array.align_virtual_addr,
  550. new_read_idx << 2);
  551. }
  552. } else {
  553. dprintk(CVP_WARN,
  554. "BAD packet received, read_idx: %#x, pkt_size: %d\n",
  555. read_idx, packet_size_in_words << 2);
  556. dprintk(CVP_WARN, "Dropping this packet\n");
  557. new_read_idx = write_idx;
  558. rc = -ENODATA;
  559. }
  560. if (new_read_idx != queue->qhdr_write_idx)
  561. queue->qhdr_rx_req = 0;
  562. else
  563. queue->qhdr_rx_req = receive_request;
  564. queue->qhdr_read_idx = new_read_idx;
  565. /*
  566. * mb() to ensure qhdr is updated in main memory
  567. * so that iris reads the updated header values
  568. */
  569. mb();
  570. *pb_tx_req_is_set = (queue->qhdr_tx_req == 1) ? 1 : 0;
  571. spin_unlock(&qinfo->hfi_lock);
  572. if (!(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  573. msg_pkt = (struct cvp_hfi_msg_session_hdr *)packet;
  574. dprintk(CVP_CMD, "%s: "
  575. "pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  576. __func__, msg_pkt->packet_type,
  577. msg_pkt->session_id,
  578. msg_pkt->client_data.transaction_id,
  579. msg_pkt->client_data.kdata & (FENCE_BIT - 1));
  580. }
  581. if ((msm_cvp_debug & CVP_PKT) &&
  582. !(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  583. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  584. __dump_packet(packet, CVP_PKT);
  585. }
  586. return rc;
  587. }
  588. static int __smem_alloc(struct iris_hfi_device *dev, struct cvp_mem_addr *mem,
  589. u32 size, u32 align, u32 flags)
  590. {
  591. struct msm_cvp_smem *alloc = &mem->mem_data;
  592. int rc = 0;
  593. if (!dev || !mem || !size) {
  594. dprintk(CVP_ERR, "Invalid Params\n");
  595. return -EINVAL;
  596. }
  597. dprintk(CVP_INFO, "start to alloc size: %d, flags: %d\n", size, flags);
  598. alloc->flags = flags;
  599. rc = msm_cvp_smem_alloc(size, align, 1, (void *)dev->res, alloc);
  600. if (rc) {
  601. dprintk(CVP_ERR, "Alloc failed\n");
  602. rc = -ENOMEM;
  603. goto fail_smem_alloc;
  604. }
  605. dprintk(CVP_MEM, "%s: ptr = %pK, size = %d\n", __func__,
  606. alloc->kvaddr, size);
  607. mem->mem_size = alloc->size;
  608. mem->align_virtual_addr = alloc->kvaddr;
  609. mem->align_device_addr = alloc->device_addr;
  610. alloc->pkt_type = 0;
  611. alloc->buf_idx = 0;
  612. return rc;
  613. fail_smem_alloc:
  614. return rc;
  615. }
  616. static void __smem_free(struct iris_hfi_device *dev, struct msm_cvp_smem *mem)
  617. {
  618. if (!dev || !mem) {
  619. dprintk(CVP_ERR, "invalid param %pK %pK\n", dev, mem);
  620. return;
  621. }
  622. msm_cvp_smem_free(mem);
  623. }
  624. static void __write_register(struct iris_hfi_device *device,
  625. u32 reg, u32 value)
  626. {
  627. u32 hwiosymaddr = reg;
  628. u8 *base_addr;
  629. if (!device) {
  630. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  631. return;
  632. }
  633. __strict_check(device);
  634. if (!device->power_enabled) {
  635. dprintk(CVP_WARN,
  636. "HFI Write register failed : Power is OFF\n");
  637. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  638. return;
  639. }
  640. base_addr = device->cvp_hal_data->register_base;
  641. dprintk(CVP_REG, "Base addr: %pK, written to: %#x, Value: %#x...\n",
  642. base_addr, hwiosymaddr, value);
  643. base_addr += hwiosymaddr;
  644. writel_relaxed(value, base_addr);
  645. /*
  646. * Memory barrier to make sure value is written into the register.
  647. */
  648. wmb();
  649. }
  650. static int __read_gcc_register(struct iris_hfi_device *device, u32 reg)
  651. {
  652. int rc = 0;
  653. u8 *base_addr;
  654. if (!device) {
  655. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  656. return -EINVAL;
  657. }
  658. __strict_check(device);
  659. if (!device->power_enabled) {
  660. dprintk(CVP_WARN,
  661. "%s HFI Read register failed : Power is OFF\n",
  662. __func__);
  663. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  664. return -EINVAL;
  665. }
  666. base_addr = device->cvp_hal_data->gcc_reg_base;
  667. rc = readl_relaxed(base_addr + reg);
  668. /*
  669. * Memory barrier to make sure value is read correctly from the
  670. * register.
  671. */
  672. rmb();
  673. dprintk(CVP_REG,
  674. "GCC Base addr: %pK, read from: %#x, value: %#x...\n",
  675. base_addr, reg, rc);
  676. return rc;
  677. }
  678. static int __read_register(struct iris_hfi_device *device, u32 reg)
  679. {
  680. int rc = 0;
  681. u8 *base_addr;
  682. if (!device) {
  683. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  684. return -EINVAL;
  685. }
  686. __strict_check(device);
  687. if (!device->power_enabled) {
  688. dprintk(CVP_WARN,
  689. "HFI Read register failed : Power is OFF\n");
  690. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  691. return -EINVAL;
  692. }
  693. base_addr = device->cvp_hal_data->register_base;
  694. rc = readl_relaxed(base_addr + reg);
  695. /*
  696. * Memory barrier to make sure value is read correctly from the
  697. * register.
  698. */
  699. rmb();
  700. dprintk(CVP_REG, "Base addr: %pK, read from: %#x, value: %#x...\n",
  701. base_addr, reg, rc);
  702. return rc;
  703. }
  704. static bool __is_ctl_power_on(struct iris_hfi_device *device)
  705. {
  706. u32 reg;
  707. reg = __read_register(device, CVP_CC_MVS1C_GDSCR);
  708. if (!(reg & 0x80000000))
  709. return false;
  710. reg = __read_register(device, CVP_CC_MVS1C_CBCR);
  711. if (reg & 0x80000000)
  712. return false;
  713. return true;
  714. }
  715. static int __set_registers(struct iris_hfi_device *device)
  716. {
  717. struct msm_cvp_core *core;
  718. struct msm_cvp_platform_data *pdata;
  719. struct reg_set *reg_set;
  720. int i;
  721. if (!device->res) {
  722. dprintk(CVP_ERR,
  723. "device resources null, cannot set registers\n");
  724. return -EINVAL ;
  725. }
  726. core = cvp_driver->cvp_core;
  727. pdata = core->platform_data;
  728. reg_set = &device->res->reg_set;
  729. for (i = 0; i < reg_set->count; i++) {
  730. __write_register(device, reg_set->reg_tbl[i].reg,
  731. reg_set->reg_tbl[i].value);
  732. dprintk(CVP_REG, "write_reg offset=%x, val=%x\n",
  733. reg_set->reg_tbl[i].reg,
  734. reg_set->reg_tbl[i].value);
  735. }
  736. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  737. if (i) {
  738. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  739. return -EINVAL;
  740. }
  741. __write_register(device, CVP_CPU_CS_AXI4_QOS,
  742. pdata->noc_qos->axi_qos);
  743. __write_register(device,
  744. CVP_NOC_RGE_PRIORITYLUT_LOW +
  745. device->res->qos_noc_rge_niu_offset,
  746. pdata->noc_qos->prioritylut_low);
  747. __write_register(device,
  748. CVP_NOC_RGE_PRIORITYLUT_HIGH +
  749. device->res->qos_noc_rge_niu_offset,
  750. pdata->noc_qos->prioritylut_high);
  751. __write_register(device,
  752. CVP_NOC_RGE_URGENCY_LOW +
  753. device->res->qos_noc_rge_niu_offset,
  754. pdata->noc_qos->urgency_low);
  755. __write_register(device,
  756. CVP_NOC_RGE_DANGERLUT_LOW +
  757. device->res->qos_noc_rge_niu_offset,
  758. pdata->noc_qos->dangerlut_low);
  759. __write_register(device,
  760. CVP_NOC_RGE_SAFELUT_LOW +
  761. device->res->qos_noc_rge_niu_offset,
  762. pdata->noc_qos->safelut_low);
  763. __write_register(device,
  764. CVP_NOC_GCE_PRIORITYLUT_LOW +
  765. device->res->qos_noc_gce_vadl_tof_niu_offset,
  766. pdata->noc_qos->prioritylut_low);
  767. __write_register(device,
  768. CVP_NOC_GCE_PRIORITYLUT_HIGH +
  769. device->res->qos_noc_gce_vadl_tof_niu_offset,
  770. pdata->noc_qos->prioritylut_high);
  771. __write_register(device,
  772. CVP_NOC_GCE_URGENCY_LOW +
  773. device->res->qos_noc_gce_vadl_tof_niu_offset,
  774. pdata->noc_qos->urgency_low);
  775. __write_register(device,
  776. CVP_NOC_GCE_DANGERLUT_LOW +
  777. device->res->qos_noc_gce_vadl_tof_niu_offset,
  778. pdata->noc_qos->dangerlut_low);
  779. __write_register(device,
  780. CVP_NOC_GCE_SAFELUT_LOW +
  781. device->res->qos_noc_gce_vadl_tof_niu_offset,
  782. pdata->noc_qos->safelut_low);
  783. __write_register(device,
  784. CVP_NOC_CDM_PRIORITYLUT_LOW +
  785. device->res->qos_noc_cdm_niu_offset,
  786. pdata->noc_qos->prioritylut_low);
  787. __write_register(device,
  788. CVP_NOC_CDM_PRIORITYLUT_HIGH +
  789. device->res->qos_noc_cdm_niu_offset,
  790. pdata->noc_qos->prioritylut_high);
  791. __write_register(device,
  792. CVP_NOC_CDM_URGENCY_LOW +
  793. device->res->qos_noc_cdm_niu_offset,
  794. pdata->noc_qos->urgency_low_ro);
  795. __write_register(device,
  796. CVP_NOC_CDM_DANGERLUT_LOW +
  797. device->res->qos_noc_cdm_niu_offset,
  798. pdata->noc_qos->dangerlut_low);
  799. __write_register(device,
  800. CVP_NOC_CDM_SAFELUT_LOW +
  801. device->res->qos_noc_cdm_niu_offset,
  802. pdata->noc_qos->safelut_low);
  803. /* Below registers write moved from FW to SW to enable UBWC */
  804. __write_register(device,
  805. CVP_NOC_RGE_NIU_DECCTL_LOW +
  806. device->res->qos_noc_rge_niu_offset,
  807. 0x1);
  808. __write_register(device,
  809. CVP_NOC_RGE_NIU_ENCCTL_LOW +
  810. device->res->qos_noc_rge_niu_offset,
  811. 0x1);
  812. __write_register(device,
  813. CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW +
  814. device->res->qos_noc_gce_vadl_tof_niu_offset,
  815. 0x1);
  816. __write_register(device,
  817. CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW +
  818. device->res->qos_noc_gce_vadl_tof_niu_offset,
  819. 0x1);
  820. __write_register(device,
  821. CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS +
  822. device->res->noc_core_err_offset,
  823. 0x3);
  824. __write_register(device,
  825. CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW +
  826. device->res->noc_main_sidebandmanager_offset,
  827. 0x1);
  828. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  829. return 0;
  830. }
  831. /*
  832. * The existence of this function is a hack for 8996 (or certain Iris versions)
  833. * to overcome a hardware bug. Whenever the GDSCs momentarily power collapse
  834. * (after calling __hand_off_regulators()), the values of the threshold
  835. * registers (typically programmed by TZ) are incorrectly reset. As a result
  836. * reprogram these registers at certain agreed upon points.
  837. */
  838. static void __set_threshold_registers(struct iris_hfi_device *device)
  839. {
  840. u32 version = __read_register(device, CVP_WRAPPER_HW_VERSION);
  841. version &= ~GENMASK(15, 0);
  842. if (version != (0x3 << 28 | 0x43 << 16))
  843. return;
  844. if (__tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESTORE_THRESHOLD))
  845. dprintk(CVP_ERR, "Failed to restore threshold values\n");
  846. }
  847. static int __unvote_buses(struct iris_hfi_device *device)
  848. {
  849. int rc = 0;
  850. struct bus_info *bus = NULL;
  851. kfree(device->bus_vote.data);
  852. device->bus_vote.data = NULL;
  853. device->bus_vote.data_count = 0;
  854. iris_hfi_for_each_bus(device, bus) {
  855. rc = cvp_set_bw(bus, 0);
  856. if (rc) {
  857. dprintk(CVP_ERR,
  858. "%s: Failed unvoting bus\n", __func__);
  859. goto err_unknown_device;
  860. }
  861. }
  862. err_unknown_device:
  863. return rc;
  864. }
  865. static int __vote_buses(struct iris_hfi_device *device,
  866. struct cvp_bus_vote_data *data, int num_data)
  867. {
  868. int rc = 0;
  869. struct bus_info *bus = NULL;
  870. struct cvp_bus_vote_data *new_data = NULL;
  871. if (!num_data) {
  872. dprintk(CVP_PWR, "No vote data available\n");
  873. goto no_data_count;
  874. } else if (!data) {
  875. dprintk(CVP_ERR, "Invalid voting data\n");
  876. return -EINVAL;
  877. }
  878. new_data = kmemdup(data, num_data * sizeof(*new_data), GFP_KERNEL);
  879. if (!new_data) {
  880. dprintk(CVP_ERR, "Can't alloc memory to cache bus votes\n");
  881. rc = -ENOMEM;
  882. goto err_no_mem;
  883. }
  884. no_data_count:
  885. kfree(device->bus_vote.data);
  886. device->bus_vote.data = new_data;
  887. device->bus_vote.data_count = num_data;
  888. iris_hfi_for_each_bus(device, bus) {
  889. if (bus) {
  890. rc = cvp_set_bw(bus, bus->range[1]);
  891. if (rc)
  892. dprintk(CVP_ERR,
  893. "Failed voting bus %s to ab %u\n",
  894. bus->name, bus->range[1]*1000);
  895. }
  896. }
  897. err_no_mem:
  898. return rc;
  899. }
  900. static int iris_hfi_vote_buses(void *dev, struct bus_info *bus, unsigned long bw)
  901. {
  902. int rc = 0;
  903. struct iris_hfi_device *device = dev;
  904. if (!device)
  905. return -EINVAL;
  906. mutex_lock(&device->lock);
  907. rc = cvp_set_bw(bus, bw);
  908. mutex_unlock(&device->lock);
  909. return rc;
  910. }
  911. static int __core_set_resource(struct iris_hfi_device *device,
  912. struct cvp_resource_hdr *resource_hdr, void *resource_value)
  913. {
  914. struct cvp_hfi_cmd_sys_set_resource_packet *pkt;
  915. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  916. int rc = 0;
  917. if (!device || !resource_hdr || !resource_value) {
  918. dprintk(CVP_ERR, "set_res: Invalid Params\n");
  919. return -EINVAL;
  920. }
  921. pkt = (struct cvp_hfi_cmd_sys_set_resource_packet *) packet;
  922. rc = call_hfi_pkt_op(device, sys_set_resource,
  923. pkt, resource_hdr, resource_value);
  924. if (rc) {
  925. dprintk(CVP_ERR, "set_res: failed to create packet\n");
  926. goto err_create_pkt;
  927. }
  928. rc = __iface_cmdq_write(device, pkt);
  929. if (rc)
  930. rc = -ENOTEMPTY;
  931. err_create_pkt:
  932. return rc;
  933. }
  934. static int __core_release_resource(struct iris_hfi_device *device,
  935. struct cvp_resource_hdr *resource_hdr)
  936. {
  937. struct cvp_hfi_cmd_sys_release_resource_packet *pkt;
  938. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  939. int rc = 0;
  940. if (!device || !resource_hdr) {
  941. dprintk(CVP_ERR, "release_res: Invalid Params\n");
  942. return -EINVAL;
  943. }
  944. pkt = (struct cvp_hfi_cmd_sys_release_resource_packet *) packet;
  945. rc = call_hfi_pkt_op(device, sys_release_resource,
  946. pkt, resource_hdr);
  947. if (rc) {
  948. dprintk(CVP_ERR, "release_res: failed to create packet\n");
  949. goto err_create_pkt;
  950. }
  951. rc = __iface_cmdq_write(device, pkt);
  952. if (rc)
  953. rc = -ENOTEMPTY;
  954. err_create_pkt:
  955. return rc;
  956. }
  957. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state)
  958. {
  959. int rc = 0;
  960. rc = qcom_scm_set_remote_state(state, TZBSP_CVP_PAS_ID);
  961. dprintk(CVP_CORE, "Set state %d, resp %d\n", state, rc);
  962. if (rc) {
  963. dprintk(CVP_ERR, "Failed qcom_scm_set_remote_state %d\n", rc);
  964. return rc;
  965. }
  966. return 0;
  967. }
  968. /*
  969. * Based on fal10_veto, X2RPMh, core_pwr_on and PWAitMode value, infer
  970. * value of xtss_sw_reset. xtss_sw_reset is a TZ register bit. Driver
  971. * cannot access it directly.
  972. *
  973. * In __boot_firmware() function, the caller of this function. It checks
  974. * "core_pwr_on" == false, basically core powered off. So this function
  975. * doesn't check core_pwr_on. Assume core_pwr_on = false.
  976. *
  977. * fal10_veto = VPU_CPU_CS_X2RPMh[2] |
  978. * ( ~VPU_CPU_CS_X2RPMh[1] & core_pwr_on ) |
  979. * ( ~VPU_CPU_CS_X2RPMh[0] & ~( xtss_sw_reset | PWaitMode ) ) ;
  980. */
  981. static inline void check_tensilica_in_reset(struct iris_hfi_device *device)
  982. {
  983. u32 X2RPMh, fal10_veto, wait_mode;
  984. X2RPMh = __read_register(device, CVP_CPU_CS_X2RPMh);
  985. X2RPMh = X2RPMh & 0x7;
  986. /* wait_mode = 1: Tensilica is in WFI mode (PWaitMode = true) */
  987. wait_mode = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  988. wait_mode = wait_mode & 0x1;
  989. fal10_veto = __read_register(device, CVP_CPU_CS_X2RPMh_STATUS);
  990. fal10_veto = fal10_veto & 0x1;
  991. dprintk(CVP_WARN, "tensilica reset check %#x %#x %#x\n",
  992. X2RPMh, wait_mode, fal10_veto);
  993. }
  994. static const char boot_states[0x40][32] = {
  995. "NOT INIT",
  996. "RST_START",
  997. "INIT_MEMCTL",
  998. "INTENABLE_RST",
  999. "LITBASE_RST",
  1000. "PREFETCH_EN",
  1001. "MPU_INIT",
  1002. "CTRL_INIT_READ",
  1003. "MEMCTL_L1_FIX",
  1004. "RESTORE_EXTRA_NW",
  1005. "CORE_RESTORE",
  1006. "COLD_BOOT",
  1007. "DISABLE_CACHE",
  1008. "BEFORE_MPU_C",
  1009. "RET_MPU_C",
  1010. "IN_MPU_C",
  1011. "IN_MPU_DEFAULT",
  1012. "IN_MPU_SYNX",
  1013. "UCR_SIZE_FAIL",
  1014. "UCR_ADDR_FAIL",
  1015. "UCR1_SIZE_FAIL",
  1016. "UCR1_ADDR_FAIL",
  1017. "UCR_OVERLAPPED_UCR1",
  1018. "UCR1_OVERLAPPED_UCR",
  1019. "UCR_EQ_UCR1",
  1020. "MPU_CHECK_DONE",
  1021. "BEFORE_INT_LOCK",
  1022. "AFTER_INT_LOCK",
  1023. "BEFORE_INT_UNLOCK",
  1024. "AFTER_INT_UNLOCK",
  1025. "CALL_START",
  1026. "MAIN_ENTRY",
  1027. "VENUS_INIT_ENTRY",
  1028. "VSYS_INIT_ENTRY",
  1029. "BEFORE_XOS_CLK",
  1030. "AFTER_XOS_CLK",
  1031. "LOG_MUTEX_INIT",
  1032. "CREATE_FRAMEWORK_ENTRY",
  1033. "DTG_INIT",
  1034. "IDLE_TASK_INIT",
  1035. "VENUS_CORE_INIT",
  1036. "HW_CORES_INIT",
  1037. "RST_THREAD_INIT",
  1038. "HOST_THREAD_INIT",
  1039. "ALL_THREADS_INIT",
  1040. "TASK_MEMPOOL",
  1041. "SESSION_MUTEX",
  1042. "SIGNALS_INIT",
  1043. "RST_SIGNAL_INIT",
  1044. "INTR_EN_HOST",
  1045. "INTR_REG_HOST",
  1046. "INTR_EN_DSP",
  1047. "INTR_REG_DSP",
  1048. "X2HSOFTINTEN",
  1049. "H2XSOFTINTEN",
  1050. "CPU2DSPINTEN",
  1051. "DSP2CPUINT_SWRESET",
  1052. "THREADS_START",
  1053. "RST_THREAD_START",
  1054. "HST_THREAD_START",
  1055. "HST_THREAD_ENTRY"
  1056. };
  1057. static inline int __boot_firmware(struct iris_hfi_device *device)
  1058. {
  1059. int rc = 0, loop = 10;
  1060. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 5000;
  1061. u32 reg_gdsc;
  1062. /*
  1063. * Hand off control of regulators to h/w _after_ enabling clocks.
  1064. * Note that the GDSC will turn off when switching from normal
  1065. * (s/w triggered) to fast (HW triggered) unless the h/w vote is
  1066. * present. Since Iris isn't up yet, the GDSC will be off briefly.
  1067. */
  1068. if (__enable_hw_power_collapse(device))
  1069. dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
  1070. if (!msm_cvp_fw_low_power_mode)
  1071. goto skip_core_power_check;
  1072. while (loop) {
  1073. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  1074. if (reg_gdsc & 0x80000000) {
  1075. usleep_range(100, 200);
  1076. loop--;
  1077. } else {
  1078. break;
  1079. }
  1080. }
  1081. if (!loop)
  1082. dprintk(CVP_ERR, "fail to power off CORE during resume\n");
  1083. skip_core_power_check:
  1084. ctrl_init_val = BIT(0);
  1085. /* RUMI: CVP_CTRL_INIT in MPTest has bit 0 and 3 set */
  1086. __write_register(device, CVP_CTRL_INIT, ctrl_init_val);
  1087. while (!(ctrl_status & CVP_CTRL_INIT_STATUS__M) && count < max_tries) {
  1088. ctrl_status = __read_register(device, CVP_CTRL_STATUS);
  1089. if ((ctrl_status & CVP_CTRL_ERROR_STATUS__M) == 0x4) {
  1090. dprintk(CVP_ERR, "invalid setting for UC_REGION\n");
  1091. rc = -ENODATA;
  1092. break;
  1093. }
  1094. /* Reduce to 50, 100 on silicon */
  1095. usleep_range(50, 100);
  1096. count++;
  1097. }
  1098. if (!(ctrl_status & CVP_CTRL_INIT_STATUS__M)) {
  1099. ctrl_init_val = __read_register(device, CVP_CTRL_INIT);
  1100. dprintk(CVP_ERR,
  1101. "Failed to boot FW status: %x %x %s\n",
  1102. ctrl_status, ctrl_init_val,
  1103. boot_states[(ctrl_status >> 9) & 0x3f]);
  1104. check_tensilica_in_reset(device);
  1105. rc = -ENODEV;
  1106. }
  1107. /* Enable interrupt before sending commands to tensilica */
  1108. __write_register(device, CVP_CPU_CS_H2XSOFTINTEN, 0x1);
  1109. __write_register(device, CVP_CPU_CS_X2RPMh, 0x0);
  1110. return rc;
  1111. }
  1112. static int iris_hfi_resume(void *dev)
  1113. {
  1114. int rc = 0;
  1115. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1116. if (!device) {
  1117. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1118. return -EINVAL;
  1119. }
  1120. dprintk(CVP_CORE, "Resuming Iris\n");
  1121. mutex_lock(&device->lock);
  1122. rc = __resume(device);
  1123. mutex_unlock(&device->lock);
  1124. return rc;
  1125. }
  1126. static int iris_hfi_suspend(void *dev)
  1127. {
  1128. int rc = 0;
  1129. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1130. if (!device) {
  1131. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1132. return -EINVAL;
  1133. } else if (!device->res->sw_power_collapsible) {
  1134. return -ENOTSUPP;
  1135. }
  1136. dprintk(CVP_CORE, "Suspending Iris\n");
  1137. mutex_lock(&device->lock);
  1138. rc = __power_collapse(device, true);
  1139. if (rc) {
  1140. dprintk(CVP_WARN, "%s: Iris is busy\n", __func__);
  1141. rc = -EBUSY;
  1142. }
  1143. mutex_unlock(&device->lock);
  1144. /* Cancel pending delayed works if any */
  1145. if (!rc)
  1146. cancel_delayed_work(&iris_hfi_pm_work);
  1147. return rc;
  1148. }
  1149. void cvp_dump_csr(struct iris_hfi_device *dev)
  1150. {
  1151. u32 reg;
  1152. if (!dev)
  1153. return;
  1154. if (!dev->power_enabled || dev->reg_dumped)
  1155. return;
  1156. reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
  1157. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
  1158. reg = __read_register(dev, CVP_CPU_CS_SCIACMDARG0);
  1159. dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
  1160. //reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
  1161. //dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
  1162. //reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
  1163. //dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
  1164. reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
  1165. dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
  1166. reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
  1167. dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
  1168. reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
  1169. dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
  1170. reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
  1171. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
  1172. reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  1173. dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
  1174. dump_noc_reg(dev);
  1175. dev->reg_dumped = true;
  1176. }
  1177. static int iris_hfi_flush_debug_queue(void *dev)
  1178. {
  1179. int rc = 0;
  1180. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1181. if (!device) {
  1182. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1183. return -EINVAL;
  1184. }
  1185. mutex_lock(&device->lock);
  1186. if (!device->power_enabled) {
  1187. dprintk(CVP_WARN, "%s: iris power off\n", __func__);
  1188. rc = -EINVAL;
  1189. goto exit;
  1190. }
  1191. cvp_dump_csr(device);
  1192. __flush_debug_queue(device, NULL);
  1193. exit:
  1194. mutex_unlock(&device->lock);
  1195. return rc;
  1196. }
  1197. static int iris_hfi_scale_clocks(void *dev, u32 freq)
  1198. {
  1199. int rc = 0;
  1200. struct iris_hfi_device *device = dev;
  1201. if (!device) {
  1202. dprintk(CVP_ERR, "Invalid args: %pK\n", device);
  1203. return -EINVAL;
  1204. }
  1205. mutex_lock(&device->lock);
  1206. if (__resume(device)) {
  1207. dprintk(CVP_ERR, "Resume from power collapse failed\n");
  1208. rc = -ENODEV;
  1209. goto exit;
  1210. }
  1211. rc = msm_cvp_set_clocks_impl(device, freq);
  1212. exit:
  1213. mutex_unlock(&device->lock);
  1214. return rc;
  1215. }
  1216. /* Writes into cmdq without raising an interrupt */
  1217. static int __iface_cmdq_write_relaxed(struct iris_hfi_device *device,
  1218. void *pkt, bool *requires_interrupt)
  1219. {
  1220. struct cvp_iface_q_info *q_info;
  1221. struct cvp_hal_cmd_pkt_hdr *cmd_packet;
  1222. int result = -E2BIG;
  1223. if (!device || !pkt) {
  1224. dprintk(CVP_ERR, "Invalid Params\n");
  1225. return -EINVAL;
  1226. }
  1227. __strict_check(device);
  1228. if (!__core_in_valid_state(device)) {
  1229. dprintk(CVP_ERR, "%s - fw not in init state\n", __func__);
  1230. result = -EINVAL;
  1231. goto err_q_null;
  1232. }
  1233. cmd_packet = (struct cvp_hal_cmd_pkt_hdr *)pkt;
  1234. device->last_packet_type = cmd_packet->packet_type;
  1235. q_info = &device->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1236. if (!q_info) {
  1237. dprintk(CVP_ERR, "cannot write to shared Q's\n");
  1238. goto err_q_null;
  1239. }
  1240. if (!q_info->q_array.align_virtual_addr) {
  1241. dprintk(CVP_ERR, "cannot write to shared CMD Q's\n");
  1242. result = -ENODATA;
  1243. goto err_q_null;
  1244. }
  1245. if (__resume(device)) {
  1246. dprintk(CVP_ERR, "%s: Power on failed\n", __func__);
  1247. goto err_q_write;
  1248. }
  1249. if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) {
  1250. if (device->res->sw_power_collapsible) {
  1251. cancel_delayed_work(&iris_hfi_pm_work);
  1252. if (!queue_delayed_work(device->iris_pm_workq,
  1253. &iris_hfi_pm_work,
  1254. msecs_to_jiffies(
  1255. device->res->msm_cvp_pwr_collapse_delay))) {
  1256. dprintk(CVP_PWR,
  1257. "PM work already scheduled\n");
  1258. }
  1259. }
  1260. result = 0;
  1261. } else {
  1262. dprintk(CVP_ERR, "__iface_cmdq_write: queue full\n");
  1263. }
  1264. err_q_write:
  1265. err_q_null:
  1266. return result;
  1267. }
  1268. static int __iface_cmdq_write(struct iris_hfi_device *device, void *pkt)
  1269. {
  1270. bool needs_interrupt = false;
  1271. int rc = __iface_cmdq_write_relaxed(device, pkt, &needs_interrupt);
  1272. int i = 0;
  1273. if (!rc && needs_interrupt) {
  1274. /* Consumer of cmdq prefers that we raise an interrupt */
  1275. rc = 0;
  1276. if (!__is_ctl_power_on(device))
  1277. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1278. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  1279. if (i) {
  1280. dprintk(CVP_WARN, "%s Fail acquire xo_reset at %d\n", __func__, __LINE__);
  1281. return -EINVAL;
  1282. }
  1283. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1284. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  1285. }
  1286. return rc;
  1287. }
  1288. static int __iface_msgq_read(struct iris_hfi_device *device, void *pkt)
  1289. {
  1290. u32 tx_req_is_set = 0;
  1291. int rc = 0;
  1292. struct cvp_iface_q_info *q_info;
  1293. int i = 0;
  1294. if (!pkt) {
  1295. dprintk(CVP_ERR, "Invalid Params\n");
  1296. return -EINVAL;
  1297. }
  1298. __strict_check(device);
  1299. if (!__core_in_valid_state(device)) {
  1300. dprintk(CVP_WARN, "%s - fw not in init state\n", __func__);
  1301. rc = -EINVAL;
  1302. goto read_error_null;
  1303. }
  1304. q_info = &device->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1305. if (q_info->q_array.align_virtual_addr == NULL) {
  1306. dprintk(CVP_ERR, "cannot read from shared MSG Q's\n");
  1307. rc = -ENODATA;
  1308. goto read_error_null;
  1309. }
  1310. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1311. if (tx_req_is_set) {
  1312. if (!__is_ctl_power_on(device))
  1313. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1314. i = call_iris_op(device, reset_control_acquire_name, device,
  1315. "cvp_xo_reset");
  1316. if (i) {
  1317. dprintk(CVP_WARN, "%s Fail acquire xo_reset at %d\n",
  1318. __func__, __LINE__);
  1319. return -EINVAL;
  1320. }
  1321. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1322. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  1323. }
  1324. rc = 0;
  1325. } else
  1326. rc = -ENODATA;
  1327. read_error_null:
  1328. return rc;
  1329. }
  1330. static int __iface_dbgq_read(struct iris_hfi_device *device, void *pkt)
  1331. {
  1332. u32 tx_req_is_set = 0;
  1333. int rc = 0;
  1334. struct cvp_iface_q_info *q_info;
  1335. int i = 0;
  1336. if (!pkt) {
  1337. dprintk(CVP_ERR, "Invalid Params\n");
  1338. return -EINVAL;
  1339. }
  1340. __strict_check(device);
  1341. q_info = &device->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1342. if (q_info->q_array.align_virtual_addr == NULL) {
  1343. dprintk(CVP_ERR, "cannot read from shared DBG Q's\n");
  1344. rc = -ENODATA;
  1345. goto dbg_error_null;
  1346. }
  1347. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1348. if (tx_req_is_set) {
  1349. if (!__is_ctl_power_on(device))
  1350. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1351. i = call_iris_op(device, reset_control_acquire_name, device,
  1352. "cvp_xo_reset");
  1353. if (i) {
  1354. dprintk(CVP_WARN, "%s Fail acquire xo_reset at %d\n",
  1355. __func__, __LINE__);
  1356. return -EINVAL;
  1357. }
  1358. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1359. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  1360. }
  1361. rc = 0;
  1362. } else
  1363. rc = -ENODATA;
  1364. dbg_error_null:
  1365. return rc;
  1366. }
  1367. static void __set_queue_hdr_defaults(struct cvp_hfi_queue_header *q_hdr)
  1368. {
  1369. q_hdr->qhdr_status = 0x1;
  1370. q_hdr->qhdr_type = CVP_IFACEQ_DFLT_QHDR;
  1371. q_hdr->qhdr_q_size = CVP_IFACEQ_QUEUE_SIZE / 4;
  1372. q_hdr->qhdr_pkt_size = 0;
  1373. q_hdr->qhdr_rx_wm = 0x1;
  1374. q_hdr->qhdr_tx_wm = 0x1;
  1375. q_hdr->qhdr_rx_req = 0x1;
  1376. q_hdr->qhdr_tx_req = 0x0;
  1377. q_hdr->qhdr_rx_irq_status = 0x0;
  1378. q_hdr->qhdr_tx_irq_status = 0x0;
  1379. q_hdr->qhdr_read_idx = 0x0;
  1380. q_hdr->qhdr_write_idx = 0x0;
  1381. }
  1382. /*
  1383. *Unused, keep for reference
  1384. */
  1385. /*
  1386. static void __interface_dsp_queues_release(struct iris_hfi_device *device)
  1387. {
  1388. int i;
  1389. struct msm_cvp_smem *mem_data = &device->dsp_iface_q_table.mem_data;
  1390. struct context_bank_info *cb = mem_data->mapping_info.cb_info;
  1391. if (!device->dsp_iface_q_table.align_virtual_addr) {
  1392. dprintk(CVP_ERR, "%s: already released\n", __func__);
  1393. return;
  1394. }
  1395. dma_unmap_single_attrs(cb->dev, mem_data->device_addr,
  1396. mem_data->size, DMA_BIDIRECTIONAL, 0);
  1397. dma_free_coherent(device->res->mem_cdsp.dev, mem_data->size,
  1398. mem_data->kvaddr, mem_data->dma_handle);
  1399. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1400. device->dsp_iface_queues[i].q_hdr = NULL;
  1401. device->dsp_iface_queues[i].q_array.align_virtual_addr = NULL;
  1402. device->dsp_iface_queues[i].q_array.align_device_addr = 0;
  1403. }
  1404. device->dsp_iface_q_table.align_virtual_addr = NULL;
  1405. device->dsp_iface_q_table.align_device_addr = 0;
  1406. }
  1407. */
  1408. static int __interface_dsp_queues_init(struct iris_hfi_device *dev)
  1409. {
  1410. int rc = 0;
  1411. u32 i;
  1412. struct cvp_iface_q_info *iface_q;
  1413. int offset = 0;
  1414. phys_addr_t fw_bias = 0;
  1415. size_t q_size;
  1416. struct msm_cvp_smem *mem_data;
  1417. void *kvaddr;
  1418. dma_addr_t dma_handle;
  1419. dma_addr_t iova;
  1420. struct context_bank_info *cb;
  1421. q_size = ALIGN(QUEUE_SIZE, SZ_1M);
  1422. mem_data = &dev->dsp_iface_q_table.mem_data;
  1423. if (mem_data->kvaddr) {
  1424. memset((void *)mem_data->kvaddr, 0, q_size);
  1425. cvp_dsp_init_hfi_queue_hdr(dev);
  1426. return 0;
  1427. }
  1428. /* Allocate dsp queues from CDSP device memory */
  1429. kvaddr = dma_alloc_coherent(dev->res->mem_cdsp.dev, q_size,
  1430. &dma_handle, GFP_KERNEL);
  1431. if (IS_ERR_OR_NULL(kvaddr)) {
  1432. dprintk(CVP_ERR, "%s: failed dma allocation\n", __func__);
  1433. goto fail_dma_alloc;
  1434. }
  1435. cb = msm_cvp_smem_get_context_bank(dev->res, SMEM_CDSP);
  1436. if (!cb) {
  1437. dprintk(CVP_ERR,
  1438. "%s: failed to get DSP context bank\n", __func__);
  1439. goto fail_dma_map;
  1440. }
  1441. iova = dma_map_single_attrs(cb->dev, phys_to_virt(dma_handle),
  1442. q_size, DMA_BIDIRECTIONAL, 0);
  1443. if (dma_mapping_error(cb->dev, iova)) {
  1444. dprintk(CVP_ERR, "%s: failed dma mapping\n", __func__);
  1445. goto fail_dma_map;
  1446. }
  1447. dprintk(CVP_DSP,
  1448. "%s: kvaddr %pK dma_handle %#llx iova %#llx size %zd\n",
  1449. __func__, kvaddr, dma_handle, iova, q_size);
  1450. memset(mem_data, 0, sizeof(struct msm_cvp_smem));
  1451. mem_data->kvaddr = kvaddr;
  1452. mem_data->device_addr = iova;
  1453. mem_data->dma_handle = dma_handle;
  1454. mem_data->size = q_size;
  1455. mem_data->mapping_info.cb_info = cb;
  1456. if (!is_iommu_present(dev->res))
  1457. fw_bias = dev->cvp_hal_data->firmware_base;
  1458. dev->dsp_iface_q_table.align_virtual_addr = kvaddr;
  1459. dev->dsp_iface_q_table.align_device_addr = iova - fw_bias;
  1460. dev->dsp_iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1461. offset = dev->dsp_iface_q_table.mem_size;
  1462. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1463. iface_q = &dev->dsp_iface_queues[i];
  1464. iface_q->q_array.align_device_addr = iova + offset - fw_bias;
  1465. iface_q->q_array.align_virtual_addr = kvaddr + offset;
  1466. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1467. offset += iface_q->q_array.mem_size;
  1468. spin_lock_init(&iface_q->hfi_lock);
  1469. }
  1470. cvp_dsp_init_hfi_queue_hdr(dev);
  1471. return rc;
  1472. fail_dma_map:
  1473. dma_free_coherent(dev->res->mem_cdsp.dev, q_size, kvaddr, dma_handle);
  1474. fail_dma_alloc:
  1475. return -ENOMEM;
  1476. }
  1477. static void __interface_queues_release(struct iris_hfi_device *device)
  1478. {
  1479. #ifdef CONFIG_EVA_TVM
  1480. int i;
  1481. struct cvp_hfi_mem_map_table *qdss;
  1482. struct cvp_hfi_mem_map *mem_map;
  1483. int num_entries = device->res->qdss_addr_set.count;
  1484. unsigned long mem_map_table_base_addr;
  1485. struct context_bank_info *cb;
  1486. if (device->qdss.align_virtual_addr) {
  1487. qdss = (struct cvp_hfi_mem_map_table *)
  1488. device->qdss.align_virtual_addr;
  1489. qdss->mem_map_num_entries = num_entries;
  1490. mem_map_table_base_addr =
  1491. device->qdss.align_device_addr +
  1492. sizeof(struct cvp_hfi_mem_map_table);
  1493. qdss->mem_map_table_base_addr =
  1494. (u32)mem_map_table_base_addr;
  1495. if ((unsigned long)qdss->mem_map_table_base_addr !=
  1496. mem_map_table_base_addr) {
  1497. dprintk(CVP_ERR,
  1498. "Invalid mem_map_table_base_addr %#lx",
  1499. mem_map_table_base_addr);
  1500. }
  1501. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1502. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1503. for (i = 0; cb && i < num_entries; i++) {
  1504. iommu_unmap(cb->domain,
  1505. mem_map[i].virtual_addr,
  1506. mem_map[i].size);
  1507. }
  1508. __smem_free(device, &device->qdss.mem_data);
  1509. }
  1510. __smem_free(device, &device->iface_q_table.mem_data);
  1511. __smem_free(device, &device->sfr.mem_data);
  1512. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1513. device->iface_queues[i].q_hdr = NULL;
  1514. device->iface_queues[i].q_array.align_virtual_addr = NULL;
  1515. device->iface_queues[i].q_array.align_device_addr = 0;
  1516. }
  1517. device->iface_q_table.align_virtual_addr = NULL;
  1518. device->iface_q_table.align_device_addr = 0;
  1519. device->qdss.align_virtual_addr = NULL;
  1520. device->qdss.align_device_addr = 0;
  1521. device->sfr.align_virtual_addr = NULL;
  1522. device->sfr.align_device_addr = 0;
  1523. device->mem_addr.align_virtual_addr = NULL;
  1524. device->mem_addr.align_device_addr = 0;
  1525. #endif
  1526. }
  1527. static int __get_qdss_iommu_virtual_addr(struct iris_hfi_device *dev,
  1528. struct cvp_hfi_mem_map *mem_map,
  1529. struct iommu_domain *domain)
  1530. {
  1531. int i;
  1532. int rc = 0;
  1533. dma_addr_t iova = QDSS_IOVA_START;
  1534. int num_entries = dev->res->qdss_addr_set.count;
  1535. struct addr_range *qdss_addr_tbl = dev->res->qdss_addr_set.addr_tbl;
  1536. if (!num_entries)
  1537. return -ENODATA;
  1538. for (i = 0; i < num_entries; i++) {
  1539. if (domain) {
  1540. rc = iommu_map(domain, iova,
  1541. qdss_addr_tbl[i].start,
  1542. qdss_addr_tbl[i].size,
  1543. IOMMU_READ | IOMMU_WRITE);
  1544. if (rc) {
  1545. dprintk(CVP_ERR,
  1546. "IOMMU QDSS mapping failed for addr %#x\n",
  1547. qdss_addr_tbl[i].start);
  1548. rc = -ENOMEM;
  1549. break;
  1550. }
  1551. } else {
  1552. iova = qdss_addr_tbl[i].start;
  1553. }
  1554. mem_map[i].virtual_addr = (u32)iova;
  1555. mem_map[i].physical_addr = qdss_addr_tbl[i].start;
  1556. mem_map[i].size = qdss_addr_tbl[i].size;
  1557. mem_map[i].attr = 0x0;
  1558. iova += mem_map[i].size;
  1559. }
  1560. if (i < num_entries) {
  1561. dprintk(CVP_ERR,
  1562. "QDSS mapping failed, Freeing other entries %d\n", i);
  1563. for (--i; domain && i >= 0; i--) {
  1564. iommu_unmap(domain,
  1565. mem_map[i].virtual_addr,
  1566. mem_map[i].size);
  1567. }
  1568. }
  1569. return rc;
  1570. }
  1571. static void __setup_ucregion_memory_map(struct iris_hfi_device *device)
  1572. {
  1573. __write_register(device, CVP_UC_REGION_ADDR,
  1574. (u32)device->iface_q_table.align_device_addr);
  1575. __write_register(device, CVP_UC_REGION_SIZE, SHARED_QSIZE);
  1576. __write_register(device, CVP_QTBL_ADDR,
  1577. (u32)device->iface_q_table.align_device_addr);
  1578. __write_register(device, CVP_QTBL_INFO, 0x01);
  1579. if (device->sfr.align_device_addr)
  1580. __write_register(device, CVP_SFR_ADDR,
  1581. (u32)device->sfr.align_device_addr);
  1582. if (device->qdss.align_device_addr)
  1583. __write_register(device, CVP_MMAP_ADDR,
  1584. (u32)device->qdss.align_device_addr);
  1585. call_iris_op(device, setup_dsp_uc_memmap, device);
  1586. }
  1587. static void __hfi_queue_init(struct iris_hfi_device *dev)
  1588. {
  1589. int i, offset = 0;
  1590. struct cvp_hfi_queue_table_header *q_tbl_hdr;
  1591. struct cvp_iface_q_info *iface_q;
  1592. struct cvp_hfi_queue_header *q_hdr;
  1593. if (!dev)
  1594. return;
  1595. offset += dev->iface_q_table.mem_size;
  1596. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1597. iface_q = &dev->iface_queues[i];
  1598. iface_q->q_array.align_device_addr =
  1599. dev->iface_q_table.align_device_addr + offset;
  1600. iface_q->q_array.align_virtual_addr =
  1601. dev->iface_q_table.align_virtual_addr + offset;
  1602. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1603. offset += iface_q->q_array.mem_size;
  1604. iface_q->q_hdr = CVP_IFACEQ_GET_QHDR_START_ADDR(
  1605. dev->iface_q_table.align_virtual_addr, i);
  1606. __set_queue_hdr_defaults(iface_q->q_hdr);
  1607. spin_lock_init(&iface_q->hfi_lock);
  1608. }
  1609. q_tbl_hdr = (struct cvp_hfi_queue_table_header *)
  1610. dev->iface_q_table.align_virtual_addr;
  1611. q_tbl_hdr->qtbl_version = 0;
  1612. q_tbl_hdr->device_addr = (void *)dev;
  1613. strlcpy(q_tbl_hdr->name, "msm_cvp", sizeof(q_tbl_hdr->name));
  1614. q_tbl_hdr->qtbl_size = CVP_IFACEQ_TABLE_SIZE;
  1615. q_tbl_hdr->qtbl_qhdr0_offset =
  1616. sizeof(struct cvp_hfi_queue_table_header);
  1617. q_tbl_hdr->qtbl_qhdr_size = sizeof(struct cvp_hfi_queue_header);
  1618. q_tbl_hdr->qtbl_num_q = CVP_IFACEQ_NUMQ;
  1619. q_tbl_hdr->qtbl_num_active_q = CVP_IFACEQ_NUMQ;
  1620. iface_q = &dev->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1621. q_hdr = iface_q->q_hdr;
  1622. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1623. q_hdr->qhdr_type |= HFI_Q_ID_HOST_TO_CTRL_CMD_Q;
  1624. iface_q = &dev->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1625. q_hdr = iface_q->q_hdr;
  1626. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1627. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_MSG_Q;
  1628. iface_q = &dev->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1629. q_hdr = iface_q->q_hdr;
  1630. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1631. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
  1632. /*
  1633. * Set receive request to zero on debug queue as there is no
  1634. * need of interrupt from cvp hardware for debug messages
  1635. */
  1636. q_hdr->qhdr_rx_req = 0;
  1637. }
  1638. static void __sfr_init(struct iris_hfi_device *dev)
  1639. {
  1640. struct cvp_hfi_sfr_struct *vsfr;
  1641. if (!dev)
  1642. return;
  1643. vsfr = (struct cvp_hfi_sfr_struct *) dev->sfr.align_virtual_addr;
  1644. if (vsfr)
  1645. vsfr->bufSize = ALIGNED_SFR_SIZE;
  1646. }
  1647. static int __interface_queues_init(struct iris_hfi_device *dev)
  1648. {
  1649. int rc = 0;
  1650. struct cvp_hfi_mem_map_table *qdss;
  1651. struct cvp_hfi_mem_map *mem_map;
  1652. struct cvp_mem_addr *mem_addr;
  1653. int num_entries = dev->res->qdss_addr_set.count;
  1654. phys_addr_t fw_bias = 0;
  1655. size_t q_size;
  1656. unsigned long mem_map_table_base_addr;
  1657. struct context_bank_info *cb;
  1658. q_size = SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE;
  1659. mem_addr = &dev->mem_addr;
  1660. if (!is_iommu_present(dev->res))
  1661. fw_bias = dev->cvp_hal_data->firmware_base;
  1662. if (dev->iface_q_table.align_virtual_addr) {
  1663. memset((void *)dev->iface_q_table.align_virtual_addr,
  1664. 0, q_size);
  1665. goto hfi_queue_init;
  1666. }
  1667. rc = __smem_alloc(dev, mem_addr, q_size, 1, SMEM_UNCACHED);
  1668. if (rc) {
  1669. dprintk(CVP_ERR, "iface_q_table_alloc_fail\n");
  1670. goto fail_alloc_queue;
  1671. }
  1672. dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
  1673. dev->iface_q_table.align_device_addr = mem_addr->align_device_addr -
  1674. fw_bias;
  1675. dev->iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1676. dev->iface_q_table.mem_data = mem_addr->mem_data;
  1677. hfi_queue_init:
  1678. __hfi_queue_init(dev);
  1679. if (dev->sfr.align_virtual_addr) {
  1680. memset((void *)dev->sfr.align_virtual_addr,
  1681. 0, ALIGNED_SFR_SIZE);
  1682. goto sfr_init;
  1683. }
  1684. rc = __smem_alloc(dev, mem_addr, ALIGNED_SFR_SIZE, 1, SMEM_UNCACHED);
  1685. if (rc) {
  1686. dprintk(CVP_WARN, "sfr_alloc_fail: SFR not will work\n");
  1687. dev->sfr.align_device_addr = 0;
  1688. } else {
  1689. dev->sfr.align_device_addr = mem_addr->align_device_addr -
  1690. fw_bias;
  1691. dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr;
  1692. dev->sfr.mem_size = ALIGNED_SFR_SIZE;
  1693. dev->sfr.mem_data = mem_addr->mem_data;
  1694. }
  1695. sfr_init:
  1696. __sfr_init(dev);
  1697. if (dev->qdss.align_virtual_addr)
  1698. goto dsp_hfi_queue_init;
  1699. if ((msm_cvp_fw_debug_mode & HFI_DEBUG_MODE_QDSS) && num_entries) {
  1700. rc = __smem_alloc(dev, mem_addr, ALIGNED_QDSS_SIZE, 1,
  1701. SMEM_UNCACHED);
  1702. if (rc) {
  1703. dprintk(CVP_WARN,
  1704. "qdss_alloc_fail: QDSS messages logging will not work\n");
  1705. dev->qdss.align_device_addr = 0;
  1706. } else {
  1707. dev->qdss.align_device_addr =
  1708. mem_addr->align_device_addr - fw_bias;
  1709. dev->qdss.align_virtual_addr =
  1710. mem_addr->align_virtual_addr;
  1711. dev->qdss.mem_size = ALIGNED_QDSS_SIZE;
  1712. dev->qdss.mem_data = mem_addr->mem_data;
  1713. }
  1714. }
  1715. if (dev->qdss.align_virtual_addr) {
  1716. qdss =
  1717. (struct cvp_hfi_mem_map_table *)dev->qdss.align_virtual_addr;
  1718. qdss->mem_map_num_entries = num_entries;
  1719. mem_map_table_base_addr = dev->qdss.align_device_addr +
  1720. sizeof(struct cvp_hfi_mem_map_table);
  1721. qdss->mem_map_table_base_addr = mem_map_table_base_addr;
  1722. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1723. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1724. if (!cb) {
  1725. dprintk(CVP_ERR,
  1726. "%s: failed to get context bank\n", __func__);
  1727. return -EINVAL;
  1728. }
  1729. rc = __get_qdss_iommu_virtual_addr(dev, mem_map, cb->domain);
  1730. if (rc) {
  1731. dprintk(CVP_ERR,
  1732. "IOMMU mapping failed, Freeing qdss memdata\n");
  1733. __smem_free(dev, &dev->qdss.mem_data);
  1734. dev->qdss.align_virtual_addr = NULL;
  1735. dev->qdss.align_device_addr = 0;
  1736. }
  1737. }
  1738. dsp_hfi_queue_init:
  1739. rc = __interface_dsp_queues_init(dev);
  1740. if (rc) {
  1741. dprintk(CVP_ERR, "dsp_queues_init failed\n");
  1742. goto fail_alloc_queue;
  1743. }
  1744. __setup_ucregion_memory_map(dev);
  1745. return 0;
  1746. fail_alloc_queue:
  1747. return -ENOMEM;
  1748. }
  1749. static int __sys_set_debug(struct iris_hfi_device *device, u32 debug)
  1750. {
  1751. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1752. int rc = 0;
  1753. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1754. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1755. rc = call_hfi_pkt_op(device, sys_debug_config, pkt, debug);
  1756. if (rc) {
  1757. dprintk(CVP_WARN,
  1758. "Debug mode setting to FW failed\n");
  1759. return -ENOTEMPTY;
  1760. }
  1761. if (__iface_cmdq_write(device, pkt))
  1762. return -ENOTEMPTY;
  1763. return 0;
  1764. }
  1765. static int __sys_set_idle_indicator(struct iris_hfi_device *device,
  1766. bool enable)
  1767. {
  1768. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1769. int rc = 0;
  1770. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1771. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1772. rc = call_hfi_pkt_op(device, sys_set_idle_indicator, pkt, enable);
  1773. if (__iface_cmdq_write(device, pkt))
  1774. return -ENOTEMPTY;
  1775. return 0;
  1776. }
  1777. static int __sys_set_coverage(struct iris_hfi_device *device, u32 mode)
  1778. {
  1779. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1780. int rc = 0;
  1781. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1782. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1783. rc = call_hfi_pkt_op(device, sys_coverage_config,
  1784. pkt, mode);
  1785. if (rc) {
  1786. dprintk(CVP_WARN,
  1787. "Coverage mode setting to FW failed\n");
  1788. return -ENOTEMPTY;
  1789. }
  1790. if (__iface_cmdq_write(device, pkt)) {
  1791. dprintk(CVP_WARN, "Failed to send coverage pkt to f/w\n");
  1792. return -ENOTEMPTY;
  1793. }
  1794. return 0;
  1795. }
  1796. static int __sys_set_power_control(struct iris_hfi_device *device,
  1797. bool enable)
  1798. {
  1799. struct regulator_info *rinfo;
  1800. bool supported = false;
  1801. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1802. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1803. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1804. iris_hfi_for_each_regulator(device, rinfo) {
  1805. if (rinfo->has_hw_power_collapse) {
  1806. supported = true;
  1807. break;
  1808. }
  1809. }
  1810. if (!supported)
  1811. return 0;
  1812. call_hfi_pkt_op(device, sys_power_control, pkt, enable);
  1813. if (__iface_cmdq_write(device, pkt))
  1814. return -ENOTEMPTY;
  1815. return 0;
  1816. }
  1817. static void cvp_pm_qos_update(struct iris_hfi_device *device, bool vote_on)
  1818. {
  1819. u32 latency, off_vote_cnt;
  1820. int i, err = 0;
  1821. spin_lock(&device->res->pm_qos.lock);
  1822. off_vote_cnt = device->res->pm_qos.off_vote_cnt;
  1823. spin_unlock(&device->res->pm_qos.lock);
  1824. if (vote_on && off_vote_cnt)
  1825. return;
  1826. latency = vote_on ? device->res->pm_qos.latency_us :
  1827. PM_QOS_RESUME_LATENCY_DEFAULT_VALUE;
  1828. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  1829. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  1830. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  1831. continue;
  1832. err = dev_pm_qos_update_request(
  1833. &device->res->pm_qos.pm_qos_hdls[i],
  1834. latency);
  1835. if (err < 0) {
  1836. if (vote_on) {
  1837. dprintk(CVP_WARN,
  1838. "pm qos on failed %d\n", err);
  1839. } else {
  1840. dprintk(CVP_WARN,
  1841. "pm qos off failed %d\n", err);
  1842. }
  1843. }
  1844. }
  1845. }
  1846. static int iris_pm_qos_update(void *device)
  1847. {
  1848. struct iris_hfi_device *dev;
  1849. if (!device) {
  1850. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  1851. return -ENODEV;
  1852. }
  1853. dev = device;
  1854. mutex_lock(&dev->lock);
  1855. cvp_pm_qos_update(dev, true);
  1856. mutex_unlock(&dev->lock);
  1857. return 0;
  1858. }
  1859. static int __hwfence_regs_map(struct iris_hfi_device *device)
  1860. {
  1861. int rc = 0;
  1862. struct context_bank_info *cb;
  1863. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1864. if (!cb) {
  1865. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1866. return -EINVAL;
  1867. }
  1868. if (device->res->reg_mappings.ipclite_phyaddr != 0) {
  1869. rc = iommu_map(cb->domain,
  1870. device->res->reg_mappings.ipclite_iova,
  1871. device->res->reg_mappings.ipclite_phyaddr,
  1872. device->res->reg_mappings.ipclite_size,
  1873. IOMMU_READ | IOMMU_WRITE);
  1874. if (rc) {
  1875. dprintk(CVP_ERR, "map ipclite fail %d %#x %#x %#x\n",
  1876. rc, device->res->reg_mappings.ipclite_iova,
  1877. device->res->reg_mappings.ipclite_phyaddr,
  1878. device->res->reg_mappings.ipclite_size);
  1879. return rc;
  1880. }
  1881. }
  1882. if (device->res->reg_mappings.hwmutex_phyaddr != 0) {
  1883. rc = iommu_map(cb->domain,
  1884. device->res->reg_mappings.hwmutex_iova,
  1885. device->res->reg_mappings.hwmutex_phyaddr,
  1886. device->res->reg_mappings.hwmutex_size,
  1887. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1888. if (rc) {
  1889. dprintk(CVP_ERR, "map hwmutex fail %d %#x %#x %#x\n",
  1890. rc, device->res->reg_mappings.hwmutex_iova,
  1891. device->res->reg_mappings.hwmutex_phyaddr,
  1892. device->res->reg_mappings.hwmutex_size);
  1893. return rc;
  1894. }
  1895. }
  1896. if (device->res->reg_mappings.aon_phyaddr != 0) {
  1897. rc = iommu_map(cb->domain,
  1898. device->res->reg_mappings.aon_iova,
  1899. device->res->reg_mappings.aon_phyaddr,
  1900. device->res->reg_mappings.aon_size,
  1901. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1902. if (rc) {
  1903. dprintk(CVP_ERR, "map aon fail %d %#x %#x %#x\n",
  1904. rc, device->res->reg_mappings.aon_iova,
  1905. device->res->reg_mappings.aon_phyaddr,
  1906. device->res->reg_mappings.aon_size);
  1907. return rc;
  1908. }
  1909. }
  1910. if (device->res->reg_mappings.timer_phyaddr != 0) {
  1911. rc = iommu_map(cb->domain,
  1912. device->res->reg_mappings.timer_iova,
  1913. device->res->reg_mappings.timer_phyaddr,
  1914. device->res->reg_mappings.timer_size,
  1915. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1916. if (rc) {
  1917. dprintk(CVP_ERR, "map timer fail %d %#x %#x %#x\n",
  1918. rc, device->res->reg_mappings.timer_iova,
  1919. device->res->reg_mappings.timer_phyaddr,
  1920. device->res->reg_mappings.timer_size);
  1921. return rc;
  1922. }
  1923. }
  1924. return rc;
  1925. }
  1926. static int __hwfence_regs_unmap(struct iris_hfi_device *device)
  1927. {
  1928. int rc = 0;
  1929. struct context_bank_info *cb;
  1930. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1931. if (!cb) {
  1932. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1933. return -EINVAL;
  1934. }
  1935. if (device->res->reg_mappings.ipclite_iova != 0) {
  1936. iommu_unmap(cb->domain,
  1937. device->res->reg_mappings.ipclite_iova,
  1938. device->res->reg_mappings.ipclite_size);
  1939. }
  1940. if (device->res->reg_mappings.hwmutex_iova != 0) {
  1941. iommu_unmap(cb->domain,
  1942. device->res->reg_mappings.hwmutex_iova,
  1943. device->res->reg_mappings.hwmutex_size);
  1944. }
  1945. if (device->res->reg_mappings.aon_iova != 0) {
  1946. iommu_unmap(cb->domain,
  1947. device->res->reg_mappings.aon_iova,
  1948. device->res->reg_mappings.aon_size);
  1949. }
  1950. if (device->res->reg_mappings.timer_iova != 0) {
  1951. iommu_unmap(cb->domain,
  1952. device->res->reg_mappings.timer_iova,
  1953. device->res->reg_mappings.timer_size);
  1954. }
  1955. return rc;
  1956. }
  1957. static int iris_hfi_core_init(void *device)
  1958. {
  1959. int rc = 0;
  1960. u32 ipcc_iova;
  1961. struct cvp_hfi_cmd_sys_init_packet pkt;
  1962. struct cvp_hfi_cmd_sys_get_property_packet version_pkt;
  1963. struct iris_hfi_device *dev;
  1964. if (!device) {
  1965. dprintk(CVP_ERR, "Invalid device\n");
  1966. return -ENODEV;
  1967. }
  1968. dev = device;
  1969. dprintk(CVP_CORE, "Core initializing\n");
  1970. pm_stay_awake(dev->res->pdev->dev.parent);
  1971. mutex_lock(&dev->lock);
  1972. dev->bus_vote.data =
  1973. kzalloc(sizeof(struct cvp_bus_vote_data), GFP_KERNEL);
  1974. if (!dev->bus_vote.data) {
  1975. dprintk(CVP_ERR, "Bus vote data memory is not allocated\n");
  1976. rc = -ENOMEM;
  1977. goto err_no_mem;
  1978. }
  1979. dev->bus_vote.data_count = 1;
  1980. dev->bus_vote.data->power_mode = CVP_POWER_TURBO;
  1981. __hwfence_regs_map(dev);
  1982. rc = __power_on_init(dev);
  1983. if (rc) {
  1984. dprintk(CVP_ERR, "Failed to power on init EVA\n");
  1985. goto err_load_fw;
  1986. }
  1987. rc = cvp_synx_recover();
  1988. if (rc) {
  1989. dprintk(CVP_ERR, "Failed to recover synx\n");
  1990. goto err_core_init;
  1991. }
  1992. /* mmrm registration */
  1993. if (msm_cvp_mmrm_enabled) {
  1994. rc = msm_cvp_mmrm_register(device);
  1995. if (rc) {
  1996. dprintk(CVP_ERR, "Failed to register mmrm client\n");
  1997. goto err_core_init;
  1998. }
  1999. }
  2000. __set_state(dev, IRIS_STATE_INIT);
  2001. dev->reg_dumped = false;
  2002. dprintk(CVP_CORE, "Dev_Virt: %pa, Reg_Virt: %pK\n",
  2003. &dev->cvp_hal_data->firmware_base,
  2004. dev->cvp_hal_data->register_base);
  2005. rc = __interface_queues_init(dev);
  2006. if (rc) {
  2007. dprintk(CVP_ERR, "failed to init queues\n");
  2008. rc = -ENOMEM;
  2009. goto err_core_init;
  2010. }
  2011. cvp_register_va_md_region();
  2012. // Add node for dev struct
  2013. add_va_node_to_list(CVP_QUEUE_DUMP, dev,
  2014. sizeof(struct iris_hfi_device),
  2015. "iris_hfi_device-dev", false);
  2016. add_queue_header_to_va_md_list((void*)dev);
  2017. add_hfi_queue_to_va_md_list((void*)dev);
  2018. rc = msm_cvp_map_ipcc_regs(&ipcc_iova);
  2019. if (!rc) {
  2020. dprintk(CVP_CORE, "IPCC iova 0x%x\n", ipcc_iova);
  2021. __write_register(dev, CVP_MMAP_ADDR, ipcc_iova);
  2022. }
  2023. rc = __load_fw(dev);
  2024. if (rc) {
  2025. dprintk(CVP_ERR, "Failed to load Iris FW\n");
  2026. goto err_core_init;
  2027. }
  2028. rc = __boot_firmware(dev);
  2029. if (rc) {
  2030. dprintk(CVP_ERR, "Failed to start core\n");
  2031. rc = -ENODEV;
  2032. goto err_core_init;
  2033. }
  2034. dev->version = __read_register(dev, CVP_VERSION_INFO);
  2035. rc = call_hfi_pkt_op(dev, sys_init, &pkt, 0);
  2036. if (rc) {
  2037. dprintk(CVP_ERR, "Failed to create sys init pkt\n");
  2038. goto err_core_init;
  2039. }
  2040. if (__iface_cmdq_write(dev, &pkt)) {
  2041. rc = -ENOTEMPTY;
  2042. goto err_core_init;
  2043. }
  2044. rc = call_hfi_pkt_op(dev, sys_image_version, &version_pkt);
  2045. if (rc || __iface_cmdq_write(dev, &version_pkt))
  2046. dprintk(CVP_WARN, "Failed to send image version pkt to f/w\n");
  2047. __sys_set_debug(device, msm_cvp_fw_debug);
  2048. __enable_subcaches(device);
  2049. __set_subcaches(device);
  2050. __set_ubwc_config(device);
  2051. __sys_set_idle_indicator(device, true);
  2052. if (dev->res->pm_qos.latency_us) {
  2053. int err = 0;
  2054. u32 i, cpu;
  2055. dev->res->pm_qos.pm_qos_hdls = kcalloc(
  2056. dev->res->pm_qos.silver_count,
  2057. sizeof(struct dev_pm_qos_request),
  2058. GFP_KERNEL);
  2059. if (!dev->res->pm_qos.pm_qos_hdls) {
  2060. dprintk(CVP_WARN, "Failed allocate pm_qos_hdls\n");
  2061. goto pm_qos_bail;
  2062. }
  2063. for (i = 0; i < dev->res->pm_qos.silver_count; i++) {
  2064. cpu = dev->res->pm_qos.silver_cores[i];
  2065. if (!cpu_possible(cpu))
  2066. continue;
  2067. err = dev_pm_qos_add_request(
  2068. get_cpu_device(cpu),
  2069. &dev->res->pm_qos.pm_qos_hdls[i],
  2070. DEV_PM_QOS_RESUME_LATENCY,
  2071. dev->res->pm_qos.latency_us);
  2072. if (err < 0)
  2073. dprintk(CVP_WARN,
  2074. "%s pm_qos_add_req %d failed\n",
  2075. __func__, i);
  2076. }
  2077. }
  2078. pm_qos_bail:
  2079. mutex_unlock(&dev->lock);
  2080. cvp_dsp_send_hfi_queue();
  2081. pm_relax(dev->res->pdev->dev.parent);
  2082. dprintk(CVP_CORE, "Core inited successfully\n");
  2083. return 0;
  2084. err_core_init:
  2085. __set_state(dev, IRIS_STATE_DEINIT);
  2086. __unload_fw(dev);
  2087. if (dev->mmrm_cvp)
  2088. {
  2089. msm_cvp_mmrm_deregister(dev);
  2090. }
  2091. err_load_fw:
  2092. __hwfence_regs_unmap(dev);
  2093. err_no_mem:
  2094. dprintk(CVP_ERR, "Core init failed\n");
  2095. mutex_unlock(&dev->lock);
  2096. pm_relax(dev->res->pdev->dev.parent);
  2097. return rc;
  2098. }
  2099. static int iris_hfi_core_release(void *dev)
  2100. {
  2101. int rc = 0, i;
  2102. struct iris_hfi_device *device = dev;
  2103. struct cvp_hal_session *session, *next;
  2104. struct dev_pm_qos_request *qos_hdl;
  2105. u32 ipcc_iova;
  2106. if (!device) {
  2107. dprintk(CVP_ERR, "invalid device\n");
  2108. return -ENODEV;
  2109. }
  2110. mutex_lock(&device->lock);
  2111. dprintk(CVP_WARN, "Core releasing\n");
  2112. if (device->res->pm_qos.latency_us &&
  2113. device->res->pm_qos.pm_qos_hdls) {
  2114. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  2115. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  2116. continue;
  2117. qos_hdl = &device->res->pm_qos.pm_qos_hdls[i];
  2118. if ((qos_hdl != NULL) && dev_pm_qos_request_active(qos_hdl))
  2119. dev_pm_qos_remove_request(qos_hdl);
  2120. }
  2121. kfree(device->res->pm_qos.pm_qos_hdls);
  2122. device->res->pm_qos.pm_qos_hdls = NULL;
  2123. }
  2124. __resume(device);
  2125. __set_state(device, IRIS_STATE_DEINIT);
  2126. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  2127. if (rc)
  2128. dprintk(CVP_WARN, "Failed to suspend cvp FW%d\n", rc);
  2129. __dsp_shutdown(device);
  2130. __disable_subcaches(device);
  2131. ipcc_iova = __read_register(device, CVP_MMAP_ADDR);
  2132. msm_cvp_unmap_ipcc_regs(ipcc_iova);
  2133. __unload_fw(device);
  2134. __hwfence_regs_unmap(device);
  2135. if (msm_cvp_mmrm_enabled) {
  2136. rc = msm_cvp_mmrm_deregister(device);
  2137. if (rc) {
  2138. dprintk(CVP_ERR,
  2139. "%s: Failed msm_cvp_mmrm_deregister:%d\n",
  2140. __func__, rc);
  2141. }
  2142. }
  2143. /* unlink all sessions from device */
  2144. list_for_each_entry_safe(session, next, &device->sess_head, list) {
  2145. list_del(&session->list);
  2146. session->device = NULL;
  2147. }
  2148. dprintk(CVP_CORE, "Core released successfully\n");
  2149. mutex_unlock(&device->lock);
  2150. return rc;
  2151. }
  2152. static void __core_clear_interrupt(struct iris_hfi_device *device)
  2153. {
  2154. u32 intr_status = 0, mask = 0;
  2155. int i = 0;
  2156. if (!device) {
  2157. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2158. return;
  2159. }
  2160. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  2161. if (i) {
  2162. dprintk(CVP_WARN, "%s Fail acquire xo_reset at %d\n", __func__, __LINE__);
  2163. return;
  2164. }
  2165. intr_status = __read_register(device, CVP_WRAPPER_INTR_STATUS);
  2166. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  2167. mask = (CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK | CVP_FATAL_INTR_BMSK);
  2168. if (intr_status & mask) {
  2169. device->intr_status |= intr_status;
  2170. device->reg_count++;
  2171. dprintk(CVP_CORE,
  2172. "INTERRUPT for device: %pK: times: %d status: %d\n",
  2173. device, device->reg_count, intr_status);
  2174. } else {
  2175. device->spur_count++;
  2176. }
  2177. __write_register(device, CVP_CPU_CS_A2HSOFTINTCLR, 1);
  2178. }
  2179. static int iris_hfi_core_trigger_ssr(void *device,
  2180. enum hal_ssr_trigger_type type)
  2181. {
  2182. struct cvp_hfi_cmd_sys_test_ssr_packet pkt;
  2183. int rc = 0;
  2184. struct iris_hfi_device *dev;
  2185. cvp_free_va_md_list();
  2186. if (!device) {
  2187. dprintk(CVP_ERR, "invalid device\n");
  2188. return -ENODEV;
  2189. }
  2190. dev = device;
  2191. if (mutex_trylock(&dev->lock)) {
  2192. rc = call_hfi_pkt_op(dev, ssr_cmd, type, &pkt);
  2193. if (rc) {
  2194. dprintk(CVP_ERR, "%s: failed to create packet\n",
  2195. __func__);
  2196. goto err_create_pkt;
  2197. }
  2198. if (__iface_cmdq_write(dev, &pkt))
  2199. rc = -ENOTEMPTY;
  2200. } else {
  2201. return -EAGAIN;
  2202. }
  2203. err_create_pkt:
  2204. mutex_unlock(&dev->lock);
  2205. return rc;
  2206. }
  2207. static void __set_default_sys_properties(struct iris_hfi_device *device)
  2208. {
  2209. if (__sys_set_debug(device, msm_cvp_fw_debug))
  2210. dprintk(CVP_WARN, "Setting fw_debug msg ON failed\n");
  2211. if (__sys_set_power_control(device, msm_cvp_fw_low_power_mode))
  2212. dprintk(CVP_WARN, "Setting h/w power collapse ON failed\n");
  2213. }
  2214. static void __session_clean(struct cvp_hal_session *session)
  2215. {
  2216. struct cvp_hal_session *temp, *next;
  2217. struct iris_hfi_device *device;
  2218. if (!session || !session->device) {
  2219. dprintk(CVP_WARN, "%s: invalid params\n", __func__);
  2220. return;
  2221. }
  2222. device = session->device;
  2223. dprintk(CVP_SESS, "deleted the session: %pK\n", session);
  2224. /*
  2225. * session might have been removed from the device list in
  2226. * core_release, so check and remove if it is in the list
  2227. */
  2228. list_for_each_entry_safe(temp, next, &device->sess_head, list) {
  2229. if (session == temp) {
  2230. list_del(&session->list);
  2231. break;
  2232. }
  2233. }
  2234. /* Poison the session handle with zeros */
  2235. *session = (struct cvp_hal_session){ {0} };
  2236. kfree(session);
  2237. }
  2238. static int iris_hfi_session_clean(void *session)
  2239. {
  2240. struct cvp_hal_session *sess_close;
  2241. struct iris_hfi_device *device;
  2242. if (!session || session == (void *)0xdeadbeef) {
  2243. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2244. return -EINVAL;
  2245. }
  2246. sess_close = session;
  2247. device = sess_close->device;
  2248. if (!device) {
  2249. dprintk(CVP_ERR, "Invalid device handle %s\n", __func__);
  2250. return -EINVAL;
  2251. }
  2252. mutex_lock(&device->lock);
  2253. __session_clean(sess_close);
  2254. mutex_unlock(&device->lock);
  2255. return 0;
  2256. }
  2257. static int iris_debug_hook(void *device)
  2258. {
  2259. struct iris_hfi_device *dev = device;
  2260. u32 val;
  2261. if (!device) {
  2262. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  2263. return -ENODEV;
  2264. }
  2265. //__write_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0x11);
  2266. //__write_register(dev, CVP_WRAPPER_TZ_CPU_CLOCK_CONFIG, 0x1);
  2267. dprintk(CVP_ERR, "Halt Tensilica and core and axi\n");
  2268. return 0;
  2269. /******* FDU & MPU *****/
  2270. #define CVP0_CVP_SS_FDU_SECURE_ENABLE 0x90
  2271. #define CVP0_CVP_SS_MPU_SECURE_ENABLE 0x94
  2272. #define CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE 0xA0
  2273. #define CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE 0xA4
  2274. #define CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE 0xA8
  2275. #define CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE 0xAC
  2276. val = __read_register(dev, CVP0_CVP_SS_FDU_SECURE_ENABLE);
  2277. dprintk(CVP_ERR, "FDU_SECURE_ENABLE %#x\n", val);
  2278. val = __read_register(dev, CVP0_CVP_SS_MPU_SECURE_ENABLE);
  2279. dprintk(CVP_ERR, "MPU_SECURE_ENABLE %#x\n", val);
  2280. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE);
  2281. dprintk(CVP_ERR, "ARP_THREAD_0_SECURE_ENABLE %#x\n", val);
  2282. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE);
  2283. dprintk(CVP_ERR, "ARP_THREAD_1_SECURE_ENABLE %#x\n", val);
  2284. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE);
  2285. dprintk(CVP_ERR, "ARP_THREAD_2_SECURE_ENABLE %#x\n", val);
  2286. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE);
  2287. dprintk(CVP_ERR, "ARP_THREAD_3_SECURE_ENABLE %#x\n", val);
  2288. if (true)
  2289. return 0;
  2290. /***** GCE *******
  2291. * Bit 0 of below register is CDM secure enable for GCE
  2292. * CDM buffer will be in CB4 if set
  2293. */
  2294. #define CVP_GCE_GCE_SS_CP_CTL 0x51100
  2295. /* STATUS bit0 && CFG bit 4 of below register set,
  2296. * expect pixel buffers in CB3,
  2297. * otherwise in CB0
  2298. * CFG bit 9:8 b01 -> LMC input in CB3
  2299. * CFG bit 9:8 b10 -> LMC input in CB4
  2300. */
  2301. #define CVP_GCE0_CP_STATUS 0x51080
  2302. #define CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG 0x52020
  2303. val = __read_register(dev, CVP_GCE_GCE_SS_CP_CTL);
  2304. dprintk(CVP_ERR, "CVP_GCE_GCE_SS_CP_CTL %#x\n", val);
  2305. val = __read_register(dev, CVP_GCE0_CP_STATUS);
  2306. dprintk(CVP_ERR, "CVP_GCE0_CP_STATUS %#x\n", val);
  2307. val = __read_register(dev, CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG);
  2308. dprintk(CVP_ERR, "CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2309. /***** RGE *****
  2310. * Bit 0 of below regiser is CDM secure enable for RGE
  2311. * CDM buffer to be in CB4 i fset
  2312. */
  2313. #define CVP_RGE0_TOPRGE_CP_CTL 0x31010
  2314. /* CFG bit 4 && IN bit 0:
  2315. * if both are set, expect CB3 or CB4 depending on IN 6:4 field
  2316. * either is clear, expect CB0
  2317. */
  2318. #define CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG 0x32020
  2319. #define CVP_RGE0_TOPSPARE_IN 0x311F4
  2320. val = __read_register(dev, CVP_RGE0_TOPRGE_CP_CTL);
  2321. dprintk(CVP_ERR, "CVP_RGE0_TOPRGE_CP_CTL %#x\n", val);
  2322. val = __read_register(dev, CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2323. dprintk(CVP_ERR, "CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2324. val = __read_register(dev, CVP_RGE0_TOPSPARE_IN);
  2325. dprintk(CVP_ERR, "CVP_RGE0_TOPSPARE_IN %#x\n", val);
  2326. /****** VADL ******
  2327. * Bit 0 of below register is CDM secure enable for VADL
  2328. * CDM buffer will bei in CB4 if set
  2329. */
  2330. #define CVP_VADL0_VADL_SS_CP_CTL 0x21010
  2331. /* Below registers are used the same way as RGE */
  2332. #define CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG 0x22020
  2333. #define CVP_VADL0_SPARE_IN 0x211F4
  2334. val = __read_register(dev, CVP_VADL0_VADL_SS_CP_CTL);
  2335. dprintk(CVP_ERR, "CVP_VADL0_VADL_SS_CP_CTL %#x\n", val);
  2336. val = __read_register(dev, CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2337. dprintk(CVP_ERR, "CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2338. val = __read_register(dev, CVP_VADL0_SPARE_IN);
  2339. dprintk(CVP_ERR, "CVP_VADL0_SPARE_IN %#x\n", val);
  2340. /****** ITOF *****
  2341. * Below registers are used the same way as RGE
  2342. */
  2343. #define CVP_ITOF0_TOF_SS_CP_CTL 0x41010
  2344. #define CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG 0x42020
  2345. #define CVP_ITOF0_TOF_SS_SPARE_IN 0x411F4
  2346. val = __read_register(dev, CVP_ITOF0_TOF_SS_CP_CTL);
  2347. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_CP_CTL %#x\n", val);
  2348. val = __read_register(dev, CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2349. dprintk(CVP_ERR, "CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2350. val = __read_register(dev, CVP_ITOF0_TOF_SS_SPARE_IN);
  2351. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_SPARE_IN %#x\n", val);
  2352. return 0;
  2353. }
  2354. static int iris_hfi_session_init(void *device, void *session_id,
  2355. void **new_session)
  2356. {
  2357. struct cvp_hfi_cmd_sys_session_init_packet pkt;
  2358. struct iris_hfi_device *dev;
  2359. struct cvp_hal_session *s;
  2360. if (!device || !new_session) {
  2361. dprintk(CVP_ERR, "%s - invalid input\n", __func__);
  2362. return -EINVAL;
  2363. }
  2364. dev = device;
  2365. mutex_lock(&dev->lock);
  2366. s = kzalloc(sizeof(*s), GFP_KERNEL);
  2367. if (!s) {
  2368. dprintk(CVP_ERR, "new session fail: Out of memory\n");
  2369. goto err_session_init_fail;
  2370. }
  2371. s->session_id = session_id;
  2372. s->device = dev;
  2373. dprintk(CVP_SESS,
  2374. "%s: inst %pK, session %pK\n", __func__, session_id, s);
  2375. list_add_tail(&s->list, &dev->sess_head);
  2376. __set_default_sys_properties(device);
  2377. if (call_hfi_pkt_op(dev, session_init, &pkt, s)) {
  2378. dprintk(CVP_ERR, "session_init: failed to create packet\n");
  2379. goto err_session_init_fail;
  2380. }
  2381. *new_session = s;
  2382. if (__iface_cmdq_write(dev, &pkt))
  2383. goto err_session_init_fail;
  2384. mutex_unlock(&dev->lock);
  2385. return 0;
  2386. err_session_init_fail:
  2387. if (s)
  2388. __session_clean(s);
  2389. *new_session = NULL;
  2390. mutex_unlock(&dev->lock);
  2391. return -EINVAL;
  2392. }
  2393. static int __send_session_cmd(struct cvp_hal_session *session, int pkt_type)
  2394. {
  2395. struct cvp_hal_session_cmd_pkt pkt;
  2396. int rc = 0;
  2397. struct iris_hfi_device *device = session->device;
  2398. if (!__is_session_valid(device, session, __func__))
  2399. return -ECONNRESET;
  2400. rc = call_hfi_pkt_op(device, session_cmd,
  2401. &pkt, pkt_type, session);
  2402. if (rc == -EPERM)
  2403. return 0;
  2404. if (rc) {
  2405. dprintk(CVP_ERR, "send session cmd: create pkt failed\n");
  2406. goto err_create_pkt;
  2407. }
  2408. if (__iface_cmdq_write(session->device, &pkt))
  2409. rc = -ENOTEMPTY;
  2410. err_create_pkt:
  2411. return rc;
  2412. }
  2413. static int iris_hfi_session_end(void *session)
  2414. {
  2415. struct cvp_hal_session *sess;
  2416. struct iris_hfi_device *device;
  2417. int rc = 0;
  2418. if (!session) {
  2419. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2420. return -EINVAL;
  2421. }
  2422. sess = session;
  2423. device = sess->device;
  2424. if (!device) {
  2425. dprintk(CVP_ERR, "Invalid session %s\n", __func__);
  2426. return -EINVAL;
  2427. }
  2428. mutex_lock(&device->lock);
  2429. if (msm_cvp_fw_coverage) {
  2430. if (__sys_set_coverage(sess->device, msm_cvp_fw_coverage))
  2431. dprintk(CVP_WARN, "Fw_coverage msg ON failed\n");
  2432. }
  2433. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_END);
  2434. mutex_unlock(&device->lock);
  2435. return rc;
  2436. }
  2437. static int iris_hfi_session_abort(void *sess)
  2438. {
  2439. struct cvp_hal_session *session = sess;
  2440. struct iris_hfi_device *device;
  2441. int rc = 0;
  2442. if (!session || !session->device) {
  2443. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2444. return -EINVAL;
  2445. }
  2446. device = session->device;
  2447. mutex_lock(&device->lock);
  2448. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_ABORT);
  2449. mutex_unlock(&device->lock);
  2450. return rc;
  2451. }
  2452. static int iris_hfi_session_set_buffers(void *sess, u32 iova, u32 size)
  2453. {
  2454. struct cvp_hfi_cmd_session_set_buffers_packet pkt;
  2455. int rc = 0;
  2456. struct cvp_hal_session *session = sess;
  2457. struct iris_hfi_device *device;
  2458. if (!session || !session->device || !iova || !size) {
  2459. dprintk(CVP_ERR, "Invalid Params\n");
  2460. return -EINVAL;
  2461. }
  2462. device = session->device;
  2463. mutex_lock(&device->lock);
  2464. if (!__is_session_valid(device, session, __func__)) {
  2465. rc = -ECONNRESET;
  2466. goto err_create_pkt;
  2467. }
  2468. rc = call_hfi_pkt_op(device, session_set_buffers,
  2469. &pkt, session, iova, size);
  2470. if (rc) {
  2471. dprintk(CVP_ERR, "set buffers: failed to create packet\n");
  2472. goto err_create_pkt;
  2473. }
  2474. if (__iface_cmdq_write(session->device, &pkt))
  2475. rc = -ENOTEMPTY;
  2476. err_create_pkt:
  2477. mutex_unlock(&device->lock);
  2478. return rc;
  2479. }
  2480. static int iris_hfi_session_release_buffers(void *sess)
  2481. {
  2482. struct cvp_session_release_buffers_packet pkt;
  2483. int rc = 0;
  2484. struct cvp_hal_session *session = sess;
  2485. struct iris_hfi_device *device;
  2486. if (!session || session == (void *)0xdeadbeef || !session->device) {
  2487. dprintk(CVP_ERR, "Invalid Params\n");
  2488. return -EINVAL;
  2489. }
  2490. device = session->device;
  2491. mutex_lock(&device->lock);
  2492. if (!__is_session_valid(device, session, __func__)) {
  2493. rc = -ECONNRESET;
  2494. goto err_create_pkt;
  2495. }
  2496. rc = call_hfi_pkt_op(device, session_release_buffers, &pkt, session);
  2497. if (rc) {
  2498. dprintk(CVP_ERR, "release buffers: failed to create packet\n");
  2499. goto err_create_pkt;
  2500. }
  2501. if (__iface_cmdq_write(session->device, &pkt))
  2502. rc = -ENOTEMPTY;
  2503. err_create_pkt:
  2504. mutex_unlock(&device->lock);
  2505. return rc;
  2506. }
  2507. static int iris_hfi_session_send(void *sess,
  2508. struct eva_kmd_hfi_packet *in_pkt)
  2509. {
  2510. int rc = 0;
  2511. struct eva_kmd_hfi_packet pkt;
  2512. struct cvp_hal_session *session = sess;
  2513. struct iris_hfi_device *device;
  2514. if (!session || !session->device) {
  2515. dprintk(CVP_ERR, "invalid session");
  2516. return -ENODEV;
  2517. }
  2518. device = session->device;
  2519. mutex_lock(&device->lock);
  2520. if (!__is_session_valid(device, session, __func__)) {
  2521. rc = -ECONNRESET;
  2522. goto err_send_pkt;
  2523. }
  2524. rc = call_hfi_pkt_op(device, session_send,
  2525. &pkt, session, in_pkt);
  2526. if (rc) {
  2527. dprintk(CVP_ERR,
  2528. "failed to create pkt\n");
  2529. goto err_send_pkt;
  2530. }
  2531. if (__iface_cmdq_write(session->device, &pkt))
  2532. rc = -ENOTEMPTY;
  2533. err_send_pkt:
  2534. mutex_unlock(&device->lock);
  2535. return rc;
  2536. return rc;
  2537. }
  2538. static int iris_hfi_session_flush(void *sess)
  2539. {
  2540. struct cvp_hal_session *session = sess;
  2541. struct iris_hfi_device *device;
  2542. int rc = 0;
  2543. if (!session || !session->device) {
  2544. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2545. return -EINVAL;
  2546. }
  2547. device = session->device;
  2548. mutex_lock(&device->lock);
  2549. rc = __send_session_cmd(session, HFI_CMD_SESSION_CVP_FLUSH);
  2550. mutex_unlock(&device->lock);
  2551. return rc;
  2552. }
  2553. static int iris_hfi_session_start(void *sess)
  2554. {
  2555. struct cvp_hal_session *session = sess;
  2556. struct iris_hfi_device *device;
  2557. int rc = 0;
  2558. if (!session || !session->device) {
  2559. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2560. return -EINVAL;
  2561. }
  2562. device = session->device;
  2563. mutex_lock(&device->lock);
  2564. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_START);
  2565. mutex_unlock(&device->lock);
  2566. return rc;
  2567. }
  2568. static int iris_hfi_session_stop(void *sess)
  2569. {
  2570. struct cvp_hal_session *session = sess;
  2571. struct iris_hfi_device *device;
  2572. int rc = 0;
  2573. if (!session || !session->device) {
  2574. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2575. return -EINVAL;
  2576. }
  2577. device = session->device;
  2578. mutex_lock(&device->lock);
  2579. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_STOP);
  2580. mutex_unlock(&device->lock);
  2581. return rc;
  2582. }
  2583. static void __process_fatal_error(
  2584. struct iris_hfi_device *device)
  2585. {
  2586. struct msm_cvp_cb_cmd_done cmd_done = {0};
  2587. device->callback(HAL_SYS_ERROR, &cmd_done);
  2588. }
  2589. static int __prepare_pc(struct iris_hfi_device *device)
  2590. {
  2591. int rc = 0;
  2592. struct cvp_hfi_cmd_sys_pc_prep_packet pkt;
  2593. rc = call_hfi_pkt_op(device, sys_pc_prep, &pkt);
  2594. if (rc) {
  2595. dprintk(CVP_ERR, "Failed to create sys pc prep pkt\n");
  2596. goto err_pc_prep;
  2597. }
  2598. if (__iface_cmdq_write(device, &pkt))
  2599. rc = -ENOTEMPTY;
  2600. if (rc)
  2601. dprintk(CVP_ERR, "Failed to prepare iris for power off");
  2602. err_pc_prep:
  2603. return rc;
  2604. }
  2605. static void iris_hfi_pm_handler(struct work_struct *work)
  2606. {
  2607. int rc = 0;
  2608. struct msm_cvp_core *core;
  2609. struct iris_hfi_device *device;
  2610. core = cvp_driver->cvp_core;
  2611. if (core)
  2612. device = core->dev_ops->hfi_device_data;
  2613. else
  2614. return;
  2615. if (!device) {
  2616. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2617. return;
  2618. }
  2619. dprintk(CVP_PWR,
  2620. "Entering %s\n", __func__);
  2621. /*
  2622. * It is ok to check this variable outside the lock since
  2623. * it is being updated in this context only
  2624. */
  2625. if (device->skip_pc_count >= CVP_MAX_PC_SKIP_COUNT) {
  2626. dprintk(CVP_WARN, "Failed to PC for %d times\n",
  2627. device->skip_pc_count);
  2628. device->skip_pc_count = 0;
  2629. __process_fatal_error(device);
  2630. return;
  2631. }
  2632. mutex_lock(&device->lock);
  2633. if (gfa_cv.state == DSP_SUSPEND)
  2634. rc = __power_collapse(device, true);
  2635. else
  2636. rc = __power_collapse(device, false);
  2637. mutex_unlock(&device->lock);
  2638. switch (rc) {
  2639. case 0:
  2640. device->skip_pc_count = 0;
  2641. /* Cancel pending delayed works if any */
  2642. cancel_delayed_work(&iris_hfi_pm_work);
  2643. dprintk(CVP_PWR, "%s: power collapse successful!\n",
  2644. __func__);
  2645. break;
  2646. case -EBUSY:
  2647. device->skip_pc_count = 0;
  2648. dprintk(CVP_PWR, "%s: retry PC as cvp is busy\n", __func__);
  2649. queue_delayed_work(device->iris_pm_workq,
  2650. &iris_hfi_pm_work, msecs_to_jiffies(
  2651. device->res->msm_cvp_pwr_collapse_delay));
  2652. break;
  2653. case -EAGAIN:
  2654. device->skip_pc_count++;
  2655. dprintk(CVP_WARN, "%s: retry power collapse (count %d)\n",
  2656. __func__, device->skip_pc_count);
  2657. queue_delayed_work(device->iris_pm_workq,
  2658. &iris_hfi_pm_work, msecs_to_jiffies(
  2659. device->res->msm_cvp_pwr_collapse_delay));
  2660. break;
  2661. default:
  2662. dprintk(CVP_ERR, "%s: power collapse failed\n", __func__);
  2663. break;
  2664. }
  2665. }
  2666. static int __power_collapse(struct iris_hfi_device *device, bool force)
  2667. {
  2668. int rc = 0;
  2669. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  2670. int count = 0;
  2671. const int max_tries = 150;
  2672. if (!device) {
  2673. dprintk(CVP_ERR, "%s: invalid params\n", __func__);
  2674. return -EINVAL;
  2675. }
  2676. if (!device->power_enabled) {
  2677. dprintk(CVP_PWR, "%s: Power already disabled\n",
  2678. __func__);
  2679. goto exit;
  2680. }
  2681. rc = __core_in_valid_state(device);
  2682. if (!rc) {
  2683. dprintk(CVP_WARN,
  2684. "Core is in bad state, Skipping power collapse\n");
  2685. return -EINVAL;
  2686. }
  2687. rc = __dsp_suspend(device, force);
  2688. if (rc == -EBUSY)
  2689. goto exit;
  2690. else if (rc)
  2691. goto skip_power_off;
  2692. __flush_debug_queue(device, device->raw_packet);
  2693. pc_ready = __read_register(device, CVP_CTRL_STATUS) &
  2694. CVP_CTRL_STATUS_PC_READY;
  2695. if (!pc_ready) {
  2696. wfi_status = __read_register(device,
  2697. CVP_WRAPPER_CPU_STATUS);
  2698. idle_status = __read_register(device,
  2699. CVP_CTRL_STATUS);
  2700. if (!(wfi_status & BIT(0))) {
  2701. dprintk(CVP_WARN,
  2702. "Skipping PC as wfi_status (%#x) bit not set\n",
  2703. wfi_status);
  2704. goto skip_power_off;
  2705. }
  2706. if (!(idle_status & BIT(30))) {
  2707. dprintk(CVP_WARN,
  2708. "Skipping PC as idle_status (%#x) bit not set\n",
  2709. idle_status);
  2710. goto skip_power_off;
  2711. }
  2712. rc = __prepare_pc(device);
  2713. if (rc) {
  2714. dprintk(CVP_WARN, "Failed PC %d\n", rc);
  2715. goto skip_power_off;
  2716. }
  2717. while (count < max_tries) {
  2718. wfi_status = __read_register(device,
  2719. CVP_WRAPPER_CPU_STATUS);
  2720. pc_ready = __read_register(device,
  2721. CVP_CTRL_STATUS);
  2722. if ((wfi_status & BIT(0)) && (pc_ready &
  2723. CVP_CTRL_STATUS_PC_READY))
  2724. break;
  2725. usleep_range(150, 250);
  2726. count++;
  2727. }
  2728. if (count == max_tries) {
  2729. dprintk(CVP_ERR,
  2730. "Skip PC. Core is not ready (%#x, %#x)\n",
  2731. wfi_status, pc_ready);
  2732. goto skip_power_off;
  2733. }
  2734. } else {
  2735. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  2736. if (!(wfi_status & BIT(0))) {
  2737. dprintk(CVP_WARN,
  2738. "Skip PC as wfi_status (%#x) bit not set\n",
  2739. wfi_status);
  2740. goto skip_power_off;
  2741. }
  2742. }
  2743. rc = __suspend(device);
  2744. if (rc)
  2745. dprintk(CVP_ERR, "Failed __suspend\n");
  2746. exit:
  2747. return rc;
  2748. skip_power_off:
  2749. dprintk(CVP_PWR, "Skip PC(%#x, %#x, %#x)\n",
  2750. wfi_status, idle_status, pc_ready);
  2751. __flush_debug_queue(device, device->raw_packet);
  2752. return -EAGAIN;
  2753. }
  2754. static void __process_sys_error(struct iris_hfi_device *device)
  2755. {
  2756. struct cvp_hfi_sfr_struct *vsfr = NULL;
  2757. vsfr = (struct cvp_hfi_sfr_struct *)device->sfr.align_virtual_addr;
  2758. if (vsfr) {
  2759. void *p = memchr(vsfr->rg_data, '\0', vsfr->bufSize);
  2760. /*
  2761. * SFR isn't guaranteed to be NULL terminated
  2762. * since SYS_ERROR indicates that Iris is in the
  2763. * process of crashing.
  2764. */
  2765. if (p == NULL)
  2766. vsfr->rg_data[vsfr->bufSize - 1] = '\0';
  2767. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2768. vsfr->rg_data);
  2769. }
  2770. }
  2771. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet)
  2772. {
  2773. bool local_packet = false;
  2774. enum cvp_msg_prio log_level = CVP_FW;
  2775. if (!device) {
  2776. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  2777. return;
  2778. }
  2779. if (!packet) {
  2780. packet = kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  2781. if (!packet) {
  2782. dprintk(CVP_ERR, "In %s() Fail to allocate mem\n",
  2783. __func__);
  2784. return;
  2785. }
  2786. local_packet = true;
  2787. /*
  2788. * Local packek is used when something FATAL occurred.
  2789. * It is good to print these logs by default.
  2790. */
  2791. log_level = CVP_ERR;
  2792. }
  2793. #define SKIP_INVALID_PKT(pkt_size, payload_size, pkt_hdr_size) ({ \
  2794. if (pkt_size < pkt_hdr_size || \
  2795. payload_size < MIN_PAYLOAD_SIZE || \
  2796. payload_size > \
  2797. (pkt_size - pkt_hdr_size + sizeof(u8))) { \
  2798. dprintk(CVP_ERR, \
  2799. "%s: invalid msg size - %d\n", \
  2800. __func__, pkt->msg_size); \
  2801. continue; \
  2802. } \
  2803. })
  2804. while (!__iface_dbgq_read(device, packet)) {
  2805. struct cvp_hfi_packet_header *pkt =
  2806. (struct cvp_hfi_packet_header *) packet;
  2807. if (pkt->size < sizeof(struct cvp_hfi_packet_header)) {
  2808. dprintk(CVP_ERR, "Invalid pkt size - %s\n",
  2809. __func__);
  2810. continue;
  2811. }
  2812. if (pkt->packet_type == HFI_MSG_SYS_DEBUG) {
  2813. struct cvp_hfi_msg_sys_debug_packet *pkt =
  2814. (struct cvp_hfi_msg_sys_debug_packet *) packet;
  2815. SKIP_INVALID_PKT(pkt->size,
  2816. pkt->msg_size, sizeof(*pkt));
  2817. /*
  2818. * All fw messages starts with new line character. This
  2819. * causes dprintk to print this message in two lines
  2820. * in the kernel log. Ignoring the first character
  2821. * from the message fixes this to print it in a single
  2822. * line.
  2823. */
  2824. pkt->rg_msg_data[pkt->msg_size-1] = '\0';
  2825. dprintk(log_level, "%s", &pkt->rg_msg_data[1]);
  2826. }
  2827. }
  2828. #undef SKIP_INVALID_PKT
  2829. if (local_packet)
  2830. kfree(packet);
  2831. }
  2832. static bool __is_session_valid(struct iris_hfi_device *device,
  2833. struct cvp_hal_session *session, const char *func)
  2834. {
  2835. struct cvp_hal_session *temp = NULL;
  2836. if (!device || !session)
  2837. goto invalid;
  2838. list_for_each_entry(temp, &device->sess_head, list)
  2839. if (session == temp)
  2840. return true;
  2841. invalid:
  2842. dprintk(CVP_WARN, "%s: device %pK, invalid session %pK\n",
  2843. func, device, session);
  2844. return false;
  2845. }
  2846. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  2847. u32 session_id)
  2848. {
  2849. struct cvp_hal_session *temp = NULL;
  2850. list_for_each_entry(temp, &device->sess_head, list) {
  2851. if (session_id == hash32_ptr(temp))
  2852. return temp;
  2853. }
  2854. return NULL;
  2855. }
  2856. #define _INVALID_MSG_ "Unrecognized MSG (%#x) session (%pK), discarding\n"
  2857. #define _INVALID_STATE_ "Ignore responses from %d to %d invalid state\n"
  2858. #define _DEVFREQ_FAIL_ "Failed to add devfreq device bus %s governor %s: %d\n"
  2859. static void process_system_msg(struct msm_cvp_cb_info *info,
  2860. struct iris_hfi_device *device,
  2861. void *raw_packet)
  2862. {
  2863. struct cvp_hal_sys_init_done sys_init_done = {0};
  2864. switch (info->response_type) {
  2865. case HAL_SYS_ERROR:
  2866. __process_sys_error(device);
  2867. break;
  2868. case HAL_SYS_RELEASE_RESOURCE_DONE:
  2869. dprintk(CVP_CORE, "Received SYS_RELEASE_RESOURCE\n");
  2870. break;
  2871. case HAL_SYS_INIT_DONE:
  2872. dprintk(CVP_CORE, "Received SYS_INIT_DONE\n");
  2873. sys_init_done.capabilities =
  2874. device->sys_init_capabilities;
  2875. cvp_hfi_process_sys_init_done_prop_read(
  2876. (struct cvp_hfi_msg_sys_init_done_packet *)
  2877. raw_packet, &sys_init_done);
  2878. info->response.cmd.data.sys_init_done = sys_init_done;
  2879. break;
  2880. default:
  2881. break;
  2882. }
  2883. }
  2884. static void **get_session_id(struct msm_cvp_cb_info *info)
  2885. {
  2886. void **session_id = NULL;
  2887. /* For session-related packets, validate session */
  2888. switch (info->response_type) {
  2889. case HAL_SESSION_INIT_DONE:
  2890. case HAL_SESSION_END_DONE:
  2891. case HAL_SESSION_ABORT_DONE:
  2892. case HAL_SESSION_START_DONE:
  2893. case HAL_SESSION_STOP_DONE:
  2894. case HAL_SESSION_FLUSH_DONE:
  2895. case HAL_SESSION_SET_BUFFER_DONE:
  2896. case HAL_SESSION_SUSPEND_DONE:
  2897. case HAL_SESSION_RESUME_DONE:
  2898. case HAL_SESSION_SET_PROP_DONE:
  2899. case HAL_SESSION_GET_PROP_DONE:
  2900. case HAL_SESSION_RELEASE_BUFFER_DONE:
  2901. case HAL_SESSION_REGISTER_BUFFER_DONE:
  2902. case HAL_SESSION_UNREGISTER_BUFFER_DONE:
  2903. case HAL_SESSION_PROPERTY_INFO:
  2904. case HAL_SESSION_EVENT_CHANGE:
  2905. case HAL_SESSION_DUMP_NOTIFY:
  2906. case HAL_SESSION_ERROR:
  2907. session_id = &info->response.cmd.session_id;
  2908. break;
  2909. case HAL_RESPONSE_UNUSED:
  2910. default:
  2911. session_id = NULL;
  2912. break;
  2913. }
  2914. return session_id;
  2915. }
  2916. static void print_msg_hdr(void *hdr)
  2917. {
  2918. struct cvp_hfi_msg_session_hdr *new_hdr =
  2919. (struct cvp_hfi_msg_session_hdr *)hdr;
  2920. dprintk(CVP_HFI, "HFI MSG received: %x %x %x %x %x %x %x %#llx\n",
  2921. new_hdr->size, new_hdr->packet_type,
  2922. new_hdr->session_id,
  2923. new_hdr->client_data.transaction_id,
  2924. new_hdr->client_data.data1,
  2925. new_hdr->client_data.data2,
  2926. new_hdr->error_type,
  2927. new_hdr->client_data.kdata);
  2928. }
  2929. static int __response_handler(struct iris_hfi_device *device)
  2930. {
  2931. struct msm_cvp_cb_info *packets;
  2932. int packet_count = 0;
  2933. u8 *raw_packet = NULL;
  2934. bool requeue_pm_work = true;
  2935. if (!device || device->state != IRIS_STATE_INIT)
  2936. return 0;
  2937. packets = device->response_pkt;
  2938. raw_packet = device->raw_packet;
  2939. if (!raw_packet || !packets) {
  2940. dprintk(CVP_ERR,
  2941. "%s: Invalid args : Res pkt = %pK, Raw pkt = %pK\n",
  2942. __func__, packets, raw_packet);
  2943. return 0;
  2944. }
  2945. if (device->intr_status & CVP_FATAL_INTR_BMSK) {
  2946. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CPU_NOC_BMSK)
  2947. dprintk(CVP_ERR, "Received Xtensa NOC error\n");
  2948. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CORE_NOC_BMSK)
  2949. dprintk(CVP_ERR, "Received CVP core NOC error\n");
  2950. }
  2951. /* Bleed the msg queue dry of packets */
  2952. while (!__iface_msgq_read(device, raw_packet)) {
  2953. void **session_id = NULL;
  2954. struct msm_cvp_cb_info *info = &packets[packet_count++];
  2955. struct cvp_hfi_msg_session_hdr *hdr =
  2956. (struct cvp_hfi_msg_session_hdr *)raw_packet;
  2957. int rc = 0;
  2958. print_msg_hdr(hdr);
  2959. rc = cvp_hfi_process_msg_packet(0, raw_packet, info);
  2960. if (rc) {
  2961. dprintk(CVP_WARN,
  2962. "Corrupt/unknown packet found, discarding\n");
  2963. --packet_count;
  2964. continue;
  2965. } else if (info->response_type == HAL_NO_RESP) {
  2966. --packet_count;
  2967. continue;
  2968. }
  2969. /* Process the packet types that we're interested in */
  2970. process_system_msg(info, device, raw_packet);
  2971. session_id = get_session_id(info);
  2972. /*
  2973. * hfi_process_msg_packet provides a session_id that's a hashed
  2974. * value of struct cvp_hal_session, we need to coerce the hashed
  2975. * value back to pointer that we can use. Ideally, hfi_process\
  2976. * _msg_packet should take care of this, but it doesn't have
  2977. * required information for it
  2978. */
  2979. if (session_id) {
  2980. struct cvp_hal_session *session = NULL;
  2981. if (upper_32_bits((uintptr_t)*session_id) != 0) {
  2982. dprintk(CVP_ERR,
  2983. "Upper 32-bits != 0 for sess_id=%pK\n",
  2984. *session_id);
  2985. }
  2986. session = __get_session(device,
  2987. (u32)(uintptr_t)*session_id);
  2988. if (!session) {
  2989. dprintk(CVP_ERR, _INVALID_MSG_,
  2990. info->response_type,
  2991. *session_id);
  2992. --packet_count;
  2993. continue;
  2994. }
  2995. *session_id = session->session_id;
  2996. }
  2997. if (packet_count >= cvp_max_packets) {
  2998. dprintk(CVP_WARN,
  2999. "Too many packets in message queue!\n");
  3000. break;
  3001. }
  3002. /* do not read packets after sys error packet */
  3003. if (info->response_type == HAL_SYS_ERROR)
  3004. break;
  3005. }
  3006. if (requeue_pm_work && device->res->sw_power_collapsible) {
  3007. cancel_delayed_work(&iris_hfi_pm_work);
  3008. if (!queue_delayed_work(device->iris_pm_workq,
  3009. &iris_hfi_pm_work,
  3010. msecs_to_jiffies(
  3011. device->res->msm_cvp_pwr_collapse_delay))) {
  3012. dprintk(CVP_ERR, "PM work already scheduled\n");
  3013. }
  3014. }
  3015. __flush_debug_queue(device, raw_packet);
  3016. return packet_count;
  3017. }
  3018. irqreturn_t iris_hfi_core_work_handler(int irq, void *data)
  3019. {
  3020. struct msm_cvp_core *core;
  3021. struct iris_hfi_device *device;
  3022. int num_responses = 0, i = 0;
  3023. u32 intr_status;
  3024. static bool warning_on = true;
  3025. core = cvp_driver->cvp_core;
  3026. if (core)
  3027. device = core->dev_ops->hfi_device_data;
  3028. else
  3029. return IRQ_HANDLED;
  3030. mutex_lock(&device->lock);
  3031. if (!__core_in_valid_state(device)) {
  3032. if (warning_on) {
  3033. dprintk(CVP_WARN, "%s Core not in init state\n",
  3034. __func__);
  3035. warning_on = false;
  3036. }
  3037. goto err_no_work;
  3038. }
  3039. warning_on = true;
  3040. if (!device->callback) {
  3041. dprintk(CVP_ERR, "No interrupt callback function: %pK\n",
  3042. device);
  3043. goto err_no_work;
  3044. }
  3045. if (__resume(device)) {
  3046. dprintk(CVP_ERR, "%s: Power enable failed\n", __func__);
  3047. goto err_no_work;
  3048. }
  3049. __core_clear_interrupt(device);
  3050. num_responses = __response_handler(device);
  3051. dprintk(CVP_HFI, "%s:: cvp_driver_debug num_responses = %d ",
  3052. __func__, num_responses);
  3053. err_no_work:
  3054. /* Keep the interrupt status before releasing device lock */
  3055. intr_status = device->intr_status;
  3056. mutex_unlock(&device->lock);
  3057. /*
  3058. * Issue the callbacks outside of the locked contex to preserve
  3059. * re-entrancy.
  3060. */
  3061. for (i = 0; !IS_ERR_OR_NULL(device->response_pkt) &&
  3062. i < num_responses; ++i) {
  3063. struct msm_cvp_cb_info *r = &device->response_pkt[i];
  3064. void *rsp = (void *)&r->response;
  3065. if (!__core_in_valid_state(device)) {
  3066. dprintk(CVP_ERR,
  3067. _INVALID_STATE_, (i + 1), num_responses);
  3068. break;
  3069. }
  3070. dprintk(CVP_HFI, "Processing response %d of %d, type %d\n",
  3071. (i + 1), num_responses, r->response_type);
  3072. /* callback = void cvp_handle_cmd_response() */
  3073. device->callback(r->response_type, rsp);
  3074. }
  3075. /* We need re-enable the irq which was disabled in ISR handler */
  3076. if (!(intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  3077. enable_irq(device->cvp_hal_data->irq);
  3078. return IRQ_HANDLED;
  3079. }
  3080. irqreturn_t cvp_hfi_isr(int irq, void *dev)
  3081. {
  3082. disable_irq_nosync(irq);
  3083. return IRQ_WAKE_THREAD;
  3084. }
  3085. static void iris_hfi_wd_work_handler(struct work_struct *work)
  3086. {
  3087. struct msm_cvp_core *core;
  3088. struct iris_hfi_device *device;
  3089. struct msm_cvp_cb_cmd_done response = {0};
  3090. enum hal_command_response cmd = HAL_SYS_WATCHDOG_TIMEOUT;
  3091. core = cvp_driver->cvp_core;
  3092. if (core)
  3093. device = core->dev_ops->hfi_device_data;
  3094. else
  3095. return;
  3096. if (msm_cvp_hw_wd_recovery) {
  3097. dprintk(CVP_ERR, "Cleaning up as HW WD recovery is enable %d\n",
  3098. msm_cvp_hw_wd_recovery);
  3099. __print_sidebandmanager_regs(device);
  3100. response.device_id = 0;
  3101. handle_sys_error(cmd, (void *) &response);
  3102. enable_irq(device->cvp_hal_data->irq_wd);
  3103. }
  3104. else {
  3105. dprintk(CVP_ERR, "Crashing the device as HW WD recovery is disable %d\n",
  3106. msm_cvp_hw_wd_recovery);
  3107. BUG_ON(1);
  3108. }
  3109. }
  3110. static DECLARE_WORK(iris_hfi_wd_work, iris_hfi_wd_work_handler);
  3111. irqreturn_t iris_hfi_isr_wd(int irq, void *dev)
  3112. {
  3113. struct iris_hfi_device *device = dev;
  3114. dprintk(CVP_ERR, "Got HW WDOG IRQ at %llu! \n", get_aon_time());
  3115. disable_irq_nosync(irq);
  3116. queue_work(device->cvp_workq, &iris_hfi_wd_work);
  3117. return IRQ_HANDLED;
  3118. }
  3119. static int __init_reset_clk(struct msm_cvp_platform_resources *res,
  3120. int reset_index)
  3121. {
  3122. int rc = 0;
  3123. struct reset_control *rst;
  3124. struct reset_info *rst_info;
  3125. struct reset_set *rst_set = &res->reset_set;
  3126. if (!rst_set->reset_tbl)
  3127. return 0;
  3128. rst_info = &rst_set->reset_tbl[reset_index];
  3129. rst = rst_info->rst;
  3130. dprintk(CVP_PWR, "reset_clk: name %s rst %pK required_stage=%d\n",
  3131. rst_set->reset_tbl[reset_index].name, rst, rst_info->required_stage);
  3132. if (rst)
  3133. goto skip_reset_init;
  3134. if (rst_info->required_stage == CVP_ON_USE) {
  3135. rst = reset_control_get_exclusive_released(&res->pdev->dev,
  3136. rst_set->reset_tbl[reset_index].name);
  3137. if (IS_ERR(rst)) {
  3138. rc = PTR_ERR(rst);
  3139. dprintk(CVP_ERR, "reset get exclusive fail %d\n", rc);
  3140. return rc;
  3141. }
  3142. dprintk(CVP_PWR, "reset_clk: name %s get exclusive rst %llx\n",
  3143. rst_set->reset_tbl[reset_index].name, rst);
  3144. } else if (rst_info->required_stage == CVP_ON_INIT) {
  3145. rst = devm_reset_control_get(&res->pdev->dev,
  3146. rst_set->reset_tbl[reset_index].name);
  3147. if (IS_ERR(rst)) {
  3148. rc = PTR_ERR(rst);
  3149. dprintk(CVP_ERR, "reset get fail %d\n", rc);
  3150. return rc;
  3151. }
  3152. dprintk(CVP_PWR, "reset_clk: name %s get rst %llx\n",
  3153. rst_set->reset_tbl[reset_index].name, rst);
  3154. } else {
  3155. dprintk(CVP_ERR, "Invalid reset stage\n");
  3156. return -EINVAL;
  3157. }
  3158. rst_set->reset_tbl[reset_index].rst = rst;
  3159. rst_info->state = RESET_INIT;
  3160. return 0;
  3161. skip_reset_init:
  3162. return rc;
  3163. }
  3164. static int __reset_control_assert_name(struct iris_hfi_device *device,
  3165. const char *name)
  3166. {
  3167. struct reset_info *rcinfo = NULL;
  3168. int rc = 0;
  3169. bool found = false;
  3170. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3171. if (strcmp(rcinfo->name, name))
  3172. continue;
  3173. found = true;
  3174. rc = reset_control_assert(rcinfo->rst);
  3175. if (rc)
  3176. dprintk(CVP_ERR,
  3177. "%s: failed to assert reset control (%s), rc = %d\n",
  3178. __func__, rcinfo->name, rc);
  3179. else
  3180. dprintk(CVP_PWR, "%s: assert reset control (%s)\n",
  3181. __func__, rcinfo->name);
  3182. break;
  3183. }
  3184. if (!found) {
  3185. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3186. __func__, name);
  3187. rc = -EINVAL;
  3188. }
  3189. return rc;
  3190. }
  3191. static int __reset_control_deassert_name(struct iris_hfi_device *device,
  3192. const char *name)
  3193. {
  3194. struct reset_info *rcinfo = NULL;
  3195. int rc = 0;
  3196. bool found = false;
  3197. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3198. if (strcmp(rcinfo->name, name))
  3199. continue;
  3200. found = true;
  3201. rc = reset_control_deassert(rcinfo->rst);
  3202. if (rc)
  3203. dprintk(CVP_ERR,
  3204. "%s: deassert reset control for (%s) failed, rc %d\n",
  3205. __func__, rcinfo->name, rc);
  3206. else
  3207. dprintk(CVP_PWR, "%s: deassert reset control (%s)\n",
  3208. __func__, rcinfo->name);
  3209. break;
  3210. }
  3211. if (!found) {
  3212. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3213. __func__, name);
  3214. rc = -EINVAL;
  3215. }
  3216. return rc;
  3217. }
  3218. static int __reset_control_acquire(struct iris_hfi_device *device,
  3219. const char *name)
  3220. {
  3221. struct reset_info *rcinfo = NULL;
  3222. int rc = 0;
  3223. bool found = false;
  3224. int max_retries = 10000;
  3225. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3226. if (strcmp(rcinfo->name, name))
  3227. continue;
  3228. found = true;
  3229. if (rcinfo->state == RESET_ACQUIRED)
  3230. return rc;
  3231. acquire_again:
  3232. rc = reset_control_acquire(rcinfo->rst);
  3233. if (rc) {
  3234. if (rc == -EBUSY) {
  3235. usleep_range(100, 150);
  3236. max_retries--;
  3237. if (max_retries) {
  3238. goto acquire_again;
  3239. } else {
  3240. dprintk(CVP_ERR,
  3241. "%s acquire %s -EBUSY\n",
  3242. __func__, rcinfo->name);
  3243. BUG_ON(1);
  3244. }
  3245. } else {
  3246. dprintk(CVP_ERR,
  3247. "%s: acquire failed (%s) rc %d\n",
  3248. __func__, rcinfo->name, rc);
  3249. rc = -EINVAL;
  3250. }
  3251. } else {
  3252. dprintk(CVP_PWR, "%s: reset acquire succeed (%s)\n",
  3253. __func__, rcinfo->name);
  3254. rcinfo->state = RESET_ACQUIRED;
  3255. }
  3256. break;
  3257. }
  3258. if (!found) {
  3259. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3260. __func__, name);
  3261. rc = -EINVAL;
  3262. }
  3263. return rc;
  3264. }
  3265. static int __reset_control_release(struct iris_hfi_device *device,
  3266. const char *name)
  3267. {
  3268. struct reset_info *rcinfo = NULL;
  3269. int rc = 0;
  3270. bool found = false;
  3271. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3272. if (strcmp(rcinfo->name, name))
  3273. continue;
  3274. found = true;
  3275. if (rcinfo->state != RESET_ACQUIRED) {
  3276. dprintk(CVP_WARN, "Double releasing reset clk?\n");
  3277. return -EINVAL;
  3278. }
  3279. reset_control_release(rcinfo->rst);
  3280. dprintk(CVP_PWR, "%s: reset release succeed (%s)\n",
  3281. __func__, rcinfo->name);
  3282. rcinfo->state = RESET_RELEASED;
  3283. break;
  3284. }
  3285. if (!found) {
  3286. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3287. __func__, name);
  3288. rc = -EINVAL;
  3289. }
  3290. return rc;
  3291. }
  3292. static void __deinit_bus(struct iris_hfi_device *device)
  3293. {
  3294. struct bus_info *bus = NULL;
  3295. if (!device)
  3296. return;
  3297. kfree(device->bus_vote.data);
  3298. device->bus_vote = CVP_DEFAULT_BUS_VOTE;
  3299. iris_hfi_for_each_bus_reverse(device, bus) {
  3300. dev_set_drvdata(bus->dev, NULL);
  3301. icc_put(bus->client);
  3302. bus->client = NULL;
  3303. }
  3304. }
  3305. static int __init_bus(struct iris_hfi_device *device)
  3306. {
  3307. struct bus_info *bus = NULL;
  3308. int rc = 0;
  3309. if (!device)
  3310. return -EINVAL;
  3311. iris_hfi_for_each_bus(device, bus) {
  3312. /*
  3313. * This is stupid, but there's no other easy way to ahold
  3314. * of struct bus_info in iris_hfi_devfreq_*()
  3315. */
  3316. WARN(dev_get_drvdata(bus->dev), "%s's drvdata already set\n",
  3317. dev_name(bus->dev));
  3318. dev_set_drvdata(bus->dev, device);
  3319. bus->client = icc_get(&device->res->pdev->dev,
  3320. bus->master, bus->slave);
  3321. if (IS_ERR_OR_NULL(bus->client)) {
  3322. rc = PTR_ERR(bus->client) ?: -EBADHANDLE;
  3323. dprintk(CVP_ERR, "Failed to register bus %s: %d\n",
  3324. bus->name, rc);
  3325. bus->client = NULL;
  3326. goto err_add_dev;
  3327. }
  3328. }
  3329. return 0;
  3330. err_add_dev:
  3331. __deinit_bus(device);
  3332. return rc;
  3333. }
  3334. static void __deinit_regulators(struct iris_hfi_device *device)
  3335. {
  3336. struct regulator_info *rinfo = NULL;
  3337. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3338. if (rinfo->regulator) {
  3339. regulator_put(rinfo->regulator);
  3340. rinfo->regulator = NULL;
  3341. }
  3342. }
  3343. }
  3344. static int __init_regulators(struct iris_hfi_device *device)
  3345. {
  3346. int rc = 0;
  3347. struct regulator_info *rinfo = NULL;
  3348. iris_hfi_for_each_regulator(device, rinfo) {
  3349. rinfo->regulator = regulator_get(&device->res->pdev->dev,
  3350. rinfo->name);
  3351. if (IS_ERR_OR_NULL(rinfo->regulator)) {
  3352. rc = PTR_ERR(rinfo->regulator) ?: -EBADHANDLE;
  3353. dprintk(CVP_ERR, "Failed to get regulator: %s\n",
  3354. rinfo->name);
  3355. rinfo->regulator = NULL;
  3356. goto err_reg_get;
  3357. }
  3358. }
  3359. return 0;
  3360. err_reg_get:
  3361. __deinit_regulators(device);
  3362. return rc;
  3363. }
  3364. static void __deinit_subcaches(struct iris_hfi_device *device)
  3365. {
  3366. struct subcache_info *sinfo = NULL;
  3367. if (!device) {
  3368. dprintk(CVP_ERR, "deinit_subcaches: invalid device %pK\n",
  3369. device);
  3370. goto exit;
  3371. }
  3372. if (!is_sys_cache_present(device))
  3373. goto exit;
  3374. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3375. if (sinfo->subcache) {
  3376. dprintk(CVP_CORE, "deinit_subcaches: %s\n",
  3377. sinfo->name);
  3378. llcc_slice_putd(sinfo->subcache);
  3379. sinfo->subcache = NULL;
  3380. }
  3381. }
  3382. exit:
  3383. return;
  3384. }
  3385. static int __init_subcaches(struct iris_hfi_device *device)
  3386. {
  3387. int rc = 0;
  3388. struct subcache_info *sinfo = NULL;
  3389. if (!device) {
  3390. dprintk(CVP_ERR, "init_subcaches: invalid device %pK\n",
  3391. device);
  3392. return -EINVAL;
  3393. }
  3394. if (!is_sys_cache_present(device))
  3395. return 0;
  3396. iris_hfi_for_each_subcache(device, sinfo) {
  3397. if (!strcmp("cvp", sinfo->name)) {
  3398. sinfo->subcache = llcc_slice_getd(LLCC_CVP);
  3399. } else if (!strcmp("cvpfw", sinfo->name)) {
  3400. sinfo->subcache = llcc_slice_getd(LLCC_CVPFW);
  3401. } else {
  3402. dprintk(CVP_ERR, "Invalid subcache name %s\n",
  3403. sinfo->name);
  3404. }
  3405. if (IS_ERR_OR_NULL(sinfo->subcache)) {
  3406. rc = PTR_ERR(sinfo->subcache) ?
  3407. PTR_ERR(sinfo->subcache) : -EBADHANDLE;
  3408. dprintk(CVP_ERR,
  3409. "init_subcaches: invalid subcache: %s rc %d\n",
  3410. sinfo->name, rc);
  3411. sinfo->subcache = NULL;
  3412. goto err_subcache_get;
  3413. }
  3414. dprintk(CVP_CORE, "init_subcaches: %s\n",
  3415. sinfo->name);
  3416. }
  3417. return 0;
  3418. err_subcache_get:
  3419. __deinit_subcaches(device);
  3420. return rc;
  3421. }
  3422. static int __init_resources(struct iris_hfi_device *device,
  3423. struct msm_cvp_platform_resources *res)
  3424. {
  3425. int i, rc = 0;
  3426. rc = __init_regulators(device);
  3427. if (rc) {
  3428. dprintk(CVP_ERR, "Failed to get all regulators\n");
  3429. return -ENODEV;
  3430. }
  3431. rc = msm_cvp_init_clocks(device);
  3432. if (rc) {
  3433. dprintk(CVP_ERR, "Failed to init clocks\n");
  3434. rc = -ENODEV;
  3435. goto err_init_clocks;
  3436. }
  3437. for (i = 0; i < device->res->reset_set.count; i++) {
  3438. rc = __init_reset_clk(res, i);
  3439. if (rc) {
  3440. dprintk(CVP_ERR, "Failed to init reset clocks\n");
  3441. rc = -ENODEV;
  3442. goto err_init_reset_clk;
  3443. }
  3444. }
  3445. rc = __init_bus(device);
  3446. if (rc) {
  3447. dprintk(CVP_ERR, "Failed to init bus: %d\n", rc);
  3448. goto err_init_bus;
  3449. }
  3450. rc = __init_subcaches(device);
  3451. if (rc)
  3452. dprintk(CVP_WARN, "Failed to init subcaches: %d\n", rc);
  3453. device->sys_init_capabilities =
  3454. kzalloc(sizeof(struct msm_cvp_capability)
  3455. * CVP_MAX_SESSIONS, GFP_KERNEL);
  3456. return rc;
  3457. err_init_reset_clk:
  3458. err_init_bus:
  3459. msm_cvp_deinit_clocks(device);
  3460. err_init_clocks:
  3461. __deinit_regulators(device);
  3462. return rc;
  3463. }
  3464. static void __deinit_resources(struct iris_hfi_device *device)
  3465. {
  3466. __deinit_subcaches(device);
  3467. __deinit_bus(device);
  3468. msm_cvp_deinit_clocks(device);
  3469. __deinit_regulators(device);
  3470. kfree(device->sys_init_capabilities);
  3471. device->sys_init_capabilities = NULL;
  3472. }
  3473. static int __disable_regulator_impl(struct regulator_info *rinfo,
  3474. struct iris_hfi_device *device)
  3475. {
  3476. int rc = 0;
  3477. dprintk(CVP_PWR, "Disabling regulator %s\n", rinfo->name);
  3478. /*
  3479. * This call is needed. Driver needs to acquire the control back
  3480. * from HW in order to disable the regualtor. Else the behavior
  3481. * is unknown.
  3482. */
  3483. rc = __acquire_regulator(rinfo, device);
  3484. if (rc) {
  3485. /*
  3486. * This is somewhat fatal, but nothing we can do
  3487. * about it. We can't disable the regulator w/o
  3488. * getting it back under s/w control
  3489. */
  3490. dprintk(CVP_WARN,
  3491. "Failed to acquire control on %s\n",
  3492. rinfo->name);
  3493. goto disable_regulator_failed;
  3494. }
  3495. /*Acquire XO_RESET to avoid race condition with video*/
  3496. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3497. if (rc) {
  3498. dprintk(CVP_ERR,
  3499. "XO_RESET could not be acquired: skip disabling the regulator %s\n",
  3500. rinfo->name);
  3501. return -EINVAL;
  3502. }
  3503. rc = regulator_disable(rinfo->regulator);
  3504. /*Release XO_RESET after regulator is enabled.*/
  3505. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3506. if (rc) {
  3507. dprintk(CVP_WARN,
  3508. "Failed to disable %s: %d\n",
  3509. rinfo->name, rc);
  3510. goto disable_regulator_failed;
  3511. }
  3512. return 0;
  3513. disable_regulator_failed:
  3514. /* Bring attention to this issue */
  3515. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3516. return rc;
  3517. }
  3518. static int __disable_hw_power_collapse(struct iris_hfi_device *device)
  3519. {
  3520. int rc = 0;
  3521. if (!msm_cvp_fw_low_power_mode) {
  3522. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3523. return 0;
  3524. }
  3525. rc = __take_back_regulators(device);
  3526. if (rc)
  3527. dprintk(CVP_WARN,
  3528. "%s : Failed to disable HW power collapse %d\n",
  3529. __func__, rc);
  3530. return rc;
  3531. }
  3532. static int __enable_hw_power_collapse(struct iris_hfi_device *device)
  3533. {
  3534. int rc = 0;
  3535. if (!msm_cvp_fw_low_power_mode) {
  3536. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3537. return 0;
  3538. }
  3539. rc = __hand_off_regulators(device);
  3540. if (rc)
  3541. dprintk(CVP_WARN,
  3542. "%s : Failed to enable HW power collapse %d\n",
  3543. __func__, rc);
  3544. return rc;
  3545. }
  3546. static int __enable_regulator(struct iris_hfi_device *device,
  3547. const char *name)
  3548. {
  3549. int rc = 0;
  3550. struct regulator_info *rinfo;
  3551. iris_hfi_for_each_regulator(device, rinfo) {
  3552. if (strcmp(rinfo->name, name))
  3553. continue;
  3554. /*Acquire XO_RESET to avoid race condition with video*/
  3555. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3556. if (rc) {
  3557. dprintk(CVP_ERR,
  3558. "XO_RESET could not be acquired: skip enabling the regulator %s\n",
  3559. rinfo->name);
  3560. return -EINVAL;
  3561. }
  3562. rc = regulator_enable(rinfo->regulator);
  3563. /*Release XO_RESET after regulator is enabled.*/
  3564. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3565. if (rc) {
  3566. dprintk(CVP_ERR, "Failed to enable %s: %d\n",
  3567. rinfo->name, rc);
  3568. return rc;
  3569. }
  3570. if (!regulator_is_enabled(rinfo->regulator)) {
  3571. dprintk(CVP_ERR,"%s: regulator %s not enabled\n",
  3572. __func__, rinfo->name);
  3573. regulator_disable(rinfo->regulator);
  3574. return -EINVAL;
  3575. }
  3576. dprintk(CVP_PWR, "Enabled regulator %s\n", rinfo->name);
  3577. return 0;
  3578. }
  3579. dprintk(CVP_ERR, "regulator %s not found\n", name);
  3580. return -EINVAL;
  3581. }
  3582. static int __disable_regulator(struct iris_hfi_device *device,
  3583. const char *name)
  3584. {
  3585. struct regulator_info *rinfo;
  3586. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3587. if (strcmp(rinfo->name, name))
  3588. continue;
  3589. __disable_regulator_impl(rinfo, device);
  3590. dprintk(CVP_PWR, "%s Disabled regulator %s\n", __func__, name);
  3591. return 0;
  3592. }
  3593. dprintk(CVP_ERR, "%s regulator %s not found\n", __func__, name);
  3594. return -EINVAL;
  3595. }
  3596. static int __enable_subcaches(struct iris_hfi_device *device)
  3597. {
  3598. int rc = 0;
  3599. u32 c = 0;
  3600. struct subcache_info *sinfo;
  3601. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3602. return 0;
  3603. /* Activate subcaches */
  3604. iris_hfi_for_each_subcache(device, sinfo) {
  3605. rc = llcc_slice_activate(sinfo->subcache);
  3606. if (rc) {
  3607. dprintk(CVP_WARN, "Failed to activate %s: %d\n",
  3608. sinfo->name, rc);
  3609. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3610. goto err_activate_fail;
  3611. }
  3612. sinfo->isactive = true;
  3613. dprintk(CVP_CORE, "Activated subcache %s\n", sinfo->name);
  3614. c++;
  3615. }
  3616. dprintk(CVP_CORE, "Activated %d Subcaches to CVP\n", c);
  3617. return 0;
  3618. err_activate_fail:
  3619. __release_subcaches(device);
  3620. __disable_subcaches(device);
  3621. return 0;
  3622. }
  3623. static int __set_subcaches(struct iris_hfi_device *device)
  3624. {
  3625. int rc = 0;
  3626. u32 c = 0;
  3627. struct subcache_info *sinfo;
  3628. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3629. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3630. struct cvp_hfi_resource_subcache_type *sc_res;
  3631. struct cvp_resource_hdr rhdr;
  3632. if (device->res->sys_cache_res_set || msm_cvp_syscache_disable) {
  3633. dprintk(CVP_CORE, "Subcaches already set or disabled\n");
  3634. return 0;
  3635. }
  3636. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3637. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3638. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3639. iris_hfi_for_each_subcache(device, sinfo) {
  3640. if (sinfo->isactive) {
  3641. sc_res[c].size = sinfo->subcache->slice_size;
  3642. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3643. c++;
  3644. }
  3645. }
  3646. /* Set resource to CVP for activated subcaches */
  3647. if (c) {
  3648. dprintk(CVP_CORE, "Setting %d Subcaches\n", c);
  3649. rhdr.resource_handle = sc_res_info; /* cookie */
  3650. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3651. sc_res_info->num_entries = c;
  3652. rc = __core_set_resource(device, &rhdr, (void *)sc_res_info);
  3653. if (rc) {
  3654. dprintk(CVP_WARN, "Failed to set subcaches %d\n", rc);
  3655. goto err_fail_set_subacaches;
  3656. }
  3657. iris_hfi_for_each_subcache(device, sinfo) {
  3658. if (sinfo->isactive)
  3659. sinfo->isset = true;
  3660. }
  3661. dprintk(CVP_CORE, "Set Subcaches done to CVP\n");
  3662. device->res->sys_cache_res_set = true;
  3663. }
  3664. return 0;
  3665. err_fail_set_subacaches:
  3666. __disable_subcaches(device);
  3667. return 0;
  3668. }
  3669. static int __release_subcaches(struct iris_hfi_device *device)
  3670. {
  3671. struct subcache_info *sinfo;
  3672. int rc = 0;
  3673. u32 c = 0;
  3674. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3675. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3676. struct cvp_hfi_resource_subcache_type *sc_res;
  3677. struct cvp_resource_hdr rhdr;
  3678. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3679. return 0;
  3680. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3681. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3682. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3683. /* Release resource command to Iris */
  3684. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3685. if (sinfo->isset) {
  3686. /* Update the entry */
  3687. sc_res[c].size = sinfo->subcache->slice_size;
  3688. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3689. c++;
  3690. sinfo->isset = false;
  3691. }
  3692. }
  3693. if (c > 0) {
  3694. dprintk(CVP_CORE, "Releasing %d subcaches\n", c);
  3695. rhdr.resource_handle = sc_res_info; /* cookie */
  3696. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3697. rc = __core_release_resource(device, &rhdr);
  3698. if (rc)
  3699. dprintk(CVP_WARN,
  3700. "Failed to release %d subcaches\n", c);
  3701. }
  3702. device->res->sys_cache_res_set = false;
  3703. return 0;
  3704. }
  3705. static int __disable_subcaches(struct iris_hfi_device *device)
  3706. {
  3707. struct subcache_info *sinfo;
  3708. int rc = 0;
  3709. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3710. return 0;
  3711. /* De-activate subcaches */
  3712. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3713. if (sinfo->isactive) {
  3714. dprintk(CVP_CORE, "De-activate subcache %s\n",
  3715. sinfo->name);
  3716. rc = llcc_slice_deactivate(sinfo->subcache);
  3717. if (rc) {
  3718. dprintk(CVP_WARN,
  3719. "Failed to de-activate %s: %d\n",
  3720. sinfo->name, rc);
  3721. }
  3722. sinfo->isactive = false;
  3723. }
  3724. }
  3725. return 0;
  3726. }
  3727. static void interrupt_init_iris2(struct iris_hfi_device *device)
  3728. {
  3729. u32 mask_val = 0;
  3730. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  3731. mask_val = __read_register(device, CVP_WRAPPER_INTR_MASK);
  3732. /* Write 0 to unmask CPU and WD interrupts */
  3733. mask_val &= ~(CVP_FATAL_INTR_BMSK | CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK);
  3734. __write_register(device, CVP_WRAPPER_INTR_MASK, mask_val);
  3735. dprintk(CVP_REG, "Init irq: reg: %x, mask value %x\n",
  3736. CVP_WRAPPER_INTR_MASK, mask_val);
  3737. mask_val = 0;
  3738. mask_val = __read_register(device, CVP_SS_IRQ_MASK);
  3739. mask_val &= ~(CVP_SS_INTR_BMASK);
  3740. __write_register(device, CVP_SS_IRQ_MASK, mask_val);
  3741. dprintk(CVP_REG, "Init irq_wd: reg: %x, mask value %x\n",
  3742. CVP_SS_IRQ_MASK, mask_val);
  3743. }
  3744. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device)
  3745. {
  3746. /* initialize DSP QTBL & UCREGION with CPU queues */
  3747. __write_register(device, HFI_DSP_QTBL_ADDR,
  3748. (u32)device->dsp_iface_q_table.align_device_addr);
  3749. __write_register(device, HFI_DSP_UC_REGION_ADDR,
  3750. (u32)device->dsp_iface_q_table.align_device_addr);
  3751. __write_register(device, HFI_DSP_UC_REGION_SIZE,
  3752. device->dsp_iface_q_table.mem_data.size);
  3753. }
  3754. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device)
  3755. {
  3756. __write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);
  3757. }
  3758. static int __set_ubwc_config(struct iris_hfi_device *device)
  3759. {
  3760. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  3761. int rc = 0;
  3762. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  3763. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  3764. if (!device->res->ubwc_config)
  3765. return 0;
  3766. rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,
  3767. device->res->ubwc_config);
  3768. if (rc) {
  3769. dprintk(CVP_WARN,
  3770. "ubwc config setting to FW failed\n");
  3771. rc = -ENOTEMPTY;
  3772. goto fail_to_set_ubwc_config;
  3773. }
  3774. if (__iface_cmdq_write(device, pkt)) {
  3775. rc = -ENOTEMPTY;
  3776. goto fail_to_set_ubwc_config;
  3777. }
  3778. fail_to_set_ubwc_config:
  3779. return rc;
  3780. }
  3781. static int __power_on_controller(struct iris_hfi_device *device)
  3782. {
  3783. int rc = 0;
  3784. rc = __enable_regulator(device, "cvp");
  3785. if (rc) {
  3786. dprintk(CVP_ERR, "Failed to enable ctrler: %d\n", rc);
  3787. return rc;
  3788. }
  3789. rc = msm_cvp_prepare_enable_clk(device, "sleep_clk");
  3790. if (rc) {
  3791. dprintk(CVP_ERR, "Failed to enable sleep clk: %d\n", rc);
  3792. goto fail_reset_clks;
  3793. }
  3794. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  3795. if (rc)
  3796. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  3797. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  3798. if (rc)
  3799. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  3800. /* wait for deassert */
  3801. usleep_range(300, 400);
  3802. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  3803. if (rc)
  3804. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  3805. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  3806. if (rc)
  3807. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  3808. rc = msm_cvp_prepare_enable_clk(device, "gcc_video_axi1");
  3809. if (rc) {
  3810. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  3811. goto fail_reset_clks;
  3812. }
  3813. rc = msm_cvp_prepare_enable_clk(device, "cvp_clk");
  3814. if (rc) {
  3815. dprintk(CVP_ERR, "Failed to enable cvp_clk: %d\n", rc);
  3816. goto fail_enable_clk;
  3817. }
  3818. dprintk(CVP_PWR, "EVA controller powered on\n");
  3819. return 0;
  3820. fail_enable_clk:
  3821. msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  3822. fail_reset_clks:
  3823. __disable_regulator(device, "cvp");
  3824. return rc;
  3825. }
  3826. static int __power_on_core(struct iris_hfi_device *device)
  3827. {
  3828. int rc = 0;
  3829. rc = __enable_regulator(device, "cvp-core");
  3830. if (rc) {
  3831. dprintk(CVP_ERR, "Failed to enable core: %d\n", rc);
  3832. return rc;
  3833. }
  3834. rc = msm_cvp_prepare_enable_clk(device, "video_cc_mvs1_clk_src");
  3835. if (rc) {
  3836. dprintk(CVP_ERR, "Failed to enable video_cc_mvs1_clk_src:%d\n",
  3837. rc);
  3838. __disable_regulator(device, "cvp-core");
  3839. return rc;
  3840. }
  3841. rc = msm_cvp_prepare_enable_clk(device, "core_clk");
  3842. if (rc) {
  3843. dprintk(CVP_ERR, "Failed to enable core_clk: %d\n", rc);
  3844. __disable_regulator(device, "cvp-core");
  3845. return rc;
  3846. }
  3847. /*#ifdef CONFIG_EVA_PINEAPPLE
  3848. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_ARCG_CONTROL, 0);
  3849. __write_register(device, CVP_NOC_RCGCONTROLLER_HYSTERESIS_LOW, 0x2f);
  3850. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 1);
  3851. __write_register(device, CVP_NOC_RCGCONTROLLER_MAINCTL_LOW, 1);
  3852. usleep_range(50, 100);
  3853. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 0);
  3854. #endif*/
  3855. dprintk(CVP_PWR, "EVA core powered on\n");
  3856. return 0;
  3857. }
  3858. static int __iris_power_on(struct iris_hfi_device *device)
  3859. {
  3860. int rc = 0;
  3861. u32 reg_gdsc, reg_cbcr, spare_val;
  3862. if (device->power_enabled)
  3863. return 0;
  3864. /* Vote for all hardware resources */
  3865. rc = __vote_buses(device, device->bus_vote.data,
  3866. device->bus_vote.data_count);
  3867. if (rc) {
  3868. dprintk(CVP_ERR, "Failed to vote buses, err: %d\n", rc);
  3869. goto fail_vote_buses;
  3870. }
  3871. rc = __power_on_controller(device);
  3872. if (rc)
  3873. goto fail_enable_controller;
  3874. rc = __power_on_core(device);
  3875. if (rc)
  3876. goto fail_enable_core;
  3877. rc = msm_cvp_scale_clocks(device);
  3878. if (rc) {
  3879. dprintk(CVP_WARN,
  3880. "Failed to scale clocks, perf may regress\n");
  3881. rc = 0;
  3882. } else {
  3883. dprintk(CVP_PWR, "Done with scaling\n");
  3884. }
  3885. /*Do not access registers before this point!*/
  3886. device->power_enabled = true;
  3887. /* Thomas input to debug CPU NoC hang */
  3888. __write_register(device, CVP_NOC_SBM_FAULTINEN0_LOW, 0x1);
  3889. __write_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS, 0x3);
  3890. /*
  3891. * Re-program all of the registers that get reset as a result of
  3892. * regulator_disable() and _enable()
  3893. * calling below function requires CORE powered on
  3894. */
  3895. rc = __set_registers(device);
  3896. if (rc)
  3897. goto fail_enable_core;
  3898. dprintk(CVP_CORE, "Done with register set\n");
  3899. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  3900. reg_cbcr = __read_register(device, CVP_CC_MVS1_CBCR);
  3901. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3902. rc = -EINVAL;
  3903. dprintk(CVP_ERR, "CORE power on failed gdsc %x cbcr %x\n",
  3904. reg_gdsc, reg_cbcr);
  3905. goto fail_enable_core;
  3906. }
  3907. reg_gdsc = __read_register(device, CVP_CC_MVS1C_GDSCR);
  3908. reg_cbcr = __read_register(device, CVP_CC_MVS1C_CBCR);
  3909. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3910. rc = -EINVAL;
  3911. dprintk(CVP_ERR, "CTRL power on failed gdsc %x cbcr %x\n",
  3912. reg_gdsc, reg_cbcr);
  3913. goto fail_enable_core;
  3914. }
  3915. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3916. if ((spare_val & 0x2) != 0) {
  3917. usleep_range(2000, 3000);
  3918. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3919. if ((spare_val & 0x2) != 0) {
  3920. dprintk(CVP_ERR, "WRAPPER_SPARE non-zero %#x\n", spare_val);
  3921. rc = -EINVAL;
  3922. goto fail_enable_core;
  3923. }
  3924. }
  3925. call_iris_op(device, interrupt_init, device);
  3926. dprintk(CVP_CORE, "Done with interrupt enabling\n");
  3927. device->intr_status = 0;
  3928. enable_irq(device->cvp_hal_data->irq);
  3929. __write_register(device,
  3930. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
  3931. pr_info_ratelimited(CVP_DBG_TAG "cvp (eva) powered on\n", "pwr");
  3932. return 0;
  3933. fail_enable_core:
  3934. __power_off_controller(device);
  3935. fail_enable_controller:
  3936. __unvote_buses(device);
  3937. fail_vote_buses:
  3938. device->power_enabled = false;
  3939. return rc;
  3940. }
  3941. static inline int __suspend(struct iris_hfi_device *device)
  3942. {
  3943. int rc = 0;
  3944. if (!device) {
  3945. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3946. return -EINVAL;
  3947. } else if (!device->power_enabled) {
  3948. dprintk(CVP_PWR, "Power already disabled\n");
  3949. return 0;
  3950. }
  3951. dprintk(CVP_PWR, "Entering suspend\n");
  3952. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3953. if (rc) {
  3954. dprintk(CVP_WARN, "Failed to suspend cvp core %d\n", rc);
  3955. goto err_tzbsp_suspend;
  3956. }
  3957. __disable_subcaches(device);
  3958. call_iris_op(device, power_off, device);
  3959. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  3960. cvp_pm_qos_update(device, false);
  3961. return rc;
  3962. err_tzbsp_suspend:
  3963. return rc;
  3964. }
  3965. static void __print_sidebandmanager_regs(struct iris_hfi_device *device)
  3966. {
  3967. u32 sbm_ln0_low, axi_cbcr, val;
  3968. u32 main_sbm_ln0_low = 0xdeadbeef, main_sbm_ln0_high = 0xdeadbeef;
  3969. u32 main_sbm_ln1_high = 0xdeadbeef, cpu_cs_x2rpmh;
  3970. int rc;
  3971. sbm_ln0_low =
  3972. __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3973. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3974. __write_register(device, CVP_CPU_CS_X2RPMh,
  3975. (cpu_cs_x2rpmh | CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK));
  3976. usleep_range(500, 1000);
  3977. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3978. if (!(cpu_cs_x2rpmh & CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK)) {
  3979. dprintk(CVP_WARN,
  3980. "failed set CVP_CPU_CS_X2RPMH mask %x\n",
  3981. cpu_cs_x2rpmh);
  3982. goto exit;
  3983. }
  3984. axi_cbcr = __read_gcc_register(device, CVP_GCC_VIDEO_AXI1_CBCR);
  3985. if (axi_cbcr & 0x80000000) {
  3986. dprintk(CVP_WARN, "failed to turn on AXI clock %x\n",
  3987. axi_cbcr);
  3988. goto exit;
  3989. }
  3990. /* Added by Thomas to debug CPU NoC hang */
  3991. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  3992. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRVLD_LOW %#x\n", val);
  3993. val = __read_register(device, CVP_NOC_SBM_FAULTINSTATUS0_LOW);
  3994. dprintk(CVP_ERR, "CVP_NOC_SBM_FAULTINSTATUS0_LOW %#x\n", val);
  3995. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  3996. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_LOW %#x\n", val);
  3997. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  3998. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH %#x\n", val);
  3999. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  4000. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_LOW %#x\n", val);
  4001. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  4002. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH %#x\n", val);
  4003. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  4004. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_LOW %#x\n", val);
  4005. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  4006. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH %#x\n", val);
  4007. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  4008. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_LOW %#x\n", val);
  4009. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  4010. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH %#x\n", val);
  4011. /* end of addition */
  4012. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4013. if (rc) {
  4014. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4015. goto exit;
  4016. }
  4017. main_sbm_ln0_low = __read_register(device,
  4018. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW +
  4019. device->res->noc_main_sidebandmanager_offset);
  4020. main_sbm_ln0_high = __read_register(device,
  4021. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_HIGH +
  4022. device->res->noc_main_sidebandmanager_offset);
  4023. main_sbm_ln1_high = __read_register(device,
  4024. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH +
  4025. device->res->noc_main_sidebandmanager_offset);
  4026. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4027. exit:
  4028. cpu_cs_x2rpmh = cpu_cs_x2rpmh & (~CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK);
  4029. __write_register(device, CVP_CPU_CS_X2RPMh, cpu_cs_x2rpmh);
  4030. dprintk(CVP_WARN, "Sidebandmanager regs %x %x %x %x %x\n",
  4031. sbm_ln0_low, main_sbm_ln0_low,
  4032. main_sbm_ln0_high, main_sbm_ln1_high,
  4033. cpu_cs_x2rpmh);
  4034. }
  4035. static void __enter_cpu_noc_lpi(struct iris_hfi_device *device)
  4036. {
  4037. u32 lpi_status, count = 0, max_count = 2000;
  4038. /* New addition to put CPU/Tensilica to low power */
  4039. count = 0;
  4040. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  4041. while (count < max_count) {
  4042. lpi_status = __read_register(device, CVP_WRAPPER_CPU_NOC_LPI_STATUS);
  4043. if ((lpi_status & BIT(1)) || ((lpi_status & BIT(2)) && (!(lpi_status & BIT(0))))) {
  4044. /*
  4045. * If QDENY == true, or
  4046. * If QACTIVE == true && QACCEPT == false
  4047. * Try again
  4048. */
  4049. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x0);
  4050. usleep_range(10, 20);
  4051. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  4052. usleep_range(1000, 1200);
  4053. count++;
  4054. } else {
  4055. break;
  4056. }
  4057. }
  4058. dprintk(CVP_PWR,
  4059. "%s, CPU Noc: lpi_status %x (count %d)\n", __func__, lpi_status, count);
  4060. if (count == max_count) {
  4061. u32 pc_ready, wfi_status;
  4062. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4063. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4064. dprintk(CVP_WARN,
  4065. "%s, CPU NOC not in qaccept status %x %x %x\n",
  4066. __func__, lpi_status, wfi_status, pc_ready);
  4067. __print_sidebandmanager_regs(device);
  4068. }
  4069. }
  4070. static int __power_off_controller(struct iris_hfi_device *device)
  4071. {
  4072. u32 lpi_status, count = 0, max_count = 1000;
  4073. int rc;
  4074. u32 spare_val, spare_status;
  4075. /* HPG 6.2.2 Step 1 */
  4076. __write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
  4077. /* HPG 6.2.2 Step 2, noc to low power */
  4078. __enter_cpu_noc_lpi(device);
  4079. /* HPG 6.2.2 Step 3, debug bridge to low power BYPASSED */
  4080. /* HPG 6.2.2 Step 4, debug bridge to lpi release */
  4081. __write_register(device,
  4082. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x0);
  4083. lpi_status = 0x1;
  4084. count = 0;
  4085. while (lpi_status && count < max_count) {
  4086. lpi_status = __read_register(device,
  4087. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  4088. usleep_range(50, 100);
  4089. count++;
  4090. }
  4091. dprintk(CVP_PWR,
  4092. "DBLP Release: lpi_status %d(count %d)\n",
  4093. lpi_status, count);
  4094. if (count == max_count) {
  4095. dprintk(CVP_WARN,
  4096. "DBLP Release: lpi_status %x\n", lpi_status);
  4097. }
  4098. /* PDXFIFO reset: addition for Kailua / Lanai */
  4099. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x3);
  4100. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x1);
  4101. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x0);
  4102. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x0);
  4103. /* HPG 6.2.2 Step 5 */
  4104. msm_cvp_disable_unprepare_clk(device, "cvp_clk");
  4105. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  4106. if (rc)
  4107. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  4108. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  4109. if (rc)
  4110. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  4111. /* wait for deassert */
  4112. usleep_range(1000, 1050);
  4113. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  4114. if (rc)
  4115. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  4116. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  4117. if (rc)
  4118. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  4119. /* disable EVA NoC clock */
  4120. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x1);
  4121. /* enable EVA NoC reset */
  4122. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x1);
  4123. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4124. if (rc) {
  4125. dprintk(CVP_ERR, "FATAL ERROR, HPG step 17 to 20 will be bypassed\n");
  4126. goto skip_xo_reset;
  4127. }
  4128. spare_status = 0x1;
  4129. while (spare_status != 0x0) {
  4130. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  4131. spare_status = spare_val & 0x2;
  4132. usleep_range(50, 100);
  4133. }
  4134. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x1);
  4135. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_xo_reset");
  4136. if (rc)
  4137. dprintk(CVP_ERR, "%s: assert cvp_xo_reset failed\n", __func__);
  4138. /* de-assert EVA_NoC reset */
  4139. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x0);
  4140. /* de-assert EVA video_cc XO reset and enable video_cc XO clock after 80us */
  4141. usleep_range(80, 100);
  4142. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_xo_reset");
  4143. if (rc)
  4144. dprintk(CVP_ERR, "%s: de-assert cvp_xo_reset failed\n", __func__);
  4145. /* clear XO mask bit - this step was missing in previous sequence */
  4146. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x0);
  4147. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4148. skip_xo_reset:
  4149. /* enable EVA NoC clock */
  4150. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x0);
  4151. /* De-assert EVA_CTL Force Sleep Retention */
  4152. usleep_range(400, 500);
  4153. /* HPG 6.2.2 Step 6 */
  4154. __disable_regulator(device, "cvp");
  4155. /* HPG 6.2.2 Step 7 */
  4156. rc = msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  4157. if (rc) {
  4158. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  4159. }
  4160. rc = msm_cvp_disable_unprepare_clk(device, "sleep_clk");
  4161. if (rc) {
  4162. dprintk(CVP_ERR, "Failed to disable sleep clk: %d\n", rc);
  4163. }
  4164. return 0;
  4165. }
  4166. static int __power_off_core(struct iris_hfi_device *device)
  4167. {
  4168. u32 reg_status = 0, lpi_status, config, value = 0, count = 0;
  4169. u32 warn_flag = 0, max_count = 10;
  4170. value = __read_register(device, CVP_CC_MVS1_GDSCR);
  4171. if (!(value & 0x80000000)) {
  4172. /*
  4173. * Core has been powered off by f/w.
  4174. * Check NOC reset registers to ensure
  4175. * NO outstanding NoC transactions
  4176. */
  4177. value = __read_register(device, CVP_NOC_RESET_ACK);
  4178. if (value) {
  4179. dprintk(CVP_WARN,
  4180. "Core off with NOC RESET ACK non-zero %x\n",
  4181. value);
  4182. __print_sidebandmanager_regs(device);
  4183. }
  4184. __disable_regulator(device, "cvp-core");
  4185. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4186. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4187. return 0;
  4188. } else if (!(value & 0x2)) {
  4189. /*
  4190. * HW_CONTROL PC disabled, then core is powered on for
  4191. * CVP NoC access
  4192. */
  4193. __disable_regulator(device, "cvp-core");
  4194. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4195. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4196. return 0;
  4197. }
  4198. dprintk(CVP_PWR, "Driver controls Core power off now\n");
  4199. /*
  4200. * check to make sure core clock branch enabled else
  4201. * we cannot read core idle register
  4202. */
  4203. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4204. if (config) {
  4205. dprintk(CVP_PWR,
  4206. "core clock config not enabled, enable it to access core\n");
  4207. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4208. }
  4209. /*
  4210. * add MNoC idle check before collapsing MVS1 per HPG update
  4211. * poll for NoC DMA idle -> HPG 6.2.1
  4212. *
  4213. */
  4214. do {
  4215. value = __read_register(device, CVP_SS_IDLE_STATUS);
  4216. if (value & 0x400000)
  4217. break;
  4218. else
  4219. usleep_range(1000, 2000);
  4220. count++;
  4221. } while (count < max_count);
  4222. if (count == max_count) {
  4223. dprintk(CVP_WARN, "Core fail to go idle %x\n", value);
  4224. warn_flag = 1;
  4225. }
  4226. count = 0;
  4227. max_count = 1000;
  4228. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x1);
  4229. while (!reg_status && count < max_count) {
  4230. lpi_status =
  4231. __read_register(device,
  4232. CVP_AON_WRAPPER_CVP_NOC_LPI_STATUS);
  4233. reg_status = lpi_status & BIT(0);
  4234. /* Wait for Core noc lpi status to be set */
  4235. usleep_range(50, 100);
  4236. count++;
  4237. }
  4238. dprintk(CVP_PWR,
  4239. "Core Noc: lpi_status %x noc_status %x (count %d)\n",
  4240. lpi_status, reg_status, count);
  4241. if (count == max_count) {
  4242. u32 pc_ready, wfi_status;
  4243. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4244. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4245. dprintk(CVP_WARN,
  4246. "Core NOC not in qaccept status %x %x %x %x\n",
  4247. reg_status, lpi_status, wfi_status, pc_ready);
  4248. __print_sidebandmanager_regs(device);
  4249. }
  4250. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x0);
  4251. if (warn_flag)
  4252. __print_sidebandmanager_regs(device);
  4253. /* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ) */
  4254. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x3);
  4255. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x2);
  4256. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x0);
  4257. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4258. __disable_hw_power_collapse(device);
  4259. usleep_range(100, 200);
  4260. __disable_regulator(device, "cvp-core");
  4261. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4262. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4263. return 0;
  4264. }
  4265. static void power_off_iris2(struct iris_hfi_device *device)
  4266. {
  4267. if (!device->power_enabled || !device->res->sw_power_collapsible)
  4268. return;
  4269. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  4270. disable_irq_nosync(device->cvp_hal_data->irq);
  4271. device->intr_status = 0;
  4272. __power_off_core(device);
  4273. __power_off_controller(device);
  4274. if (__unvote_buses(device))
  4275. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  4276. /*Do not access registers after this point!*/
  4277. device->power_enabled = false;
  4278. pr_info(CVP_DBG_TAG "cvp (eva) power collapsed\n", "pwr");
  4279. }
  4280. static inline int __resume(struct iris_hfi_device *device)
  4281. {
  4282. int rc = 0;
  4283. struct msm_cvp_core *core;
  4284. if (!device) {
  4285. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  4286. return -EINVAL;
  4287. } else if (device->power_enabled) {
  4288. goto exit;
  4289. } else if (!__core_in_valid_state(device)) {
  4290. dprintk(CVP_PWR, "iris_hfi_device in deinit state.");
  4291. return -EINVAL;
  4292. }
  4293. core = cvp_driver->cvp_core;
  4294. dprintk(CVP_PWR, "Resuming from power collapse\n");
  4295. rc = __iris_power_on(device);
  4296. if (rc) {
  4297. dprintk(CVP_ERR, "Failed to power on cvp\n");
  4298. goto err_iris_power_on;
  4299. }
  4300. __setup_ucregion_memory_map(device);
  4301. /* RUMI: set CVP_CTRL_INIT register to disable synx in FW */
  4302. /* Reboot the firmware */
  4303. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESUME);
  4304. if (rc) {
  4305. dprintk(CVP_ERR, "Failed to resume cvp core %d\n", rc);
  4306. goto err_set_cvp_state;
  4307. }
  4308. /* Wait for boot completion */
  4309. rc = __boot_firmware(device);
  4310. if (rc) {
  4311. dprintk(CVP_ERR, "Failed to reset cvp core\n");
  4312. goto err_reset_core;
  4313. }
  4314. /*
  4315. * Work around for H/W bug, need to reprogram these registers once
  4316. * firmware is out reset
  4317. */
  4318. __set_threshold_registers(device);
  4319. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  4320. cvp_pm_qos_update(device, true);
  4321. __sys_set_debug(device, msm_cvp_fw_debug);
  4322. __enable_subcaches(device);
  4323. __set_subcaches(device);
  4324. __dsp_resume(device);
  4325. dprintk(CVP_PWR, "Resumed from power collapse\n");
  4326. exit:
  4327. /* Don't reset skip_pc_count for SYS_PC_PREP cmd */
  4328. if (device->last_packet_type != HFI_CMD_SYS_PC_PREP)
  4329. device->skip_pc_count = 0;
  4330. return rc;
  4331. err_reset_core:
  4332. __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  4333. err_set_cvp_state:
  4334. call_iris_op(device, power_off, device);
  4335. err_iris_power_on:
  4336. dprintk(CVP_ERR, "Failed to resume from power collapse\n");
  4337. return rc;
  4338. }
  4339. static int __power_on_init(struct iris_hfi_device *device)
  4340. {
  4341. int rc = 0;
  4342. /* Initialize resources */
  4343. rc = __init_resources(device, device->res);
  4344. if (rc) {
  4345. dprintk(CVP_ERR, "Failed to init resources: %d\n", rc);
  4346. return rc;
  4347. }
  4348. rc = __initialize_packetization(device);
  4349. if (rc) {
  4350. dprintk(CVP_ERR, "Failed to initialize packetization\n");
  4351. goto fail_iris_init;
  4352. }
  4353. rc = __iris_power_on(device);
  4354. if (rc) {
  4355. dprintk(CVP_ERR, "Failed to power on iris in in load_fw\n");
  4356. goto fail_iris_init;
  4357. }
  4358. return rc;
  4359. fail_iris_init:
  4360. __deinit_resources(device);
  4361. return rc;
  4362. }
  4363. static int __load_fw(struct iris_hfi_device *device)
  4364. {
  4365. int rc = 0;
  4366. if ((!device->res->use_non_secure_pil && !device->res->firmware_base)
  4367. || device->res->use_non_secure_pil) {
  4368. rc = load_cvp_fw_impl(device);
  4369. if (rc)
  4370. goto fail_load_fw;
  4371. }
  4372. return rc;
  4373. fail_load_fw:
  4374. call_iris_op(device, power_off, device);
  4375. return rc;
  4376. }
  4377. static void __unload_fw(struct iris_hfi_device *device)
  4378. {
  4379. if (!device->resources.fw.cookie)
  4380. return;
  4381. cancel_delayed_work(&iris_hfi_pm_work);
  4382. if (device->state != IRIS_STATE_DEINIT)
  4383. flush_workqueue(device->iris_pm_workq);
  4384. /* New addition to put CPU/Tensilica to low power */
  4385. __enter_cpu_noc_lpi(device);
  4386. unload_cvp_fw_impl(device);
  4387. __interface_queues_release(device);
  4388. call_iris_op(device, power_off, device);
  4389. __deinit_resources(device);
  4390. dprintk(CVP_WARN, "Firmware unloaded\n");
  4391. }
  4392. static int iris_hfi_get_fw_info(void *dev, struct cvp_hal_fw_info *fw_info)
  4393. {
  4394. int i = 0;
  4395. struct iris_hfi_device *device = dev;
  4396. if (!device || !fw_info) {
  4397. dprintk(CVP_ERR,
  4398. "%s Invalid parameter: device = %pK fw_info = %pK\n",
  4399. __func__, device, fw_info);
  4400. return -EINVAL;
  4401. }
  4402. mutex_lock(&device->lock);
  4403. while (cvp_driver->fw_version[i++] != 'V' && i < CVP_VERSION_LENGTH)
  4404. ;
  4405. if (i == CVP_VERSION_LENGTH - 1) {
  4406. dprintk(CVP_WARN, "Iris version string is not proper\n");
  4407. fw_info->version[0] = '\0';
  4408. goto fail_version_string;
  4409. }
  4410. memcpy(&fw_info->version[0], &cvp_driver->fw_version[0],
  4411. CVP_VERSION_LENGTH);
  4412. fw_info->version[CVP_VERSION_LENGTH - 1] = '\0';
  4413. fail_version_string:
  4414. dprintk(CVP_CORE, "F/W version retrieved : %s\n", fw_info->version);
  4415. fw_info->base_addr = device->cvp_hal_data->firmware_base;
  4416. fw_info->register_base = device->res->register_base;
  4417. fw_info->register_size = device->cvp_hal_data->register_size;
  4418. fw_info->irq = device->cvp_hal_data->irq;
  4419. mutex_unlock(&device->lock);
  4420. return 0;
  4421. }
  4422. static int iris_hfi_get_core_capabilities(void *dev)
  4423. {
  4424. dprintk(CVP_CORE, "%s not supported yet!\n", __func__);
  4425. return 0;
  4426. }
  4427. static const char * const mid_names[16] = {
  4428. "CVP_FW",
  4429. "ARP_DATA",
  4430. "CVP_MPU_PIXEL",
  4431. "CVP_MPU_NON_PIXEL",
  4432. "CVP_FDU_PIXEL",
  4433. "CVP_FDU_NON_PIXEL",
  4434. "CVP_GCE_PIXEL",
  4435. "CVP_GCE_NON_PIXEL",
  4436. "CVP_TOF_PIXEL",
  4437. "CVP_TOF_NON_PIXEL",
  4438. "CVP_VADL_PIXEL",
  4439. "CVP_VADL_NON_PIXEL",
  4440. "CVP_RGE_NON_PIXEL",
  4441. "CVP_CDM",
  4442. "Invalid",
  4443. "Invalid"
  4444. };
  4445. static void __print_reg_details(u32 val)
  4446. {
  4447. u32 mid, sid;
  4448. mid = (val >> 5) & 0xF;
  4449. sid = (val >> 2) & 0x7;
  4450. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  4451. dprintk(CVP_ERR, "Sub-client:%s, SID: %d\n", mid_names[mid], sid);
  4452. }
  4453. static void __err_log(bool logging, u32 *data, const char *name, u32 val)
  4454. {
  4455. if (logging)
  4456. *data = val;
  4457. dprintk(CVP_ERR, "%s: %#x\n", name, val);
  4458. }
  4459. static void __noc_error_info_iris2(struct iris_hfi_device *device)
  4460. {
  4461. struct msm_cvp_core *core;
  4462. struct cvp_noc_log *noc_log;
  4463. u32 val = 0, regi, regii, regiii;
  4464. bool log_required = false;
  4465. int rc;
  4466. core = cvp_driver->cvp_core;
  4467. if (!core->ssr_count && core->resources.max_ssr_allowed > 1)
  4468. log_required = true;
  4469. noc_log = &core->log.noc_log;
  4470. if (noc_log->used) {
  4471. dprintk(CVP_WARN, "Data already in NoC log, skip logging\n");
  4472. return;
  4473. }
  4474. noc_log->used = 1;
  4475. __disable_hw_power_collapse(device);
  4476. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4477. regi = __read_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL);
  4478. regii = __read_register(device, CVP_CC_MVS1_CBCR);
  4479. regiii = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4480. dprintk(CVP_ERR, "noc reg check: %#x %#x %#x %#x\n",
  4481. val, regi, regii, regiii);
  4482. val = __read_register(device, CVP_NOC_ERR_SWID_LOW_OFFS);
  4483. __err_log(log_required, &noc_log->err_ctrl_swid_low,
  4484. "CVP_NOC_ERL_MAIN_SWID_LOW", val);
  4485. val = __read_register(device, CVP_NOC_ERR_SWID_HIGH_OFFS);
  4486. __err_log(log_required, &noc_log->err_ctrl_swid_high,
  4487. "CVP_NOC_ERL_MAIN_SWID_HIGH", val);
  4488. val = __read_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS);
  4489. __err_log(log_required, &noc_log->err_ctrl_mainctl_low,
  4490. "CVP_NOC_ERL_MAIN_MAINCTL_LOW", val);
  4491. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  4492. __err_log(log_required, &noc_log->err_ctrl_errvld_low,
  4493. "CVP_NOC_ERL_MAIN_ERRVLD_LOW", val);
  4494. val = __read_register(device, CVP_NOC_ERR_ERRCLR_LOW_OFFS);
  4495. __err_log(log_required, &noc_log->err_ctrl_errclr_low,
  4496. "CVP_NOC_ERL_MAIN_ERRCLR_LOW", val);
  4497. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  4498. __err_log(log_required, &noc_log->err_ctrl_errlog0_low,
  4499. "CVP_NOC_ERL_MAIN_ERRLOG0_LOW", val);
  4500. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  4501. __err_log(log_required, &noc_log->err_ctrl_errlog0_high,
  4502. "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH", val);
  4503. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  4504. __err_log(log_required, &noc_log->err_ctrl_errlog1_low,
  4505. "CVP_NOC_ERL_MAIN_ERRLOG1_LOW", val);
  4506. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  4507. __err_log(log_required, &noc_log->err_ctrl_errlog1_high,
  4508. "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH", val);
  4509. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  4510. __err_log(log_required, &noc_log->err_ctrl_errlog2_low,
  4511. "CVP_NOC_ERL_MAIN_ERRLOG2_LOW", val);
  4512. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  4513. __err_log(log_required, &noc_log->err_ctrl_errlog2_high,
  4514. "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH", val);
  4515. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  4516. __err_log(log_required, &noc_log->err_ctrl_errlog3_low,
  4517. "CVP_NOC_ERL_MAIN_ERRLOG3_LOW", val);
  4518. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  4519. __err_log(log_required, &noc_log->err_ctrl_errlog3_high,
  4520. "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH", val);
  4521. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4522. if (rc) {
  4523. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4524. return;
  4525. }
  4526. val = __read_register(device,
  4527. CVP_NOC_CORE_ERR_SWID_LOW_OFFS + device->res->noc_core_err_offset);
  4528. __err_log(log_required, &noc_log->err_core_swid_low,
  4529. "CVP_NOC__CORE_ERL_MAIN_SWID_LOW", val);
  4530. val = __read_register(device,
  4531. CVP_NOC_CORE_ERR_SWID_HIGH_OFFS + device->res->noc_core_err_offset);
  4532. __err_log(log_required, &noc_log->err_core_swid_high,
  4533. "CVP_NOC_CORE_ERL_MAIN_SWID_HIGH", val);
  4534. val = __read_register(device,
  4535. CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS + device->res->noc_core_err_offset);
  4536. __err_log(log_required, &noc_log->err_core_mainctl_low,
  4537. "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW", val);
  4538. val = __read_register(device,
  4539. CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS + device->res->noc_core_err_offset);
  4540. __err_log(log_required, &noc_log->err_core_errvld_low,
  4541. "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW", val);
  4542. val = __read_register(device,
  4543. CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS + device->res->noc_core_err_offset);
  4544. __err_log(log_required, &noc_log->err_core_errclr_low,
  4545. "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW", val);
  4546. val = __read_register(device,
  4547. CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS + device->res->noc_core_err_offset);
  4548. __err_log(log_required, &noc_log->err_core_errlog0_low,
  4549. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW", val);
  4550. val = __read_register(device,
  4551. CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS + device->res->noc_core_err_offset);
  4552. __err_log(log_required, &noc_log->err_core_errlog0_high,
  4553. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH", val);
  4554. val = __read_register(device,
  4555. CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS + device->res->noc_core_err_offset);
  4556. __err_log(log_required, &noc_log->err_core_errlog1_low,
  4557. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW", val);
  4558. val = __read_register(device,
  4559. CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS + device->res->noc_core_err_offset);
  4560. __err_log(log_required, &noc_log->err_core_errlog1_high,
  4561. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH", val);
  4562. val = __read_register(device,
  4563. CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS + device->res->noc_core_err_offset);
  4564. __err_log(log_required, &noc_log->err_core_errlog2_low,
  4565. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW", val);
  4566. val = __read_register(device,
  4567. CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS + device->res->noc_core_err_offset);
  4568. __err_log(log_required, &noc_log->err_core_errlog2_high,
  4569. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH", val);
  4570. val = __read_register(device,
  4571. CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS + device->res->noc_core_err_offset);
  4572. __err_log(log_required, &noc_log->err_core_errlog3_low,
  4573. "CORE ERRLOG3_LOW, below details", val);
  4574. __print_reg_details(val);
  4575. val = __read_register(device,
  4576. CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS + device->res->noc_core_err_offset);
  4577. __err_log(log_required, &noc_log->err_core_errlog3_high,
  4578. "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH", val);
  4579. __write_register(device,
  4580. CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS + device->res->noc_core_err_offset, 0x1);
  4581. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4582. #define CVP_SS_CLK_HALT 0x8
  4583. #define CVP_SS_CLK_EN 0xC
  4584. #define CVP_SS_ARP_TEST_BUS_CONTROL 0x700
  4585. #define CVP_SS_ARP_TEST_BUS_REGISTER 0x704
  4586. #define CVP_DMA_TEST_BUS_CONTROL 0x66A0
  4587. #define CVP_DMA_TEST_BUS_REGISTER 0x66A4
  4588. #define CVP_VPU_WRAPPER_CORE_CONFIG 0xB0088
  4589. __write_register(device, CVP_SS_CLK_HALT, 0);
  4590. __write_register(device, CVP_SS_CLK_EN, 0x3f);
  4591. __write_register(device, CVP_VPU_WRAPPER_CORE_CONFIG, 0);
  4592. }
  4593. static int iris_hfi_noc_error_info(void *dev)
  4594. {
  4595. struct iris_hfi_device *device;
  4596. if (!dev) {
  4597. dprintk(CVP_ERR, "%s: null device\n", __func__);
  4598. return -EINVAL;
  4599. }
  4600. device = dev;
  4601. mutex_lock(&device->lock);
  4602. dprintk(CVP_ERR, "%s: non error information\n", __func__);
  4603. call_iris_op(device, noc_error_info, device);
  4604. mutex_unlock(&device->lock);
  4605. return 0;
  4606. }
  4607. static int __initialize_packetization(struct iris_hfi_device *device)
  4608. {
  4609. int rc = 0;
  4610. if (!device || !device->res) {
  4611. dprintk(CVP_ERR, "%s - invalid param\n", __func__);
  4612. return -EINVAL;
  4613. }
  4614. device->packetization_type = HFI_PACKETIZATION_4XX;
  4615. device->pkt_ops = cvp_hfi_get_pkt_ops_handle(
  4616. device->packetization_type);
  4617. if (!device->pkt_ops) {
  4618. rc = -EINVAL;
  4619. dprintk(CVP_ERR, "Failed to get pkt_ops handle\n");
  4620. }
  4621. return rc;
  4622. }
  4623. void __init_cvp_ops(struct iris_hfi_device *device)
  4624. {
  4625. device->hal_ops = &hal_ops;
  4626. }
  4627. static struct iris_hfi_device *__add_device(struct msm_cvp_platform_resources *res,
  4628. hfi_cmd_response_callback callback)
  4629. {
  4630. struct iris_hfi_device *hdevice = NULL;
  4631. int rc = 0;
  4632. if (!res || !callback) {
  4633. dprintk(CVP_ERR, "Invalid Parameters\n");
  4634. return NULL;
  4635. }
  4636. hdevice = kzalloc(sizeof(*hdevice), GFP_KERNEL);
  4637. if (!hdevice) {
  4638. dprintk(CVP_ERR, "failed to allocate new device\n");
  4639. goto exit;
  4640. }
  4641. hdevice->response_pkt = kmalloc_array(cvp_max_packets,
  4642. sizeof(*hdevice->response_pkt), GFP_KERNEL);
  4643. if (!hdevice->response_pkt) {
  4644. dprintk(CVP_ERR, "failed to allocate response_pkt\n");
  4645. goto err_cleanup;
  4646. }
  4647. hdevice->raw_packet =
  4648. kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  4649. if (!hdevice->raw_packet) {
  4650. dprintk(CVP_ERR, "failed to allocate raw packet\n");
  4651. goto err_cleanup;
  4652. }
  4653. rc = vm_manager.vm_ops->vm_init_reg_and_irq(hdevice, res);
  4654. if (rc)
  4655. goto err_cleanup;
  4656. hdevice->res = res;
  4657. hdevice->callback = callback;
  4658. __init_cvp_ops(hdevice);
  4659. hdevice->cvp_workq = create_singlethread_workqueue(
  4660. "msm_cvp_workerq_iris");
  4661. if (!hdevice->cvp_workq) {
  4662. dprintk(CVP_ERR, ": create cvp workq failed\n");
  4663. goto err_cleanup;
  4664. }
  4665. hdevice->iris_pm_workq = create_singlethread_workqueue(
  4666. "pm_workerq_iris");
  4667. if (!hdevice->iris_pm_workq) {
  4668. dprintk(CVP_ERR, ": create pm workq failed\n");
  4669. goto err_cleanup;
  4670. }
  4671. mutex_init(&hdevice->lock);
  4672. INIT_LIST_HEAD(&hdevice->sess_head);
  4673. return hdevice;
  4674. err_cleanup:
  4675. if (hdevice->iris_pm_workq)
  4676. destroy_workqueue(hdevice->iris_pm_workq);
  4677. if (hdevice->cvp_workq)
  4678. destroy_workqueue(hdevice->cvp_workq);
  4679. kfree(hdevice->response_pkt);
  4680. kfree(hdevice->raw_packet);
  4681. kfree(hdevice);
  4682. exit:
  4683. return NULL;
  4684. }
  4685. static struct iris_hfi_device *__get_device(struct msm_cvp_platform_resources *res,
  4686. hfi_cmd_response_callback callback)
  4687. {
  4688. if (!res || !callback) {
  4689. dprintk(CVP_ERR, "Invalid params: %pK %pK\n", res, callback);
  4690. return NULL;
  4691. }
  4692. return __add_device(res, callback);
  4693. }
  4694. void cvp_iris_hfi_delete_device(void *device)
  4695. {
  4696. struct msm_cvp_core *core;
  4697. struct iris_hfi_device *dev = NULL;
  4698. if (!device)
  4699. return;
  4700. core = cvp_driver->cvp_core;
  4701. if (core)
  4702. dev = core->dev_ops->hfi_device_data;
  4703. if (!dev)
  4704. return;
  4705. mutex_destroy(&dev->lock);
  4706. destroy_workqueue(dev->cvp_workq);
  4707. destroy_workqueue(dev->iris_pm_workq);
  4708. free_irq(dev->cvp_hal_data->irq, dev);
  4709. iounmap(dev->cvp_hal_data->register_base);
  4710. iounmap(dev->cvp_hal_data->gcc_reg_base);
  4711. kfree(dev->cvp_hal_data);
  4712. kfree(dev->response_pkt);
  4713. kfree(dev->raw_packet);
  4714. kfree(dev);
  4715. }
  4716. static int iris_hfi_validate_session(void *sess, const char *func)
  4717. {
  4718. struct cvp_hal_session *session = sess;
  4719. int rc = 0;
  4720. struct iris_hfi_device *device;
  4721. if (!session || !session->device) {
  4722. dprintk(CVP_ERR, " %s Invalid Params %pK\n", __func__, session);
  4723. return -EINVAL;
  4724. }
  4725. device = session->device;
  4726. mutex_lock(&device->lock);
  4727. if (!__is_session_valid(device, session, func))
  4728. rc = -ECONNRESET;
  4729. mutex_unlock(&device->lock);
  4730. return rc;
  4731. }
  4732. static void iris_init_hfi_callbacks(struct cvp_hfi_ops *ops_tbl)
  4733. {
  4734. ops_tbl->core_init = iris_hfi_core_init;
  4735. ops_tbl->core_release = iris_hfi_core_release;
  4736. ops_tbl->core_trigger_ssr = iris_hfi_core_trigger_ssr;
  4737. ops_tbl->session_init = iris_hfi_session_init;
  4738. ops_tbl->session_end = iris_hfi_session_end;
  4739. ops_tbl->session_start = iris_hfi_session_start;
  4740. ops_tbl->session_stop = iris_hfi_session_stop;
  4741. ops_tbl->session_abort = iris_hfi_session_abort;
  4742. ops_tbl->session_clean = iris_hfi_session_clean;
  4743. ops_tbl->session_set_buffers = iris_hfi_session_set_buffers;
  4744. ops_tbl->session_release_buffers = iris_hfi_session_release_buffers;
  4745. ops_tbl->session_send = iris_hfi_session_send;
  4746. ops_tbl->session_flush = iris_hfi_session_flush;
  4747. ops_tbl->scale_clocks = iris_hfi_scale_clocks;
  4748. ops_tbl->vote_bus = iris_hfi_vote_buses;
  4749. ops_tbl->get_fw_info = iris_hfi_get_fw_info;
  4750. ops_tbl->get_core_capabilities = iris_hfi_get_core_capabilities;
  4751. ops_tbl->suspend = iris_hfi_suspend;
  4752. ops_tbl->resume = iris_hfi_resume;
  4753. ops_tbl->flush_debug_queue = iris_hfi_flush_debug_queue;
  4754. ops_tbl->noc_error_info = iris_hfi_noc_error_info;
  4755. ops_tbl->validate_session = iris_hfi_validate_session;
  4756. ops_tbl->pm_qos_update = iris_pm_qos_update;
  4757. ops_tbl->debug_hook = iris_debug_hook;
  4758. }
  4759. int cvp_iris_hfi_initialize(struct cvp_hfi_ops *ops_tbl,
  4760. struct msm_cvp_platform_resources *res,
  4761. hfi_cmd_response_callback callback)
  4762. {
  4763. int rc = 0;
  4764. if (!ops_tbl || !res || !callback) {
  4765. dprintk(CVP_ERR, "Invalid params: %pK %pK %pK\n",
  4766. ops_tbl, res, callback);
  4767. rc = -EINVAL;
  4768. goto err_iris_hfi_init;
  4769. }
  4770. ops_tbl->hfi_device_data = __get_device(res, callback);
  4771. if (IS_ERR_OR_NULL(ops_tbl->hfi_device_data)) {
  4772. rc = PTR_ERR(ops_tbl->hfi_device_data) ?: -EINVAL;
  4773. goto err_iris_hfi_init;
  4774. }
  4775. iris_init_hfi_callbacks(ops_tbl);
  4776. err_iris_hfi_init:
  4777. return rc;
  4778. }
  4779. static void dump_noc_reg(struct iris_hfi_device *device)
  4780. {
  4781. u32 val = 0, config;
  4782. int i;
  4783. struct regulator_info *rinfo;
  4784. int rc = 0;
  4785. if (msm_cvp_fw_low_power_mode) {
  4786. iris_hfi_for_each_regulator(device, rinfo) {
  4787. if (strcmp(rinfo->name, "cvp-core"))
  4788. continue;
  4789. rc = __acquire_regulator(rinfo, device);
  4790. if (rc)
  4791. dprintk(CVP_WARN,
  4792. "%s, Failed to acquire regulator control: %s\n",
  4793. __func__, rinfo->name);
  4794. }
  4795. }
  4796. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4797. dprintk(CVP_ERR, "%s, CVP_CC_MVS1_GDSCR: 0x%x", __func__, val);
  4798. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4799. dprintk(CVP_ERR, "%s, CVP_WRAPPER_CORE_CLOCK_CONFIG: 0x%x", __func__, config);
  4800. if (config) {
  4801. dprintk(CVP_PWR,
  4802. "core clock config not enabled, enable it to access core\n");
  4803. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4804. }
  4805. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4806. if (i) {
  4807. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4808. return;
  4809. }
  4810. val = __read_register(device, CVP_NOC_RGE_NIU_DECCTL_LOW
  4811. + device->res->qos_noc_rge_niu_offset);
  4812. dprintk(CVP_ERR, "CVP_NOC_RGE_NIU_DECCTL_LOW: 0x%x", val);
  4813. val = __read_register(device, CVP_NOC_RGE_NIU_ENCCTL_LOW
  4814. + device->res->qos_noc_rge_niu_offset);
  4815. dprintk(CVP_ERR, "CVP_NOC_RGE_NIU_ENCCTL_LOW: 0x%x", val);
  4816. val = __read_register(device, CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW
  4817. + device->res->qos_noc_gce_vadl_tof_niu_offset);
  4818. dprintk(CVP_ERR, "CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW: 0x%x", val);
  4819. val = __read_register(device, CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW
  4820. + device->res->qos_noc_gce_vadl_tof_niu_offset);
  4821. dprintk(CVP_ERR, "CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW: 0x%x", val);
  4822. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS
  4823. + device->res->noc_core_err_offset);
  4824. dprintk(CVP_ERR, "CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS: 0x%x", val);
  4825. val = __read_register(device, CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW
  4826. + device->res->noc_main_sidebandmanager_offset);
  4827. dprintk(CVP_ERR, "CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW: 0x%x", val);
  4828. dprintk(CVP_ERR, "Dumping Core NoC registers\n");
  4829. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_LOW_OFFS
  4830. + device->res->noc_core_err_offset);
  4831. dprintk(CVP_ERR, "CVP_NOC__CORE_ERL_MAIN_SWID_LOW: 0x%x", val);
  4832. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_HIGH_OFFS
  4833. + device->res->noc_core_err_offset);
  4834. dprintk(CVP_ERR, "CVVP_NOC_CORE_ERL_MAIN_SWID_HIGH 0x%x", val);
  4835. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS
  4836. + device->res->noc_core_err_offset);
  4837. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW 0x%x", val);
  4838. val = __read_register(device, CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS
  4839. + device->res->noc_core_err_offset);
  4840. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW 0x%x", val);
  4841. val = __read_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS
  4842. + device->res->noc_core_err_offset);
  4843. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW 0x%x", val);
  4844. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS
  4845. + device->res->noc_core_err_offset);
  4846. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW 0x%x", val);
  4847. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS
  4848. + device->res->noc_core_err_offset);
  4849. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH 0x%x", val);
  4850. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS
  4851. + device->res->noc_core_err_offset);
  4852. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW 0x%x", val);
  4853. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS
  4854. + device->res->noc_core_err_offset);
  4855. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH 0x%x", val);
  4856. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS
  4857. + device->res->noc_core_err_offset);
  4858. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW 0x%x", val);
  4859. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS
  4860. + device->res->noc_core_err_offset);
  4861. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH 0x%x", val);
  4862. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS
  4863. + device->res->noc_core_err_offset);
  4864. dprintk(CVP_ERR, "CORE ERRLOG3_LOW 0x%x, below details", val);
  4865. __print_reg_details(val);
  4866. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS
  4867. + device->res->noc_core_err_offset);
  4868. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH 0x%x", val);
  4869. __write_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS
  4870. + device->res->noc_core_err_offset, 0x1);
  4871. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4872. if (msm_cvp_fw_low_power_mode) {
  4873. iris_hfi_for_each_regulator(device, rinfo) {
  4874. if (strcmp(rinfo->name, "cvp-core"))
  4875. continue;
  4876. rc = __hand_off_regulator(device, rinfo);
  4877. }
  4878. }
  4879. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4880. }