ubwcp_main.c 87 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/dma-buf.h>
  8. #include <linux/slab.h>
  9. #include <linux/cdev.h>
  10. #include <linux/hashtable.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/types.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/of.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_address.h>
  17. #include <linux/genalloc.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/numa.h>
  21. #include <linux/memory_hotplug.h>
  22. #include <asm/page.h>
  23. #include <linux/delay.h>
  24. #include <linux/ubwcp_dma_heap.h>
  25. #include <linux/debugfs.h>
  26. #include <linux/clk.h>
  27. #include <linux/iommu.h>
  28. #include <linux/set_memory.h>
  29. #include <linux/range.h>
  30. MODULE_IMPORT_NS(DMA_BUF);
  31. #include "include/kernel/ubwcp.h"
  32. #include "ubwcp_hw.h"
  33. #include "include/uapi/ubwcp_ioctl.h"
  34. #define CREATE_TRACE_POINTS
  35. #include "ubwcp_trace.h"
  36. #define UBWCP_NUM_DEVICES 1
  37. #define UBWCP_DEVICE_NAME "ubwcp"
  38. #define UBWCP_BUFFER_DESC_OFFSET 64
  39. #define UBWCP_BUFFER_DESC_COUNT 256
  40. #define CACHE_ADDR(x) ((x) >> 6)
  41. #define PAGE_ADDR(x) ((x) >> 12)
  42. #define UBWCP_ALIGN(_x, _y) ((((_x) + (_y) - 1)/(_y))*(_y))
  43. #define DBG_BUF_ATTR(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  44. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  45. } while (0)
  46. #define DBG(fmt, args...) do { if (ubwcp_debug_trace_enable) \
  47. pr_err("ubwcp: %s(): " fmt "\n", __func__, ##args); \
  48. } while (0)
  49. #define ERR(fmt, args...) pr_err("ubwcp: %d: %s(): ~~~ERROR~~~: " fmt "\n", __LINE__, __func__, ##args)
  50. #define ERR_RATE_LIMIT(fmt, args...) pr_err_ratelimited("ubwcp: %s(): ~~~ERROR~~~: " fmt "\n",\
  51. __func__, ##args)
  52. #define FENTRY() DBG("")
  53. #define META_DATA_PITCH_ALIGN 64
  54. #define META_DATA_HEIGHT_ALIGN 16
  55. #define META_DATA_SIZE_ALIGN 4096
  56. #define PIXEL_DATA_SIZE_ALIGN 4096
  57. #define UBWCP_SYNC_GRANULE 0x4000000L /* 64 MB */
  58. enum ula_remove_mem_status {
  59. ULA_REMOVE_MEM_SUCCESS = 0,
  60. ULA_REMOVE_MEM_ABORTED = 1
  61. };
  62. struct ubwcp_desc {
  63. int idx;
  64. void *ptr;
  65. };
  66. /* TBD: confirm size of width/height */
  67. struct ubwcp_dimension {
  68. u16 width;
  69. u16 height;
  70. };
  71. struct ubwcp_plane_info {
  72. u16 pixel_bytes;
  73. u16 per_pixel;
  74. struct ubwcp_dimension tilesize_p; /* pixels */
  75. struct ubwcp_dimension macrotilesize_p; /* pixels */
  76. };
  77. struct ubwcp_image_format_info {
  78. u16 planes;
  79. struct ubwcp_plane_info p_info[2];
  80. };
  81. enum ubwcp_std_image_format {
  82. RGBA = 0,
  83. NV12 = 1,
  84. NV124R = 2,
  85. P010 = 3,
  86. TP10 = 4,
  87. P016 = 5,
  88. INFO_FORMAT_LIST_SIZE,
  89. STD_IMAGE_FORMAT_INVALID = 0xFF
  90. };
  91. enum ubwcp_state {
  92. UBWCP_STATE_READY = 0,
  93. UBWCP_STATE_INVALID = -1,
  94. UBWCP_STATE_FAULT = -2,
  95. };
  96. struct ubwcp_driver {
  97. /* cdev related */
  98. dev_t devt;
  99. struct class *dev_class; //sysfs dev class
  100. struct device *dev_sys; //sysfs dev
  101. struct cdev cdev; //char dev
  102. /* debugfs */
  103. struct dentry *debugfs_root;
  104. bool read_err_irq_en;
  105. bool write_err_irq_en;
  106. bool decode_err_irq_en;
  107. bool encode_err_irq_en;
  108. /* ubwcp devices */
  109. struct device *dev; //ubwcp device
  110. struct device *dev_desc_cb; //smmu dev for descriptors
  111. struct device *dev_buf_cb; //smmu dev for ubwcp buffers
  112. void __iomem *base; //ubwcp base address
  113. struct regulator *vdd;
  114. struct clk **clocks;
  115. int num_clocks;
  116. /* interrupts */
  117. int irq_range_ck_rd;
  118. int irq_range_ck_wr;
  119. int irq_encode;
  120. int irq_decode;
  121. /* ula address pool */
  122. u64 ula_pool_base;
  123. u64 ula_pool_size;
  124. struct gen_pool *ula_pool;
  125. configure_mmap mmap_config_fptr;
  126. /* HW version */
  127. u32 hw_ver_major;
  128. u32 hw_ver_minor;
  129. /* keep track of all potential buffers.
  130. * hash table index'ed using dma_buf ptr.
  131. * 2**13 = 8192 hash values
  132. */
  133. DECLARE_HASHTABLE(buf_table, 13);
  134. /* buffer descriptor */
  135. void *buffer_desc_base; /* CPU address */
  136. dma_addr_t buffer_desc_dma_handle; /* dma address */
  137. size_t buffer_desc_size;
  138. struct ubwcp_desc desc_list[UBWCP_BUFFER_DESC_COUNT];
  139. struct ubwcp_image_format_info format_info[INFO_FORMAT_LIST_SIZE];
  140. /* driver state */
  141. enum ubwcp_state state;
  142. atomic_t num_non_lin_buffers;
  143. bool mem_online;
  144. struct mutex desc_lock; /* allocate/free descriptors */
  145. spinlock_t buf_table_lock; /* add/remove dma_buf into list of managed bufffers */
  146. struct mutex mem_hotplug_lock; /* memory hotplug lock */
  147. struct mutex ula_lock; /* allocate/free ula */
  148. struct mutex ubwcp_flush_lock; /* ubwcp flush */
  149. struct mutex hw_range_ck_lock; /* range ck */
  150. struct list_head err_handler_list; /* error handler list */
  151. spinlock_t err_handler_list_lock; /* err_handler_list lock */
  152. struct dev_pagemap pgmap;
  153. };
  154. struct ubwcp_buf {
  155. struct hlist_node hnode;
  156. struct ubwcp_driver *ubwcp;
  157. struct ubwcp_buffer_attrs buf_attr;
  158. bool perm;
  159. struct ubwcp_desc *desc;
  160. bool buf_attr_set;
  161. enum dma_data_direction lock_dir;
  162. int lock_count;
  163. /* dma_buf info */
  164. struct dma_buf *dma_buf;
  165. struct dma_buf_attachment *attachment;
  166. struct sg_table *sgt;
  167. /* ula info */
  168. phys_addr_t ula_pa;
  169. size_t ula_size;
  170. /* meta metadata */
  171. struct ubwcp_hw_meta_metadata mmdata;
  172. struct mutex lock;
  173. };
  174. static struct ubwcp_driver *me;
  175. static u32 ubwcp_debug_trace_enable;
  176. static struct ubwcp_driver *ubwcp_get_driver(void)
  177. {
  178. if (!me)
  179. WARN(1, "ubwcp: driver ptr requested but driver not initialized");
  180. return me;
  181. }
  182. static void image_format_init(struct ubwcp_driver *ubwcp)
  183. { /* planes, bytes/p, Tp , MTp */
  184. ubwcp->format_info[RGBA] = (struct ubwcp_image_format_info)
  185. {1, {{4, 1, {16, 4}, {64, 16}}}};
  186. ubwcp->format_info[NV12] = (struct ubwcp_image_format_info)
  187. {2, {{1, 1, {32, 8}, {128, 32}},
  188. {2, 1, {16, 8}, { 64, 32}}}};
  189. ubwcp->format_info[NV124R] = (struct ubwcp_image_format_info)
  190. {2, {{1, 1, {64, 4}, {256, 16}},
  191. {2, 1, {32, 4}, {128, 16}}}};
  192. ubwcp->format_info[P010] = (struct ubwcp_image_format_info)
  193. {2, {{2, 1, {32, 4}, {128, 16}},
  194. {4, 1, {16, 4}, { 64, 16}}}};
  195. ubwcp->format_info[TP10] = (struct ubwcp_image_format_info)
  196. {2, {{4, 3, {48, 4}, {192, 16}},
  197. {8, 3, {24, 4}, { 96, 16}}}};
  198. ubwcp->format_info[P016] = (struct ubwcp_image_format_info)
  199. {2, {{2, 1, {32, 4}, {128, 16}},
  200. {4, 1, {16, 4}, { 64, 16}}}};
  201. }
  202. static void ubwcp_buf_desc_list_init(struct ubwcp_driver *ubwcp)
  203. {
  204. int idx;
  205. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  206. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  207. desc_list[idx].idx = -1;
  208. desc_list[idx].ptr = NULL;
  209. }
  210. }
  211. static int ubwcp_init_clocks(struct ubwcp_driver *ubwcp, struct device *dev)
  212. {
  213. const char *cname;
  214. struct property *prop;
  215. int i;
  216. ubwcp->num_clocks =
  217. of_property_count_strings(dev->of_node, "clock-names");
  218. if (ubwcp->num_clocks < 1) {
  219. ubwcp->num_clocks = 0;
  220. return 0;
  221. }
  222. ubwcp->clocks = devm_kzalloc(dev,
  223. sizeof(*ubwcp->clocks) * ubwcp->num_clocks, GFP_KERNEL);
  224. if (!ubwcp->clocks)
  225. return -ENOMEM;
  226. i = 0;
  227. of_property_for_each_string(dev->of_node, "clock-names",
  228. prop, cname) {
  229. struct clk *c = devm_clk_get(dev, cname);
  230. if (IS_ERR(c)) {
  231. ERR("Couldn't get clock: %s\n", cname);
  232. return PTR_ERR(c);
  233. }
  234. ubwcp->clocks[i] = c;
  235. ++i;
  236. }
  237. return 0;
  238. }
  239. static int ubwcp_enable_clocks(struct ubwcp_driver *ubwcp)
  240. {
  241. int i, ret = 0;
  242. for (i = 0; i < ubwcp->num_clocks; ++i) {
  243. ret = clk_prepare_enable(ubwcp->clocks[i]);
  244. if (ret) {
  245. ERR("Couldn't enable clock #%d\n", i);
  246. while (i--)
  247. clk_disable_unprepare(ubwcp->clocks[i]);
  248. break;
  249. }
  250. }
  251. return ret;
  252. }
  253. static void ubwcp_disable_clocks(struct ubwcp_driver *ubwcp)
  254. {
  255. int i;
  256. for (i = ubwcp->num_clocks; i; --i)
  257. clk_disable_unprepare(ubwcp->clocks[i - 1]);
  258. }
  259. /* UBWCP Power control */
  260. static int ubwcp_power(struct ubwcp_driver *ubwcp, bool enable)
  261. {
  262. int ret = 0;
  263. if (enable)
  264. ret = regulator_enable(ubwcp->vdd);
  265. else
  266. ret = regulator_disable(ubwcp->vdd);
  267. if (ret) {
  268. ERR("regulator call (enable: %d) failed: %d", enable, ret);
  269. return ret;
  270. }
  271. if (enable) {
  272. ret = ubwcp_enable_clocks(ubwcp);
  273. if (ret) {
  274. ERR("enable clocks failed: %d", ret);
  275. regulator_disable(ubwcp->vdd);
  276. return ret;
  277. }
  278. } else {
  279. ubwcp_disable_clocks(ubwcp);
  280. }
  281. return ret;
  282. }
  283. /* get dma_buf ptr for the given dma_buf fd */
  284. static struct dma_buf *ubwcp_dma_buf_fd_to_dma_buf(int dma_buf_fd)
  285. {
  286. struct dma_buf *dmabuf;
  287. /* TBD: dma_buf_get() results in taking ref to buf and it won't ever get
  288. * free'ed until ref count goes to 0. So we must reduce the ref count
  289. * immediately after we find our corresponding ubwcp_buf.
  290. */
  291. dmabuf = dma_buf_get(dma_buf_fd);
  292. if (IS_ERR(dmabuf)) {
  293. ERR("dmabuf ptr not found for dma_buf_fd = %d", dma_buf_fd);
  294. return NULL;
  295. }
  296. dma_buf_put(dmabuf);
  297. return dmabuf;
  298. }
  299. /* get ubwcp_buf corresponding to the given dma_buf */
  300. static struct ubwcp_buf *dma_buf_to_ubwcp_buf(struct dma_buf *dmabuf)
  301. {
  302. struct ubwcp_buf *buf = NULL;
  303. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  304. unsigned long flags;
  305. if (!dmabuf || !ubwcp)
  306. return NULL;
  307. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  308. /* look up ubwcp_buf corresponding to this dma_buf */
  309. hash_for_each_possible(ubwcp->buf_table, buf, hnode, (u64)dmabuf) {
  310. if (buf->dma_buf == dmabuf)
  311. break;
  312. }
  313. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  314. return buf;
  315. }
  316. /* return ubwcp hardware version */
  317. int ubwcp_get_hw_version(struct ubwcp_ioctl_hw_version *ver)
  318. {
  319. struct ubwcp_driver *ubwcp;
  320. FENTRY();
  321. if (!ver) {
  322. ERR("invalid version ptr");
  323. return -EINVAL;
  324. }
  325. ubwcp = ubwcp_get_driver();
  326. if (!ubwcp)
  327. return -1;
  328. if (ubwcp->state != UBWCP_STATE_FAULT)
  329. return -EPERM;
  330. ver->major = ubwcp->hw_ver_major;
  331. ver->minor = ubwcp->hw_ver_minor;
  332. return 0;
  333. }
  334. EXPORT_SYMBOL(ubwcp_get_hw_version);
  335. static int ula_add_mem(struct ubwcp_driver *ubwcp)
  336. {
  337. int ret = 0;
  338. int nid;
  339. void *ptr;
  340. nid = memory_add_physaddr_to_nid(ubwcp->ula_pool_base);
  341. DBG("calling memremap_pages()...");
  342. ubwcp->pgmap.type = MEMORY_DEVICE_GENERIC;
  343. ubwcp->pgmap.nr_range = 1;
  344. ubwcp->pgmap.range.start = ubwcp->ula_pool_base;
  345. ubwcp->pgmap.range.end = ubwcp->ula_pool_base + ubwcp->ula_pool_size - 1;
  346. trace_ubwcp_memremap_pages_start(ubwcp->ula_pool_size);
  347. ptr = memremap_pages(&ubwcp->pgmap, nid);
  348. trace_ubwcp_memremap_pages_end(ubwcp->ula_pool_size);
  349. if (IS_ERR(ptr)) {
  350. ret = IS_ERR(ptr);
  351. ERR("memremap_pages() failed st:0x%lx sz:0x%lx err: %d",
  352. ubwcp->ula_pool_base,
  353. ubwcp->ula_pool_size,
  354. ret);
  355. } else {
  356. DBG("memremap_pages() ula_pool_base:0x%llx, size:0x%zx, kernel addr:0x%p",
  357. ubwcp->ula_pool_base,
  358. ubwcp->ula_pool_size,
  359. page_to_virt(pfn_to_page(PFN_DOWN(ubwcp->ula_pool_base))));
  360. }
  361. return ret;
  362. }
  363. static int ula_map_uncached(u64 base, u64 size)
  364. {
  365. int ret;
  366. trace_ubwcp_set_direct_map_range_uncached_start(size);
  367. ret = set_direct_map_range_uncached((unsigned long)phys_to_virt(base), size >> PAGE_SHIFT);
  368. trace_ubwcp_set_direct_map_range_uncached_end(size);
  369. if (ret)
  370. ERR("set_direct_map_range_uncached failed st:0x%lx num pages:%lu err: %d",
  371. base, size >> PAGE_SHIFT, ret);
  372. return ret;
  373. }
  374. static void ula_unmap(struct ubwcp_driver *ubwcp)
  375. {
  376. DBG("Calling memunmap_pages() for ULA PA pool");
  377. trace_ubwcp_memunmap_pages_start(ubwcp->ula_pool_size);
  378. memunmap_pages(&ubwcp->pgmap);
  379. trace_ubwcp_memunmap_pages_end(ubwcp->ula_pool_size);
  380. }
  381. static void ula_sync_for_cpu(struct device *dev, u64 addr, unsigned long size)
  382. {
  383. DBG("Partial sync offset:0x%lx size:0x%lx", addr, size);
  384. trace_ubwcp_dma_sync_single_for_cpu_start(size);
  385. dma_sync_single_for_cpu(dev, addr, size, DMA_BIDIRECTIONAL);
  386. trace_ubwcp_dma_sync_single_for_cpu_end(size);
  387. }
  388. /** Remove ula memory in chunks
  389. * Abort if new buffer addition is detected
  390. * If remove succeeds or aborted, return success
  391. * status value indicates if mem was removed or aborted (not removed)
  392. * Otherwise return failure
  393. */
  394. static int ula_remove_mem(struct ubwcp_driver *ubwcp, enum ula_remove_mem_status *status)
  395. {
  396. int ret = 0;
  397. unsigned long sync_remain = ubwcp->ula_pool_size;
  398. unsigned long sync_offset = 0;
  399. unsigned long sync_size = 0;
  400. ret = ula_map_uncached(ubwcp->ula_pool_base, ubwcp->ula_pool_size);
  401. if (ret)
  402. return ret;
  403. trace_ubwcp_offline_sync_start(ubwcp->ula_pool_size);
  404. while (sync_remain > 0) {
  405. if (atomic_read(&ubwcp->num_non_lin_buffers) > 0) {
  406. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  407. ula_unmap(ubwcp);
  408. if (ula_add_mem(ubwcp)) {
  409. ERR("remove mem: failed to add back during abort");
  410. return -1;
  411. }
  412. *status = ULA_REMOVE_MEM_ABORTED;
  413. return 0;
  414. }
  415. if (UBWCP_SYNC_GRANULE > sync_remain) {
  416. sync_size = sync_remain;
  417. sync_remain = 0;
  418. } else {
  419. sync_size = UBWCP_SYNC_GRANULE;
  420. sync_remain -= UBWCP_SYNC_GRANULE;
  421. }
  422. ula_sync_for_cpu(ubwcp->dev, ubwcp->ula_pool_base + sync_offset, sync_size);
  423. sync_offset += sync_size;
  424. }
  425. trace_ubwcp_offline_sync_end(ubwcp->ula_pool_size);
  426. ula_unmap(ubwcp);
  427. *status = ULA_REMOVE_MEM_SUCCESS;
  428. return 0;
  429. }
  430. static int inc_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  431. {
  432. atomic_inc(&ubwcp->num_non_lin_buffers);
  433. mutex_lock(&ubwcp->mem_hotplug_lock);
  434. if (!ubwcp->mem_online) {
  435. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  436. ERR("Bad state: num_non_lin_buffers should not be 0");
  437. goto err;
  438. }
  439. if (ubwcp_power(ubwcp, true))
  440. goto err;
  441. if (ula_add_mem(ubwcp))
  442. goto err_add_memory;
  443. ubwcp->mem_online = true;
  444. }
  445. mutex_unlock(&ubwcp->mem_hotplug_lock);
  446. return 0;
  447. err_add_memory:
  448. ubwcp_power(ubwcp, false);
  449. err:
  450. atomic_dec(&ubwcp->num_non_lin_buffers);
  451. mutex_unlock(&ubwcp->mem_hotplug_lock);
  452. ubwcp->state = UBWCP_STATE_FAULT;
  453. return -1;
  454. }
  455. static int dec_num_non_lin_buffers(struct ubwcp_driver *ubwcp)
  456. {
  457. int ret;
  458. enum ula_remove_mem_status remove_status;
  459. atomic_dec(&ubwcp->num_non_lin_buffers);
  460. mutex_lock(&ubwcp->mem_hotplug_lock);
  461. if (atomic_read(&ubwcp->num_non_lin_buffers) == 0) {
  462. DBG("last buffer: ~~~~~~~~~~~");
  463. if (!ubwcp->mem_online) {
  464. ERR("Bad state: mem_online should not be false");
  465. goto err;
  466. }
  467. ret = ula_remove_mem(ubwcp, &remove_status);
  468. if (ret)
  469. goto err;
  470. if (remove_status == ULA_REMOVE_MEM_SUCCESS) {
  471. ubwcp->mem_online = false;
  472. if (ubwcp_power(ubwcp, false))
  473. goto err;
  474. } else if (remove_status == ULA_REMOVE_MEM_ABORTED) {
  475. DBG("ula memory offline aborted");
  476. } else {
  477. ERR("unexpected ula remove status: %d", remove_status);
  478. goto err;
  479. }
  480. }
  481. mutex_unlock(&ubwcp->mem_hotplug_lock);
  482. return 0;
  483. err:
  484. atomic_inc(&ubwcp->num_non_lin_buffers);
  485. mutex_unlock(&ubwcp->mem_hotplug_lock);
  486. ubwcp->state = UBWCP_STATE_FAULT;
  487. return -1;
  488. }
  489. /**
  490. *
  491. * Initialize ubwcp buffer for the given dma_buf. This
  492. * initializes ubwcp internal data structures and possibly hw to
  493. * use ubwcp for this buffer.
  494. *
  495. * @param dmabuf : ptr to the buffer to be configured for ubwcp
  496. *
  497. * @return int : 0 on success, otherwise error code
  498. */
  499. static int ubwcp_init_buffer(struct dma_buf *dmabuf)
  500. {
  501. struct ubwcp_buf *buf;
  502. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  503. unsigned long flags;
  504. FENTRY();
  505. trace_ubwcp_init_buffer_start(dmabuf);
  506. if (!ubwcp) {
  507. trace_ubwcp_init_buffer_end(dmabuf);
  508. return -1;
  509. }
  510. if (ubwcp->state != UBWCP_STATE_READY) {
  511. ERR("driver in invalid state: %d", ubwcp->state);
  512. trace_ubwcp_init_buffer_end(dmabuf);
  513. return -EPERM;
  514. }
  515. if (!dmabuf) {
  516. ERR("NULL dmabuf input ptr");
  517. trace_ubwcp_init_buffer_end(dmabuf);
  518. return -EINVAL;
  519. }
  520. if (dma_buf_to_ubwcp_buf(dmabuf)) {
  521. ERR("dma_buf already initialized for ubwcp");
  522. trace_ubwcp_init_buffer_end(dmabuf);
  523. return -EEXIST;
  524. }
  525. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  526. if (!buf) {
  527. ERR("failed to alloc for new ubwcp_buf");
  528. trace_ubwcp_init_buffer_end(dmabuf);
  529. return -ENOMEM;
  530. }
  531. mutex_init(&buf->lock);
  532. buf->dma_buf = dmabuf;
  533. buf->ubwcp = ubwcp;
  534. buf->buf_attr.image_format = UBWCP_LINEAR;
  535. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  536. hash_add(ubwcp->buf_table, &buf->hnode, (u64)buf->dma_buf);
  537. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  538. trace_ubwcp_init_buffer_end(dmabuf);
  539. return 0;
  540. }
  541. static void dump_attributes(struct ubwcp_buffer_attrs *attr)
  542. {
  543. DBG_BUF_ATTR("");
  544. DBG_BUF_ATTR("image_format: %d", attr->image_format);
  545. DBG_BUF_ATTR("major_ubwc_ver: %d", attr->major_ubwc_ver);
  546. DBG_BUF_ATTR("minor_ubwc_ver: %d", attr->minor_ubwc_ver);
  547. DBG_BUF_ATTR("compression_type: %d", attr->compression_type);
  548. DBG_BUF_ATTR("lossy_params: %llu", attr->lossy_params);
  549. DBG_BUF_ATTR("width: %d", attr->width);
  550. DBG_BUF_ATTR("height: %d", attr->height);
  551. DBG_BUF_ATTR("stride: %d", attr->stride);
  552. DBG_BUF_ATTR("scanlines: %d", attr->scanlines);
  553. DBG_BUF_ATTR("planar_padding: %d", attr->planar_padding);
  554. DBG_BUF_ATTR("subsample: %d", attr->subsample);
  555. DBG_BUF_ATTR("sub_system_target: %d", attr->sub_system_target);
  556. DBG_BUF_ATTR("y_offset: %d", attr->y_offset);
  557. DBG_BUF_ATTR("batch_size: %d", attr->batch_size);
  558. DBG_BUF_ATTR("");
  559. }
  560. static enum ubwcp_std_image_format to_std_format(u16 ioctl_image_format)
  561. {
  562. switch (ioctl_image_format) {
  563. case UBWCP_RGBA8888:
  564. return RGBA;
  565. case UBWCP_NV12:
  566. case UBWCP_NV12_Y:
  567. case UBWCP_NV12_UV:
  568. return NV12;
  569. case UBWCP_NV124R:
  570. case UBWCP_NV124R_Y:
  571. case UBWCP_NV124R_UV:
  572. return NV124R;
  573. case UBWCP_TP10:
  574. case UBWCP_TP10_Y:
  575. case UBWCP_TP10_UV:
  576. return TP10;
  577. case UBWCP_P010:
  578. case UBWCP_P010_Y:
  579. case UBWCP_P010_UV:
  580. return P010;
  581. case UBWCP_P016:
  582. case UBWCP_P016_Y:
  583. case UBWCP_P016_UV:
  584. return P016;
  585. default:
  586. WARN(1, "Fix this!!!");
  587. return STD_IMAGE_FORMAT_INVALID;
  588. }
  589. }
  590. static int get_stride_alignment(enum ubwcp_std_image_format format, u16 *align)
  591. {
  592. switch (format) {
  593. case TP10:
  594. *align = 64;
  595. return 0;
  596. case NV12:
  597. *align = 128;
  598. return 0;
  599. case RGBA:
  600. case NV124R:
  601. case P010:
  602. case P016:
  603. *align = 256;
  604. return 0;
  605. default:
  606. return -1;
  607. }
  608. }
  609. /* returns stride of compressed image */
  610. static u32 get_compressed_stride(struct ubwcp_driver *ubwcp,
  611. enum ubwcp_std_image_format format, u32 width)
  612. {
  613. struct ubwcp_plane_info p_info;
  614. u16 macro_tile_width_p;
  615. u16 pixel_bytes;
  616. u16 per_pixel;
  617. p_info = ubwcp->format_info[format].p_info[0];
  618. macro_tile_width_p = p_info.macrotilesize_p.width;
  619. pixel_bytes = p_info.pixel_bytes;
  620. per_pixel = p_info.per_pixel;
  621. return UBWCP_ALIGN(width, macro_tile_width_p)*pixel_bytes/per_pixel;
  622. }
  623. /* check if linear stride conforms to hw limitations
  624. * always returns false for linear image
  625. */
  626. static bool stride_is_valid(struct ubwcp_driver *ubwcp,
  627. u16 ioctl_img_fmt, u32 width, u32 lin_stride)
  628. {
  629. u32 compressed_stride;
  630. enum ubwcp_std_image_format format = to_std_format(ioctl_img_fmt);
  631. if (format == STD_IMAGE_FORMAT_INVALID)
  632. return false;
  633. if ((lin_stride < width) || (lin_stride > 64*1024)) {
  634. ERR("stride is not valid (width <= stride <= 64K): %d", lin_stride);
  635. return false;
  636. }
  637. if (format == TP10) {
  638. if(!IS_ALIGNED(lin_stride, 64)) {
  639. ERR("stride must be aligned to 64: %d", lin_stride);
  640. return false;
  641. }
  642. } else {
  643. compressed_stride = get_compressed_stride(ubwcp, format, width);
  644. if (lin_stride != compressed_stride) {
  645. ERR("linear stride: %d must be same as compressed stride: %d",
  646. lin_stride, compressed_stride);
  647. return false;
  648. }
  649. }
  650. return true;
  651. }
  652. static bool ioctl_format_is_valid(u16 ioctl_image_format)
  653. {
  654. switch (ioctl_image_format) {
  655. case UBWCP_LINEAR:
  656. case UBWCP_RGBA8888:
  657. case UBWCP_NV12:
  658. case UBWCP_NV12_Y:
  659. case UBWCP_NV12_UV:
  660. case UBWCP_NV124R:
  661. case UBWCP_NV124R_Y:
  662. case UBWCP_NV124R_UV:
  663. case UBWCP_TP10:
  664. case UBWCP_TP10_Y:
  665. case UBWCP_TP10_UV:
  666. case UBWCP_P010:
  667. case UBWCP_P010_Y:
  668. case UBWCP_P010_UV:
  669. case UBWCP_P016:
  670. case UBWCP_P016_Y:
  671. case UBWCP_P016_UV:
  672. return true;
  673. default:
  674. return false;
  675. }
  676. }
  677. /* validate buffer attributes */
  678. static bool ubwcp_buf_attrs_valid(struct ubwcp_driver *ubwcp, struct ubwcp_buffer_attrs *attr)
  679. {
  680. if (!ioctl_format_is_valid(attr->image_format)) {
  681. ERR("invalid image format: %d", attr->image_format);
  682. goto err;
  683. }
  684. if (attr->major_ubwc_ver || attr->minor_ubwc_ver) {
  685. ERR("major/minor ubwc ver must be 0. major: %d minor: %d",
  686. attr->major_ubwc_ver, attr->minor_ubwc_ver);
  687. goto err;
  688. }
  689. if (attr->compression_type != UBWCP_COMPRESSION_LOSSLESS) {
  690. ERR("compression_type is not valid: %d",
  691. attr->compression_type);
  692. goto err;
  693. }
  694. if (attr->lossy_params != 0) {
  695. ERR("lossy_params is not valid: %d", attr->lossy_params);
  696. goto err;
  697. }
  698. //TBD: some upper limit for width?
  699. if (attr->width > 10*1024) {
  700. ERR("width is invalid (above upper limit): %d", attr->width);
  701. goto err;
  702. }
  703. //TBD: some upper limit for height?
  704. if (attr->height > 10*1024) {
  705. ERR("height is invalid (above upper limit): %d", attr->height);
  706. goto err;
  707. }
  708. if (attr->image_format != UBWCP_LINEAR)
  709. if(!stride_is_valid(ubwcp, attr->image_format, attr->width, attr->stride)) {
  710. ERR("stride is invalid: %d", attr->stride);
  711. goto err;
  712. }
  713. if ((attr->scanlines < attr->height) ||
  714. (attr->scanlines > attr->height + 32*1024)) {
  715. ERR("scanlines is not valid - height: %d scanlines: %d",
  716. attr->height, attr->scanlines);
  717. goto err;
  718. }
  719. if (attr->planar_padding > 4096) {
  720. ERR("planar_padding is not valid. (<= 4096): %d",
  721. attr->planar_padding);
  722. goto err;
  723. }
  724. if (attr->subsample != UBWCP_SUBSAMPLE_4_2_0) {
  725. ERR("subsample is not valid: %d", attr->subsample);
  726. goto err;
  727. }
  728. if (attr->sub_system_target & ~UBWCP_SUBSYSTEM_TARGET_CPU) {
  729. ERR("sub_system_target other that CPU is not supported: %d",
  730. attr->sub_system_target);
  731. goto err;
  732. }
  733. if (!(attr->sub_system_target & UBWCP_SUBSYSTEM_TARGET_CPU)) {
  734. ERR("sub_system_target is not set to CPU: %d",
  735. attr->sub_system_target);
  736. goto err;
  737. }
  738. if (attr->y_offset != 0) {
  739. ERR("y_offset is not valid: %d", attr->y_offset);
  740. goto err;
  741. }
  742. if (attr->batch_size != 1) {
  743. ERR("batch_size is not valid: %d", attr->batch_size);
  744. goto err;
  745. }
  746. dump_attributes(attr);
  747. return true;
  748. err:
  749. dump_attributes(attr);
  750. return false;
  751. }
  752. /* calculate and return metadata buffer size for a given plane
  753. * and buffer attributes
  754. * NOTE: in this function, we will only pass in NV12 format.
  755. * NOT NV12_Y or NV12_UV etc.
  756. * the Y or UV information is in the "plane"
  757. * "format" here purely means "encoding format" and no information
  758. * if some plane data is missing.
  759. */
  760. static size_t metadata_buf_sz(struct ubwcp_driver *ubwcp,
  761. enum ubwcp_std_image_format format,
  762. u32 width, u32 height, u8 plane)
  763. {
  764. size_t size;
  765. u64 pitch;
  766. u64 lines;
  767. u64 tile_width;
  768. u32 tile_height;
  769. struct ubwcp_image_format_info f_info;
  770. struct ubwcp_plane_info p_info;
  771. f_info = ubwcp->format_info[format];
  772. DBG_BUF_ATTR("");
  773. DBG_BUF_ATTR("");
  774. DBG_BUF_ATTR("Calculating metadata buffer size: format = %d, plane = %d", format, plane);
  775. if (plane >= f_info.planes) {
  776. ERR("Format does not have requested plane info: format: %d, plane: %d",
  777. format, plane);
  778. WARN(1, "Fix this!!!!!");
  779. return 0;
  780. }
  781. p_info = f_info.p_info[plane];
  782. /* UV plane */
  783. if (plane == 1) {
  784. width = width/2;
  785. height = height/2;
  786. }
  787. tile_width = p_info.tilesize_p.width;
  788. tile_height = p_info.tilesize_p.height;
  789. /* pitch: # of tiles in a row
  790. * lines: # of tile rows
  791. */
  792. pitch = UBWCP_ALIGN((width + tile_width - 1)/tile_width, META_DATA_PITCH_ALIGN);
  793. lines = UBWCP_ALIGN((height + tile_height - 1)/tile_height, META_DATA_HEIGHT_ALIGN);
  794. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  795. DBG_BUF_ATTR("tile params : %d x %d (pixels)", tile_width, tile_height);
  796. DBG_BUF_ATTR("pitch : %d (%d)", pitch, width/tile_width);
  797. DBG_BUF_ATTR("lines : %d (%d)", lines, height);
  798. DBG_BUF_ATTR("size (p*l*bytes) : %d", pitch*lines*1);
  799. /* x1 below is only to clarify that we are multiplying by 1 bytes/tile */
  800. size = UBWCP_ALIGN(pitch*lines*1, META_DATA_SIZE_ALIGN);
  801. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  802. return size;
  803. }
  804. /* calculate and return size of pixel data buffer for a given plane
  805. * and buffer attributes
  806. */
  807. static size_t pixeldata_buf_sz(struct ubwcp_driver *ubwcp,
  808. u16 format, u32 width,
  809. u32 height, u8 plane)
  810. {
  811. size_t size;
  812. u64 pitch;
  813. u64 lines;
  814. u16 pixel_bytes;
  815. u16 per_pixel;
  816. u64 macro_tile_width_p;
  817. u64 macro_tile_height_p;
  818. struct ubwcp_image_format_info f_info;
  819. struct ubwcp_plane_info p_info;
  820. f_info = ubwcp->format_info[format];
  821. DBG_BUF_ATTR("");
  822. DBG_BUF_ATTR("");
  823. DBG_BUF_ATTR("Calculating Pixeldata buffer size: format = %d, plane = %d", format, plane);
  824. if (plane >= f_info.planes) {
  825. ERR("Format does not have requested plane info: format: %d, plane: %d",
  826. format, plane);
  827. WARN(1, "Fix this!!!!!");
  828. return 0;
  829. }
  830. p_info = f_info.p_info[plane];
  831. pixel_bytes = p_info.pixel_bytes;
  832. per_pixel = p_info.per_pixel;
  833. /* UV plane */
  834. if (plane == 1) {
  835. width = width/2;
  836. height = height/2;
  837. }
  838. macro_tile_width_p = p_info.macrotilesize_p.width;
  839. macro_tile_height_p = p_info.macrotilesize_p.height;
  840. /* align pixel width and height macro tile width and height */
  841. pitch = UBWCP_ALIGN(width, macro_tile_width_p);
  842. lines = UBWCP_ALIGN(height, macro_tile_height_p);
  843. DBG_BUF_ATTR("image params : %d x %d (pixels)", width, height);
  844. DBG_BUF_ATTR("macro tile params: %d x %d (pixels)", macro_tile_width_p,
  845. macro_tile_height_p);
  846. DBG_BUF_ATTR("bytes_per_pixel : %d/%d", pixel_bytes, per_pixel);
  847. DBG_BUF_ATTR("pitch : %d", pitch);
  848. DBG_BUF_ATTR("lines : %d", lines);
  849. DBG_BUF_ATTR("size (p*l*bytes) : %d", (pitch*lines*pixel_bytes)/per_pixel);
  850. size = UBWCP_ALIGN((pitch*lines*pixel_bytes)/per_pixel, PIXEL_DATA_SIZE_ALIGN);
  851. DBG_BUF_ATTR("size (aligned 4K): %zu (0x%zx)", size, size);
  852. return size;
  853. }
  854. static int get_tile_height(struct ubwcp_driver *ubwcp, enum ubwcp_std_image_format format,
  855. u8 plane)
  856. {
  857. struct ubwcp_image_format_info f_info;
  858. struct ubwcp_plane_info p_info;
  859. f_info = ubwcp->format_info[format];
  860. p_info = f_info.p_info[plane];
  861. return p_info.tilesize_p.height;
  862. }
  863. /*
  864. * plane: must be 0 or 1 (1st plane == 0, 2nd plane == 1)
  865. */
  866. static size_t ubwcp_ula_size(struct ubwcp_driver *ubwcp, u16 format,
  867. u32 stride_b, u32 scanlines, u8 plane,
  868. bool add_tile_pad)
  869. {
  870. size_t size;
  871. DBG_BUF_ATTR("%s(format = %d, plane = %d)", __func__, format, plane);
  872. /* UV plane */
  873. if (plane == 1)
  874. scanlines = scanlines/2;
  875. if (add_tile_pad) {
  876. int tile_height = get_tile_height(ubwcp, format, plane);
  877. /* Align plane size to plane tile height */
  878. scanlines = ((scanlines + tile_height - 1) / tile_height) * tile_height;
  879. }
  880. size = stride_b*scanlines;
  881. DBG_BUF_ATTR("Size of plane-%u: (%u * %u) = %zu (0x%zx)",
  882. plane, stride_b, scanlines, size, size);
  883. return size;
  884. }
  885. static int missing_plane_from_format(u16 ioctl_image_format)
  886. {
  887. int missing_plane;
  888. switch (ioctl_image_format) {
  889. case UBWCP_NV12_Y:
  890. missing_plane = 2;
  891. break;
  892. case UBWCP_NV12_UV:
  893. missing_plane = 1;
  894. break;
  895. case UBWCP_NV124R_Y:
  896. missing_plane = 2;
  897. break;
  898. case UBWCP_NV124R_UV:
  899. missing_plane = 1;
  900. break;
  901. case UBWCP_TP10_Y:
  902. missing_plane = 2;
  903. break;
  904. case UBWCP_TP10_UV:
  905. missing_plane = 1;
  906. break;
  907. case UBWCP_P010_Y:
  908. missing_plane = 2;
  909. break;
  910. case UBWCP_P010_UV:
  911. missing_plane = 1;
  912. break;
  913. case UBWCP_P016_Y:
  914. missing_plane = 2;
  915. break;
  916. case UBWCP_P016_UV:
  917. missing_plane = 1;
  918. break;
  919. default:
  920. missing_plane = 0;
  921. }
  922. return missing_plane;
  923. }
  924. static int planes_in_format(enum ubwcp_std_image_format format)
  925. {
  926. if (format == RGBA)
  927. return 1;
  928. else
  929. return 2;
  930. }
  931. static unsigned int ubwcp_get_hw_image_format_value(u16 ioctl_image_format)
  932. {
  933. enum ubwcp_std_image_format format;
  934. format = to_std_format(ioctl_image_format);
  935. switch (format) {
  936. case RGBA:
  937. return HW_BUFFER_FORMAT_RGBA;
  938. case NV12:
  939. return HW_BUFFER_FORMAT_NV12;
  940. case NV124R:
  941. return HW_BUFFER_FORMAT_NV124R;
  942. case P010:
  943. return HW_BUFFER_FORMAT_P010;
  944. case TP10:
  945. return HW_BUFFER_FORMAT_TP10;
  946. case P016:
  947. return HW_BUFFER_FORMAT_P016;
  948. default:
  949. WARN(1, "Fix this!!!!!");
  950. return 0;
  951. }
  952. }
  953. static int ubwcp_validate_uv_align(struct ubwcp_driver *ubwcp,
  954. struct ubwcp_buffer_attrs *attr,
  955. size_t ula_y_plane_size,
  956. size_t uv_start_offset)
  957. {
  958. int ret = 0;
  959. size_t ula_y_plane_size_align;
  960. size_t y_tile_align_bytes;
  961. int y_tile_height;
  962. int planes;
  963. /* Only validate UV align if there is both a Y and UV plane */
  964. planes = planes_in_format(to_std_format(attr->image_format));
  965. if (planes != 2)
  966. return 0;
  967. /* Check it is cache line size aligned */
  968. if ((uv_start_offset % 64) != 0) {
  969. ret = -EINVAL;
  970. ERR("uv_start_offset %zu not cache line aligned",
  971. uv_start_offset);
  972. goto err;
  973. }
  974. /*
  975. * Check that UV plane does not overlap with any of the Y plane’s tiles
  976. */
  977. y_tile_height = get_tile_height(ubwcp, to_std_format(attr->image_format), 0);
  978. y_tile_align_bytes = y_tile_height * attr->stride;
  979. ula_y_plane_size_align = ((ula_y_plane_size + y_tile_align_bytes - 1) /
  980. y_tile_align_bytes) * y_tile_align_bytes;
  981. if (uv_start_offset < ula_y_plane_size_align) {
  982. ret = -EINVAL;
  983. ERR("uv offset %zu less than y plane align %zu for y plane size %zu",
  984. uv_start_offset, ula_y_plane_size_align,
  985. ula_y_plane_size);
  986. goto err;
  987. }
  988. return 0;
  989. err:
  990. return ret;
  991. }
  992. /* calculate ULA buffer parms
  993. * TBD: how do we make sure uv_start address (not the offset)
  994. * is aligned per requirement: cache line
  995. */
  996. static int ubwcp_calc_ula_params(struct ubwcp_driver *ubwcp,
  997. struct ubwcp_buffer_attrs *attr,
  998. size_t *ula_size,
  999. size_t *ula_y_plane_size,
  1000. size_t *uv_start_offset)
  1001. {
  1002. size_t size;
  1003. enum ubwcp_std_image_format format;
  1004. int planes;
  1005. int missing_plane;
  1006. u32 stride;
  1007. u32 scanlines;
  1008. u32 planar_padding;
  1009. stride = attr->stride;
  1010. scanlines = attr->scanlines;
  1011. planar_padding = attr->planar_padding;
  1012. /* convert ioctl image format to standard image format */
  1013. format = to_std_format(attr->image_format);
  1014. /* Number of "expected" planes in "the standard defined" image format */
  1015. planes = planes_in_format(format);
  1016. /* any plane missing?
  1017. * valid missing_plane values:
  1018. * 0 == no plane missing
  1019. * 1 == 1st plane missing
  1020. * 2 == 2nd plane missing
  1021. */
  1022. missing_plane = missing_plane_from_format(attr->image_format);
  1023. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1024. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1025. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1026. DBG_BUF_ATTR("Planar Padding : %d", planar_padding);
  1027. if (planes == 1) {
  1028. /* uv_start beyond ULA range */
  1029. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1030. *uv_start_offset = size;
  1031. *ula_y_plane_size = size;
  1032. } else {
  1033. if (!missing_plane) {
  1034. /* size for both planes and padding */
  1035. /* Don't pad out Y plane as client would not expect this padding */
  1036. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, false);
  1037. *ula_y_plane_size = size;
  1038. size += planar_padding;
  1039. *uv_start_offset = size;
  1040. size += ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1041. } else {
  1042. if (missing_plane == 2) {
  1043. /* Y-only image, set uv_start beyond ULA range */
  1044. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 0, true);
  1045. *uv_start_offset = size;
  1046. *ula_y_plane_size = size;
  1047. } else {
  1048. /* first plane data is not there */
  1049. size = ubwcp_ula_size(ubwcp, format, stride, scanlines, 1, true);
  1050. *uv_start_offset = 0; /* uv data is at the beginning */
  1051. *ula_y_plane_size = 0;
  1052. }
  1053. }
  1054. }
  1055. //TBD: cleanup
  1056. *ula_size = size;
  1057. DBG_BUF_ATTR("Before page align: Total ULA_Size: %d (0x%x) (planes + planar padding)",
  1058. *ula_size, *ula_size);
  1059. *ula_size = UBWCP_ALIGN(size, 4096);
  1060. DBG_BUF_ATTR("After page align : Total ULA_Size: %d (0x%x) (planes + planar padding)",
  1061. *ula_size, *ula_size);
  1062. return 0;
  1063. }
  1064. /* calculate UBWCP buffer parms */
  1065. static int ubwcp_calc_ubwcp_buf_params(struct ubwcp_driver *ubwcp,
  1066. struct ubwcp_buffer_attrs *attr,
  1067. size_t *md_p0, size_t *pd_p0,
  1068. size_t *md_p1, size_t *pd_p1,
  1069. size_t *stride_tp10_b)
  1070. {
  1071. int planes;
  1072. int missing_plane;
  1073. enum ubwcp_std_image_format format;
  1074. size_t stride_tp10_p;
  1075. FENTRY();
  1076. /* convert ioctl image format to standard image format */
  1077. format = to_std_format(attr->image_format);
  1078. missing_plane = missing_plane_from_format(attr->image_format);
  1079. planes = planes_in_format(format); //pass in 0 (RGB) should return 1
  1080. DBG_BUF_ATTR("ioctl_image_format : %d, std_format: %d", attr->image_format, format);
  1081. DBG_BUF_ATTR("planes_in_format : %d", planes);
  1082. DBG_BUF_ATTR("missing_plane : %d", missing_plane);
  1083. if (!missing_plane) {
  1084. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1085. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1086. if (planes == 2) {
  1087. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1088. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1089. }
  1090. } else {
  1091. if (missing_plane == 1) {
  1092. *md_p0 = 0;
  1093. *pd_p0 = 0;
  1094. *md_p1 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1095. *pd_p1 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 1);
  1096. } else {
  1097. *md_p0 = metadata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1098. *pd_p0 = pixeldata_buf_sz(ubwcp, format, attr->width, attr->height, 0);
  1099. *md_p1 = 0;
  1100. *pd_p1 = 0;
  1101. }
  1102. }
  1103. if (format == TP10) {
  1104. stride_tp10_p = UBWCP_ALIGN(attr->width, 192);
  1105. *stride_tp10_b = (stride_tp10_p/3) + stride_tp10_p;
  1106. } else {
  1107. *stride_tp10_b = 0;
  1108. }
  1109. return 0;
  1110. }
  1111. /* reserve ULA address space of the given size */
  1112. static phys_addr_t ubwcp_ula_alloc(struct ubwcp_driver *ubwcp, size_t size)
  1113. {
  1114. phys_addr_t pa;
  1115. mutex_lock(&ubwcp->ula_lock);
  1116. pa = gen_pool_alloc(ubwcp->ula_pool, size);
  1117. DBG("addr: %p, size: %zx", pa, size);
  1118. mutex_unlock(&ubwcp->ula_lock);
  1119. return pa;
  1120. }
  1121. /* free ULA address space of the given address and size */
  1122. static void ubwcp_ula_free(struct ubwcp_driver *ubwcp, phys_addr_t pa, size_t size)
  1123. {
  1124. mutex_lock(&ubwcp->ula_lock);
  1125. if (!gen_pool_has_addr(ubwcp->ula_pool, pa, size)) {
  1126. ERR("Attempt to free mem not from gen_pool: pa: %p, size: %zx", pa, size);
  1127. goto err;
  1128. }
  1129. DBG("addr: %p, size: %zx", pa, size);
  1130. gen_pool_free(ubwcp->ula_pool, pa, size);
  1131. mutex_unlock(&ubwcp->ula_lock);
  1132. return;
  1133. err:
  1134. mutex_unlock(&ubwcp->ula_lock);
  1135. }
  1136. /* free up or expand current_pa and return the new pa */
  1137. static phys_addr_t ubwcp_ula_realloc(struct ubwcp_driver *ubwcp,
  1138. phys_addr_t pa,
  1139. size_t size,
  1140. size_t new_size)
  1141. {
  1142. if (size == new_size)
  1143. return pa;
  1144. if (pa)
  1145. ubwcp_ula_free(ubwcp, pa, size);
  1146. return ubwcp_ula_alloc(ubwcp, new_size);
  1147. }
  1148. /* unmap dma buf */
  1149. static void ubwcp_dma_unmap(struct ubwcp_buf *buf)
  1150. {
  1151. FENTRY();
  1152. if (buf->dma_buf && buf->attachment) {
  1153. DBG("Calling dma_buf_unmap_attachment()");
  1154. dma_buf_unmap_attachment(buf->attachment, buf->sgt, DMA_BIDIRECTIONAL);
  1155. buf->sgt = NULL;
  1156. dma_buf_detach(buf->dma_buf, buf->attachment);
  1157. buf->attachment = NULL;
  1158. }
  1159. }
  1160. /* dma map ubwcp buffer */
  1161. static int ubwcp_dma_map(struct ubwcp_buf *buf,
  1162. struct device *dev,
  1163. size_t iova_min_size,
  1164. dma_addr_t *iova)
  1165. {
  1166. int ret = 0;
  1167. struct dma_buf *dma_buf = buf->dma_buf;
  1168. struct dma_buf_attachment *attachment;
  1169. struct sg_table *sgt;
  1170. size_t dma_len;
  1171. /* Map buffer to SMMU and get IOVA */
  1172. attachment = dma_buf_attach(dma_buf, dev);
  1173. if (IS_ERR(attachment)) {
  1174. ret = PTR_ERR(attachment);
  1175. ERR("dma_buf_attach() failed: %d", ret);
  1176. goto err;
  1177. }
  1178. dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
  1179. dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64));
  1180. sgt = dma_buf_map_attachment(attachment, DMA_BIDIRECTIONAL);
  1181. if (IS_ERR_OR_NULL(sgt)) {
  1182. ret = PTR_ERR(sgt);
  1183. ERR("dma_buf_map_attachment() failed: %d", ret);
  1184. goto err_detach;
  1185. }
  1186. if (sgt->nents != 1) {
  1187. ERR("nents = %d", sgt->nents);
  1188. goto err_unmap;
  1189. }
  1190. /* ensure that dma_buf is big enough for the new attrs */
  1191. dma_len = sg_dma_len(sgt->sgl);
  1192. if (dma_len < iova_min_size) {
  1193. ERR("dma len: %d is less than min ubwcp buffer size: %d",
  1194. dma_len, iova_min_size);
  1195. goto err_unmap;
  1196. }
  1197. *iova = sg_dma_address(sgt->sgl);
  1198. buf->attachment = attachment;
  1199. buf->sgt = sgt;
  1200. return ret;
  1201. err_unmap:
  1202. dma_buf_unmap_attachment(attachment, sgt, DMA_BIDIRECTIONAL);
  1203. err_detach:
  1204. dma_buf_detach(dma_buf, attachment);
  1205. err:
  1206. if (!ret)
  1207. ret = -1;
  1208. return ret;
  1209. }
  1210. static void
  1211. ubwcp_pixel_to_bytes(struct ubwcp_driver *ubwcp,
  1212. enum ubwcp_std_image_format format,
  1213. u32 width_p, u32 height_p,
  1214. u32 *width_b, u32 *height_b)
  1215. {
  1216. u16 pixel_bytes;
  1217. u16 per_pixel;
  1218. struct ubwcp_image_format_info f_info;
  1219. struct ubwcp_plane_info p_info;
  1220. f_info = ubwcp->format_info[format];
  1221. p_info = f_info.p_info[0];
  1222. pixel_bytes = p_info.pixel_bytes;
  1223. per_pixel = p_info.per_pixel;
  1224. *width_b = (width_p*pixel_bytes)/per_pixel;
  1225. *height_b = (height_p*pixel_bytes)/per_pixel;
  1226. }
  1227. static void reset_buf_attrs(struct ubwcp_buf *buf)
  1228. {
  1229. struct ubwcp_hw_meta_metadata *mmdata;
  1230. struct ubwcp_driver *ubwcp;
  1231. ubwcp = buf->ubwcp;
  1232. mmdata = &buf->mmdata;
  1233. ubwcp_dma_unmap(buf);
  1234. /* reset ula params */
  1235. if (buf->ula_size) {
  1236. ubwcp_ula_free(ubwcp, buf->ula_pa, buf->ula_size);
  1237. buf->ula_size = 0;
  1238. buf->ula_pa = 0;
  1239. }
  1240. /* reset ubwcp params */
  1241. memset(mmdata, 0, sizeof(*mmdata));
  1242. buf->buf_attr_set = false;
  1243. buf->buf_attr.image_format = UBWCP_LINEAR;
  1244. }
  1245. static void print_mmdata_desc(struct ubwcp_hw_meta_metadata *mmdata)
  1246. {
  1247. DBG_BUF_ATTR("");
  1248. DBG_BUF_ATTR("--------MM_DATA DESC ---------");
  1249. DBG_BUF_ATTR("uv_start_addr : 0x%08llx (cache addr) (actual: 0x%llx)",
  1250. mmdata->uv_start_addr, mmdata->uv_start_addr << 6);
  1251. DBG_BUF_ATTR("format : 0x%08x", mmdata->format);
  1252. DBG_BUF_ATTR("stride : 0x%08x (cache addr) (actual: 0x%x)",
  1253. mmdata->stride, mmdata->stride << 6);
  1254. DBG_BUF_ATTR("stride_ubwcp : 0x%08x (cache addr) (actual: 0x%zx)",
  1255. mmdata->stride_ubwcp, mmdata->stride_ubwcp << 6);
  1256. DBG_BUF_ATTR("metadata_base_y : 0x%08x (page addr) (actual: 0x%llx)",
  1257. mmdata->metadata_base_y, mmdata->metadata_base_y << 12);
  1258. DBG_BUF_ATTR("metadata_base_uv: 0x%08x (page addr) (actual: 0x%zx)",
  1259. mmdata->metadata_base_uv, mmdata->metadata_base_uv << 12);
  1260. DBG_BUF_ATTR("buffer_y_offset : 0x%08x (page addr) (actual: 0x%zx)",
  1261. mmdata->buffer_y_offset, mmdata->buffer_y_offset << 12);
  1262. DBG_BUF_ATTR("buffer_uv_offset: 0x%08x (page addr) (actual: 0x%zx)",
  1263. mmdata->buffer_uv_offset, mmdata->buffer_uv_offset << 12);
  1264. DBG_BUF_ATTR("width_height : 0x%08x (width: 0x%x height: 0x%x)",
  1265. mmdata->width_height, mmdata->width_height >> 16, mmdata->width_height & 0xFFFF);
  1266. DBG_BUF_ATTR("");
  1267. }
  1268. /* set buffer attributes:
  1269. * Failure:
  1270. * If a call to ubwcp_set_buf_attrs() fails, any attributes set from a previously
  1271. * successful ubwcp_set_buf_attrs() will be also removed. Thus,
  1272. * ubwcp_set_buf_attrs() implicitly does "unset previous attributes" and
  1273. * then "try to set these new attributes".
  1274. *
  1275. * The result of a failed call to ubwcp_set_buf_attrs() will leave the buffer
  1276. * in a linear mode, NOT with attributes from earlier successful call.
  1277. */
  1278. int ubwcp_set_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1279. {
  1280. int ret = 0;
  1281. size_t ula_size = 0;
  1282. size_t uv_start_offset = 0;
  1283. size_t ula_y_plane_size = 0;
  1284. phys_addr_t ula_pa = 0x0;
  1285. struct ubwcp_buf *buf;
  1286. struct ubwcp_driver *ubwcp;
  1287. size_t metadata_p0;
  1288. size_t pixeldata_p0;
  1289. size_t metadata_p1;
  1290. size_t pixeldata_p1;
  1291. size_t iova_min_size;
  1292. size_t stride_tp10_b;
  1293. dma_addr_t iova_base;
  1294. struct ubwcp_hw_meta_metadata *mmdata;
  1295. u64 uv_start;
  1296. u32 stride_b;
  1297. u32 width_b;
  1298. u32 height_b;
  1299. enum ubwcp_std_image_format std_image_format;
  1300. bool is_non_lin_buf;
  1301. FENTRY();
  1302. trace_ubwcp_set_buf_attrs_start(dmabuf);
  1303. if (!dmabuf) {
  1304. ERR("NULL dmabuf input ptr");
  1305. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1306. return -EINVAL;
  1307. }
  1308. if (!attr) {
  1309. ERR("NULL attr ptr");
  1310. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1311. return -EINVAL;
  1312. }
  1313. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1314. if (!buf) {
  1315. ERR("No corresponding ubwcp_buf for the passed in dma_buf");
  1316. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1317. return -EINVAL;
  1318. }
  1319. ubwcp = buf->ubwcp;
  1320. if (ubwcp->state != UBWCP_STATE_READY)
  1321. return -EPERM;
  1322. mutex_lock(&buf->lock);
  1323. if (buf->lock_count) {
  1324. ERR("Cannot set attr when buffer is locked");
  1325. ret = -EBUSY;
  1326. goto unlock;
  1327. }
  1328. mmdata = &buf->mmdata;
  1329. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1330. //TBD: now that we have single exit point for all errors,
  1331. //we can limit this call to error only?
  1332. //also see if this can be part of reset_buf_attrs()
  1333. DBG_BUF_ATTR("resetting mmap to linear");
  1334. /* remove any earlier dma buf mmap configuration */
  1335. ret = ubwcp->mmap_config_fptr(buf->dma_buf, true, 0, 0);
  1336. if (ret) {
  1337. ERR("dma_buf_mmap_config() failed: %d", ret);
  1338. goto unlock;
  1339. }
  1340. if (!ubwcp_buf_attrs_valid(ubwcp, attr)) {
  1341. ERR("Invalid buf attrs");
  1342. goto err;
  1343. }
  1344. if (attr->image_format == UBWCP_LINEAR) {
  1345. DBG_BUF_ATTR("Linear format requested");
  1346. /* linear format request with permanent range xlation doesn't
  1347. * make sense. need to define behavior if this happens.
  1348. * note: with perm set, desc is allocated to this buffer.
  1349. */
  1350. //TBD: UBWCP_ASSERT(!buf->perm);
  1351. if (buf->buf_attr_set)
  1352. reset_buf_attrs(buf);
  1353. if (is_non_lin_buf) {
  1354. /*
  1355. * Changing buffer from ubwc to linear so decrement
  1356. * number of ubwc buffers
  1357. */
  1358. ret = dec_num_non_lin_buffers(ubwcp);
  1359. }
  1360. mutex_unlock(&buf->lock);
  1361. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1362. return ret;
  1363. }
  1364. std_image_format = to_std_format(attr->image_format);
  1365. if (std_image_format == STD_IMAGE_FORMAT_INVALID) {
  1366. ERR("Unable to map ioctl image format to std image format");
  1367. goto err;
  1368. }
  1369. /* Calculate uncompressed-buffer size. */
  1370. DBG_BUF_ATTR("");
  1371. DBG_BUF_ATTR("");
  1372. DBG_BUF_ATTR("Calculating ula params -->");
  1373. ret = ubwcp_calc_ula_params(ubwcp, attr, &ula_size, &ula_y_plane_size, &uv_start_offset);
  1374. if (ret) {
  1375. ERR("ubwcp_calc_ula_params() failed: %d", ret);
  1376. goto err;
  1377. }
  1378. ret = ubwcp_validate_uv_align(ubwcp, attr, ula_y_plane_size, uv_start_offset);
  1379. if (ret) {
  1380. ERR("ubwcp_validate_uv_align() failed: %d", ret);
  1381. goto err;
  1382. }
  1383. DBG_BUF_ATTR("");
  1384. DBG_BUF_ATTR("");
  1385. DBG_BUF_ATTR("Calculating ubwcp params -->");
  1386. ret = ubwcp_calc_ubwcp_buf_params(ubwcp, attr,
  1387. &metadata_p0, &pixeldata_p0,
  1388. &metadata_p1, &pixeldata_p1,
  1389. &stride_tp10_b);
  1390. if (ret) {
  1391. ERR("ubwcp_calc_buf_params() failed: %d", ret);
  1392. goto err;
  1393. }
  1394. iova_min_size = metadata_p0 + pixeldata_p0 + metadata_p1 + pixeldata_p1;
  1395. DBG_BUF_ATTR("");
  1396. DBG_BUF_ATTR("");
  1397. DBG_BUF_ATTR("------Summary ULA Calculated Params ------");
  1398. DBG_BUF_ATTR("ULA Size : %8zu (0x%8zx)", ula_size, ula_size);
  1399. DBG_BUF_ATTR("UV Start Offset : %8zu (0x%8zx)", uv_start_offset, uv_start_offset);
  1400. DBG_BUF_ATTR("------Summary UBCP Calculated Params ------");
  1401. DBG_BUF_ATTR("metadata_p0 : %8d (0x%8zx)", metadata_p0, metadata_p0);
  1402. DBG_BUF_ATTR("pixeldata_p0 : %8d (0x%8zx)", pixeldata_p0, pixeldata_p0);
  1403. DBG_BUF_ATTR("metadata_p1 : %8d (0x%8zx)", metadata_p1, metadata_p1);
  1404. DBG_BUF_ATTR("pixeldata_p1 : %8d (0x%8zx)", pixeldata_p1, pixeldata_p1);
  1405. DBG_BUF_ATTR("stride_tp10 : %8d (0x%8zx)", stride_tp10_b, stride_tp10_b);
  1406. DBG_BUF_ATTR("iova_min_size : %8d (0x%8zx)", iova_min_size, iova_min_size);
  1407. DBG_BUF_ATTR("");
  1408. /* assign ULA PA with uncompressed-size range */
  1409. ula_pa = ubwcp_ula_realloc(ubwcp, buf->ula_pa, buf->ula_size, ula_size);
  1410. if (!ula_pa) {
  1411. ERR("ubwcp_ula_alloc/realloc() failed. running out of ULA PA space?");
  1412. goto err;
  1413. }
  1414. buf->ula_size = ula_size;
  1415. buf->ula_pa = ula_pa;
  1416. DBG_BUF_ATTR("Allocated ULA_PA: 0x%p of size: 0x%zx", ula_pa, ula_size);
  1417. DBG_BUF_ATTR("");
  1418. /* inform ULA-PA to dma-heap: needed for dma-heap to do CMOs later on */
  1419. DBG_BUF_ATTR("Calling mmap_config(): ULA_PA: 0x%p size: 0x%zx", ula_pa, ula_size);
  1420. ret = ubwcp->mmap_config_fptr(buf->dma_buf, false, buf->ula_pa,
  1421. buf->ula_size);
  1422. if (ret) {
  1423. ERR("dma_buf_mmap_config() failed: %d", ret);
  1424. goto err;
  1425. }
  1426. /* dma map only the first time attribute is set */
  1427. if (!buf->buf_attr_set) {
  1428. /* linear -> ubwcp. map ubwcp buffer */
  1429. ret = ubwcp_dma_map(buf, ubwcp->dev_buf_cb, iova_min_size, &iova_base);
  1430. if (ret) {
  1431. ERR("ubwcp_dma_map() failed: %d", ret);
  1432. goto err;
  1433. }
  1434. DBG_BUF_ATTR("dma_buf IOVA range: 0x%llx + min_size (0x%zx): 0x%llx",
  1435. iova_base, iova_min_size, iova_base + iova_min_size);
  1436. }
  1437. uv_start = ula_pa + uv_start_offset;
  1438. if (!IS_ALIGNED(uv_start, 64)) {
  1439. ERR("ERROR: uv_start is NOT aligned to cache line");
  1440. goto err;
  1441. }
  1442. /* Convert height and width to bytes for writing to mmdata */
  1443. if (std_image_format != TP10) {
  1444. ubwcp_pixel_to_bytes(ubwcp, std_image_format, attr->width,
  1445. attr->height, &width_b, &height_b);
  1446. } else {
  1447. /* for tp10 image compression, we need to program p010 width/height */
  1448. ubwcp_pixel_to_bytes(ubwcp, P010, attr->width,
  1449. attr->height, &width_b, &height_b);
  1450. }
  1451. stride_b = attr->stride;
  1452. /* create the mmdata descriptor */
  1453. memset(mmdata, 0, sizeof(*mmdata));
  1454. mmdata->uv_start_addr = CACHE_ADDR(uv_start);
  1455. mmdata->format = ubwcp_get_hw_image_format_value(attr->image_format);
  1456. if (std_image_format != TP10) {
  1457. mmdata->stride = CACHE_ADDR(stride_b); /* uncompressed stride */
  1458. } else {
  1459. mmdata->stride = CACHE_ADDR(stride_tp10_b); /* compressed stride */
  1460. mmdata->stride_ubwcp = CACHE_ADDR(stride_b); /* uncompressed stride */
  1461. }
  1462. mmdata->metadata_base_y = PAGE_ADDR(iova_base);
  1463. mmdata->metadata_base_uv = PAGE_ADDR(iova_base + metadata_p0 + pixeldata_p0);
  1464. mmdata->buffer_y_offset = PAGE_ADDR(metadata_p0);
  1465. mmdata->buffer_uv_offset = PAGE_ADDR(metadata_p1);
  1466. /* NOTE: For version 1.1, both width & height needs to be in bytes.
  1467. * For other versions, width in bytes & height in pixels.
  1468. */
  1469. if ((ubwcp->hw_ver_major == 1) && (ubwcp->hw_ver_minor == 1))
  1470. mmdata->width_height = width_b << 16 | height_b;
  1471. else
  1472. mmdata->width_height = width_b << 16 | attr->height;
  1473. print_mmdata_desc(mmdata);
  1474. if (!is_non_lin_buf) {
  1475. /*
  1476. * Changing buffer from linear to ubwc so increment
  1477. * number of ubwc buffers
  1478. */
  1479. ret = inc_num_non_lin_buffers(ubwcp);
  1480. }
  1481. if (ret) {
  1482. ERR("inc_num_non_lin_buffers failed: %d", ret);
  1483. goto err;
  1484. }
  1485. buf->buf_attr = *attr;
  1486. buf->buf_attr_set = true;
  1487. //TBD: UBWCP_ASSERT(!buf->perm);
  1488. mutex_unlock(&buf->lock);
  1489. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1490. return 0;
  1491. err:
  1492. reset_buf_attrs(buf);
  1493. if (is_non_lin_buf) {
  1494. /*
  1495. * Changing buffer from ubwc to linear so decrement
  1496. * number of ubwc buffers
  1497. */
  1498. dec_num_non_lin_buffers(ubwcp);
  1499. }
  1500. unlock:
  1501. mutex_unlock(&buf->lock);
  1502. if (!ret)
  1503. ret = -1;
  1504. trace_ubwcp_set_buf_attrs_end(dmabuf);
  1505. return ret;
  1506. }
  1507. EXPORT_SYMBOL(ubwcp_set_buf_attrs);
  1508. /* Set buffer attributes ioctl */
  1509. static int ubwcp_set_buf_attrs_ioctl(struct ubwcp_ioctl_buffer_attrs *attr_ioctl)
  1510. {
  1511. struct dma_buf *dmabuf;
  1512. dmabuf = ubwcp_dma_buf_fd_to_dma_buf(attr_ioctl->fd);
  1513. return ubwcp_set_buf_attrs(dmabuf, &attr_ioctl->attr);
  1514. }
  1515. /* Free up the buffer descriptor */
  1516. static void ubwcp_buf_desc_free(struct ubwcp_driver *ubwcp, struct ubwcp_desc *desc)
  1517. {
  1518. int idx = desc->idx;
  1519. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1520. mutex_lock(&ubwcp->desc_lock);
  1521. desc_list[idx].idx = -1;
  1522. desc_list[idx].ptr = NULL;
  1523. DBG("freed descriptor_id: %d", idx);
  1524. mutex_unlock(&ubwcp->desc_lock);
  1525. }
  1526. /* Allocate next available buffer descriptor. */
  1527. static struct ubwcp_desc *ubwcp_buf_desc_allocate(struct ubwcp_driver *ubwcp)
  1528. {
  1529. int idx;
  1530. struct ubwcp_desc *desc_list = ubwcp->desc_list;
  1531. mutex_lock(&ubwcp->desc_lock);
  1532. for (idx = 0; idx < UBWCP_BUFFER_DESC_COUNT; idx++) {
  1533. if (desc_list[idx].idx == -1) {
  1534. desc_list[idx].idx = idx;
  1535. desc_list[idx].ptr = ubwcp->buffer_desc_base +
  1536. idx*UBWCP_BUFFER_DESC_OFFSET;
  1537. DBG("allocated descriptor_id: %d", idx);
  1538. mutex_unlock(&ubwcp->desc_lock);
  1539. return &desc_list[idx];
  1540. }
  1541. }
  1542. mutex_unlock(&ubwcp->desc_lock);
  1543. return NULL;
  1544. }
  1545. static int ubwcp_flush(struct ubwcp_driver *ubwcp)
  1546. {
  1547. int ret = 0;
  1548. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1549. trace_ubwcp_hw_flush_start(0);
  1550. ret = ubwcp_hw_flush(ubwcp->base);
  1551. trace_ubwcp_hw_flush_end(0);
  1552. if (ret)
  1553. ERR("ubwcp_hw_flush() failed, ret = %d", ret);
  1554. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1555. return ret;
  1556. }
  1557. static int range_check_disable(struct ubwcp_driver *ubwcp, int idx)
  1558. {
  1559. int ret;
  1560. mutex_lock(&ubwcp->ubwcp_flush_lock);
  1561. mutex_lock(&ubwcp->hw_range_ck_lock);
  1562. trace_ubwcp_hw_flush_start(0);
  1563. ret = ubwcp_hw_disable_range_check_with_flush(ubwcp->base, idx);
  1564. trace_ubwcp_hw_flush_end(0);
  1565. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1566. mutex_unlock(&ubwcp->ubwcp_flush_lock);
  1567. return ret;
  1568. }
  1569. static void range_check_enable(struct ubwcp_driver *ubwcp, int idx)
  1570. {
  1571. mutex_lock(&ubwcp->hw_range_ck_lock);
  1572. ubwcp_hw_enable_range_check(ubwcp->base, idx);
  1573. mutex_unlock(&ubwcp->hw_range_ck_lock);
  1574. }
  1575. /**
  1576. * Lock buffer for CPU access. This prepares ubwcp hw to allow
  1577. * CPU access to the compressed buffer. It will perform
  1578. * necessary address translation configuration and cache maintenance ops
  1579. * so that CPU can safely access ubwcp buffer, if this call is
  1580. * successful.
  1581. * Allocate descriptor if not already,
  1582. * perform CMO and then enable range check
  1583. *
  1584. * @param dmabuf : ptr to the dma buf
  1585. * @param direction : direction of access
  1586. *
  1587. * @return int : 0 on success, otherwise error code
  1588. */
  1589. static int ubwcp_lock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1590. {
  1591. int ret = 0;
  1592. struct ubwcp_buf *buf;
  1593. struct ubwcp_driver *ubwcp;
  1594. FENTRY();
  1595. trace_ubwcp_lock_start(dmabuf);
  1596. if (!dmabuf) {
  1597. ERR("NULL dmabuf input ptr");
  1598. trace_ubwcp_lock_end(dmabuf);
  1599. return -EINVAL;
  1600. }
  1601. if (!valid_dma_direction(dir)) {
  1602. ERR("invalid direction: %d", dir);
  1603. trace_ubwcp_lock_end(dmabuf);
  1604. return -EINVAL;
  1605. }
  1606. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1607. if (!buf) {
  1608. ERR("ubwcp_buf ptr not found");
  1609. trace_ubwcp_lock_end(dmabuf);
  1610. return -1;
  1611. }
  1612. ubwcp = buf->ubwcp;
  1613. if (ubwcp->state != UBWCP_STATE_READY) {
  1614. ERR("driver in invalid state: %d", ubwcp->state);
  1615. trace_ubwcp_lock_end(dmabuf);
  1616. return -EPERM;
  1617. }
  1618. mutex_lock(&buf->lock);
  1619. if (!buf->buf_attr_set) {
  1620. ERR("lock() called on buffer, but attr not set");
  1621. goto err;
  1622. }
  1623. if (buf->buf_attr.image_format == UBWCP_LINEAR) {
  1624. ERR("lock() called on linear buffer");
  1625. goto err;
  1626. }
  1627. if (!buf->lock_count) {
  1628. DBG("first lock on buffer");
  1629. /* buf->desc could already be allocated because of perm range xlation */
  1630. if (!buf->desc) {
  1631. /* allocate a buffer descriptor */
  1632. buf->desc = ubwcp_buf_desc_allocate(buf->ubwcp);
  1633. if (!buf->desc) {
  1634. ERR("ubwcp_allocate_buf_desc() failed");
  1635. goto err;
  1636. }
  1637. memcpy(buf->desc->ptr, &buf->mmdata, sizeof(buf->mmdata));
  1638. /* Flushing of updated mmdata:
  1639. * mmdata is iocoherent and ubwcp will get it from CPU cache -
  1640. * *as long as* it has not cached that itself during previous
  1641. * access to the same descriptor.
  1642. *
  1643. * During unlock of previous use of this descriptor,
  1644. * we do hw flush, which will get rid of this mmdata from
  1645. * ubwcp cache.
  1646. *
  1647. * In addition, we also do a hw flush after enable_range_ck().
  1648. * That will also get rid of any speculative fetch of mmdata
  1649. * by the ubwcp hw. At this time, the assumption is that ubwcp
  1650. * will cache mmdata only for active descriptor. But if ubwcp
  1651. * is speculatively fetching mmdata for all descriptors
  1652. * (irrespetive of enabled or not), the flush during lock
  1653. * will be necessary to make sure ubwcp sees updated mmdata
  1654. * that we just updated
  1655. */
  1656. /* program ULA range for this buffer */
  1657. DBG("setting range check: descriptor_id: %d, addr: %p, size: %zx",
  1658. buf->desc->idx, buf->ula_pa, buf->ula_size);
  1659. ubwcp_hw_set_range_check(ubwcp->base, buf->desc->idx, buf->ula_pa,
  1660. buf->ula_size);
  1661. }
  1662. /* enable range check */
  1663. DBG("enabling range check, descriptor_id: %d", buf->desc->idx);
  1664. range_check_enable(ubwcp, buf->desc->idx);
  1665. /* Flush/invalidate UBWCP caches */
  1666. /* Why: cpu could have done a speculative fetch before
  1667. * enable_range_ck() and ubwcp in process of returning "default" data
  1668. * we don't want that stashing of default data pending.
  1669. * we force completion of that and then we also cpu invalidate which
  1670. * will get rid of that line.
  1671. */
  1672. ret = ubwcp_flush(ubwcp);
  1673. if (ret) {
  1674. ubwcp->state = UBWCP_STATE_FAULT;
  1675. ERR("ubwcp_flush() failed: %d, driver state set to FAULT", ret);
  1676. goto err_flush_failed;
  1677. }
  1678. /* Flush/invalidate ULA PA from CPU caches
  1679. * TBD: if (dir == READ or BIDIRECTION) //NOT for write
  1680. * -- Confirm with Chris if this can be skipped for write
  1681. */
  1682. trace_ubwcp_dma_sync_single_for_cpu_start(buf->ula_size);
  1683. dma_sync_single_for_cpu(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1684. trace_ubwcp_dma_sync_single_for_cpu_end(buf->ula_size);
  1685. buf->lock_dir = dir;
  1686. } else {
  1687. DBG("buf already locked");
  1688. /* TBD: what if new buffer direction is not same as previous?
  1689. * must update the dir.
  1690. */
  1691. }
  1692. buf->lock_count++;
  1693. DBG("new lock_count: %d", buf->lock_count);
  1694. mutex_unlock(&buf->lock);
  1695. trace_ubwcp_lock_end(dmabuf);
  1696. return ret;
  1697. err_flush_failed:
  1698. range_check_disable(ubwcp, buf->desc->idx);
  1699. ubwcp_buf_desc_free(ubwcp, buf->desc);
  1700. buf->desc = NULL;
  1701. err:
  1702. mutex_unlock(&buf->lock);
  1703. if (!ret)
  1704. ret = -1;
  1705. trace_ubwcp_lock_end(dmabuf);
  1706. return ret;
  1707. }
  1708. /* This can be called as a result of external unlock() call or
  1709. * internally if free() is called without unlock().
  1710. */
  1711. static int unlock_internal(struct ubwcp_buf *buf, enum dma_data_direction dir, bool free_buffer)
  1712. {
  1713. int ret = 0;
  1714. struct ubwcp_driver *ubwcp;
  1715. DBG("current lock_count: %d", buf->lock_count);
  1716. if (free_buffer) {
  1717. buf->lock_count = 0;
  1718. DBG("Forced lock_count: %d", buf->lock_count);
  1719. } else {
  1720. buf->lock_count--;
  1721. DBG("new lock_count: %d", buf->lock_count);
  1722. if (buf->lock_count) {
  1723. DBG("more than 1 lock on buffer. waiting until last unlock");
  1724. return 0;
  1725. }
  1726. }
  1727. ubwcp = buf->ubwcp;
  1728. /* Flush/invalidate ULA PA from CPU caches */
  1729. //TBD: if (dir == WRITE or BIDIRECTION)
  1730. trace_ubwcp_dma_sync_single_for_device_start(buf->ula_size);
  1731. dma_sync_single_for_device(ubwcp->dev, buf->ula_pa, buf->ula_size, dir);
  1732. trace_ubwcp_dma_sync_single_for_device_end(buf->ula_size);
  1733. /* disable range check */
  1734. DBG("disabling range check");
  1735. ret = range_check_disable(ubwcp, buf->desc->idx);
  1736. if (ret) {
  1737. ubwcp->state = UBWCP_STATE_FAULT;
  1738. ERR("disable_range_check_with_flush() failed: %d, driver state set to FAULT", ret);
  1739. }
  1740. /* release descriptor if perm range xlation is not set */
  1741. if (!buf->perm) {
  1742. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1743. buf->desc = NULL;
  1744. }
  1745. return ret;
  1746. }
  1747. /**
  1748. * Unlock buffer from CPU access. This prepares ubwcp hw to
  1749. * safely allow for device access to the compressed buffer including any
  1750. * necessary cache maintenance ops. It may also free up certain ubwcp
  1751. * resources that could result in error when accessed by CPU in
  1752. * unlocked state.
  1753. *
  1754. * @param dmabuf : ptr to the dma buf
  1755. * @param direction : direction of access
  1756. *
  1757. * @return int : 0 on success, otherwise error code
  1758. */
  1759. static int ubwcp_unlock(struct dma_buf *dmabuf, enum dma_data_direction dir)
  1760. {
  1761. struct ubwcp_buf *buf;
  1762. int ret;
  1763. FENTRY();
  1764. trace_ubwcp_unlock_start(dmabuf);
  1765. if (!dmabuf) {
  1766. ERR("NULL dmabuf input ptr");
  1767. trace_ubwcp_unlock_end(dmabuf);
  1768. return -EINVAL;
  1769. }
  1770. if (!valid_dma_direction(dir)) {
  1771. ERR("invalid direction: %d", dir);
  1772. trace_ubwcp_unlock_end(dmabuf);
  1773. return -EINVAL;
  1774. }
  1775. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1776. if (!buf) {
  1777. ERR("ubwcp_buf not found");
  1778. trace_ubwcp_unlock_end(dmabuf);
  1779. return -1;
  1780. }
  1781. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1782. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1783. trace_ubwcp_unlock_end(dmabuf);
  1784. return -EPERM;
  1785. }
  1786. mutex_lock(&buf->lock);
  1787. if (!buf->lock_count) {
  1788. ERR("unlock() called on buffer which not in locked state");
  1789. trace_ubwcp_unlock_end(dmabuf);
  1790. mutex_unlock(&buf->lock);
  1791. return -1;
  1792. }
  1793. ret = unlock_internal(buf, dir, false);
  1794. mutex_unlock(&buf->lock);
  1795. trace_ubwcp_unlock_end(dmabuf);
  1796. return ret;
  1797. }
  1798. /* Return buffer attributes for the given buffer */
  1799. int ubwcp_get_buf_attrs(struct dma_buf *dmabuf, struct ubwcp_buffer_attrs *attr)
  1800. {
  1801. int ret = 0;
  1802. struct ubwcp_buf *buf;
  1803. FENTRY();
  1804. if (!dmabuf) {
  1805. ERR("NULL dmabuf input ptr");
  1806. return -EINVAL;
  1807. }
  1808. if (!attr) {
  1809. ERR("NULL attr ptr");
  1810. return -EINVAL;
  1811. }
  1812. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1813. if (!buf) {
  1814. ERR("ubwcp_buf ptr not found");
  1815. return -1;
  1816. }
  1817. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1818. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1819. return -EPERM;
  1820. }
  1821. mutex_lock(&buf->lock);
  1822. if (!buf->buf_attr_set) {
  1823. ERR("buffer attributes not set");
  1824. mutex_unlock(&buf->lock);
  1825. return -1;
  1826. }
  1827. *attr = buf->buf_attr;
  1828. mutex_unlock(&buf->lock);
  1829. return ret;
  1830. }
  1831. EXPORT_SYMBOL(ubwcp_get_buf_attrs);
  1832. /* Set permanent range translation.
  1833. * enable: Descriptor will be reserved for this buffer until disabled,
  1834. * making lock/unlock quicker.
  1835. * disable: Descriptor will not be reserved for this buffer. Instead,
  1836. * descriptor will be allocated and released for each lock/unlock.
  1837. * If currently allocated but not being used, descriptor will be
  1838. * released.
  1839. */
  1840. int ubwcp_set_perm_range_translation(struct dma_buf *dmabuf, bool enable)
  1841. {
  1842. int ret = 0;
  1843. struct ubwcp_buf *buf;
  1844. FENTRY();
  1845. if (!dmabuf) {
  1846. ERR("NULL dmabuf input ptr");
  1847. return -EINVAL;
  1848. }
  1849. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1850. if (!buf) {
  1851. ERR("ubwcp_buf not found");
  1852. return -1;
  1853. }
  1854. if (buf->ubwcp->state != UBWCP_STATE_READY) {
  1855. ERR("driver in invalid state: %d", buf->ubwcp->state);
  1856. return -EPERM;
  1857. }
  1858. /* not implemented */
  1859. if (1) {
  1860. ERR("API not implemented yet");
  1861. return -1;
  1862. }
  1863. /* TBD: make sure we acquire buf lock while setting this so there is
  1864. * no race condition with attr_set/lock/unlock
  1865. */
  1866. buf->perm = enable;
  1867. /* if "disable" and we have allocated a desc and it is not being
  1868. * used currently, release it
  1869. */
  1870. if (!enable && buf->desc && !buf->lock_count) {
  1871. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1872. buf->desc = NULL;
  1873. /* Flush/invalidate UBWCP caches */
  1874. //TBD: need to do anything?
  1875. }
  1876. return ret;
  1877. }
  1878. EXPORT_SYMBOL(ubwcp_set_perm_range_translation);
  1879. /**
  1880. * Free up ubwcp resources for this buffer.
  1881. *
  1882. * @param dmabuf : ptr to the dma buf
  1883. *
  1884. * @return int : 0 on success, otherwise error code
  1885. */
  1886. static int ubwcp_free_buffer(struct dma_buf *dmabuf)
  1887. {
  1888. int ret = 0;
  1889. struct ubwcp_buf *buf;
  1890. struct ubwcp_driver *ubwcp;
  1891. unsigned long flags;
  1892. bool is_non_lin_buf;
  1893. FENTRY();
  1894. trace_ubwcp_free_buffer_start(dmabuf);
  1895. if (!dmabuf) {
  1896. ERR("NULL dmabuf input ptr");
  1897. trace_ubwcp_free_buffer_end(dmabuf);
  1898. return -EINVAL;
  1899. }
  1900. buf = dma_buf_to_ubwcp_buf(dmabuf);
  1901. if (!buf) {
  1902. ERR("ubwcp_buf ptr not found");
  1903. trace_ubwcp_free_buffer_end(dmabuf);
  1904. return -1;
  1905. }
  1906. ubwcp = buf->ubwcp;
  1907. if (ubwcp->state != UBWCP_STATE_READY) {
  1908. ERR("driver in invalid state: %d", ubwcp->state);
  1909. trace_ubwcp_free_buffer_end(dmabuf);
  1910. return -EPERM;
  1911. }
  1912. mutex_lock(&buf->lock);
  1913. is_non_lin_buf = (buf->buf_attr.image_format != UBWCP_LINEAR);
  1914. if (buf->lock_count) {
  1915. DBG("free() called without unlock. unlock()'ing first...");
  1916. ret = unlock_internal(buf, buf->lock_dir, true);
  1917. if (ret)
  1918. ERR("unlock_internal(): failed : %d, but continuing free()", ret);
  1919. }
  1920. /* if we are still holding a desc, release it. this can happen only if perm == true */
  1921. if (buf->desc) {
  1922. WARN_ON(!buf->perm); /* TBD: change to BUG() later...*/
  1923. ubwcp_buf_desc_free(buf->ubwcp, buf->desc);
  1924. buf->desc = NULL;
  1925. }
  1926. if (buf->buf_attr_set)
  1927. reset_buf_attrs(buf);
  1928. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  1929. hash_del(&buf->hnode);
  1930. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  1931. kfree(buf);
  1932. if (is_non_lin_buf)
  1933. dec_num_non_lin_buffers(ubwcp);
  1934. trace_ubwcp_free_buffer_end(dmabuf);
  1935. return ret;
  1936. }
  1937. /* file open: TBD: increment ref count? */
  1938. static int ubwcp_open(struct inode *i, struct file *f)
  1939. {
  1940. return 0;
  1941. }
  1942. /* file open: TBD: decrement ref count? */
  1943. static int ubwcp_close(struct inode *i, struct file *f)
  1944. {
  1945. return 0;
  1946. }
  1947. /* handle IOCTLs */
  1948. static long ubwcp_ioctl(struct file *file, unsigned int ioctl_num, unsigned long ioctl_param)
  1949. {
  1950. struct ubwcp_ioctl_buffer_attrs buf_attr_ioctl;
  1951. struct ubwcp_ioctl_hw_version hw_ver;
  1952. struct ubwcp_ioctl_validate_stride validate_stride_ioctl;
  1953. struct ubwcp_ioctl_stride_align stride_align_ioctl;
  1954. enum ubwcp_std_image_format format;
  1955. struct ubwcp_driver *ubwcp;
  1956. ubwcp = ubwcp_get_driver();
  1957. if (!ubwcp)
  1958. return -EINVAL;
  1959. if (ubwcp->state != UBWCP_STATE_READY) {
  1960. ERR("driver in invalid state: %d", ubwcp->state);
  1961. return -EPERM;
  1962. }
  1963. switch (ioctl_num) {
  1964. case UBWCP_IOCTL_SET_BUF_ATTR:
  1965. if (copy_from_user(&buf_attr_ioctl, (const void __user *) ioctl_param,
  1966. sizeof(buf_attr_ioctl))) {
  1967. ERR("ERROR: copy_from_user() failed");
  1968. return -EFAULT;
  1969. }
  1970. DBG("IOCTL : SET_BUF_ATTR: fd = %d", buf_attr_ioctl.fd);
  1971. return ubwcp_set_buf_attrs_ioctl(&buf_attr_ioctl);
  1972. case UBWCP_IOCTL_GET_HW_VER:
  1973. DBG("IOCTL : GET_HW_VER");
  1974. ubwcp_get_hw_version(&hw_ver);
  1975. if (copy_to_user((void __user *)ioctl_param, &hw_ver, sizeof(hw_ver))) {
  1976. ERR("ERROR: copy_to_user() failed");
  1977. return -EFAULT;
  1978. }
  1979. break;
  1980. case UBWCP_IOCTL_GET_STRIDE_ALIGN:
  1981. DBG("IOCTL : GET_STRIDE_ALIGN");
  1982. if (copy_from_user(&stride_align_ioctl, (const void __user *) ioctl_param,
  1983. sizeof(stride_align_ioctl))) {
  1984. ERR("ERROR: copy_from_user() failed");
  1985. return -EFAULT;
  1986. }
  1987. format = to_std_format(stride_align_ioctl.image_format);
  1988. if (format == STD_IMAGE_FORMAT_INVALID)
  1989. return -EINVAL;
  1990. if (stride_align_ioctl.unused != 0)
  1991. return -EINVAL;
  1992. if (get_stride_alignment(format, &stride_align_ioctl.stride_align)) {
  1993. ERR("ERROR: copy_to_user() failed");
  1994. return -EFAULT;
  1995. }
  1996. if (copy_to_user((void __user *)ioctl_param, &stride_align_ioctl,
  1997. sizeof(stride_align_ioctl))) {
  1998. ERR("ERROR: copy_to_user() failed");
  1999. return -EFAULT;
  2000. }
  2001. break;
  2002. case UBWCP_IOCTL_VALIDATE_STRIDE:
  2003. DBG("IOCTL : VALIDATE_STRIDE");
  2004. if (copy_from_user(&validate_stride_ioctl, (const void __user *) ioctl_param,
  2005. sizeof(validate_stride_ioctl))) {
  2006. ERR("ERROR: copy_from_user() failed");
  2007. return -EFAULT;
  2008. }
  2009. format = to_std_format(validate_stride_ioctl.image_format);
  2010. if (format == STD_IMAGE_FORMAT_INVALID) {
  2011. ERR("ERROR: invalid format: %d", validate_stride_ioctl.image_format);
  2012. return -EINVAL;
  2013. }
  2014. if (validate_stride_ioctl.unused1 || validate_stride_ioctl.unused2) {
  2015. ERR("ERROR: unused values must be set to 0");
  2016. return -EINVAL;
  2017. }
  2018. validate_stride_ioctl.valid = stride_is_valid(ubwcp,
  2019. validate_stride_ioctl.image_format,
  2020. validate_stride_ioctl.width,
  2021. validate_stride_ioctl.stride);
  2022. if (copy_to_user((void __user *)ioctl_param, &validate_stride_ioctl,
  2023. sizeof(validate_stride_ioctl))) {
  2024. ERR("ERROR: copy_to_user() failed");
  2025. return -EFAULT;
  2026. }
  2027. break;
  2028. default:
  2029. ERR("Invalid ioctl_num = %d", ioctl_num);
  2030. return -EINVAL;
  2031. }
  2032. return 0;
  2033. }
  2034. static const struct file_operations ubwcp_fops = {
  2035. .owner = THIS_MODULE,
  2036. .open = ubwcp_open,
  2037. .release = ubwcp_close,
  2038. .unlocked_ioctl = ubwcp_ioctl,
  2039. };
  2040. static int read_err_r_op(void *data, u64 *value)
  2041. {
  2042. struct ubwcp_driver *ubwcp = data;
  2043. *value = ubwcp->read_err_irq_en;
  2044. return 0;
  2045. }
  2046. static int read_err_w_op(void *data, u64 value)
  2047. {
  2048. struct ubwcp_driver *ubwcp = data;
  2049. if (ubwcp->state != UBWCP_STATE_READY)
  2050. return -EPERM;
  2051. if (ubwcp_power(ubwcp, true))
  2052. goto err;
  2053. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, value);
  2054. ubwcp->read_err_irq_en = value;
  2055. if (ubwcp_power(ubwcp, false))
  2056. goto err;
  2057. return 0;
  2058. err:
  2059. ubwcp->state = UBWCP_STATE_FAULT;
  2060. return -1;
  2061. }
  2062. static int write_err_r_op(void *data, u64 *value)
  2063. {
  2064. struct ubwcp_driver *ubwcp = data;
  2065. if (ubwcp->state != UBWCP_STATE_READY)
  2066. return -EPERM;
  2067. *value = ubwcp->write_err_irq_en;
  2068. return 0;
  2069. }
  2070. static int write_err_w_op(void *data, u64 value)
  2071. {
  2072. struct ubwcp_driver *ubwcp = data;
  2073. if (ubwcp->state != UBWCP_STATE_READY)
  2074. return -EPERM;
  2075. if (ubwcp_power(ubwcp, true))
  2076. goto err;
  2077. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, value);
  2078. ubwcp->write_err_irq_en = value;
  2079. if (ubwcp_power(ubwcp, false))
  2080. goto err;
  2081. return 0;
  2082. err:
  2083. ubwcp->state = UBWCP_STATE_FAULT;
  2084. return -1;
  2085. }
  2086. static int decode_err_r_op(void *data, u64 *value)
  2087. {
  2088. struct ubwcp_driver *ubwcp = data;
  2089. if (ubwcp->state != UBWCP_STATE_READY)
  2090. return -EPERM;
  2091. *value = ubwcp->decode_err_irq_en;
  2092. return 0;
  2093. }
  2094. static int decode_err_w_op(void *data, u64 value)
  2095. {
  2096. struct ubwcp_driver *ubwcp = data;
  2097. if (ubwcp->state != UBWCP_STATE_READY)
  2098. return -EPERM;
  2099. if (ubwcp_power(ubwcp, true))
  2100. goto err;
  2101. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, value);
  2102. ubwcp->decode_err_irq_en = value;
  2103. if (ubwcp_power(ubwcp, false))
  2104. goto err;
  2105. return 0;
  2106. err:
  2107. ubwcp->state = UBWCP_STATE_FAULT;
  2108. return -1;
  2109. }
  2110. static int encode_err_r_op(void *data, u64 *value)
  2111. {
  2112. struct ubwcp_driver *ubwcp = data;
  2113. if (ubwcp->state != UBWCP_STATE_READY)
  2114. return -EPERM;
  2115. *value = ubwcp->encode_err_irq_en;
  2116. return 0;
  2117. }
  2118. static int encode_err_w_op(void *data, u64 value)
  2119. {
  2120. struct ubwcp_driver *ubwcp = data;
  2121. if (ubwcp->state != UBWCP_STATE_READY)
  2122. return -EPERM;
  2123. if (ubwcp_power(ubwcp, true))
  2124. goto err;
  2125. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, value);
  2126. ubwcp->encode_err_irq_en = value;
  2127. if (ubwcp_power(ubwcp, false))
  2128. goto err;
  2129. return 0;
  2130. err:
  2131. ubwcp->state = UBWCP_STATE_FAULT;
  2132. return -1;
  2133. }
  2134. static int reg_rw_trace_w_op(void *data, u64 value)
  2135. {
  2136. struct ubwcp_driver *ubwcp = data;
  2137. if (ubwcp->state != UBWCP_STATE_READY)
  2138. return -EPERM;
  2139. ubwcp_hw_trace_set(value);
  2140. return 0;
  2141. }
  2142. static int reg_rw_trace_r_op(void *data, u64 *value)
  2143. {
  2144. struct ubwcp_driver *ubwcp = data;
  2145. bool trace_status;
  2146. if (ubwcp->state != UBWCP_STATE_READY)
  2147. return -EPERM;
  2148. ubwcp_hw_trace_get(&trace_status);
  2149. *value = trace_status;
  2150. return 0;
  2151. }
  2152. DEFINE_DEBUGFS_ATTRIBUTE(read_err_fops, read_err_r_op, read_err_w_op, "%d\n");
  2153. DEFINE_DEBUGFS_ATTRIBUTE(decode_err_fops, decode_err_r_op, decode_err_w_op, "%d\n");
  2154. DEFINE_DEBUGFS_ATTRIBUTE(write_err_fops, write_err_r_op, write_err_w_op, "%d\n");
  2155. DEFINE_DEBUGFS_ATTRIBUTE(encode_err_fops, encode_err_r_op, encode_err_w_op, "%d\n");
  2156. DEFINE_DEBUGFS_ATTRIBUTE(reg_rw_trace_fops, reg_rw_trace_r_op, reg_rw_trace_w_op, "%d\n");
  2157. static void ubwcp_debugfs_init(struct ubwcp_driver *ubwcp)
  2158. {
  2159. struct dentry *debugfs_root;
  2160. struct dentry *dfile;
  2161. debugfs_root = debugfs_create_dir("ubwcp", NULL);
  2162. if (IS_ERR_OR_NULL(debugfs_root)) {
  2163. ERR("Failed to create debugfs for ubwcp\n");
  2164. return;
  2165. }
  2166. debugfs_create_u32("debug_trace_enable", 0644, debugfs_root, &ubwcp_debug_trace_enable);
  2167. dfile = debugfs_create_file("reg_rw_trace_en", 0644, debugfs_root, ubwcp, &reg_rw_trace_fops);
  2168. if (IS_ERR_OR_NULL(dfile)) {
  2169. ERR("failed to create reg_rw_trace_en debugfs file");
  2170. goto err;
  2171. }
  2172. dfile = debugfs_create_file("read_err_irq_en", 0644, debugfs_root, ubwcp, &read_err_fops);
  2173. if (IS_ERR_OR_NULL(dfile)) {
  2174. ERR("failed to create read_err_irq debugfs file");
  2175. goto err;
  2176. }
  2177. dfile = debugfs_create_file("write_err_irq_en", 0644, debugfs_root, ubwcp, &write_err_fops);
  2178. if (IS_ERR_OR_NULL(dfile)) {
  2179. ERR("failed to create write_err_irq debugfs file");
  2180. goto err;
  2181. }
  2182. dfile = debugfs_create_file("decode_err_irq_en", 0644, debugfs_root, ubwcp,
  2183. &decode_err_fops);
  2184. if (IS_ERR_OR_NULL(dfile)) {
  2185. ERR("failed to create decode_err_irq debugfs file");
  2186. goto err;
  2187. }
  2188. dfile = debugfs_create_file("encode_err_irq_en", 0644, debugfs_root, ubwcp,
  2189. &encode_err_fops);
  2190. if (IS_ERR_OR_NULL(dfile)) {
  2191. ERR("failed to create encode_err_irq debugfs file");
  2192. goto err;
  2193. }
  2194. ubwcp->debugfs_root = debugfs_root;
  2195. return;
  2196. err:
  2197. debugfs_remove_recursive(ubwcp->debugfs_root);
  2198. ubwcp->debugfs_root = NULL;
  2199. }
  2200. static void ubwcp_debugfs_deinit(struct ubwcp_driver *ubwcp)
  2201. {
  2202. debugfs_remove_recursive(ubwcp->debugfs_root);
  2203. }
  2204. /* ubwcp char device initialization */
  2205. static int ubwcp_cdev_init(struct ubwcp_driver *ubwcp)
  2206. {
  2207. int ret;
  2208. dev_t devt;
  2209. struct class *dev_class;
  2210. struct device *dev_sys;
  2211. /* allocate major device number (/proc/devices -> major_num ubwcp) */
  2212. ret = alloc_chrdev_region(&devt, 0, UBWCP_NUM_DEVICES, UBWCP_DEVICE_NAME);
  2213. if (ret) {
  2214. ERR("alloc_chrdev_region() failed: %d", ret);
  2215. return ret;
  2216. }
  2217. /* create device class (/sys/class/ubwcp_class) */
  2218. dev_class = class_create(THIS_MODULE, "ubwcp_class");
  2219. if (IS_ERR(dev_class)) {
  2220. ERR("class_create() failed");
  2221. return -1;
  2222. }
  2223. /* Create device and register with sysfs
  2224. * (/sys/class/ubwcp_class/ubwcp/... -> dev/power/subsystem/uevent)
  2225. */
  2226. dev_sys = device_create(dev_class, NULL, devt, NULL,
  2227. UBWCP_DEVICE_NAME);
  2228. if (IS_ERR(dev_sys)) {
  2229. ERR("device_create() failed");
  2230. return -1;
  2231. }
  2232. /* register file operations and get cdev */
  2233. cdev_init(&ubwcp->cdev, &ubwcp_fops);
  2234. /* associate cdev and device major/minor with file system
  2235. * can do file ops on /dev/ubwcp after this
  2236. */
  2237. ret = cdev_add(&ubwcp->cdev, devt, 1);
  2238. if (ret) {
  2239. ERR("cdev_add() failed");
  2240. return -1;
  2241. }
  2242. ubwcp->devt = devt;
  2243. ubwcp->dev_class = dev_class;
  2244. ubwcp->dev_sys = dev_sys;
  2245. return 0;
  2246. }
  2247. static void ubwcp_cdev_deinit(struct ubwcp_driver *ubwcp)
  2248. {
  2249. device_destroy(ubwcp->dev_class, ubwcp->devt);
  2250. class_destroy(ubwcp->dev_class);
  2251. cdev_del(&ubwcp->cdev);
  2252. unregister_chrdev_region(ubwcp->devt, UBWCP_NUM_DEVICES);
  2253. }
  2254. struct handler_node {
  2255. struct list_head list;
  2256. u32 client_id;
  2257. ubwcp_error_handler_t handler;
  2258. void *data;
  2259. };
  2260. int ubwcp_register_error_handler(u32 client_id, ubwcp_error_handler_t handler,
  2261. void *data)
  2262. {
  2263. struct handler_node *node;
  2264. unsigned long flags;
  2265. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2266. if (!ubwcp)
  2267. return -EINVAL;
  2268. if (client_id != -1)
  2269. return -EINVAL;
  2270. if (!handler)
  2271. return -EINVAL;
  2272. if (ubwcp->state != UBWCP_STATE_READY)
  2273. return -EPERM;
  2274. node = kzalloc(sizeof(*node), GFP_KERNEL);
  2275. if (!node)
  2276. return -ENOMEM;
  2277. node->client_id = client_id;
  2278. node->handler = handler;
  2279. node->data = data;
  2280. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2281. list_add_tail(&node->list, &ubwcp->err_handler_list);
  2282. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2283. return 0;
  2284. }
  2285. EXPORT_SYMBOL(ubwcp_register_error_handler);
  2286. static void ubwcp_notify_error_handlers(struct ubwcp_err_info *err)
  2287. {
  2288. struct handler_node *node;
  2289. unsigned long flags;
  2290. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2291. if (!ubwcp)
  2292. return;
  2293. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2294. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2295. node->handler(err, node->data);
  2296. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2297. }
  2298. int ubwcp_unregister_error_handler(u32 client_id)
  2299. {
  2300. int ret = -EINVAL;
  2301. struct handler_node *node;
  2302. unsigned long flags;
  2303. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2304. if (!ubwcp)
  2305. return -EINVAL;
  2306. if (ubwcp->state != UBWCP_STATE_INVALID)
  2307. return -EPERM;
  2308. spin_lock_irqsave(&ubwcp->err_handler_list_lock, flags);
  2309. list_for_each_entry(node, &ubwcp->err_handler_list, list)
  2310. if (node->client_id == client_id) {
  2311. list_del(&node->list);
  2312. kfree(node);
  2313. ret = 0;
  2314. break;
  2315. }
  2316. spin_unlock_irqrestore(&ubwcp->err_handler_list_lock, flags);
  2317. return ret;
  2318. }
  2319. EXPORT_SYMBOL(ubwcp_unregister_error_handler);
  2320. /* get ubwcp_buf corresponding to the ULA PA*/
  2321. static struct dma_buf *get_dma_buf_from_ulapa(phys_addr_t addr)
  2322. {
  2323. struct ubwcp_buf *buf = NULL;
  2324. struct dma_buf *ret_buf = NULL;
  2325. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2326. unsigned long flags;
  2327. u32 i;
  2328. if (!ubwcp)
  2329. return NULL;
  2330. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2331. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2332. if (buf->ula_pa <= addr && addr < buf->ula_pa + buf->ula_size) {
  2333. ret_buf = buf->dma_buf;
  2334. break;
  2335. }
  2336. }
  2337. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2338. return ret_buf;
  2339. }
  2340. /* get ubwcp_buf corresponding to the IOVA*/
  2341. static struct dma_buf *get_dma_buf_from_iova(unsigned long addr)
  2342. {
  2343. struct ubwcp_buf *buf = NULL;
  2344. struct dma_buf *ret_buf = NULL;
  2345. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2346. unsigned long flags;
  2347. u32 i;
  2348. if (!ubwcp)
  2349. return NULL;
  2350. spin_lock_irqsave(&ubwcp->buf_table_lock, flags);
  2351. hash_for_each(ubwcp->buf_table, i, buf, hnode) {
  2352. unsigned long iova_base;
  2353. unsigned int iova_size;
  2354. if (!buf->sgt)
  2355. continue;
  2356. iova_base = sg_dma_address(buf->sgt->sgl);
  2357. iova_size = sg_dma_len(buf->sgt->sgl);
  2358. if (iova_base <= addr && addr < iova_base + iova_size) {
  2359. ret_buf = buf->dma_buf;
  2360. break;
  2361. }
  2362. }
  2363. spin_unlock_irqrestore(&ubwcp->buf_table_lock, flags);
  2364. return ret_buf;
  2365. }
  2366. int ubwcp_iommu_fault_handler(struct iommu_domain *domain, struct device *dev,
  2367. unsigned long iova, int flags, void *data)
  2368. {
  2369. int ret = 0;
  2370. struct ubwcp_err_info err;
  2371. struct ubwcp_driver *ubwcp = ubwcp_get_driver();
  2372. struct device *cb_dev = (struct device *)data;
  2373. if (!ubwcp) {
  2374. ret = -EINVAL;
  2375. goto err;
  2376. }
  2377. err.err_code = UBWCP_SMMU_FAULT;
  2378. if (cb_dev == ubwcp->dev_desc_cb)
  2379. err.smmu_err.iommu_dev_id = UBWCP_DESC_CB_ID;
  2380. else if (cb_dev == ubwcp->dev_buf_cb)
  2381. err.smmu_err.iommu_dev_id = UBWCP_BUF_CB_ID;
  2382. else
  2383. err.smmu_err.iommu_dev_id = UBWCP_UNKNOWN_CB_ID;
  2384. err.smmu_err.dmabuf = get_dma_buf_from_iova(iova);
  2385. err.smmu_err.iova = iova;
  2386. err.smmu_err.iommu_fault_flags = flags;
  2387. ERR_RATE_LIMIT("ubwcp_err: err code: %d (smmu), iommu_dev_id: %d, iova: 0x%llx, flags: 0x%x",
  2388. err.err_code, err.smmu_err.iommu_dev_id, err.smmu_err.iova,
  2389. err.smmu_err.iommu_fault_flags);
  2390. ubwcp_notify_error_handlers(&err);
  2391. err:
  2392. return ret;
  2393. }
  2394. static irqreturn_t ubwcp_irq_handler(int irq, void *ptr)
  2395. {
  2396. struct ubwcp_driver *ubwcp;
  2397. void __iomem *base;
  2398. phys_addr_t addr;
  2399. struct ubwcp_err_info err;
  2400. ubwcp = (struct ubwcp_driver *) ptr;
  2401. base = ubwcp->base;
  2402. if (irq == ubwcp->irq_range_ck_rd) {
  2403. addr = ubwcp_hw_interrupt_src_address(base, 0) << 6;
  2404. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2405. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2406. err.translation_err.ula_pa = addr;
  2407. err.translation_err.read = true;
  2408. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2409. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2410. ubwcp_notify_error_handlers(&err);
  2411. ubwcp_hw_interrupt_clear(ubwcp->base, 0);
  2412. } else if (irq == ubwcp->irq_range_ck_wr) {
  2413. addr = ubwcp_hw_interrupt_src_address(base, 1) << 6;
  2414. err.err_code = UBWCP_RANGE_TRANSLATION_ERROR;
  2415. err.translation_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2416. err.translation_err.ula_pa = addr;
  2417. err.translation_err.read = false;
  2418. ERR_RATE_LIMIT("ubwcp_err: err code: %d (range), dmabuf: 0x%llx, read: %d, addr: 0x%llx",
  2419. err.err_code, err.translation_err.dmabuf, err.translation_err.read, addr);
  2420. ubwcp_notify_error_handlers(&err);
  2421. ubwcp_hw_interrupt_clear(ubwcp->base, 1);
  2422. } else if (irq == ubwcp->irq_encode) {
  2423. addr = ubwcp_hw_interrupt_src_address(base, 3) << 6;
  2424. err.err_code = UBWCP_ENCODE_ERROR;
  2425. err.enc_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2426. err.enc_err.ula_pa = addr;
  2427. ERR_RATE_LIMIT("ubwcp_err: err code: %d (encode), dmabuf: 0x%llx, addr: 0x%llx",
  2428. err.err_code, err.enc_err.dmabuf, addr);
  2429. ubwcp_notify_error_handlers(&err);
  2430. ubwcp_hw_interrupt_clear(ubwcp->base, 3);
  2431. } else if (irq == ubwcp->irq_decode) {
  2432. addr = ubwcp_hw_interrupt_src_address(base, 2) << 6;
  2433. err.err_code = UBWCP_DECODE_ERROR;
  2434. err.dec_err.dmabuf = get_dma_buf_from_ulapa(addr);
  2435. err.dec_err.ula_pa = addr;
  2436. ERR_RATE_LIMIT("ubwcp_err: err code: %d (decode), dmabuf: 0x%llx, addr: 0x%llx",
  2437. err.err_code, err.enc_err.dmabuf, addr);
  2438. ubwcp_notify_error_handlers(&err);
  2439. ubwcp_hw_interrupt_clear(ubwcp->base, 2);
  2440. } else {
  2441. ERR("unknown irq: %d", irq);
  2442. return IRQ_NONE;
  2443. }
  2444. return IRQ_HANDLED;
  2445. }
  2446. static int ubwcp_interrupt_register(struct platform_device *pdev, struct ubwcp_driver *ubwcp)
  2447. {
  2448. int ret = 0;
  2449. struct device *dev = &pdev->dev;
  2450. FENTRY();
  2451. ubwcp->irq_range_ck_rd = platform_get_irq(pdev, 0);
  2452. if (ubwcp->irq_range_ck_rd < 0)
  2453. return ubwcp->irq_range_ck_rd;
  2454. ubwcp->irq_range_ck_wr = platform_get_irq(pdev, 1);
  2455. if (ubwcp->irq_range_ck_wr < 0)
  2456. return ubwcp->irq_range_ck_wr;
  2457. ubwcp->irq_encode = platform_get_irq(pdev, 2);
  2458. if (ubwcp->irq_encode < 0)
  2459. return ubwcp->irq_encode;
  2460. ubwcp->irq_decode = platform_get_irq(pdev, 3);
  2461. if (ubwcp->irq_decode < 0)
  2462. return ubwcp->irq_decode;
  2463. DBG("got irqs: %d %d %d %d", ubwcp->irq_range_ck_rd,
  2464. ubwcp->irq_range_ck_wr,
  2465. ubwcp->irq_encode,
  2466. ubwcp->irq_decode);
  2467. ret = devm_request_irq(dev, ubwcp->irq_range_ck_rd, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2468. if (ret) {
  2469. ERR("request_irq() failed. irq: %d ret: %d",
  2470. ubwcp->irq_range_ck_rd, ret);
  2471. return ret;
  2472. }
  2473. ret = devm_request_irq(dev, ubwcp->irq_range_ck_wr, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2474. if (ret) {
  2475. ERR("request_irq() failed. irq: %d ret: %d",
  2476. ubwcp->irq_range_ck_wr, ret);
  2477. return ret;
  2478. }
  2479. ret = devm_request_irq(dev, ubwcp->irq_encode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2480. if (ret) {
  2481. ERR("request_irq() failed. irq: %d ret: %d",
  2482. ubwcp->irq_encode, ret);
  2483. return ret;
  2484. }
  2485. ret = devm_request_irq(dev, ubwcp->irq_decode, ubwcp_irq_handler, 0, "ubwcp", ubwcp);
  2486. if (ret) {
  2487. ERR("request_irq() failed. irq: %d ret: %d",
  2488. ubwcp->irq_decode, ret);
  2489. return ret;
  2490. }
  2491. return ret;
  2492. }
  2493. /* ubwcp device probe */
  2494. static int qcom_ubwcp_probe(struct platform_device *pdev)
  2495. {
  2496. int ret = 0;
  2497. struct ubwcp_driver *ubwcp;
  2498. struct device *ubwcp_dev = &pdev->dev;
  2499. FENTRY();
  2500. ubwcp = devm_kzalloc(ubwcp_dev, sizeof(*ubwcp), GFP_KERNEL);
  2501. if (!ubwcp) {
  2502. ERR("devm_kzalloc() failed");
  2503. return -ENOMEM;
  2504. }
  2505. ubwcp->dev = &pdev->dev;
  2506. ret = dma_set_mask_and_coherent(ubwcp->dev, DMA_BIT_MASK(64));
  2507. #ifdef UBWCP_USE_SMC
  2508. {
  2509. struct resource res;
  2510. of_address_to_resource(ubwcp_dev->of_node, 0, &res);
  2511. ubwcp->base = (void __iomem *) res.start;
  2512. DBG("Using SMC calls. base: %p", ubwcp->base);
  2513. }
  2514. #else
  2515. ubwcp->base = devm_platform_ioremap_resource(pdev, 0);
  2516. if (IS_ERR(ubwcp->base)) {
  2517. ERR("devm ioremap() failed: %d", PTR_ERR(ubwcp->base));
  2518. return PTR_ERR(ubwcp->base);
  2519. }
  2520. DBG("ubwcp->base: %p", ubwcp->base);
  2521. #endif
  2522. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 0, &ubwcp->ula_pool_base);
  2523. if (ret) {
  2524. ERR("failed reading ula_range (base): %d", ret);
  2525. return ret;
  2526. }
  2527. DBG("ubwcp: ula_range: base = 0x%lx", ubwcp->ula_pool_base);
  2528. ret = of_property_read_u64_index(ubwcp_dev->of_node, "ula_range", 1, &ubwcp->ula_pool_size);
  2529. if (ret) {
  2530. ERR("failed reading ula_range (size): %d", ret);
  2531. return ret;
  2532. }
  2533. DBG("ubwcp: ula_range: size = 0x%lx", ubwcp->ula_pool_size);
  2534. INIT_LIST_HEAD(&ubwcp->err_handler_list);
  2535. /* driver initial state */
  2536. ubwcp->state = UBWCP_STATE_INVALID;
  2537. atomic_set(&ubwcp->num_non_lin_buffers, 0);
  2538. ubwcp->mem_online = false;
  2539. mutex_init(&ubwcp->desc_lock);
  2540. spin_lock_init(&ubwcp->buf_table_lock);
  2541. mutex_init(&ubwcp->mem_hotplug_lock);
  2542. mutex_init(&ubwcp->ula_lock);
  2543. mutex_init(&ubwcp->ubwcp_flush_lock);
  2544. mutex_init(&ubwcp->hw_range_ck_lock);
  2545. spin_lock_init(&ubwcp->err_handler_list_lock);
  2546. /* Regulator */
  2547. ubwcp->vdd = devm_regulator_get(ubwcp_dev, "vdd");
  2548. if (IS_ERR_OR_NULL(ubwcp->vdd)) {
  2549. ret = PTR_ERR(ubwcp->vdd);
  2550. ERR("devm_regulator_get() failed: %d", ret);
  2551. return -1;
  2552. }
  2553. ret = ubwcp_init_clocks(ubwcp, ubwcp_dev);
  2554. if (ret) {
  2555. ERR("failed to initialize ubwcp clocks err: %d", ret);
  2556. return ret;
  2557. }
  2558. if (ubwcp_power(ubwcp, true))
  2559. return -1;
  2560. if (ubwcp_cdev_init(ubwcp))
  2561. return -1;
  2562. /* disable all interrupts (reset value has some interrupts enabled by default) */
  2563. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2564. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2565. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2566. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2567. if (ubwcp_interrupt_register(pdev, ubwcp))
  2568. return -1;
  2569. ubwcp_debugfs_init(ubwcp);
  2570. /* create ULA pool */
  2571. ubwcp->ula_pool = gen_pool_create(12, -1);
  2572. if (!ubwcp->ula_pool) {
  2573. ERR("failed gen_pool_create()");
  2574. ret = -1;
  2575. goto err_pool_create;
  2576. }
  2577. ret = gen_pool_add(ubwcp->ula_pool, ubwcp->ula_pool_base, ubwcp->ula_pool_size, -1);
  2578. if (ret) {
  2579. ERR("failed gen_pool_add(): %d", ret);
  2580. ret = -1;
  2581. goto err_pool_add;
  2582. }
  2583. /* register the default config mmap function. */
  2584. ubwcp->mmap_config_fptr = msm_ubwcp_dma_buf_configure_mmap;
  2585. hash_init(ubwcp->buf_table);
  2586. ubwcp_buf_desc_list_init(ubwcp);
  2587. image_format_init(ubwcp);
  2588. /* one time hw init */
  2589. ubwcp_hw_one_time_init(ubwcp->base);
  2590. ubwcp_hw_version(ubwcp->base, &ubwcp->hw_ver_major, &ubwcp->hw_ver_minor);
  2591. pr_err("ubwcp: hw version: major %d, minor %d\n", ubwcp->hw_ver_major, ubwcp->hw_ver_minor);
  2592. if (ubwcp->hw_ver_major == 0) {
  2593. ERR("Failed to read HW version");
  2594. ret = -1;
  2595. goto err_pool_add;
  2596. }
  2597. /* set pdev->dev->driver_data = ubwcp */
  2598. platform_set_drvdata(pdev, ubwcp);
  2599. /* enable interrupts */
  2600. if (ubwcp->read_err_irq_en)
  2601. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, true);
  2602. if (ubwcp->write_err_irq_en)
  2603. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, true);
  2604. if (ubwcp->decode_err_irq_en)
  2605. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, true);
  2606. if (ubwcp->encode_err_irq_en)
  2607. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, true);
  2608. /* Turn OFF until buffers are allocated */
  2609. if (ubwcp_power(ubwcp, false)) {
  2610. ret = -1;
  2611. goto err_power_off;
  2612. }
  2613. ret = msm_ubwcp_set_ops(ubwcp_init_buffer, ubwcp_free_buffer, ubwcp_lock, ubwcp_unlock);
  2614. if (ret) {
  2615. ERR("msm_ubwcp_set_ops() failed: %d", ret);
  2616. goto err_power_off;
  2617. } else {
  2618. DBG("msm_ubwcp_set_ops(): success"); }
  2619. me = ubwcp;
  2620. return ret;
  2621. err_power_off:
  2622. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2623. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2624. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2625. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2626. err_pool_add:
  2627. gen_pool_destroy(ubwcp->ula_pool);
  2628. err_pool_create:
  2629. ubwcp_cdev_deinit(ubwcp);
  2630. return ret;
  2631. }
  2632. /* buffer context bank device probe */
  2633. static int ubwcp_probe_cb_buf(struct platform_device *pdev)
  2634. {
  2635. struct ubwcp_driver *ubwcp;
  2636. struct iommu_domain *domain = NULL;
  2637. FENTRY();
  2638. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2639. if (!ubwcp) {
  2640. ERR("failed to get ubwcp ptr");
  2641. return -EINVAL;
  2642. }
  2643. ubwcp->dev_buf_cb = &pdev->dev;
  2644. domain = iommu_get_domain_for_dev(ubwcp->dev_buf_cb);
  2645. if (domain)
  2646. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_buf_cb);
  2647. if (ubwcp->dev_desc_cb)
  2648. ubwcp->state = UBWCP_STATE_READY;
  2649. return 0;
  2650. }
  2651. /* descriptor context bank device probe */
  2652. static int ubwcp_probe_cb_desc(struct platform_device *pdev)
  2653. {
  2654. int ret = 0;
  2655. struct ubwcp_driver *ubwcp;
  2656. struct iommu_domain *domain = NULL;
  2657. FENTRY();
  2658. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2659. if (!ubwcp) {
  2660. ERR("failed to get ubwcp ptr");
  2661. return -EINVAL;
  2662. }
  2663. ubwcp->buffer_desc_size = UBWCP_BUFFER_DESC_OFFSET *
  2664. UBWCP_BUFFER_DESC_COUNT;
  2665. ubwcp->dev_desc_cb = &pdev->dev;
  2666. dma_set_max_seg_size(ubwcp->dev_desc_cb, DMA_BIT_MASK(32));
  2667. dma_set_seg_boundary(ubwcp->dev_desc_cb, (unsigned long)DMA_BIT_MASK(64));
  2668. /* Allocate buffer descriptors. UBWCP is iocoherent device.
  2669. * Thus we don't need to flush after updates to buffer descriptors.
  2670. */
  2671. ubwcp->buffer_desc_base = dma_alloc_coherent(ubwcp->dev_desc_cb,
  2672. ubwcp->buffer_desc_size,
  2673. &ubwcp->buffer_desc_dma_handle,
  2674. GFP_KERNEL);
  2675. if (!ubwcp->buffer_desc_base) {
  2676. ERR("failed to allocate desc buffer");
  2677. return -ENOMEM;
  2678. }
  2679. DBG("desc_base = %p size = %zu", ubwcp->buffer_desc_base,
  2680. ubwcp->buffer_desc_size);
  2681. ret = ubwcp_power(ubwcp, true);
  2682. if (ret) {
  2683. ERR("failed to power on");
  2684. goto err;
  2685. }
  2686. ubwcp_hw_set_buf_desc(ubwcp->base, (u64) ubwcp->buffer_desc_dma_handle,
  2687. UBWCP_BUFFER_DESC_OFFSET);
  2688. ret = ubwcp_power(ubwcp, false);
  2689. if (ret) {
  2690. ERR("failed to power off");
  2691. goto err;
  2692. }
  2693. domain = iommu_get_domain_for_dev(ubwcp->dev_desc_cb);
  2694. if (domain)
  2695. iommu_set_fault_handler(domain, ubwcp_iommu_fault_handler, ubwcp->dev_desc_cb);
  2696. if (ubwcp->dev_buf_cb)
  2697. ubwcp->state = UBWCP_STATE_READY;
  2698. return ret;
  2699. err:
  2700. dma_free_coherent(ubwcp->dev_desc_cb,
  2701. ubwcp->buffer_desc_size,
  2702. ubwcp->buffer_desc_base,
  2703. ubwcp->buffer_desc_dma_handle);
  2704. ubwcp->buffer_desc_base = NULL;
  2705. ubwcp->buffer_desc_dma_handle = 0;
  2706. ubwcp->dev_desc_cb = NULL;
  2707. return -1;
  2708. }
  2709. /* buffer context bank device remove */
  2710. static int ubwcp_remove_cb_buf(struct platform_device *pdev)
  2711. {
  2712. struct ubwcp_driver *ubwcp;
  2713. FENTRY();
  2714. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2715. if (!ubwcp) {
  2716. ERR("failed to get ubwcp ptr");
  2717. return -EINVAL;
  2718. }
  2719. ubwcp->state = UBWCP_STATE_INVALID;
  2720. ubwcp->dev_buf_cb = NULL;
  2721. return 0;
  2722. }
  2723. /* descriptor context bank device remove */
  2724. static int ubwcp_remove_cb_desc(struct platform_device *pdev)
  2725. {
  2726. struct ubwcp_driver *ubwcp;
  2727. FENTRY();
  2728. ubwcp = dev_get_drvdata(pdev->dev.parent);
  2729. if (!ubwcp) {
  2730. ERR("failed to get ubwcp ptr");
  2731. return -EINVAL;
  2732. }
  2733. if (!ubwcp->dev_desc_cb) {
  2734. ERR("ubwcp->dev_desc_cb == NULL");
  2735. return -1;
  2736. }
  2737. ubwcp_power(ubwcp, true);
  2738. ubwcp_hw_set_buf_desc(ubwcp->base, 0x0, 0x0);
  2739. ubwcp_power(ubwcp, false);
  2740. ubwcp->state = UBWCP_STATE_INVALID;
  2741. dma_free_coherent(ubwcp->dev_desc_cb,
  2742. ubwcp->buffer_desc_size,
  2743. ubwcp->buffer_desc_base,
  2744. ubwcp->buffer_desc_dma_handle);
  2745. ubwcp->buffer_desc_base = NULL;
  2746. ubwcp->buffer_desc_dma_handle = 0;
  2747. return 0;
  2748. }
  2749. /* ubwcp device remove */
  2750. static int qcom_ubwcp_remove(struct platform_device *pdev)
  2751. {
  2752. size_t avail;
  2753. size_t psize;
  2754. struct ubwcp_driver *ubwcp;
  2755. FENTRY();
  2756. /* get pdev->dev->driver_data = ubwcp */
  2757. ubwcp = platform_get_drvdata(pdev);
  2758. if (!ubwcp) {
  2759. ERR("ubwcp == NULL");
  2760. return -1;
  2761. }
  2762. ubwcp_power(ubwcp, true);
  2763. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_READ_ERROR, false);
  2764. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_WRITE_ERROR, false);
  2765. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_ENCODE_ERROR, false);
  2766. ubwcp_hw_interrupt_enable(ubwcp->base, INTERRUPT_DECODE_ERROR, false);
  2767. ubwcp_power(ubwcp, false);
  2768. ubwcp->state = UBWCP_STATE_INVALID;
  2769. /* before destroying, make sure pool is empty. otherwise pool_destroy() panics.
  2770. * TBD: remove this check for production code and let it panic
  2771. */
  2772. avail = gen_pool_avail(ubwcp->ula_pool);
  2773. psize = gen_pool_size(ubwcp->ula_pool);
  2774. if (psize != avail) {
  2775. ERR("gen_pool is not empty! avail: %zx size: %zx", avail, psize);
  2776. ERR("skipping pool destroy....cause it will PANIC. Fix this!!!!");
  2777. WARN(1, "Fix this!");
  2778. } else {
  2779. gen_pool_destroy(ubwcp->ula_pool);
  2780. }
  2781. ubwcp_debugfs_deinit(ubwcp);
  2782. ubwcp_cdev_deinit(ubwcp);
  2783. return 0;
  2784. }
  2785. /* top level ubwcp device probe function */
  2786. static int ubwcp_probe(struct platform_device *pdev)
  2787. {
  2788. const char *compatible = "";
  2789. FENTRY();
  2790. trace_ubwcp_probe(pdev);
  2791. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2792. return qcom_ubwcp_probe(pdev);
  2793. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2794. return ubwcp_probe_cb_desc(pdev);
  2795. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2796. return ubwcp_probe_cb_buf(pdev);
  2797. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2798. ERR("unknown device: %s", compatible);
  2799. WARN_ON(1);
  2800. return -EINVAL;
  2801. }
  2802. /* top level ubwcp device remove function */
  2803. static int ubwcp_remove(struct platform_device *pdev)
  2804. {
  2805. const char *compatible = "";
  2806. FENTRY();
  2807. trace_ubwcp_remove(pdev);
  2808. /* TBD: what if buffers are still allocated? locked? etc.
  2809. * also should turn off power?
  2810. */
  2811. if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp"))
  2812. return qcom_ubwcp_remove(pdev);
  2813. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-desc"))
  2814. return ubwcp_remove_cb_desc(pdev);
  2815. else if (of_device_is_compatible(pdev->dev.of_node, "qcom,ubwcp-context-bank-buf"))
  2816. return ubwcp_remove_cb_buf(pdev);
  2817. of_property_read_string(pdev->dev.of_node, "compatible", &compatible);
  2818. ERR("unknown device: %s", compatible);
  2819. WARN_ON(1);
  2820. return -EINVAL;
  2821. }
  2822. static const struct of_device_id ubwcp_dt_match[] = {
  2823. {.compatible = "qcom,ubwcp"},
  2824. {.compatible = "qcom,ubwcp-context-bank-desc"},
  2825. {.compatible = "qcom,ubwcp-context-bank-buf"},
  2826. {}
  2827. };
  2828. struct platform_driver ubwcp_platform_driver = {
  2829. .probe = ubwcp_probe,
  2830. .remove = ubwcp_remove,
  2831. .driver = {
  2832. .name = "qcom,ubwcp",
  2833. .of_match_table = ubwcp_dt_match,
  2834. },
  2835. };
  2836. int ubwcp_init(void)
  2837. {
  2838. int ret = 0;
  2839. DBG("+++++++++++");
  2840. ret = platform_driver_register(&ubwcp_platform_driver);
  2841. if (ret)
  2842. ERR("platform_driver_register() failed: %d", ret);
  2843. return ret;
  2844. }
  2845. void ubwcp_exit(void)
  2846. {
  2847. platform_driver_unregister(&ubwcp_platform_driver);
  2848. DBG("-----------");
  2849. }
  2850. module_init(ubwcp_init);
  2851. module_exit(ubwcp_exit);
  2852. MODULE_LICENSE("GPL");