wcd9378.c 126 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_RX0 1
  31. #define AUX_RX_PATH_RX1 1
  32. #define SWR_BASECLK_19P2MHZ (0x01)
  33. #define SWR_BASECLK_24P576MHZ (0x03)
  34. #define SWR_BASECLK_22P5792MHZ (0x04)
  35. #define SWR_CLKSCALE_DIV2 (0x02)
  36. #define ADC_MODE_VAL_HIFI 0x01
  37. #define ADC_MODE_VAL_NORMAL 0x03
  38. #define ADC_MODE_VAL_LP 0x05
  39. #define PWR_LEVEL_LOHIFI_VAL 0x00
  40. #define PWR_LEVEL_LP_VAL 0x01
  41. #define PWR_LEVEL_HIFI_VAL 0x02
  42. #define PWR_LEVEL_ULP_VAL 0x03
  43. #define WCD9378_MBQ_ENABLE_MASK 0x2000
  44. #define MICB_USAGE_VAL_DISABLE 0x00
  45. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  46. #define MICB_USAGE_VAL_1P2V 0x02
  47. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  48. #define MICB_USAGE_VAL_2P5V 0x04
  49. #define MICB_USAGE_VAL_2P75V 0x05
  50. #define MICB_USAGE_VAL_2P2V 0xF0
  51. #define MICB_USAGE_VAL_2P7V 0xF1
  52. #define MICB_USAGE_VAL_2P8V 0xF2
  53. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  54. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  55. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  56. #define MICB_NUM_MAX 3
  57. #define NUM_ATTEMPTS 20
  58. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  59. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  60. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  61. SNDRV_PCM_RATE_384000)
  62. /* Fractional Rates */
  63. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  64. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  65. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  66. SNDRV_PCM_FMTBIT_S24_LE |\
  67. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  68. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  69. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  70. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  71. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  72. .tlv.p = (tlv_array), \
  73. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  74. .put = wcd9378_ear_pa_put_gain, \
  75. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  76. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  77. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  78. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  79. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  80. .tlv.p = (tlv_array), \
  81. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  82. .put = wcd9378_aux_pa_put_gain, \
  83. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  84. enum {
  85. CODEC_TX = 0,
  86. CODEC_RX,
  87. };
  88. enum {
  89. RX2_HP_MODE,
  90. RX2_NORMAL_MODE,
  91. };
  92. enum {
  93. WCD_ADC1 = 0,
  94. WCD_ADC2,
  95. WCD_ADC3,
  96. WCD_ADC4,
  97. ALLOW_BUCK_DISABLE,
  98. HPH_COMP_DELAY,
  99. HPH_PA_DELAY,
  100. AMIC2_BCS_ENABLE,
  101. WCD_SUPPLIES_LPM_MODE,
  102. WCD_ADC1_MODE,
  103. WCD_ADC2_MODE,
  104. WCD_ADC3_MODE,
  105. WCD_ADC4_MODE,
  106. WCD_AUX_EN,
  107. WCD_EAR_EN,
  108. };
  109. enum {
  110. NOSJ_SA_STEREO_3SM = 0,
  111. SJ_SA_AUX_2SM,
  112. NOSJ_SA_STEREO_3SM_1HDR,
  113. SJ_SA_AUX_2SM_1HDR,
  114. NOSJ_SA_EAR_3SM,
  115. SJ_SA_EAR_2SM,
  116. NOSJ_SA_EAR_3SM_1HDR,
  117. SJ_SA_EAR_2SM_1HDR,
  118. SJ_1HDR_SA_AUX_1SM,
  119. SJ_1HDR_SA_EAR_1SM,
  120. SJ_SA_STEREO_2SM,
  121. SJ_NOMIC_SA_EAR_3SM,
  122. SJ_NOMIC_SA_AUX_3SM,
  123. WCD_SYS_USAGE_MAX,
  124. };
  125. enum {
  126. NO_MICB_USED,
  127. MICB1,
  128. MICB2,
  129. MICB3,
  130. MICB_NUM,
  131. };
  132. enum {
  133. ADC_MODE_INVALID = 0,
  134. ADC_MODE_HIFI,
  135. ADC_MODE_NORMAL,
  136. ADC_MODE_LP,
  137. };
  138. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
  139. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(aux_pa_gain, 600, -600);
  140. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  141. static int wcd9378_reset(struct device *dev);
  142. static int wcd9378_reset_low(struct device *dev);
  143. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
  144. static void wcd9378_class_load(struct snd_soc_component *component);
  145. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  146. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  147. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  148. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  149. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  150. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  151. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  152. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  153. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  154. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  155. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  156. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  157. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  158. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  159. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  160. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  161. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  162. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  163. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  164. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  165. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  166. };
  167. static int wcd9378_handle_post_irq(void *data)
  168. {
  169. struct wcd9378_priv *wcd9378 = data;
  170. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  171. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  172. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  173. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  174. wcd9378->tx_swr_dev->slave_irq_pending =
  175. ((sts1 || sts2 || !sts3) ? true : false);
  176. return IRQ_HANDLED;
  177. }
  178. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  179. .name = "wcd9378",
  180. .irqs = wcd9378_regmap_irqs,
  181. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  182. .num_regs = 3,
  183. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  184. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  185. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  186. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  187. .use_ack = 1,
  188. .runtime_pm = false,
  189. .handle_post_irq = wcd9378_handle_post_irq,
  190. .irq_drv_data = NULL,
  191. };
  192. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  193. {
  194. int ret = 0;
  195. int bank = 0;
  196. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  197. if (ret)
  198. return -EINVAL;
  199. return ((bank & 0x40) ? 1 : 0);
  200. }
  201. static int wcd9378_init_reg(struct snd_soc_component *component)
  202. {
  203. /*0.9 Volts*/
  204. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  205. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  206. /*BG_EN ENABLE*/
  207. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  208. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  209. usleep_range(1000, 1010);
  210. /*LDOL_BG_SEL SLEEP_BG*/
  211. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  212. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  213. usleep_range(1000, 1010);
  214. /*Start up analog master bias. Sequence cannot change*/
  215. /*VBG_FINE_ADJ 0.005 Volts*/
  216. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  217. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  218. /*ANALOG_BIAS_EN ENABLE*/
  219. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  220. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  221. /*PRECHRG_EN ENABLE*/
  222. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  223. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  224. usleep_range(10000, 10010);
  225. /*PRECHRG_EN DISABLE*/
  226. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  227. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  228. /*End Analog Master Bias enable*/
  229. /*SEQ_BYPASS ENABLE*/
  230. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  231. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  232. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  233. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  234. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  235. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  236. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  237. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  238. /*IBIAS_LDO_DRIVER 5e-06*/
  239. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  240. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  241. /*IBIAS_LDO_DRIVER 5e-06*/
  242. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  243. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  244. /*SHORT_PROT_EN ENABLE*/
  245. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  246. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  247. /*OCP FSM EN*/
  248. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  249. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  250. /*SCD OP EN*/
  251. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  252. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  253. /*OCP DET EN*/
  254. snd_soc_component_update_bits(component, WCD9378_HPH_L_TEST,
  255. WCD9378_HPH_L_TEST_OCP_DET_EN_MASK, 0x01);
  256. /*OCP DET EN*/
  257. snd_soc_component_update_bits(component, WCD9378_HPH_R_TEST,
  258. WCD9378_HPH_R_TEST_OCP_DET_EN_MASK, 0x01);
  259. /*HD2_RES_DIV_CTL_L 82.77*/
  260. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  261. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  262. /*HD2_RES_DIV_CTL_R 82.77*/
  263. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  264. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  265. /*OPAMP_CHOP_CLK_EN DISABLE*/
  266. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  267. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  268. /*RDAC_GAINCTL 0.55*/
  269. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  270. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  271. /*HPH_UP_T0: 0.002*/
  272. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  273. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  274. /*HPH_UP_T9: 0.002*/
  275. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  276. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  277. /*HPH_DN_T0: 0.007*/
  278. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  279. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  280. wcd9378_class_load(component);
  281. return 0;
  282. }
  283. static int wcd9378_set_port_params(struct snd_soc_component *component,
  284. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  285. u8 *ch_mask, u32 *ch_rate,
  286. u8 *port_type, u8 path)
  287. {
  288. int i, j;
  289. u8 num_ports = 0;
  290. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  291. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  292. switch (path) {
  293. case CODEC_RX:
  294. map = &wcd9378->rx_port_mapping;
  295. num_ports = wcd9378->num_rx_ports;
  296. break;
  297. case CODEC_TX:
  298. map = &wcd9378->tx_port_mapping;
  299. num_ports = wcd9378->num_tx_ports;
  300. break;
  301. default:
  302. dev_err(component->dev, "%s Invalid path selected %u\n",
  303. __func__, path);
  304. return -EINVAL;
  305. }
  306. for (i = 0; i <= num_ports; i++) {
  307. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  308. if ((*map)[i][j].slave_port_type == slv_prt_type)
  309. goto found;
  310. }
  311. }
  312. found:
  313. if (i > num_ports || j == MAX_CH_PER_PORT) {
  314. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  315. __func__, slv_prt_type);
  316. return -EINVAL;
  317. }
  318. *port_id = i;
  319. *num_ch = (*map)[i][j].num_ch;
  320. *ch_mask = (*map)[i][j].ch_mask;
  321. *ch_rate = (*map)[i][j].ch_rate;
  322. *port_type = (*map)[i][j].master_port_type;
  323. return 0;
  324. }
  325. static int wcd9378_parse_port_params(struct device *dev,
  326. char *prop, u8 path)
  327. {
  328. u32 *dt_array, map_size, max_uc;
  329. int ret = 0;
  330. u32 cnt = 0;
  331. u32 i, j;
  332. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  333. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  334. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  335. switch (path) {
  336. case CODEC_TX:
  337. map = &wcd9378->tx_port_params;
  338. map_uc = &wcd9378->swr_tx_port_params;
  339. break;
  340. default:
  341. ret = -EINVAL;
  342. goto err_port_map;
  343. }
  344. if (!of_find_property(dev->of_node, prop,
  345. &map_size)) {
  346. dev_err(dev, "missing port mapping prop %s\n", prop);
  347. ret = -EINVAL;
  348. goto err_port_map;
  349. }
  350. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  351. if (max_uc != SWR_UC_MAX) {
  352. dev_err(dev, "%s: port params not provided for all usecases\n",
  353. __func__);
  354. ret = -EINVAL;
  355. goto err_port_map;
  356. }
  357. dt_array = kzalloc(map_size, GFP_KERNEL);
  358. if (!dt_array) {
  359. ret = -ENOMEM;
  360. goto err_alloc;
  361. }
  362. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  363. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  364. if (ret) {
  365. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  366. __func__, prop);
  367. goto err_pdata_fail;
  368. }
  369. for (i = 0; i < max_uc; i++) {
  370. for (j = 0; j < SWR_NUM_PORTS; j++) {
  371. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  372. (*map)[i][j].offset1 = dt_array[cnt];
  373. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  374. }
  375. (*map_uc)[i].pp = &(*map)[i][0];
  376. }
  377. kfree(dt_array);
  378. return 0;
  379. err_pdata_fail:
  380. kfree(dt_array);
  381. err_alloc:
  382. err_port_map:
  383. return ret;
  384. }
  385. static int wcd9378_parse_port_mapping(struct device *dev,
  386. char *prop, u8 path)
  387. {
  388. u32 *dt_array, map_size, map_length;
  389. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  390. u32 slave_port_type, master_port_type;
  391. u32 i, ch_iter = 0;
  392. int ret = 0;
  393. u8 *num_ports = NULL;
  394. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  395. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  396. switch (path) {
  397. case CODEC_RX:
  398. map = &wcd9378->rx_port_mapping;
  399. num_ports = &wcd9378->num_rx_ports;
  400. break;
  401. case CODEC_TX:
  402. map = &wcd9378->tx_port_mapping;
  403. num_ports = &wcd9378->num_tx_ports;
  404. break;
  405. default:
  406. dev_err(dev, "%s Invalid path selected %u\n",
  407. __func__, path);
  408. return -EINVAL;
  409. }
  410. if (!of_find_property(dev->of_node, prop,
  411. &map_size)) {
  412. dev_err(dev, "missing port mapping prop %s\n", prop);
  413. ret = -EINVAL;
  414. goto err_port_map;
  415. }
  416. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  417. dt_array = kzalloc(map_size, GFP_KERNEL);
  418. if (!dt_array) {
  419. ret = -ENOMEM;
  420. goto err_alloc;
  421. }
  422. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  423. NUM_SWRS_DT_PARAMS * map_length);
  424. if (ret) {
  425. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  426. __func__, prop);
  427. goto err_pdata_fail;
  428. }
  429. for (i = 0; i < map_length; i++) {
  430. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  431. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  432. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  433. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  434. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  435. if (port_num != old_port_num)
  436. ch_iter = 0;
  437. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  438. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  439. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  440. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  441. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  442. old_port_num = port_num;
  443. }
  444. *num_ports = port_num;
  445. kfree(dt_array);
  446. return 0;
  447. err_pdata_fail:
  448. kfree(dt_array);
  449. err_alloc:
  450. err_port_map:
  451. return ret;
  452. }
  453. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  454. u8 slv_port_type, int clk_rate,
  455. u8 enable)
  456. {
  457. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  458. u8 port_id, num_ch, ch_mask;
  459. u8 ch_type = 0;
  460. u32 ch_rate;
  461. int slave_ch_idx;
  462. u8 num_port = 1;
  463. int ret = 0;
  464. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  465. &num_ch, &ch_mask, &ch_rate,
  466. &ch_type, CODEC_TX);
  467. if (ret)
  468. return ret;
  469. if (clk_rate)
  470. ch_rate = clk_rate;
  471. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  472. if (slave_ch_idx != -EINVAL)
  473. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  474. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  475. __func__, slave_ch_idx, ch_type);
  476. if (enable)
  477. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  478. num_port, &ch_mask, &ch_rate,
  479. &num_ch, &ch_type);
  480. else
  481. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  482. num_port, &ch_mask, &ch_type);
  483. return ret;
  484. }
  485. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  486. u8 slv_port_type, u8 enable)
  487. {
  488. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  489. u8 port_id, num_ch, ch_mask, port_type;
  490. u32 ch_rate;
  491. u8 num_port = 1;
  492. int ret = 0;
  493. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  494. &num_ch, &ch_mask, &ch_rate,
  495. &port_type, CODEC_RX);
  496. if (ret)
  497. return ret;
  498. if (enable)
  499. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  500. num_port, &ch_mask, &ch_rate,
  501. &num_ch, &port_type);
  502. else
  503. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  504. num_port, &ch_mask, &port_type);
  505. return ret;
  506. }
  507. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  508. struct snd_kcontrol *kcontrol,
  509. int event)
  510. {
  511. struct snd_soc_component *component =
  512. snd_soc_dapm_to_component(w->dapm);
  513. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  514. int mode = wcd9378->hph_mode;
  515. int ret = 0;
  516. int bank = 0;
  517. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  518. w->name, event);
  519. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  520. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  521. wcd9378_rx_connect_port(component, CLSH,
  522. SND_SOC_DAPM_EVENT_ON(event));
  523. }
  524. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  525. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  526. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  527. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
  528. ret = swr_slvdev_datapath_control(
  529. wcd9378->rx_swr_dev,
  530. wcd9378->rx_swr_dev->dev_num,
  531. false);
  532. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
  533. }
  534. return ret;
  535. }
  536. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  537. struct snd_kcontrol *kcontrol,
  538. int event)
  539. {
  540. struct snd_soc_component *component =
  541. snd_soc_dapm_to_component(w->dapm);
  542. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  543. u32 dmic_clk_reg, dmic_clk_en_reg;
  544. s32 *dmic_clk_cnt;
  545. u8 dmic_ctl_shift = 0;
  546. u8 dmic_clk_shift = 0;
  547. u8 dmic_clk_mask = 0;
  548. u32 dmic2_left_en = 0;
  549. int ret = 0;
  550. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  551. w->name, event);
  552. switch (w->shift) {
  553. case 0:
  554. case 1:
  555. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  556. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  557. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  558. dmic_clk_mask = 0x0F;
  559. dmic_clk_shift = 0x00;
  560. dmic_ctl_shift = 0x00;
  561. break;
  562. case 2:
  563. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  564. fallthrough;
  565. case 3:
  566. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  567. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  568. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  569. dmic_clk_mask = 0xF0;
  570. dmic_clk_shift = 0x04;
  571. dmic_ctl_shift = 0x01;
  572. break;
  573. case 4:
  574. case 5:
  575. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  576. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  577. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  578. dmic_clk_mask = 0x0F;
  579. dmic_clk_shift = 0x00;
  580. dmic_ctl_shift = 0x02;
  581. break;
  582. default:
  583. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  584. __func__);
  585. return -EINVAL;
  586. };
  587. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  588. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  589. switch (event) {
  590. case SND_SOC_DAPM_PRE_PMU:
  591. snd_soc_component_update_bits(component,
  592. WCD9378_CDC_AMIC_CTL,
  593. (0x01 << dmic_ctl_shift), 0x00);
  594. /* 250us sleep as per HW requirement */
  595. usleep_range(250, 260);
  596. if (dmic2_left_en)
  597. snd_soc_component_update_bits(component,
  598. dmic2_left_en, 0x80, 0x80);
  599. /* Setting DMIC clock rate to 2.4MHz */
  600. snd_soc_component_update_bits(component,
  601. dmic_clk_reg, dmic_clk_mask,
  602. (0x03 << dmic_clk_shift));
  603. snd_soc_component_update_bits(component,
  604. dmic_clk_en_reg, 0x08, 0x08);
  605. /* enable clock scaling */
  606. snd_soc_component_update_bits(component,
  607. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  608. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  609. wcd9378->tx_swr_dev->dev_num,
  610. true);
  611. break;
  612. case SND_SOC_DAPM_POST_PMD:
  613. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  614. false);
  615. snd_soc_component_update_bits(component,
  616. WCD9378_CDC_AMIC_CTL,
  617. (0x01 << dmic_ctl_shift),
  618. (0x01 << dmic_ctl_shift));
  619. if (dmic2_left_en)
  620. snd_soc_component_update_bits(component,
  621. dmic2_left_en, 0x80, 0x00);
  622. snd_soc_component_update_bits(component,
  623. dmic_clk_en_reg, 0x08, 0x00);
  624. break;
  625. };
  626. return ret;
  627. }
  628. /*
  629. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  630. * @micb_mv: micbias in mv
  631. *
  632. * return register value converted
  633. */
  634. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  635. {
  636. /* min micbias voltage is 1V and maximum is 2.85V */
  637. if (micb_mv < 1000 || micb_mv > 2850) {
  638. pr_err("%s: unsupported micbias voltage\n", __func__);
  639. return -EINVAL;
  640. }
  641. return (micb_mv - 1000) / 50;
  642. }
  643. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  644. /*
  645. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  646. * @component: handle to snd_soc_component *
  647. * @req_volt: micbias voltage to be set
  648. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  649. *
  650. * return 0 if adjustment is success or error code in case of failure
  651. */
  652. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  653. u32 micb_mv, int micb_num)
  654. {
  655. int vcout_ctl;
  656. switch (micb_mv) {
  657. case 2200:
  658. return MICB_USAGE_VAL_2P2V;
  659. case 2700:
  660. return MICB_USAGE_VAL_2P7V;
  661. case 2800:
  662. return MICB_USAGE_VAL_2P8V;
  663. default:
  664. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  665. if (micb_num == MIC_BIAS_1) {
  666. snd_soc_component_update_bits(component,
  667. WCD9378_MICB_REMAP_TABLE_VAL_3,
  668. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  669. vcout_ctl);
  670. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  671. } else if (micb_num == MIC_BIAS_2) {
  672. snd_soc_component_update_bits(component,
  673. WCD9378_MICB_REMAP_TABLE_VAL_4,
  674. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  675. vcout_ctl);
  676. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  677. } else if (micb_num == MIC_BIAS_3) {
  678. snd_soc_component_update_bits(component,
  679. WCD9378_MICB_REMAP_TABLE_VAL_5,
  680. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  681. vcout_ctl);
  682. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  683. }
  684. }
  685. return 0;
  686. }
  687. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  688. u32 micb_mv, int micb_num)
  689. {
  690. switch (micb_mv) {
  691. case 0:
  692. return MICB_USAGE_VAL_PULL_DOWN;
  693. case 1200:
  694. return MICB_USAGE_VAL_1P2V;
  695. case 1800:
  696. return MICB_USAGE_VAL_1P8VORPULLUP;
  697. case 2500:
  698. return MICB_USAGE_VAL_2P5V;
  699. case 2750:
  700. return MICB_USAGE_VAL_2P75V;
  701. default:
  702. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  703. }
  704. return MICB_USAGE_VAL_DISABLE;
  705. }
  706. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  707. int req_volt, int micb_num)
  708. {
  709. struct wcd9378_priv *wcd9378 =
  710. snd_soc_component_get_drvdata(component);
  711. int micb_usage = 0, micb_mask = 0, req_vout_ctl;
  712. int sm_num = 0;
  713. struct wcd9378_pdata *pdata = NULL;
  714. pdata = dev_get_platdata(wcd9378->dev);
  715. if (wcd9378 == NULL) {
  716. dev_err(component->dev,
  717. "%s: wcd9378 private data is NULL\n", __func__);
  718. return -EINVAL;
  719. }
  720. for (sm_num = 0; sm_num < SIM_MIC_NUM; sm_num++)
  721. if (wcd9378->micb_sel[sm_num] == micb_num)
  722. break;
  723. if ((sm_num == SIM_MIC_NUM) && (micb_num != MIC_BIAS_2)) {
  724. pr_err("%s: cannot find the simple mic function which connect to micbias_%d\n",
  725. __func__, micb_num);
  726. return -EINVAL;
  727. }
  728. switch (sm_num) {
  729. case SIM_MIC0:
  730. micb_usage = WCD9378_IT11_USAGE;
  731. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  732. break;
  733. case SIM_MIC1:
  734. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  735. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  736. break;
  737. case SIM_MIC2:
  738. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  739. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  740. break;
  741. default:
  742. if (micb_num == MIC_BIAS_2) {
  743. micb_usage = WCD9378_IT31_MICB;
  744. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  745. }
  746. break;
  747. }
  748. mutex_lock(&wcd9378->micb_lock);
  749. req_vout_ctl =
  750. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  751. snd_soc_component_update_bits(component,
  752. micb_usage, micb_mask, req_vout_ctl);
  753. mutex_unlock(&wcd9378->micb_lock);
  754. return 0;
  755. }
  756. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  757. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  758. bool bcs_disable)
  759. {
  760. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  761. if (wcd9378->update_wcd_event) {
  762. if (bcs_disable)
  763. wcd9378->update_wcd_event(wcd9378->handle,
  764. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  765. else
  766. wcd9378->update_wcd_event(wcd9378->handle,
  767. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  768. }
  769. }
  770. static int wcd9378_get_clk_rate(int mode)
  771. {
  772. int rate;
  773. switch (mode) {
  774. case ADC_MODE_LP:
  775. rate = SWR_CLK_RATE_4P8MHZ;
  776. break;
  777. case ADC_MODE_INVALID:
  778. case ADC_MODE_NORMAL:
  779. case ADC_MODE_HIFI:
  780. default:
  781. rate = SWR_CLK_RATE_9P6MHZ;
  782. break;
  783. }
  784. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  785. return rate;
  786. }
  787. static int wcd9378_get_adc_mode_val(int mode)
  788. {
  789. int ret = 0;
  790. switch (mode) {
  791. case ADC_MODE_INVALID:
  792. case ADC_MODE_NORMAL:
  793. ret = ADC_MODE_VAL_NORMAL;
  794. break;
  795. case ADC_MODE_HIFI:
  796. ret = ADC_MODE_VAL_HIFI;
  797. break;
  798. case ADC_MODE_LP:
  799. ret = ADC_MODE_VAL_LP;
  800. break;
  801. default:
  802. ret = -EINVAL;
  803. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  804. break;
  805. }
  806. return ret;
  807. }
  808. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  809. struct snd_kcontrol *kcontrol, int event)
  810. {
  811. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  812. struct wcd9378_priv *wcd9378 =
  813. snd_soc_component_get_drvdata(component);
  814. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  815. int act_ps = 0;
  816. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  817. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  818. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  819. w->name, w->shift, event);
  820. switch (event) {
  821. case SND_SOC_DAPM_PRE_PMU:
  822. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  823. if (mode_val < 0) {
  824. dev_dbg(component->dev,
  825. "%s: invalid mode, setting to normal mode\n",
  826. __func__);
  827. mode_val = ADC_MODE_VAL_NORMAL;
  828. }
  829. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  830. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  831. WCD9378_TX_NEW_TX_CH12_MUX) &
  832. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  833. if (!wcd9378->bcs_dis) {
  834. wcd9378_tx_connect_port(component, MBHC,
  835. SWR_CLK_RATE_4P8MHZ, true);
  836. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  837. }
  838. }
  839. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  840. wcd9378_tx_connect_port(component, w->shift, rate,
  841. true);
  842. if (wcd9378->va_amic_en)
  843. wcd9378_micbias_control(component, w->shift,
  844. MICB_PULLUP_ENABLE, true);
  845. else
  846. wcd9378_micbias_control(component, w->shift,
  847. MICB_ENABLE, true);
  848. switch (w->shift) {
  849. case ADC1:
  850. /*SMP MIC0 IT11 USAGE SET*/
  851. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  852. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  853. /*Hold TXFE in Initialization During Startup*/
  854. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  855. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  856. /*Power up TX0 sequencer*/
  857. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  858. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  859. break;
  860. case ADC2:
  861. if (wcd9378->sjmic_support) {
  862. /*SMP JACK IT31 USAGE SET*/
  863. snd_soc_component_update_bits(component,
  864. WCD9378_IT31_USAGE,
  865. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  866. /*Power up TX1 sequencer*/
  867. snd_soc_component_update_bits(component,
  868. WCD9378_PDE34_REQ_PS,
  869. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  870. } else {
  871. /*SMP MIC1 IT11 USAGE SET*/
  872. snd_soc_component_update_bits(component,
  873. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  874. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  875. mode_val);
  876. /*Hold TXFE in Initialization During Startup*/
  877. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  878. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  879. /*Power up TX1 sequencer*/
  880. snd_soc_component_update_bits(component,
  881. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  882. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  883. 0x00);
  884. }
  885. break;
  886. case ADC3:
  887. /*SMP MIC2 IT11 USAGE SET*/
  888. snd_soc_component_update_bits(component,
  889. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  890. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  891. mode_val);
  892. /*Hold TXFE in Initialization During Startup*/
  893. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  894. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  895. /*Power up TX2 sequencer*/
  896. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  897. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  898. break;
  899. default:
  900. break;
  901. }
  902. /*default delay 800us*/
  903. usleep_range(800, 810);
  904. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
  905. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  906. wcd9378->tx_swr_dev->dev_num,
  907. true);
  908. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
  909. switch (w->shift) {
  910. case ADC1:
  911. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  912. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  913. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  914. if (act_ps)
  915. dev_dbg(component->dev, "%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
  916. __func__, act_ps);
  917. else
  918. dev_dbg(component->dev, "%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
  919. __func__, act_ps);
  920. break;
  921. case ADC2:
  922. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  923. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  924. if (wcd9378->sjmic_support)
  925. act_ps = snd_soc_component_read(component,
  926. WCD9378_PDE34_ACT_PS);
  927. else
  928. act_ps = snd_soc_component_read(component,
  929. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  930. if (act_ps)
  931. dev_dbg(component->dev, "%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
  932. __func__, act_ps);
  933. else
  934. dev_dbg(component->dev, "%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
  935. __func__, act_ps);
  936. break;
  937. case ADC3:
  938. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  939. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  940. act_ps = snd_soc_component_read(component,
  941. WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
  942. if (act_ps)
  943. dev_dbg(component->dev, "%s: tx2 sequencer didnot power on, act_ps: 0x%0x\n",
  944. __func__, act_ps);
  945. else
  946. dev_dbg(component->dev, "%s: tx2 sequencer power on successful, act_ps: 0x%0x\n",
  947. __func__, act_ps);
  948. break;
  949. };
  950. break;
  951. case SND_SOC_DAPM_POST_PMD:
  952. wcd9378_tx_connect_port(component, w->shift, 0, false);
  953. if (w->shift == ADC2 &&
  954. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  955. wcd9378_tx_connect_port(component, MBHC, 0,
  956. false);
  957. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  958. }
  959. switch (w->shift) {
  960. case ADC1:
  961. /*Normal TXFE Startup*/
  962. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  963. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  964. /*tear down TX0 sequencer*/
  965. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  966. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  967. break;
  968. case ADC2:
  969. /*tear down TX1 sequencer*/
  970. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  971. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  972. /*Normal TXFE Startup*/
  973. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  974. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  975. /*tear down TX1 sequencer*/
  976. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  977. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  978. break;
  979. case ADC3:
  980. /*Normal TXFE Startup*/
  981. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  982. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  983. /*tear down TX2 sequencer*/
  984. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  985. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  986. break;
  987. default:
  988. break;
  989. }
  990. /*default delay 800us*/
  991. usleep_range(800, 810);
  992. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
  993. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  994. wcd9378->tx_swr_dev->dev_num,
  995. false);
  996. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
  997. if (wcd9378->va_amic_en)
  998. wcd9378_micbias_control(component, w->shift,
  999. MICB_PULLUP_DISABLE, true);
  1000. else
  1001. wcd9378_micbias_control(component, w->shift,
  1002. MICB_DISABLE, true);
  1003. break;
  1004. default:
  1005. break;
  1006. }
  1007. return ret;
  1008. }
  1009. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1010. struct snd_kcontrol *kcontrol,
  1011. int event)
  1012. {
  1013. struct snd_soc_component *component =
  1014. snd_soc_dapm_to_component(w->dapm);
  1015. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1016. int ret = 0;
  1017. switch (event) {
  1018. case SND_SOC_DAPM_PRE_PMU:
  1019. wcd9378_tx_connect_port(component, w->shift,
  1020. SWR_CLK_RATE_2P4MHZ, true);
  1021. break;
  1022. case SND_SOC_DAPM_POST_PMD:
  1023. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1024. wcd9378->tx_swr_dev->dev_num,
  1025. false);
  1026. break;
  1027. };
  1028. return ret;
  1029. }
  1030. static int wcd9378_tx_num_get(struct snd_soc_component *component,
  1031. int micb_num)
  1032. {
  1033. int sm_num = 0;
  1034. struct wcd9378_priv *wcd9378 =
  1035. snd_soc_component_get_drvdata(component);
  1036. for (sm_num = SIM_MIC0; sm_num <= SIM_MIC2; sm_num++) {
  1037. if (wcd9378->micb_sel[sm_num] == micb_num) {
  1038. if (sm_num == SIM_MIC0)
  1039. return ADC1;
  1040. else if (sm_num == SIM_MIC1)
  1041. return ADC2;
  1042. else if (sm_num == SIM_MIC2)
  1043. return ADC3;
  1044. else
  1045. return -EINVAL;
  1046. }
  1047. }
  1048. return -EINVAL;
  1049. }
  1050. static int wcd9378_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1051. struct snd_kcontrol *kcontrol,
  1052. int event)
  1053. {
  1054. struct snd_soc_component *component =
  1055. snd_soc_dapm_to_component(w->dapm);
  1056. int micb_num = 0, tx_num = 0;
  1057. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1058. __func__, w->name, event);
  1059. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1060. micb_num = MIC_BIAS_1;
  1061. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1062. micb_num = MIC_BIAS_2;
  1063. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1064. micb_num = MIC_BIAS_3;
  1065. else
  1066. return -EINVAL;
  1067. tx_num = wcd9378_tx_num_get(component, micb_num);
  1068. if (tx_num < 0)
  1069. pr_err("%s: SM MB SEL should be set properly\n", __func__);
  1070. switch (event) {
  1071. case SND_SOC_DAPM_PRE_PMU:
  1072. wcd9378_micbias_control(component, tx_num,
  1073. MICB_ENABLE, true);
  1074. break;
  1075. case SND_SOC_DAPM_POST_PMU:
  1076. usleep_range(1000, 1100);
  1077. break;
  1078. case SND_SOC_DAPM_POST_PMD:
  1079. wcd9378_micbias_control(component, tx_num,
  1080. MICB_DISABLE, true);
  1081. break;
  1082. };
  1083. return 0;
  1084. }
  1085. static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1086. struct snd_kcontrol *kcontrol,
  1087. int event)
  1088. {
  1089. struct snd_soc_component *component =
  1090. snd_soc_dapm_to_component(w->dapm);
  1091. int micb_num = 0, tx_num = 0;
  1092. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1093. __func__, w->name, event);
  1094. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1095. micb_num = MIC_BIAS_1;
  1096. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1097. micb_num = MIC_BIAS_2;
  1098. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1099. micb_num = MIC_BIAS_3;
  1100. else
  1101. return -EINVAL;
  1102. tx_num = wcd9378_tx_num_get(component, micb_num);
  1103. if (tx_num < 0)
  1104. pr_err("%s: SM MB SEL should be set properly\n", __func__);
  1105. switch (event) {
  1106. case SND_SOC_DAPM_PRE_PMU:
  1107. wcd9378_micbias_control(component, tx_num,
  1108. MICB_PULLUP_ENABLE, true);
  1109. break;
  1110. case SND_SOC_DAPM_POST_PMU:
  1111. usleep_range(1000, 1100);
  1112. break;
  1113. case SND_SOC_DAPM_POST_PMD:
  1114. wcd9378_micbias_control(component, tx_num,
  1115. MICB_PULLUP_DISABLE, true);
  1116. break;
  1117. };
  1118. return 0;
  1119. }
  1120. /*
  1121. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1122. * @component: handle to snd_soc_component *
  1123. *
  1124. * return wcd9378_mbhc handle or error code in case of failure
  1125. */
  1126. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1127. {
  1128. struct wcd9378_priv *wcd9378;
  1129. if (!component) {
  1130. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1131. return NULL;
  1132. }
  1133. wcd9378 = snd_soc_component_get_drvdata(component);
  1134. if (!wcd9378) {
  1135. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1136. return NULL;
  1137. }
  1138. return wcd9378->mbhc;
  1139. }
  1140. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1141. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1142. struct snd_kcontrol *kcontrol,
  1143. int event)
  1144. {
  1145. struct snd_soc_component *component =
  1146. snd_soc_dapm_to_component(w->dapm);
  1147. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1148. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1149. w->name, event);
  1150. switch (event) {
  1151. case SND_SOC_DAPM_PRE_PMU:
  1152. /*HPHL ENABLE*/
  1153. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1154. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1155. wcd9378_rx_connect_port(component, HPH_L, true);
  1156. if (wcd9378->comp1_enable) {
  1157. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1158. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1159. wcd9378_rx_connect_port(component, COMP_L, true);
  1160. }
  1161. if (wcd9378->update_wcd_event)
  1162. wcd9378->update_wcd_event(wcd9378->handle,
  1163. SLV_BOLERO_EVT_RX_MUTE,
  1164. (WCD_RX1 << 0x10));
  1165. break;
  1166. case SND_SOC_DAPM_POST_PMD:
  1167. /*HPHL DISABLE*/
  1168. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1169. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1170. wcd9378_rx_connect_port(component, HPH_L, false);
  1171. if (wcd9378->comp1_enable) {
  1172. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1173. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
  1174. wcd9378_rx_connect_port(component, COMP_R, false);
  1175. }
  1176. break;
  1177. default:
  1178. break;
  1179. };
  1180. return 0;
  1181. }
  1182. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1183. struct snd_kcontrol *kcontrol,
  1184. int event)
  1185. {
  1186. struct snd_soc_component *component =
  1187. snd_soc_dapm_to_component(w->dapm);
  1188. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1189. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1190. w->name, event);
  1191. switch (event) {
  1192. case SND_SOC_DAPM_PRE_PMU:
  1193. /*HPHR ENABLE*/
  1194. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1195. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1196. wcd9378_rx_connect_port(component, HPH_R, true);
  1197. if (wcd9378->comp2_enable) {
  1198. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1199. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1200. wcd9378_rx_connect_port(component, COMP_R, true);
  1201. }
  1202. break;
  1203. case SND_SOC_DAPM_POST_PMD:
  1204. /*HPHR DISABLE*/
  1205. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1206. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1207. wcd9378_rx_connect_port(component, HPH_R, false);
  1208. if (wcd9378->comp2_enable) {
  1209. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1210. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
  1211. wcd9378_rx_connect_port(component, COMP_R, false);
  1212. }
  1213. break;
  1214. default:
  1215. break;
  1216. };
  1217. return 0;
  1218. }
  1219. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1220. struct snd_kcontrol *kcontrol,
  1221. int event)
  1222. {
  1223. struct snd_soc_component *component =
  1224. snd_soc_dapm_to_component(w->dapm);
  1225. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1226. int ret;
  1227. int bank = 0;
  1228. int act_ps = 0;
  1229. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1230. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1231. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1232. w->name, event);
  1233. switch (event) {
  1234. case SND_SOC_DAPM_PRE_PMU:
  1235. if (wcd9378->update_wcd_event)
  1236. wcd9378->update_wcd_event(wcd9378->handle,
  1237. SLV_BOLERO_EVT_RX_MUTE,
  1238. (WCD_RX1 << 0x10 | 0x01));
  1239. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1240. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1241. wcd9378->rx_swr_dev->dev_num,
  1242. true);
  1243. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1244. if (wcd9378->update_wcd_event)
  1245. wcd9378->update_wcd_event(wcd9378->handle,
  1246. SLV_BOLERO_EVT_RX_MUTE,
  1247. (WCD_RX1 << 0x10));
  1248. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1249. if (act_ps)
  1250. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1251. __func__, act_ps);
  1252. else
  1253. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1254. __func__, act_ps);
  1255. break;
  1256. case SND_SOC_DAPM_POST_PMD:
  1257. if (wcd9378->update_wcd_event)
  1258. wcd9378->update_wcd_event(wcd9378->handle,
  1259. SLV_BOLERO_EVT_RX_MUTE,
  1260. (WCD_RX1 << 0x10 | 0x1));
  1261. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1262. wcd9378->update_wcd_event(wcd9378->handle,
  1263. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1264. (WCD_RX1 << 0x10));
  1265. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1266. WCD_EVENT_POST_HPHL_PA_OFF,
  1267. &wcd9378->mbhc->wcd_mbhc);
  1268. break;
  1269. default:
  1270. break;
  1271. };
  1272. return 0;
  1273. }
  1274. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1275. struct snd_kcontrol *kcontrol,
  1276. int event)
  1277. {
  1278. struct snd_soc_component *component =
  1279. snd_soc_dapm_to_component(w->dapm);
  1280. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1281. int ret;
  1282. int act_ps = 0;
  1283. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1284. w->name, event);
  1285. switch (event) {
  1286. case SND_SOC_DAPM_PRE_PMU:
  1287. if (wcd9378->update_wcd_event)
  1288. wcd9378->update_wcd_event(wcd9378->handle,
  1289. SLV_BOLERO_EVT_RX_MUTE,
  1290. (WCD_RX2 << 0x10 | 0x1));
  1291. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1292. wcd9378->rx_swr_dev->dev_num,
  1293. true);
  1294. if (wcd9378->update_wcd_event)
  1295. wcd9378->update_wcd_event(wcd9378->handle,
  1296. SLV_BOLERO_EVT_RX_MUTE,
  1297. (WCD_RX2 << 0x10));
  1298. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1299. if (act_ps)
  1300. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1301. __func__, act_ps);
  1302. else
  1303. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1304. __func__, act_ps);
  1305. break;
  1306. case SND_SOC_DAPM_POST_PMD:
  1307. if (wcd9378->update_wcd_event)
  1308. wcd9378->update_wcd_event(wcd9378->handle,
  1309. SLV_BOLERO_EVT_RX_MUTE,
  1310. (WCD_RX2 << 0x10 | 0x1));
  1311. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1312. wcd9378->update_wcd_event(wcd9378->handle,
  1313. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1314. (WCD_RX2 << 0x10));
  1315. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1316. WCD_EVENT_POST_HPHR_PA_OFF,
  1317. &wcd9378->mbhc->wcd_mbhc);
  1318. break;
  1319. default:
  1320. break;
  1321. };
  1322. return 0;
  1323. }
  1324. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1325. struct snd_kcontrol *kcontrol,
  1326. int event)
  1327. {
  1328. struct snd_soc_component *component =
  1329. snd_soc_dapm_to_component(w->dapm);
  1330. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1331. int ret = 0;
  1332. int bank = 0;
  1333. int act_ps = 0;
  1334. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1335. w->name, event);
  1336. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1337. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1338. switch (event) {
  1339. case SND_SOC_DAPM_PRE_PMU:
  1340. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1341. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1342. wcd9378->rx_swr_dev->dev_num,
  1343. true);
  1344. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1345. wcd9378->aux_rx_path =
  1346. (snd_soc_component_read(
  1347. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1348. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK) >> 0x03;
  1349. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1350. if (wcd9378->update_wcd_event)
  1351. wcd9378->update_wcd_event(wcd9378->handle,
  1352. SLV_BOLERO_EVT_RX_MUTE,
  1353. (WCD_RX2 << 0x10));
  1354. } else {
  1355. if (wcd9378->update_wcd_event)
  1356. wcd9378->update_wcd_event(wcd9378->handle,
  1357. SLV_BOLERO_EVT_RX_MUTE,
  1358. (WCD_RX3 << 0x10));
  1359. }
  1360. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1361. if (act_ps)
  1362. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1363. __func__, act_ps);
  1364. else
  1365. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1366. __func__, act_ps);
  1367. break;
  1368. case SND_SOC_DAPM_POST_PMD:
  1369. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1370. if (wcd9378->update_wcd_event)
  1371. wcd9378->update_wcd_event(wcd9378->handle,
  1372. SLV_BOLERO_EVT_RX_MUTE,
  1373. (WCD_RX2 << 0x10 | 0x1));
  1374. } else {
  1375. if (wcd9378->update_wcd_event)
  1376. wcd9378->update_wcd_event(wcd9378->handle,
  1377. SLV_BOLERO_EVT_RX_MUTE,
  1378. (WCD_RX3 << 0x10 | 0x1));
  1379. }
  1380. break;
  1381. };
  1382. return ret;
  1383. }
  1384. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1385. struct snd_kcontrol *kcontrol,
  1386. int event)
  1387. {
  1388. struct snd_soc_component *component =
  1389. snd_soc_dapm_to_component(w->dapm);
  1390. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1391. int ret = 0, bank = 0;
  1392. int act_ps = 0;
  1393. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1394. w->name, event);
  1395. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1396. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1397. switch (event) {
  1398. case SND_SOC_DAPM_PRE_PMU:
  1399. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1400. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1401. wcd9378->rx_swr_dev->dev_num,
  1402. true);
  1403. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1404. wcd9378->ear_rx_path =
  1405. (snd_soc_component_read(
  1406. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1407. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK) >> 0x02;
  1408. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1409. if (wcd9378->update_wcd_event)
  1410. wcd9378->update_wcd_event(wcd9378->handle,
  1411. SLV_BOLERO_EVT_RX_MUTE,
  1412. (WCD_RX1 << 0x10));
  1413. } else {
  1414. if (wcd9378->update_wcd_event)
  1415. wcd9378->update_wcd_event(wcd9378->handle,
  1416. SLV_BOLERO_EVT_RX_MUTE,
  1417. (WCD_RX3 << 0x10));
  1418. }
  1419. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1420. if (act_ps)
  1421. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1422. __func__, act_ps);
  1423. else
  1424. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1425. __func__, act_ps);
  1426. break;
  1427. case SND_SOC_DAPM_POST_PMD:
  1428. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1429. if (wcd9378->update_wcd_event)
  1430. wcd9378->update_wcd_event(wcd9378->handle,
  1431. SLV_BOLERO_EVT_RX_MUTE,
  1432. (WCD_RX1 << 0x10 | 0x1));
  1433. } else {
  1434. if (wcd9378->update_wcd_event)
  1435. wcd9378->update_wcd_event(wcd9378->handle,
  1436. SLV_BOLERO_EVT_RX_MUTE,
  1437. (WCD_RX3 << 0x10 | 0x1));
  1438. }
  1439. break;
  1440. };
  1441. return ret;
  1442. }
  1443. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1444. {
  1445. switch (hph_mode) {
  1446. case CLS_H_LOHIFI:
  1447. case CLS_AB_LOHIFI:
  1448. return PWR_LEVEL_LOHIFI_VAL;
  1449. case CLS_H_LP:
  1450. case CLS_AB_LP:
  1451. return PWR_LEVEL_LP_VAL;
  1452. case CLS_H_HIFI:
  1453. case CLS_AB_HIFI:
  1454. return PWR_LEVEL_HIFI_VAL;
  1455. case CLS_H_ULP:
  1456. case CLS_AB:
  1457. case CLS_H_NORMAL:
  1458. default:
  1459. return PWR_LEVEL_ULP_VAL;
  1460. }
  1461. return PWR_LEVEL_ULP_VAL;
  1462. }
  1463. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1464. {
  1465. struct wcd9378_priv *wcd9378 =
  1466. snd_soc_component_get_drvdata(component);
  1467. if ((!wcd9378->comp1_enable) &&
  1468. (!wcd9378->comp2_enable)) {
  1469. dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
  1470. snd_soc_component_update_bits(component,
  1471. (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
  1472. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1473. wcd9378->hph_gain >> 8);
  1474. snd_soc_component_update_bits(component,
  1475. WCD9378_FU42_CH_VOL_CH1,
  1476. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1477. wcd9378->hph_gain & 0x00ff);
  1478. snd_soc_component_update_bits(component,
  1479. (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
  1480. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1481. wcd9378->hph_gain >> 8);
  1482. snd_soc_component_update_bits(component,
  1483. WCD9378_FU42_CH_VOL_CH2,
  1484. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1485. wcd9378->hph_gain & 0x00ff);
  1486. }
  1487. }
  1488. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
  1489. {
  1490. u16 clk_scale_reg = 0;
  1491. u8 clk_rst = 0x00, scale_rst = 0x00;
  1492. u8 swr_base_clk = 0, swr_clk_scale = 0;
  1493. struct wcd9378_priv *wcd9378 = NULL;
  1494. struct swr_device *swr_dev = NULL;
  1495. wcd9378 = dev_get_drvdata(dev);
  1496. if (!wcd9378)
  1497. return -EINVAL;
  1498. if (path == RX_PATH) {
  1499. swr_dev = wcd9378->rx_swr_dev;
  1500. swr_base_clk = wcd9378->swr_base_clk;
  1501. swr_clk_scale = wcd9378->swr_clk_scale;
  1502. } else {
  1503. swr_dev = wcd9378->tx_swr_dev;
  1504. swr_base_clk = SWR_BASECLK_19P2MHZ;
  1505. swr_clk_scale = SWR_CLKSCALE_DIV2;
  1506. }
  1507. clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  1508. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  1509. if (enable) {
  1510. swr_write(swr_dev, swr_dev->dev_num,
  1511. SWRS_SCP_BASE_CLK_BASE, &swr_base_clk);
  1512. swr_write(swr_dev, swr_dev->dev_num,
  1513. clk_scale_reg, &swr_clk_scale);
  1514. } else {
  1515. swr_write(swr_dev, swr_dev->dev_num,
  1516. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  1517. swr_write(swr_dev, swr_dev->dev_num,
  1518. clk_scale_reg, &scale_rst);
  1519. }
  1520. return 0;
  1521. }
  1522. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1523. struct snd_kcontrol *kcontrol, int event)
  1524. {
  1525. struct snd_soc_component *component =
  1526. snd_soc_dapm_to_component(w->dapm);
  1527. struct wcd9378_priv *wcd9378 =
  1528. snd_soc_component_get_drvdata(component);
  1529. int power_level;
  1530. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1531. u8 scp_commit_val = 0x2;
  1532. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1533. w->name, event);
  1534. switch (event) {
  1535. case SND_SOC_DAPM_PRE_PMU:
  1536. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1537. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1538. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1539. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1540. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1541. }
  1542. if ((wcd9378->hph_mode == CLS_AB) ||
  1543. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1544. (wcd9378->hph_mode == CLS_AB_LP) ||
  1545. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1546. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1547. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1548. /*GET HPH_MODE*/
  1549. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1550. /*SET HPH_MODE*/
  1551. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1552. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1553. /*TURN ON HPH SEQUENCER*/
  1554. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1555. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1556. /*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
  1557. wcd9378_hph_set_channel_volume(component);
  1558. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1559. /*PA delay is 22400us*/
  1560. usleep_range(22500, 22510);
  1561. else
  1562. /*COMP delay is 9400us*/
  1563. usleep_range(9500, 9510);
  1564. /*RX0 unmute*/
  1565. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1566. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
  1567. /*RX1 unmute*/
  1568. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1569. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
  1570. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
  1571. break;
  1572. case SND_SOC_DAPM_POST_PMD:
  1573. /*RX0 mute*/
  1574. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1575. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
  1576. /*RX1 mute*/
  1577. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1578. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
  1579. /*TEAR DOWN HPH SEQUENCER*/
  1580. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1581. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1582. if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
  1583. /*PA delay is 24250us*/
  1584. usleep_range(24300, 24310);
  1585. else
  1586. /*COMP delay is 11250us*/
  1587. usleep_range(11300, 11310);
  1588. break;
  1589. default:
  1590. break;
  1591. };
  1592. return 0;
  1593. }
  1594. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1595. struct snd_kcontrol *kcontrol,
  1596. int event)
  1597. {
  1598. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1599. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1600. int ear_rx0 = 0;
  1601. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1602. w->name, event);
  1603. ear_rx0 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1604. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK;
  1605. switch (event) {
  1606. case SND_SOC_DAPM_PRE_PMU:
  1607. /*CHECK IF EAR CONNET TO RX2*/
  1608. if (!ear_rx0) {
  1609. pr_debug("%s: ear rx2 enter\n", __func__);
  1610. /*FORCE CLASS_AB EN*/
  1611. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1612. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1613. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1614. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1615. /*RX2 ENABLE*/
  1616. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1617. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1618. if (wcd9378->rx2_clk_mode)
  1619. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1620. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1621. wcd9378_rx_connect_port(component, LO, true);
  1622. } else {
  1623. pr_debug("%s: ear rx0 enter\n", __func__);
  1624. if (wcd9378->comp1_enable) {
  1625. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1626. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1627. wcd9378_rx_connect_port(component, COMP_L, true);
  1628. }
  1629. wcd9378_rx_connect_port(component, HPH_L, true);
  1630. }
  1631. break;
  1632. case SND_SOC_DAPM_POST_PMD:
  1633. if (ear_rx0) {
  1634. /*RX0 DISABLE*/
  1635. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1636. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1637. wcd9378_rx_connect_port(component, HPH_L, false);
  1638. if (wcd9378->comp1_enable) {
  1639. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1640. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1641. wcd9378_rx_connect_port(component, COMP_L, false);
  1642. }
  1643. } else {
  1644. /*RX1 DISABLE*/
  1645. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1646. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1647. wcd9378_rx_connect_port(component, LO, false);
  1648. }
  1649. break;
  1650. };
  1651. return 0;
  1652. }
  1653. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1654. struct snd_kcontrol *kcontrol,
  1655. int event)
  1656. {
  1657. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1658. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1659. int aux_rx1 = 0;
  1660. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1661. w->name, event);
  1662. aux_rx1 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1663. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK;
  1664. switch (event) {
  1665. case SND_SOC_DAPM_PRE_PMU:
  1666. if (aux_rx1) {
  1667. wcd9378_rx_connect_port(component, HPH_R, true);
  1668. } else {
  1669. /*RX2 ENABLE*/
  1670. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1671. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1672. if (wcd9378->rx2_clk_mode)
  1673. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1674. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1675. wcd9378_rx_connect_port(component, LO, true);
  1676. }
  1677. break;
  1678. case SND_SOC_DAPM_POST_PMD:
  1679. if (aux_rx1) {
  1680. wcd9378_rx_connect_port(component, HPH_R, false);
  1681. } else {
  1682. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1683. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1684. wcd9378_rx_connect_port(component, LO, false);
  1685. }
  1686. break;
  1687. };
  1688. return 0;
  1689. }
  1690. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1691. struct snd_kcontrol *kcontrol, int event)
  1692. {
  1693. struct snd_soc_component *component =
  1694. snd_soc_dapm_to_component(w->dapm);
  1695. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1696. w->name, event);
  1697. switch (event) {
  1698. case SND_SOC_DAPM_PRE_PMU:
  1699. /*TURN ON AMP SEQUENCER*/
  1700. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1701. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1702. /*default delay 8550us*/
  1703. usleep_range(8600, 8610);
  1704. /*FU23 UNMUTE*/
  1705. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1706. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1707. break;
  1708. case SND_SOC_DAPM_POST_PMD:
  1709. /*FU23 MUTE*/
  1710. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1711. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1712. /*TEAR DOWN AMP SEQUENCER*/
  1713. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1714. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1715. /*default delay 1530us*/
  1716. usleep_range(15400, 15410);
  1717. break;
  1718. default:
  1719. break;
  1720. };
  1721. return 0;
  1722. }
  1723. int wcd9378_micbias_control(struct snd_soc_component *component,
  1724. unsigned char tx_path, int req, bool is_dapm)
  1725. {
  1726. struct wcd9378_priv *wcd9378 =
  1727. snd_soc_component_get_drvdata(component);
  1728. struct wcd9378_pdata *pdata =
  1729. dev_get_platdata(wcd9378->dev);
  1730. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1731. int micb_num = 0, micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1732. int pre_off_event = 0, post_off_event = 0;
  1733. int post_on_event = 0, post_dapm_off = 0;
  1734. int post_dapm_on = 0;
  1735. int pull_up_mask = 0, pull_up_en = 0;
  1736. int micb_index = 0, ret = 0;
  1737. switch (tx_path) {
  1738. case ADC1:
  1739. micb_num = wcd9378->micb_sel[0];
  1740. micb_usage = WCD9378_IT11_MICB;
  1741. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1742. break;
  1743. case ADC2:
  1744. if (wcd9378->sjmic_support) {
  1745. micb_num = MIC_BIAS_2;
  1746. micb_usage = WCD9378_IT31_MICB;
  1747. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  1748. } else {
  1749. micb_num = wcd9378->micb_sel[1];
  1750. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1751. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1752. }
  1753. break;
  1754. case ADC3:
  1755. micb_num = wcd9378->micb_sel[2];
  1756. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1757. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1758. break;
  1759. default:
  1760. pr_err("%s: unsupport tx path\n", __func__);
  1761. return -EINVAL;
  1762. }
  1763. switch (micb_num) {
  1764. case MIC_BIAS_1:
  1765. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1766. pull_up_en = 0x01;
  1767. micb_usage_val = mb->micb1_usage_val;
  1768. break;
  1769. case MIC_BIAS_2:
  1770. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1771. pull_up_en = 0x02;
  1772. micb_usage_val = mb->micb2_usage_val;
  1773. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1774. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1775. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1776. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1777. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1778. break;
  1779. case MIC_BIAS_3:
  1780. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1781. pull_up_en = 0x04;
  1782. micb_usage_val = mb->micb3_usage_val;
  1783. break;
  1784. default:
  1785. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1786. __func__, micb_num);
  1787. return -EINVAL;
  1788. }
  1789. mutex_lock(&wcd9378->micb_lock);
  1790. micb_index = micb_num - 1;
  1791. switch (req) {
  1792. case MICB_PULLUP_ENABLE:
  1793. if (!wcd9378->dev_up) {
  1794. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1795. __func__, req);
  1796. ret = -ENODEV;
  1797. goto done;
  1798. }
  1799. wcd9378->pullup_ref[micb_index]++;
  1800. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1801. (wcd9378->micb_ref[micb_index] == 0)) {
  1802. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1803. pull_up_mask, pull_up_en);
  1804. snd_soc_component_update_bits(component,
  1805. micb_usage, micb_mask, 0x03);
  1806. }
  1807. break;
  1808. case MICB_PULLUP_DISABLE:
  1809. if (wcd9378->pullup_ref[micb_index] > 0)
  1810. wcd9378->pullup_ref[micb_index]--;
  1811. if (!wcd9378->dev_up) {
  1812. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1813. __func__, req);
  1814. ret = -ENODEV;
  1815. goto done;
  1816. }
  1817. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  1818. (wcd9378->micb_ref[micb_index] == 0))
  1819. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  1820. break;
  1821. case MICB_ENABLE:
  1822. dev_dbg(component->dev, "%s: micbias enable enter\n",
  1823. __func__);
  1824. if (!wcd9378->dev_up) {
  1825. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1826. __func__, req);
  1827. ret = -ENODEV;
  1828. goto done;
  1829. }
  1830. wcd9378->micb_ref[micb_index]++;
  1831. if (wcd9378->micb_ref[micb_index] == 1) {
  1832. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  1833. __func__, micb_usage, micb_usage_val);
  1834. snd_soc_component_update_bits(component,
  1835. micb_usage, micb_mask, micb_usage_val);
  1836. if (post_on_event)
  1837. blocking_notifier_call_chain(
  1838. &wcd9378->mbhc->notifier,
  1839. post_on_event,
  1840. &wcd9378->mbhc->wcd_mbhc);
  1841. }
  1842. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  1843. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1844. post_dapm_on,
  1845. &wcd9378->mbhc->wcd_mbhc);
  1846. break;
  1847. case MICB_DISABLE:
  1848. if (wcd9378->micb_ref[micb_index] > 0)
  1849. wcd9378->micb_ref[micb_index]--;
  1850. if ((wcd9378->micb_ref[micb_index] == 0) &&
  1851. (wcd9378->pullup_ref[micb_index] > 0)) {
  1852. /*PULL UP?*/
  1853. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1854. pull_up_mask, pull_up_en);
  1855. snd_soc_component_update_bits(component, micb_usage,
  1856. micb_mask, 0x03);
  1857. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  1858. (wcd9378->pullup_ref[micb_index] == 0)) {
  1859. if (pre_off_event && wcd9378->mbhc)
  1860. blocking_notifier_call_chain(
  1861. &wcd9378->mbhc->notifier,
  1862. pre_off_event,
  1863. &wcd9378->mbhc->wcd_mbhc);
  1864. snd_soc_component_update_bits(component, micb_usage,
  1865. micb_mask, 0x00);
  1866. if (post_off_event && wcd9378->mbhc)
  1867. blocking_notifier_call_chain(
  1868. &wcd9378->mbhc->notifier,
  1869. post_off_event,
  1870. &wcd9378->mbhc->wcd_mbhc);
  1871. }
  1872. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  1873. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1874. post_dapm_off,
  1875. &wcd9378->mbhc->wcd_mbhc);
  1876. break;
  1877. default:
  1878. dev_err(component->dev, "%s: Invalid req event: %d\n",
  1879. __func__, req);
  1880. return -EINVAL;
  1881. }
  1882. dev_dbg(component->dev,
  1883. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1884. __func__, micb_num, wcd9378->micb_ref[micb_index],
  1885. wcd9378->pullup_ref[micb_index]);
  1886. done:
  1887. mutex_unlock(&wcd9378->micb_lock);
  1888. return ret;
  1889. }
  1890. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  1891. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  1892. {
  1893. int ret = 0;
  1894. uint8_t devnum = 0;
  1895. int num_retry = NUM_ATTEMPTS;
  1896. do {
  1897. /* retry after 4ms */
  1898. usleep_range(4000, 4010);
  1899. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1900. } while (ret && --num_retry);
  1901. if (ret)
  1902. dev_err(&swr_dev->dev,
  1903. "%s get devnum %d for dev addr %llx failed\n",
  1904. __func__, devnum, swr_dev->addr);
  1905. swr_dev->dev_num = devnum;
  1906. return 0;
  1907. }
  1908. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1909. struct wcd_mbhc_config *mbhc_cfg)
  1910. {
  1911. if (mbhc_cfg->enable_usbc_analog) {
  1912. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  1913. & 0x20))
  1914. return true;
  1915. }
  1916. return false;
  1917. }
  1918. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  1919. struct notifier_block *nblock,
  1920. bool enable)
  1921. {
  1922. struct wcd9378_priv *wcd9378_priv = NULL;
  1923. if (component == NULL) {
  1924. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  1925. return -EINVAL;
  1926. }
  1927. wcd9378_priv = snd_soc_component_get_drvdata(component);
  1928. wcd9378_priv->notify_swr_dmic = enable;
  1929. if (enable)
  1930. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  1931. nblock);
  1932. else
  1933. return blocking_notifier_chain_unregister(
  1934. &wcd9378_priv->notifier, nblock);
  1935. }
  1936. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  1937. static int wcd9378_event_notify(struct notifier_block *block,
  1938. unsigned long val,
  1939. void *data)
  1940. {
  1941. u16 event = (val & 0xffff);
  1942. int ret = 0;
  1943. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  1944. struct snd_soc_component *component = wcd9378->component;
  1945. struct wcd_mbhc *mbhc;
  1946. int rx_clk_type;
  1947. switch (event) {
  1948. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1949. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  1950. snd_soc_component_update_bits(component,
  1951. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  1952. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  1953. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  1954. }
  1955. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  1956. snd_soc_component_update_bits(component,
  1957. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  1958. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  1959. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  1960. }
  1961. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  1962. snd_soc_component_update_bits(component,
  1963. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  1964. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  1965. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  1966. }
  1967. break;
  1968. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1969. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  1970. 0xC0, 0x00);
  1971. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1972. 0x80, 0x00);
  1973. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1974. 0x80, 0x00);
  1975. break;
  1976. case BOLERO_SLV_EVT_SSR_DOWN:
  1977. wcd9378->dev_up = false;
  1978. if (wcd9378->notify_swr_dmic)
  1979. blocking_notifier_call_chain(&wcd9378->notifier,
  1980. WCD9378_EVT_SSR_DOWN,
  1981. NULL);
  1982. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  1983. mbhc = &wcd9378->mbhc->wcd_mbhc;
  1984. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  1985. mbhc->mbhc_cfg);
  1986. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  1987. wcd9378_reset_low(wcd9378->dev);
  1988. break;
  1989. case BOLERO_SLV_EVT_SSR_UP:
  1990. wcd9378_reset(wcd9378->dev);
  1991. /* allow reset to take effect */
  1992. usleep_range(10000, 10010);
  1993. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  1994. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  1995. wcd9378->tx_swr_dev->scp1_val = 0;
  1996. wcd9378->tx_swr_dev->scp2_val = 0;
  1997. wcd9378->rx_swr_dev->scp1_val = 0;
  1998. wcd9378->rx_swr_dev->scp2_val = 0;
  1999. wcd9378_init_reg(component);
  2000. regcache_mark_dirty(wcd9378->regmap);
  2001. regcache_sync(wcd9378->regmap);
  2002. /* Initialize MBHC module */
  2003. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2004. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  2005. if (ret) {
  2006. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2007. __func__);
  2008. } else {
  2009. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2010. }
  2011. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  2012. wcd9378->dev_up = true;
  2013. if (wcd9378->notify_swr_dmic)
  2014. blocking_notifier_call_chain(&wcd9378->notifier,
  2015. WCD9378_EVT_SSR_UP,
  2016. NULL);
  2017. if (wcd9378->usbc_hs_status)
  2018. mdelay(500);
  2019. break;
  2020. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2021. snd_soc_component_update_bits(component,
  2022. WCD9378_TOP_CLK_CFG, 0x06,
  2023. ((val >> 0x10) << 0x01));
  2024. rx_clk_type = (val >> 0x10);
  2025. switch (rx_clk_type) {
  2026. case RX_CLK_12P288MHZ:
  2027. wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
  2028. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2029. break;
  2030. case RX_CLK_11P2896MHZ:
  2031. wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
  2032. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2033. break;
  2034. default:
  2035. wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
  2036. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2037. break;
  2038. }
  2039. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2040. __func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
  2041. break;
  2042. default:
  2043. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2044. break;
  2045. }
  2046. return 0;
  2047. }
  2048. static int wcd9378_wakeup(void *handle, bool enable)
  2049. {
  2050. struct wcd9378_priv *priv;
  2051. int ret = 0;
  2052. if (!handle) {
  2053. pr_err("%s: NULL handle\n", __func__);
  2054. return -EINVAL;
  2055. }
  2056. priv = (struct wcd9378_priv *)handle;
  2057. if (!priv->tx_swr_dev) {
  2058. pr_err("%s: tx swr dev is NULL\n", __func__);
  2059. return -EINVAL;
  2060. }
  2061. mutex_lock(&priv->wakeup_lock);
  2062. if (enable)
  2063. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2064. else
  2065. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2066. mutex_unlock(&priv->wakeup_lock);
  2067. return ret;
  2068. }
  2069. static inline int wcd9378_tx_path_get(const char *wname,
  2070. unsigned int *path_num)
  2071. {
  2072. int ret = 0;
  2073. char *widget_name = NULL;
  2074. char *w_name = NULL;
  2075. char *path_num_char = NULL;
  2076. char *path_name = NULL;
  2077. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2078. if (!widget_name)
  2079. return -EINVAL;
  2080. w_name = widget_name;
  2081. path_name = strsep(&widget_name, " ");
  2082. if (!path_name) {
  2083. pr_err("%s: Invalid widget name = %s\n",
  2084. __func__, widget_name);
  2085. ret = -EINVAL;
  2086. goto err;
  2087. }
  2088. path_num_char = strpbrk(path_name, "0123");
  2089. if (!path_num_char) {
  2090. pr_err("%s: tx path index not found\n",
  2091. __func__);
  2092. ret = -EINVAL;
  2093. goto err;
  2094. }
  2095. ret = kstrtouint(path_num_char, 10, path_num);
  2096. if (ret < 0)
  2097. pr_err("%s: Invalid tx path = %s\n",
  2098. __func__, w_name);
  2099. err:
  2100. kfree(w_name);
  2101. return ret;
  2102. }
  2103. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2104. struct snd_ctl_elem_value *ucontrol)
  2105. {
  2106. struct snd_soc_component *component =
  2107. snd_soc_kcontrol_component(kcontrol);
  2108. struct wcd9378_priv *wcd9378 = NULL;
  2109. int ret = 0;
  2110. unsigned int path = 0;
  2111. if (!component)
  2112. return -EINVAL;
  2113. wcd9378 = snd_soc_component_get_drvdata(component);
  2114. if (!wcd9378)
  2115. return -EINVAL;
  2116. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2117. if (ret < 0)
  2118. return ret;
  2119. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2120. return 0;
  2121. }
  2122. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2123. struct snd_ctl_elem_value *ucontrol)
  2124. {
  2125. struct snd_soc_component *component =
  2126. snd_soc_kcontrol_component(kcontrol);
  2127. struct wcd9378_priv *wcd9378 = NULL;
  2128. u32 mode_val;
  2129. unsigned int path = 0;
  2130. int ret = 0;
  2131. if (!component)
  2132. return -EINVAL;
  2133. wcd9378 = snd_soc_component_get_drvdata(component);
  2134. if (!wcd9378)
  2135. return -EINVAL;
  2136. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2137. if (ret)
  2138. return ret;
  2139. mode_val = ucontrol->value.enumerated.item[0];
  2140. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2141. wcd9378->tx_mode[path] = mode_val;
  2142. return 0;
  2143. }
  2144. static int wcd9378_sys_usage_get(struct snd_kcontrol *kcontrol,
  2145. struct snd_ctl_elem_value *ucontrol)
  2146. {
  2147. struct snd_soc_component *component =
  2148. snd_soc_kcontrol_component(kcontrol);
  2149. u32 sys_usage_val = 0;
  2150. if (!component)
  2151. return -EINVAL;
  2152. sys_usage_val = (snd_soc_component_read(component, WCD9378_SYS_USAGE_CTRL) &
  2153. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK);
  2154. ucontrol->value.integer.value[0] = sys_usage_val;
  2155. return 0;
  2156. }
  2157. static int wcd9378_sys_usage_put(struct snd_kcontrol *kcontrol,
  2158. struct snd_ctl_elem_value *ucontrol)
  2159. {
  2160. struct snd_soc_component *component =
  2161. snd_soc_kcontrol_component(kcontrol);
  2162. struct wcd9378_priv *wcd9378 = NULL;
  2163. u32 sys_usage_val = 0;
  2164. if (!component)
  2165. return -EINVAL;
  2166. wcd9378 = snd_soc_component_get_drvdata(component);
  2167. if (!wcd9378)
  2168. return -EINVAL;
  2169. sys_usage_val = ucontrol->value.enumerated.item[0];
  2170. if (sys_usage_val >= WCD_SYS_USAGE_MAX) {
  2171. dev_err(component->dev, "%s: unsupport sys_usage_val: %d\n",
  2172. __func__, sys_usage_val);
  2173. return -EINVAL;
  2174. }
  2175. if (wcd9378->sys_usage != sys_usage_val)
  2176. snd_soc_component_update_bits(component,
  2177. WCD9378_SYS_USAGE_CTRL,
  2178. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  2179. sys_usage_val);
  2180. wcd9378->sys_usage = sys_usage_val;
  2181. switch (wcd9378->sys_usage) {
  2182. case SJ_SA_AUX_2SM:
  2183. case SJ_SA_AUX_2SM_1HDR:
  2184. case SJ_SA_EAR_2SM:
  2185. case SJ_SA_EAR_2SM_1HDR:
  2186. case SJ_1HDR_SA_AUX_1SM:
  2187. case SJ_1HDR_SA_EAR_1SM:
  2188. wcd9378->sjmic_support = true;
  2189. break;
  2190. case NOSJ_SA_STEREO_3SM:
  2191. case NOSJ_SA_STEREO_3SM_1HDR:
  2192. case NOSJ_SA_EAR_3SM:
  2193. case NOSJ_SA_EAR_3SM_1HDR:
  2194. case SJ_NOMIC_SA_EAR_3SM:
  2195. case SJ_NOMIC_SA_AUX_3SM:
  2196. wcd9378->sjmic_support = false;
  2197. break;
  2198. default:
  2199. dev_err(component->dev, "%s: unsupport sys_usage: %d\n",
  2200. __func__, wcd9378->sys_usage);
  2201. return -EINVAL;
  2202. }
  2203. dev_err(component->dev, "%s: sys_usage_val: %d, sjmic_support: %d\n",
  2204. __func__, wcd9378->sys_usage, wcd9378->sjmic_support);
  2205. return 0;
  2206. }
  2207. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2208. struct snd_ctl_elem_value *ucontrol)
  2209. {
  2210. struct snd_soc_component *component =
  2211. snd_soc_kcontrol_component(kcontrol);
  2212. u32 loopback_mode = 0;
  2213. if (!component)
  2214. return -EINVAL;
  2215. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2216. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2217. ucontrol->value.integer.value[0] = loopback_mode;
  2218. return 0;
  2219. }
  2220. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2221. struct snd_ctl_elem_value *ucontrol)
  2222. {
  2223. struct snd_soc_component *component =
  2224. snd_soc_kcontrol_component(kcontrol);
  2225. u32 loopback_mode = 0;
  2226. if (!component)
  2227. return -EINVAL;
  2228. loopback_mode = ucontrol->value.enumerated.item[0];
  2229. snd_soc_component_update_bits(component,
  2230. WCD9378_LOOP_BACK_MODE,
  2231. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2232. loopback_mode);
  2233. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2234. __func__, loopback_mode);
  2235. return 0;
  2236. }
  2237. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2238. struct snd_ctl_elem_value *ucontrol)
  2239. {
  2240. struct snd_soc_component *component =
  2241. snd_soc_kcontrol_component(kcontrol);
  2242. u32 aux_dsm_in = 0;
  2243. if (!component)
  2244. return -EINVAL;
  2245. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2246. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2247. ucontrol->value.integer.value[0] = aux_dsm_in;
  2248. return 0;
  2249. }
  2250. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2251. struct snd_ctl_elem_value *ucontrol)
  2252. {
  2253. struct snd_soc_component *component =
  2254. snd_soc_kcontrol_component(kcontrol);
  2255. u32 aux_dsm_in = 0;
  2256. if (!component)
  2257. return -EINVAL;
  2258. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2259. snd_soc_component_update_bits(component,
  2260. WCD9378_LB_IN_SEL_CTL,
  2261. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2262. aux_dsm_in);
  2263. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2264. __func__, aux_dsm_in);
  2265. return 0;
  2266. }
  2267. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2268. struct snd_ctl_elem_value *ucontrol)
  2269. {
  2270. struct snd_soc_component *component =
  2271. snd_soc_kcontrol_component(kcontrol);
  2272. u32 hph_dsm_in = 0;
  2273. if (!component)
  2274. return -EINVAL;
  2275. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2276. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2277. ucontrol->value.integer.value[0] = hph_dsm_in;
  2278. return 0;
  2279. }
  2280. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2281. struct snd_ctl_elem_value *ucontrol)
  2282. {
  2283. struct snd_soc_component *component =
  2284. snd_soc_kcontrol_component(kcontrol);
  2285. u32 hph_dsm_in = 0;
  2286. if (!component)
  2287. return -EINVAL;
  2288. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2289. snd_soc_component_update_bits(component,
  2290. WCD9378_LB_IN_SEL_CTL,
  2291. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2292. hph_dsm_in);
  2293. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2294. __func__, hph_dsm_in);
  2295. return 0;
  2296. }
  2297. static inline int wcd9378_simple_mic_num_get(const char *wname,
  2298. unsigned int *sm_num)
  2299. {
  2300. int ret = 0;
  2301. char *widget_name = NULL;
  2302. char *w_name = NULL;
  2303. char *sm_num_char = NULL;
  2304. char *sm_name = NULL;
  2305. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2306. if (!widget_name)
  2307. return -EINVAL;
  2308. w_name = widget_name;
  2309. sm_name = strsep(&widget_name, " ");
  2310. if (!sm_name) {
  2311. pr_err("%s: Invalid widget name = %s\n",
  2312. __func__, widget_name);
  2313. ret = -EINVAL;
  2314. goto err;
  2315. }
  2316. sm_num_char = strpbrk(sm_name, "0123");
  2317. if (!sm_num_char) {
  2318. pr_err("%s: simple mic index not found\n",
  2319. __func__);
  2320. ret = -EINVAL;
  2321. goto err;
  2322. }
  2323. ret = kstrtouint(sm_num_char, 10, sm_num);
  2324. if (ret < 0)
  2325. pr_err("%s: Invalid micb num = %s\n",
  2326. __func__, w_name);
  2327. err:
  2328. kfree(w_name);
  2329. return ret;
  2330. }
  2331. static int wcd9378_mb_sel_get(struct snd_kcontrol *kcontrol,
  2332. struct snd_ctl_elem_value *ucontrol)
  2333. {
  2334. struct snd_soc_component *component =
  2335. snd_soc_kcontrol_component(kcontrol);
  2336. struct wcd9378_priv *wcd9378 = NULL;
  2337. int ret = 0;
  2338. unsigned int sm_num = 0;
  2339. if (!component)
  2340. return -EINVAL;
  2341. wcd9378 = snd_soc_component_get_drvdata(component);
  2342. if (!wcd9378)
  2343. return -EINVAL;
  2344. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2345. if (ret < 0)
  2346. return ret;
  2347. ucontrol->value.integer.value[0] = wcd9378->micb_sel[sm_num];
  2348. return 0;
  2349. }
  2350. static int wcd9378_mb_sel_put(struct snd_kcontrol *kcontrol,
  2351. struct snd_ctl_elem_value *ucontrol)
  2352. {
  2353. struct snd_soc_component *component =
  2354. snd_soc_kcontrol_component(kcontrol);
  2355. struct wcd9378_priv *wcd9378 = NULL;
  2356. u32 micb_num = 0, sm_sel = 0, sm_sel_mask = 0;
  2357. unsigned int sm_num = 0;
  2358. int ret = 0;
  2359. if (!component)
  2360. return -EINVAL;
  2361. wcd9378 = snd_soc_component_get_drvdata(component);
  2362. if (!wcd9378)
  2363. return -EINVAL;
  2364. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2365. if (ret)
  2366. return ret;
  2367. switch (sm_num) {
  2368. case SIM_MIC0:
  2369. sm_sel = WCD9378_SM0_MB_SEL;
  2370. sm_sel_mask = WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK;
  2371. break;
  2372. case SIM_MIC1:
  2373. sm_sel = WCD9378_SM1_MB_SEL;
  2374. sm_sel_mask = WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK;
  2375. break;
  2376. case SIM_MIC2:
  2377. sm_sel = WCD9378_SM2_MB_SEL;
  2378. sm_sel_mask = WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK;
  2379. break;
  2380. default:
  2381. pr_err("%s: unsupport sm_num: %d\n", __func__, sm_num);
  2382. return -EINVAL;
  2383. }
  2384. micb_num = ucontrol->value.enumerated.item[0];
  2385. if (micb_num >= MICB_NUM) {
  2386. pr_err("%s: unsupport micb num\n", __func__);
  2387. return -EINVAL;
  2388. }
  2389. snd_soc_component_update_bits(component, sm_sel,
  2390. sm_sel_mask, micb_num);
  2391. wcd9378->micb_sel[sm_num] = micb_num;
  2392. dev_err(component->dev, "%s: sm%d_mb_sel :%d\n",
  2393. __func__, sm_num, micb_num);
  2394. return 0;
  2395. }
  2396. /*TBD: NEED CHECK THE LOGIC*/
  2397. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2398. struct snd_ctl_elem_value *ucontrol)
  2399. {
  2400. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2401. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2402. u16 offset = ucontrol->value.enumerated.item[0];
  2403. u32 temp = 0;
  2404. temp = 0x00 - offset * 0x180;
  2405. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2406. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2407. return 0;
  2408. }
  2409. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2410. struct snd_ctl_elem_value *ucontrol)
  2411. {
  2412. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2413. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2414. u32 temp = 0;
  2415. u16 offset = 0;
  2416. temp = 0 - wcd9378->hph_gain;
  2417. offset = (u16)(temp & 0xffff);
  2418. offset /= 0x180;
  2419. ucontrol->value.enumerated.item[0] = offset;
  2420. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2421. return 0;
  2422. }
  2423. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2424. struct snd_ctl_elem_value *ucontrol)
  2425. {
  2426. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2427. struct wcd9378_priv *wcd9378 =
  2428. snd_soc_component_get_drvdata(component);
  2429. if (ucontrol->value.enumerated.item[0])
  2430. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2431. else
  2432. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2433. return 1;
  2434. }
  2435. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2436. struct snd_ctl_elem_value *ucontrol)
  2437. {
  2438. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2439. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2440. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2441. return 0;
  2442. }
  2443. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2444. struct snd_ctl_elem_value *ucontrol)
  2445. {
  2446. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2447. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2448. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2449. return 0;
  2450. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2451. return 1;
  2452. }
  2453. /* wcd9378_codec_get_dev_num - returns swr device number
  2454. * @component: Codec instance
  2455. *
  2456. * Return: swr device number on success or negative error
  2457. * code on failure.
  2458. */
  2459. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2460. {
  2461. struct wcd9378_priv *wcd9378;
  2462. if (!component)
  2463. return -EINVAL;
  2464. wcd9378 = snd_soc_component_get_drvdata(component);
  2465. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2466. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2467. return -EINVAL;
  2468. }
  2469. return wcd9378->rx_swr_dev->dev_num;
  2470. }
  2471. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2472. static int wcd9378_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
  2473. struct snd_ctl_elem_value *ucontrol)
  2474. {
  2475. struct snd_soc_component *component =
  2476. snd_soc_kcontrol_component(kcontrol);
  2477. struct wcd9378_priv *wcd9378 =
  2478. snd_soc_component_get_drvdata(component);
  2479. if (wcd9378->comp1_enable) {
  2480. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2481. return -EINVAL;
  2482. }
  2483. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2484. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2485. ucontrol->value.integer.value[0]);
  2486. return 1;
  2487. }
  2488. static int wcd9378_aux_pa_put_gain(struct snd_kcontrol *kcontrol,
  2489. struct snd_ctl_elem_value *ucontrol)
  2490. {
  2491. struct snd_soc_component *component =
  2492. snd_soc_kcontrol_component(kcontrol);
  2493. struct wcd9378_priv *wcd9378 =
  2494. snd_soc_component_get_drvdata(component);
  2495. if (wcd9378->comp1_enable) {
  2496. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2497. return -EINVAL;
  2498. }
  2499. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2500. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2501. ucontrol->value.integer.value[0]);
  2502. return 1;
  2503. }
  2504. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2505. struct snd_ctl_elem_value *ucontrol)
  2506. {
  2507. struct snd_soc_component *component =
  2508. snd_soc_kcontrol_component(kcontrol);
  2509. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2510. bool hphr;
  2511. struct soc_multi_mixer_control *mc;
  2512. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2513. hphr = mc->shift;
  2514. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2515. wcd9378->comp1_enable;
  2516. return 0;
  2517. }
  2518. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2519. struct snd_ctl_elem_value *ucontrol)
  2520. {
  2521. struct snd_soc_component *component =
  2522. snd_soc_kcontrol_component(kcontrol);
  2523. struct wcd9378_priv *wcd9378 =
  2524. snd_soc_component_get_drvdata(component);
  2525. int value = ucontrol->value.integer.value[0];
  2526. bool hphr;
  2527. struct soc_multi_mixer_control *mc;
  2528. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2529. hphr = mc->shift;
  2530. if (hphr)
  2531. wcd9378->comp2_enable = value;
  2532. else
  2533. wcd9378->comp1_enable = value;
  2534. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2535. return 0;
  2536. }
  2537. static int wcd9378_get_va_amic_switch(struct snd_kcontrol *kcontrol,
  2538. struct snd_ctl_elem_value *ucontrol)
  2539. {
  2540. struct snd_soc_component *component =
  2541. snd_soc_kcontrol_component(kcontrol);
  2542. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2543. ucontrol->value.integer.value[0] = wcd9378->va_amic_en;
  2544. return 0;
  2545. }
  2546. static int wcd9378_set_va_amic_switch(struct snd_kcontrol *kcontrol,
  2547. struct snd_ctl_elem_value *ucontrol)
  2548. {
  2549. struct snd_soc_component *component =
  2550. snd_soc_kcontrol_component(kcontrol);
  2551. struct wcd9378_priv *wcd9378 =
  2552. snd_soc_component_get_drvdata(component);
  2553. int value = ucontrol->value.integer.value[0];
  2554. wcd9378->va_amic_en = value;
  2555. return 0;
  2556. }
  2557. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2558. struct snd_kcontrol *kcontrol,
  2559. int event)
  2560. {
  2561. struct snd_soc_component *component =
  2562. snd_soc_dapm_to_component(w->dapm);
  2563. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2564. struct wcd9378_pdata *pdata = NULL;
  2565. int ret = 0;
  2566. pdata = dev_get_platdata(wcd9378->dev);
  2567. if (!pdata) {
  2568. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2569. return -EINVAL;
  2570. }
  2571. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2572. wcd9378->supplies,
  2573. pdata->regulator,
  2574. pdata->num_supplies,
  2575. "cdc-vdd-buck"))
  2576. return 0;
  2577. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2578. w->name, event);
  2579. switch (event) {
  2580. case SND_SOC_DAPM_PRE_PMU:
  2581. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2582. dev_dbg(component->dev,
  2583. "%s: buck already in enabled state\n",
  2584. __func__);
  2585. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2586. return 0;
  2587. }
  2588. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2589. wcd9378->supplies,
  2590. pdata->regulator,
  2591. pdata->num_supplies,
  2592. "cdc-vdd-buck");
  2593. if (ret == -EINVAL) {
  2594. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2595. __func__);
  2596. return ret;
  2597. }
  2598. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2599. /*
  2600. * 200us sleep is required after LDO is enabled as per
  2601. * HW requirement
  2602. */
  2603. usleep_range(200, 250);
  2604. break;
  2605. case SND_SOC_DAPM_POST_PMD:
  2606. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2607. break;
  2608. }
  2609. return 0;
  2610. }
  2611. const char * const tx_master_ch_text[] = {
  2612. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2613. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2614. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2615. "SWRM_PCM_IN",
  2616. };
  2617. const struct soc_enum tx_master_ch_enum =
  2618. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2619. tx_master_ch_text);
  2620. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2621. {
  2622. u8 ch_type = 0;
  2623. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2624. ch_type = ADC1;
  2625. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2626. ch_type = ADC2;
  2627. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2628. ch_type = ADC3;
  2629. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2630. ch_type = ADC4;
  2631. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2632. ch_type = DMIC0;
  2633. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2634. ch_type = DMIC1;
  2635. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2636. ch_type = MBHC;
  2637. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2638. ch_type = DMIC2;
  2639. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2640. ch_type = DMIC3;
  2641. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2642. ch_type = DMIC4;
  2643. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2644. ch_type = DMIC5;
  2645. else
  2646. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2647. if (ch_type)
  2648. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2649. else
  2650. *ch_idx = -EINVAL;
  2651. }
  2652. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2653. struct snd_ctl_elem_value *ucontrol)
  2654. {
  2655. struct snd_soc_component *component =
  2656. snd_soc_kcontrol_component(kcontrol);
  2657. struct wcd9378_priv *wcd9378 = NULL;
  2658. int slave_ch_idx = -EINVAL;
  2659. if (component == NULL)
  2660. return -EINVAL;
  2661. wcd9378 = snd_soc_component_get_drvdata(component);
  2662. if (wcd9378 == NULL)
  2663. return -EINVAL;
  2664. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2665. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2666. return -EINVAL;
  2667. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2668. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2669. return 0;
  2670. }
  2671. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2672. struct snd_ctl_elem_value *ucontrol)
  2673. {
  2674. struct snd_soc_component *component =
  2675. snd_soc_kcontrol_component(kcontrol);
  2676. struct wcd9378_priv *wcd9378 = NULL;
  2677. int slave_ch_idx = -EINVAL, idx = 0;
  2678. if (component == NULL)
  2679. return -EINVAL;
  2680. wcd9378 = snd_soc_component_get_drvdata(component);
  2681. if (wcd9378 == NULL)
  2682. return -EINVAL;
  2683. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2684. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2685. return -EINVAL;
  2686. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2687. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2688. __func__, ucontrol->value.enumerated.item[0]);
  2689. idx = ucontrol->value.enumerated.item[0];
  2690. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2691. return -EINVAL;
  2692. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2693. return 0;
  2694. }
  2695. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2696. struct snd_ctl_elem_value *ucontrol)
  2697. {
  2698. struct snd_soc_component *component =
  2699. snd_soc_kcontrol_component(kcontrol);
  2700. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2701. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2702. return 0;
  2703. }
  2704. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2705. struct snd_ctl_elem_value *ucontrol)
  2706. {
  2707. struct snd_soc_component *component =
  2708. snd_soc_kcontrol_component(kcontrol);
  2709. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2710. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2711. return 0;
  2712. }
  2713. static const char * const sys_usage_text[] = {
  2714. "NOSJ_SA_STEREO_3SM", "SJ_SA_AUX_2SM", "NOSJ_SA_STEREO_3SM_1HDR",
  2715. "SJ_SA_AUX_2SM_1HDR", "NOSJ_SA_EAR_3SM", "SJ_SA_EAR_2SM", "NOSJ_SA_EAR_3SM_1HDR",
  2716. "SJ_SA_EAR_2SM_1HDR", "SJ_1HDR_SA_AUX_1SM", "SJ_1HDR_SA_EAR_1SM",
  2717. "SJ_SA_STEREO_2SM", "SJ_NOMIC_SA_EAR_3SM", "SJ_NOMIC_SA_AUX_3SM",
  2718. };
  2719. static const struct soc_enum sys_usage_enum =
  2720. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sys_usage_text),
  2721. sys_usage_text);
  2722. static const char * const loopback_mode_text[] = {
  2723. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2724. };
  2725. static const struct soc_enum loopback_mode_enum =
  2726. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2727. loopback_mode_text);
  2728. static const char * const aux_dsm_text[] = {
  2729. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2730. };
  2731. static const struct soc_enum aux_dsm_enum =
  2732. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2733. aux_dsm_text);
  2734. static const char * const hph_dsm_text[] = {
  2735. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2736. };
  2737. static const struct soc_enum hph_dsm_enum =
  2738. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2739. hph_dsm_text);
  2740. static const char * const tx_mode_mux_text[] = {
  2741. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2742. };
  2743. static const struct soc_enum tx_mode_mux_enum =
  2744. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2745. tx_mode_mux_text);
  2746. static const char * const micb_sel_text[] = {
  2747. "NO_MICB", "MICB1", "MICB2", "MICB3",
  2748. };
  2749. static const struct soc_enum sm_micb_enum =
  2750. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micb_sel_text),
  2751. micb_sel_text);
  2752. static const char * const rx2_mode_text[] = {
  2753. "HP", "NORMAL",
  2754. };
  2755. static const struct soc_enum rx2_mode_enum =
  2756. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2757. rx2_mode_text);
  2758. static const char * const rx_hph_mode_mux_text[] = {
  2759. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2760. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2761. };
  2762. static const struct soc_enum rx_hph_mode_mux_enum =
  2763. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2764. rx_hph_mode_mux_text);
  2765. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2766. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2767. wcd9378_get_compander, wcd9378_set_compander),
  2768. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2769. wcd9378_get_compander, wcd9378_set_compander),
  2770. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2771. wcd9378_bcs_get, wcd9378_bcs_put),
  2772. SOC_SINGLE_EXT("VA_AMIC_MIXER Switch", SND_SOC_NOPM, 0, 1, 0,
  2773. wcd9378_get_va_amic_switch, wcd9378_set_va_amic_switch),
  2774. SOC_ENUM_EXT("SYS_USAGE Mode", sys_usage_enum,
  2775. wcd9378_sys_usage_get, wcd9378_sys_usage_put),
  2776. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2777. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2778. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2779. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2780. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2781. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2782. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2783. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2784. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2785. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2786. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2787. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2788. SOC_ENUM_EXT("SM0 MICB SEL", sm_micb_enum,
  2789. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2790. SOC_ENUM_EXT("SM1 MICB SEL", sm_micb_enum,
  2791. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2792. SOC_ENUM_EXT("SM2 MICB SEL", sm_micb_enum,
  2793. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2794. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2795. NULL, wcd9378_rx2_mode_put),
  2796. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2797. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2798. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2799. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2800. WCD9378_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD9378_ANA_EAR_COMPANDER_CTL,
  2801. 2, 0x10, 0, ear_pa_gain),
  2802. WCD9378_AUX_PA_GAIN_TLV("AUX_PA Volume", WCD9378_AUX_INT_MISC,
  2803. 0, 0x8, 0, aux_pa_gain),
  2804. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2805. analog_gain),
  2806. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2807. analog_gain),
  2808. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2809. analog_gain),
  2810. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2811. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2812. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2813. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2814. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2815. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2816. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2817. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2818. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2819. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2820. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2821. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2822. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2823. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2824. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2825. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2826. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2827. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2828. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2829. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2830. };
  2831. static const struct snd_kcontrol_new dmic1_switch[] = {
  2832. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2833. };
  2834. static const struct snd_kcontrol_new dmic2_switch[] = {
  2835. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2836. };
  2837. static const struct snd_kcontrol_new dmic3_switch[] = {
  2838. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2839. };
  2840. static const struct snd_kcontrol_new dmic4_switch[] = {
  2841. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2842. };
  2843. static const struct snd_kcontrol_new dmic5_switch[] = {
  2844. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2845. };
  2846. static const struct snd_kcontrol_new dmic6_switch[] = {
  2847. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2848. };
  2849. static const char * const adc1_mux_text[] = {
  2850. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2851. };
  2852. static const char * const adc2_mux_text[] = {
  2853. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2854. };
  2855. static const char * const adc3_mux_text[] = {
  2856. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC2", "CH3_AMIC3", "CH3_AMIC4"
  2857. };
  2858. static const char * const ear_mux_text[] = {
  2859. "RX2", "RX0"
  2860. };
  2861. static const char * const aux_mux_text[] = {
  2862. "RX2", "RX1"
  2863. };
  2864. static const struct soc_enum adc1_enum =
  2865. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2866. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2867. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2868. static const struct soc_enum adc2_enum =
  2869. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2870. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2871. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2872. static const struct soc_enum adc3_enum =
  2873. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2874. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2875. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2876. static const struct soc_enum ear_enum =
  2877. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2878. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT,
  2879. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2880. static const struct soc_enum aux_enum =
  2881. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2882. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT,
  2883. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2884. static const struct snd_kcontrol_new tx_adc1_mux =
  2885. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2886. static const struct snd_kcontrol_new tx_adc2_mux =
  2887. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2888. static const struct snd_kcontrol_new tx_adc3_mux =
  2889. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2890. static const struct snd_kcontrol_new ear_mux =
  2891. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2892. static const struct snd_kcontrol_new aux_mux =
  2893. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2894. static const struct snd_kcontrol_new dac1_switch[] = {
  2895. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2896. };
  2897. static const struct snd_kcontrol_new dac2_switch[] = {
  2898. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2899. };
  2900. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2901. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2902. };
  2903. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2904. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2905. };
  2906. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2907. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2908. };
  2909. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2910. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2911. };
  2912. static const struct snd_kcontrol_new rx0_switch[] = {
  2913. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2914. };
  2915. static const struct snd_kcontrol_new rx1_switch[] = {
  2916. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2917. };
  2918. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2919. /*input widgets*/
  2920. SND_SOC_DAPM_INPUT("AMIC1"),
  2921. SND_SOC_DAPM_INPUT("AMIC2"),
  2922. SND_SOC_DAPM_INPUT("AMIC3"),
  2923. SND_SOC_DAPM_INPUT("AMIC4"),
  2924. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2925. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2926. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2927. /*tx widgets*/
  2928. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  2929. NULL, 0, wcd9378_tx_sequencer_enable,
  2930. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2931. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  2932. NULL, 0, wcd9378_tx_sequencer_enable,
  2933. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2934. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  2935. NULL, 0, wcd9378_tx_sequencer_enable,
  2936. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2937. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  2938. &tx_adc1_mux),
  2939. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2940. &tx_adc2_mux),
  2941. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2942. &tx_adc3_mux),
  2943. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2944. wcd9378_codec_enable_dmic,
  2945. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2946. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2947. wcd9378_codec_enable_dmic,
  2948. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2949. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2950. wcd9378_codec_enable_dmic,
  2951. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2952. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2953. wcd9378_codec_enable_dmic,
  2954. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2955. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2956. wcd9378_codec_enable_dmic,
  2957. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2958. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2959. wcd9378_codec_enable_dmic,
  2960. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2961. /*rx widgets*/
  2962. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2963. wcd9378_codec_hphl_dac_event,
  2964. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2965. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2966. wcd9378_codec_hphr_dac_event,
  2967. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2968. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  2969. wcd9378_hph_sequencer_enable,
  2970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2971. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2972. wcd9378_codec_enable_hphl_pa,
  2973. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2974. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2975. wcd9378_codec_enable_hphr_pa,
  2976. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2977. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  2978. NULL, 0, wcd9378_sa_sequencer_enable,
  2979. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2980. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2981. wcd9378_codec_ear_dac_event,
  2982. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2983. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2984. wcd9378_codec_aux_dac_event,
  2985. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2986. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2987. wcd9378_codec_enable_ear_pa,
  2988. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2989. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2990. wcd9378_codec_enable_aux_pa,
  2991. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2992. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2993. wcd9378_codec_enable_vdd_buck,
  2994. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2995. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2996. wcd9378_enable_clsh,
  2997. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2998. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2999. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3000. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3001. SND_SOC_DAPM_POST_PMD),
  3002. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3003. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3004. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3005. SND_SOC_DAPM_POST_PMD),
  3006. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3007. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3008. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3009. SND_SOC_DAPM_POST_PMD),
  3010. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3011. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3012. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3013. SND_SOC_DAPM_POST_PMD),
  3014. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3015. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3016. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3017. SND_SOC_DAPM_POST_PMD),
  3018. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3019. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3020. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3021. SND_SOC_DAPM_POST_PMD),
  3022. /* micbias widgets*/
  3023. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3024. wcd9378_codec_enable_micbias,
  3025. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3026. SND_SOC_DAPM_POST_PMD),
  3027. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3028. wcd9378_codec_enable_micbias,
  3029. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3030. SND_SOC_DAPM_POST_PMD),
  3031. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3032. wcd9378_codec_enable_micbias,
  3033. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3034. SND_SOC_DAPM_POST_PMD),
  3035. /* micbias pull up widgets*/
  3036. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3037. wcd9378_codec_enable_micbias_pullup,
  3038. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3039. SND_SOC_DAPM_POST_PMD),
  3040. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3041. wcd9378_codec_enable_micbias_pullup,
  3042. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3043. SND_SOC_DAPM_POST_PMD),
  3044. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3045. wcd9378_codec_enable_micbias_pullup,
  3046. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3047. SND_SOC_DAPM_POST_PMD),
  3048. /* rx mixer widgets*/
  3049. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3050. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3051. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3052. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3053. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3054. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3055. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3056. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3057. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3058. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3059. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3060. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3061. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3062. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3063. /*output widgets tx*/
  3064. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3065. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3066. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3067. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3068. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3069. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3070. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3071. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3072. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3073. /*output widgets rx*/
  3074. SND_SOC_DAPM_OUTPUT("EAR"),
  3075. SND_SOC_DAPM_OUTPUT("AUX"),
  3076. SND_SOC_DAPM_OUTPUT("HPHL"),
  3077. SND_SOC_DAPM_OUTPUT("HPHR"),
  3078. };
  3079. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3080. /*ADC-1 (channel-1)*/
  3081. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3082. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3083. {"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
  3084. {"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
  3085. {"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
  3086. {"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
  3087. /*ADC-2 (channel-2)*/
  3088. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3089. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3090. {"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
  3091. {"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
  3092. {"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
  3093. {"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
  3094. /*ADC-3 (channel-3)*/
  3095. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3096. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3097. {"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
  3098. {"ADC3 MUX", "CH3_AMIC2", "AMIC2"},
  3099. {"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
  3100. {"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
  3101. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3102. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3103. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3104. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3105. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3106. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3107. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3108. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3109. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3110. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3111. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3112. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3113. /*Headphone playback*/
  3114. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3115. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3116. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3117. {"RDAC1", NULL, "HPH SEQUENCER"},
  3118. {"HPHL_RDAC", "Switch", "RDAC1"},
  3119. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3120. {"HPHL", NULL, "HPHL PGA"},
  3121. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3122. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3123. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3124. {"RDAC2", NULL, "HPH SEQUENCER"},
  3125. {"HPHR_RDAC", "Switch", "RDAC2"},
  3126. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3127. {"HPHR", NULL, "HPHR PGA"},
  3128. /*Amplier playback*/
  3129. {"IN3_AUX", NULL, "VDD_BUCK"},
  3130. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3131. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3132. {"EAR_MUX", "RX2", "IN3_AUX"},
  3133. {"DAC1", "Switch", "EAR_MUX"},
  3134. {"EAR_RDAC", NULL, "DAC1"},
  3135. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3136. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3137. {"EAR PGA", NULL, "EAR_MIXER"},
  3138. {"EAR", NULL, "EAR PGA"},
  3139. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3140. {"AUX_MUX", "RX2", "IN3_AUX"},
  3141. {"DAC2", "Switch", "AUX_MUX"},
  3142. {"AUX_RDAC", NULL, "DAC2"},
  3143. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3144. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3145. {"AUX PGA", NULL, "AUX_MIXER"},
  3146. {"AUX", NULL, "AUX PGA"},
  3147. };
  3148. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3149. void *file_private_data,
  3150. struct file *file,
  3151. char __user *buf, size_t count,
  3152. loff_t pos)
  3153. {
  3154. struct wcd9378_priv *priv;
  3155. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3156. int len = 0;
  3157. priv = (struct wcd9378_priv *) entry->private_data;
  3158. if (!priv) {
  3159. pr_err("%s: wcd9378 priv is null\n", __func__);
  3160. return -EINVAL;
  3161. }
  3162. switch (priv->version) {
  3163. case WCD9378_VERSION_1_0:
  3164. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3165. break;
  3166. default:
  3167. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3168. }
  3169. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3170. }
  3171. static struct snd_info_entry_ops wcd9378_info_ops = {
  3172. .read = wcd9378_version_read,
  3173. };
  3174. /*
  3175. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3176. * @codec_root: The parent directory
  3177. * @component: component instance
  3178. *
  3179. * Creates wcd9378 module, version entry under the given
  3180. * parent directory.
  3181. *
  3182. * Return: 0 on success or negative error code on failure.
  3183. */
  3184. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3185. struct snd_soc_component *component)
  3186. {
  3187. struct snd_info_entry *version_entry;
  3188. struct wcd9378_priv *priv;
  3189. struct snd_soc_card *card;
  3190. if (!codec_root || !component)
  3191. return -EINVAL;
  3192. priv = snd_soc_component_get_drvdata(component);
  3193. if (priv->entry) {
  3194. dev_dbg(priv->dev,
  3195. "%s:wcd9378 module already created\n", __func__);
  3196. return 0;
  3197. }
  3198. card = component->card;
  3199. priv->entry = snd_info_create_module_entry(codec_root->module,
  3200. "wcd9378", codec_root);
  3201. if (!priv->entry) {
  3202. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3203. __func__);
  3204. return -ENOMEM;
  3205. }
  3206. priv->entry->mode = S_IFDIR | 0555;
  3207. if (snd_info_register(priv->entry) < 0) {
  3208. snd_info_free_entry(priv->entry);
  3209. return -ENOMEM;
  3210. }
  3211. version_entry = snd_info_create_card_entry(card->snd_card,
  3212. "version",
  3213. priv->entry);
  3214. if (!version_entry) {
  3215. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3216. __func__);
  3217. snd_info_free_entry(priv->entry);
  3218. return -ENOMEM;
  3219. }
  3220. version_entry->private_data = priv;
  3221. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3222. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3223. version_entry->c.ops = &wcd9378_info_ops;
  3224. if (snd_info_register(version_entry) < 0) {
  3225. snd_info_free_entry(version_entry);
  3226. snd_info_free_entry(priv->entry);
  3227. return -ENOMEM;
  3228. }
  3229. priv->version_entry = version_entry;
  3230. return 0;
  3231. }
  3232. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3233. static void wcd9378_class_load(struct snd_soc_component *component)
  3234. {
  3235. /*SMP AMP CLASS LOADING*/
  3236. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3237. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3238. usleep_range(20000, 20010);
  3239. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3240. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3241. /*SMP JACK CLASS LOADING*/
  3242. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3243. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3244. usleep_range(30000, 30010);
  3245. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3246. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3247. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3248. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3249. /*SMP MIC0 CLASS LOADING*/
  3250. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3251. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3252. usleep_range(5000, 5010);
  3253. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3254. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3255. /*SMP MIC1 CLASS LOADING*/
  3256. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3257. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3258. usleep_range(5000, 5010);
  3259. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3260. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3261. /*SMP MIC2 CLASS LOADING*/
  3262. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3263. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3264. usleep_range(5000, 5010);
  3265. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3266. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3267. }
  3268. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3269. {
  3270. struct wcd9378_priv *wcd9378 =
  3271. snd_soc_component_get_drvdata(component);
  3272. struct wcd9378_pdata *pdata =
  3273. dev_get_platdata(wcd9378->dev);
  3274. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3275. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3276. mb->micb1_mv, MIC_BIAS_1);
  3277. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3278. mb->micb2_mv, MIC_BIAS_2);
  3279. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3280. mb->micb3_mv, MIC_BIAS_3);
  3281. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3282. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3283. }
  3284. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3285. {
  3286. struct wcd9378_priv *wcd9378 =
  3287. snd_soc_component_get_drvdata(component);
  3288. if (snd_soc_component_read(component,
  3289. WCD9378_EFUSE_REG_29)
  3290. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3291. if (((snd_soc_component_read(component,
  3292. WCD9378_EFUSE_REG_29) &
  3293. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3294. return true;
  3295. else
  3296. return false;
  3297. } else {
  3298. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3299. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3300. return true;
  3301. else
  3302. return false;
  3303. }
  3304. return 0;
  3305. }
  3306. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3307. {
  3308. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3309. struct snd_soc_dapm_context *dapm =
  3310. snd_soc_component_get_dapm(component);
  3311. int ret = -EINVAL;
  3312. wcd9378 = snd_soc_component_get_drvdata(component);
  3313. if (!wcd9378)
  3314. return -EINVAL;
  3315. wcd9378->component = component;
  3316. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3317. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3318. ret = wcd9378_wcd_mode_check(component);
  3319. if (!ret) {
  3320. dev_err(component->dev, "wcd mode check failed\n");
  3321. ret = -EINVAL;
  3322. goto exit;
  3323. }
  3324. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3325. if (ret) {
  3326. pr_err("%s: mbhc initialization failed\n", __func__);
  3327. ret = -EINVAL;
  3328. goto exit;
  3329. }
  3330. dev_dbg(component->dev, "%s: mbhc init done\n", __func__);
  3331. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3332. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3333. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3334. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3335. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3336. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3337. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3338. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3339. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3340. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3341. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3342. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3343. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3344. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3345. snd_soc_dapm_sync(dapm);
  3346. wcd_cls_h_init(&wcd9378->clsh_info);
  3347. wcd9378_init_reg(component);
  3348. wcd9378_micb_value_convert(component);
  3349. wcd9378->version = WCD9378_VERSION_1_0;
  3350. /* Register event notifier */
  3351. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3352. if (wcd9378->register_notifier) {
  3353. ret = wcd9378->register_notifier(wcd9378->handle,
  3354. &wcd9378->nblock,
  3355. true);
  3356. if (ret) {
  3357. dev_err(component->dev,
  3358. "%s: Failed to register notifier %d\n",
  3359. __func__, ret);
  3360. return ret;
  3361. }
  3362. }
  3363. exit:
  3364. return ret;
  3365. }
  3366. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3367. {
  3368. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3369. if (!wcd9378) {
  3370. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3371. __func__);
  3372. return;
  3373. }
  3374. if (wcd9378->register_notifier)
  3375. wcd9378->register_notifier(wcd9378->handle,
  3376. &wcd9378->nblock,
  3377. false);
  3378. }
  3379. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3380. {
  3381. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3382. if (!wcd9378)
  3383. return 0;
  3384. wcd9378->dapm_bias_off = true;
  3385. return 0;
  3386. }
  3387. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3388. {
  3389. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3390. if (!wcd9378)
  3391. return 0;
  3392. wcd9378->dapm_bias_off = false;
  3393. return 0;
  3394. }
  3395. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3396. .name = WCD9378_DRV_NAME,
  3397. .probe = wcd9378_soc_codec_probe,
  3398. .remove = wcd9378_soc_codec_remove,
  3399. .controls = wcd9378_snd_controls,
  3400. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3401. .dapm_widgets = wcd9378_dapm_widgets,
  3402. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3403. .dapm_routes = wcd9378_audio_map,
  3404. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3405. .suspend = wcd9378_soc_codec_suspend,
  3406. .resume = wcd9378_soc_codec_resume,
  3407. };
  3408. static int wcd9378_reset(struct device *dev)
  3409. {
  3410. struct wcd9378_priv *wcd9378 = NULL;
  3411. int rc = 0;
  3412. int value = 0;
  3413. if (!dev)
  3414. return -ENODEV;
  3415. wcd9378 = dev_get_drvdata(dev);
  3416. if (!wcd9378)
  3417. return -EINVAL;
  3418. if (!wcd9378->rst_np) {
  3419. dev_err(dev, "%s: reset gpio device node not specified\n",
  3420. __func__);
  3421. return -EINVAL;
  3422. }
  3423. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3424. if (value > 0)
  3425. return 0;
  3426. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3427. if (rc) {
  3428. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3429. __func__);
  3430. return -EPROBE_DEFER;
  3431. }
  3432. /* 20us sleep required after pulling the reset gpio to LOW */
  3433. usleep_range(20, 30);
  3434. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3435. if (rc) {
  3436. dev_err(dev, "%s: wcd active state request fail!\n",
  3437. __func__);
  3438. return -EPROBE_DEFER;
  3439. }
  3440. /* 20us sleep required after pulling the reset gpio to HIGH */
  3441. usleep_range(20, 30);
  3442. return rc;
  3443. }
  3444. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3445. u32 *val)
  3446. {
  3447. int rc = 0;
  3448. rc = of_property_read_u32(dev->of_node, name, val);
  3449. if (rc)
  3450. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3451. __func__, name, dev->of_node->full_name);
  3452. return rc;
  3453. }
  3454. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3455. struct wcd9378_micbias_setting *mb)
  3456. {
  3457. u32 prop_val = 0;
  3458. int rc = 0;
  3459. /* MB1 */
  3460. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3461. NULL)) {
  3462. rc = wcd9378_read_of_property_u32(dev,
  3463. "qcom,cdc-micbias1-mv",
  3464. &prop_val);
  3465. if (!rc)
  3466. mb->micb1_mv = prop_val;
  3467. } else {
  3468. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3469. __func__);
  3470. }
  3471. /* MB2 */
  3472. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3473. NULL)) {
  3474. rc = wcd9378_read_of_property_u32(dev,
  3475. "qcom,cdc-micbias2-mv",
  3476. &prop_val);
  3477. if (!rc)
  3478. mb->micb2_mv = prop_val;
  3479. } else {
  3480. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3481. __func__);
  3482. }
  3483. /* MB3 */
  3484. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3485. NULL)) {
  3486. rc = wcd9378_read_of_property_u32(dev,
  3487. "qcom,cdc-micbias3-mv",
  3488. &prop_val);
  3489. if (!rc)
  3490. mb->micb3_mv = prop_val;
  3491. } else {
  3492. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3493. __func__);
  3494. }
  3495. }
  3496. static int wcd9378_reset_low(struct device *dev)
  3497. {
  3498. struct wcd9378_priv *wcd9378 = NULL;
  3499. int rc = 0;
  3500. if (!dev)
  3501. return -ENODEV;
  3502. wcd9378 = dev_get_drvdata(dev);
  3503. if (!wcd9378)
  3504. return -EINVAL;
  3505. if (!wcd9378->rst_np) {
  3506. dev_err(dev, "%s: reset gpio device node not specified\n",
  3507. __func__);
  3508. return -EINVAL;
  3509. }
  3510. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3511. if (rc) {
  3512. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3513. __func__);
  3514. return rc;
  3515. }
  3516. /* 20us sleep required after pulling the reset gpio to LOW */
  3517. usleep_range(20, 30);
  3518. return rc;
  3519. }
  3520. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3521. {
  3522. struct wcd9378_pdata *pdata = NULL;
  3523. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3524. GFP_KERNEL);
  3525. if (!pdata)
  3526. return NULL;
  3527. pdata->rst_np = of_parse_phandle(dev->of_node,
  3528. "qcom,wcd-rst-gpio-node", 0);
  3529. if (!pdata->rst_np) {
  3530. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3531. __func__, "qcom,wcd-rst-gpio-node",
  3532. dev->of_node->full_name);
  3533. return NULL;
  3534. }
  3535. /* Parse power supplies */
  3536. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3537. &pdata->num_supplies);
  3538. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3539. dev_err(dev, "%s: no power supplies defined for codec\n",
  3540. __func__);
  3541. return NULL;
  3542. }
  3543. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3544. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3545. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3546. return pdata;
  3547. }
  3548. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3549. {
  3550. .name = "wcd9378_cdc",
  3551. .playback = {
  3552. .stream_name = "WCD9378_AIF Playback",
  3553. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3554. .formats = WCD9378_FORMATS,
  3555. .rate_max = 384000,
  3556. .rate_min = 8000,
  3557. .channels_min = 1,
  3558. .channels_max = 4,
  3559. },
  3560. .capture = {
  3561. .stream_name = "WCD9378_AIF Capture",
  3562. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3563. .formats = WCD9378_FORMATS,
  3564. .rate_max = 384000,
  3565. .rate_min = 8000,
  3566. .channels_min = 1,
  3567. .channels_max = 4,
  3568. },
  3569. },
  3570. };
  3571. static int wcd9378_bind(struct device *dev)
  3572. {
  3573. int ret = 0;
  3574. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3575. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3576. /*
  3577. * Add 5msec delay to provide sufficient time for
  3578. * soundwire auto enumeration of slave devices as
  3579. * per HW requirement.
  3580. */
  3581. usleep_range(5000, 5010);
  3582. ret = component_bind_all(dev, wcd9378);
  3583. if (ret) {
  3584. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3585. __func__, ret);
  3586. return ret;
  3587. }
  3588. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3589. if (!wcd9378->rx_swr_dev) {
  3590. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3591. __func__);
  3592. ret = -ENODEV;
  3593. goto err;
  3594. }
  3595. wcd9378->rx_swr_dev->paging_support = true;
  3596. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3597. if (!wcd9378->tx_swr_dev) {
  3598. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3599. __func__);
  3600. ret = -ENODEV;
  3601. goto err;
  3602. }
  3603. wcd9378->tx_swr_dev->paging_support = true;
  3604. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3605. wcd9378->swr_tx_port_params);
  3606. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3607. &wcd9378_regmap_config);
  3608. if (!wcd9378->regmap) {
  3609. dev_err(dev, "%s: Regmap init failed\n",
  3610. __func__);
  3611. goto err;
  3612. }
  3613. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3614. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3615. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3616. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3617. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3618. wcd9378->irq_info.codec_name = "WCD9378";
  3619. wcd9378->irq_info.regmap = wcd9378->regmap;
  3620. wcd9378->irq_info.dev = dev;
  3621. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3622. if (ret) {
  3623. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3624. __func__, ret);
  3625. goto err;
  3626. }
  3627. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3628. __func__);
  3629. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3630. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3631. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3632. if (ret) {
  3633. dev_err(dev, "%s: Codec registration failed\n",
  3634. __func__);
  3635. goto err_irq;
  3636. }
  3637. wcd9378->dev_up = true;
  3638. return ret;
  3639. err_irq:
  3640. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3641. err:
  3642. component_unbind_all(dev, wcd9378);
  3643. return ret;
  3644. }
  3645. static void wcd9378_unbind(struct device *dev)
  3646. {
  3647. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3648. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3649. snd_soc_unregister_component(dev);
  3650. component_unbind_all(dev, wcd9378);
  3651. }
  3652. static const struct of_device_id wcd9378_dt_match[] = {
  3653. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3654. {}
  3655. };
  3656. static const struct component_master_ops wcd9378_comp_ops = {
  3657. .bind = wcd9378_bind,
  3658. .unbind = wcd9378_unbind,
  3659. };
  3660. static int wcd9378_compare_of(struct device *dev, void *data)
  3661. {
  3662. return dev->of_node == data;
  3663. }
  3664. static void wcd9378_release_of(struct device *dev, void *data)
  3665. {
  3666. of_node_put(data);
  3667. }
  3668. static int wcd9378_add_slave_components(struct device *dev,
  3669. struct component_match **matchptr)
  3670. {
  3671. struct device_node *np, *rx_node, *tx_node;
  3672. np = dev->of_node;
  3673. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3674. if (!rx_node) {
  3675. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3676. return -ENODEV;
  3677. }
  3678. of_node_get(rx_node);
  3679. component_match_add_release(dev, matchptr,
  3680. wcd9378_release_of,
  3681. wcd9378_compare_of,
  3682. rx_node);
  3683. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3684. if (!tx_node) {
  3685. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3686. return -ENODEV;
  3687. }
  3688. of_node_get(tx_node);
  3689. component_match_add_release(dev, matchptr,
  3690. wcd9378_release_of,
  3691. wcd9378_compare_of,
  3692. tx_node);
  3693. return 0;
  3694. }
  3695. static int wcd9378_probe(struct platform_device *pdev)
  3696. {
  3697. struct component_match *match = NULL;
  3698. struct wcd9378_priv *wcd9378 = NULL;
  3699. struct wcd9378_pdata *pdata = NULL;
  3700. struct wcd_ctrl_platform_data *plat_data = NULL;
  3701. struct device *dev = &pdev->dev;
  3702. int ret;
  3703. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3704. GFP_KERNEL);
  3705. if (!wcd9378)
  3706. return -ENOMEM;
  3707. dev_set_drvdata(dev, wcd9378);
  3708. wcd9378->dev = dev;
  3709. pdata = wcd9378_populate_dt_data(dev);
  3710. if (!pdata) {
  3711. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3712. return -EINVAL;
  3713. }
  3714. dev->platform_data = pdata;
  3715. wcd9378->rst_np = pdata->rst_np;
  3716. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3717. pdata->regulator, pdata->num_supplies);
  3718. if (!wcd9378->supplies) {
  3719. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3720. __func__);
  3721. return ret;
  3722. }
  3723. plat_data = dev_get_platdata(dev->parent);
  3724. if (!plat_data) {
  3725. dev_err(dev, "%s: platform data from parent is NULL\n",
  3726. __func__);
  3727. return -EINVAL;
  3728. }
  3729. wcd9378->handle = (void *)plat_data->handle;
  3730. if (!wcd9378->handle) {
  3731. dev_err(dev, "%s: handle is NULL\n", __func__);
  3732. return -EINVAL;
  3733. }
  3734. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3735. if (!wcd9378->update_wcd_event) {
  3736. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3737. __func__);
  3738. return -EINVAL;
  3739. }
  3740. wcd9378->register_notifier = plat_data->register_notifier;
  3741. if (!wcd9378->register_notifier) {
  3742. dev_err(dev, "%s: register_notifier api is null!\n",
  3743. __func__);
  3744. return -EINVAL;
  3745. }
  3746. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3747. &wcd9378->wcd_mode);
  3748. if (ret) {
  3749. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3750. __func__);
  3751. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3752. }
  3753. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3754. pdata->regulator,
  3755. pdata->num_supplies);
  3756. if (ret) {
  3757. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3758. __func__);
  3759. return ret;
  3760. }
  3761. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3762. CODEC_RX);
  3763. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3764. CODEC_TX);
  3765. if (ret) {
  3766. dev_err(dev, "Failed to read port mapping\n");
  3767. goto err;
  3768. }
  3769. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3770. CODEC_TX);
  3771. if (ret) {
  3772. dev_err(dev, "Failed to read port params\n");
  3773. goto err;
  3774. }
  3775. mutex_init(&wcd9378->wakeup_lock);
  3776. mutex_init(&wcd9378->micb_lock);
  3777. ret = wcd9378_add_slave_components(dev, &match);
  3778. if (ret)
  3779. goto err_lock_init;
  3780. ret = wcd9378_reset(dev);
  3781. if (ret == -EPROBE_DEFER) {
  3782. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3783. goto err_lock_init;
  3784. }
  3785. wcd9378->wakeup = wcd9378_wakeup;
  3786. return component_master_add_with_match(dev,
  3787. &wcd9378_comp_ops, match);
  3788. err_lock_init:
  3789. mutex_destroy(&wcd9378->micb_lock);
  3790. mutex_destroy(&wcd9378->wakeup_lock);
  3791. err:
  3792. return ret;
  3793. }
  3794. static int wcd9378_remove(struct platform_device *pdev)
  3795. {
  3796. struct wcd9378_priv *wcd9378 = NULL;
  3797. wcd9378 = platform_get_drvdata(pdev);
  3798. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3799. mutex_destroy(&wcd9378->micb_lock);
  3800. mutex_destroy(&wcd9378->wakeup_lock);
  3801. dev_set_drvdata(&pdev->dev, NULL);
  3802. return 0;
  3803. }
  3804. #ifdef CONFIG_PM_SLEEP
  3805. static int wcd9378_suspend(struct device *dev)
  3806. {
  3807. struct wcd9378_priv *wcd9378 = NULL;
  3808. int ret = 0;
  3809. struct wcd9378_pdata *pdata = NULL;
  3810. if (!dev)
  3811. return -ENODEV;
  3812. wcd9378 = dev_get_drvdata(dev);
  3813. if (!wcd9378)
  3814. return -EINVAL;
  3815. pdata = dev_get_platdata(wcd9378->dev);
  3816. if (!pdata) {
  3817. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3818. return -EINVAL;
  3819. }
  3820. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3821. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3822. wcd9378->supplies,
  3823. pdata->regulator,
  3824. pdata->num_supplies,
  3825. "cdc-vdd-buck");
  3826. if (ret == -EINVAL) {
  3827. dev_err(dev, "%s: vdd buck is not disabled\n",
  3828. __func__);
  3829. return 0;
  3830. }
  3831. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3832. }
  3833. if (wcd9378->dapm_bias_off) {
  3834. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3835. wcd9378->supplies,
  3836. pdata->regulator,
  3837. pdata->num_supplies,
  3838. true);
  3839. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3840. }
  3841. return 0;
  3842. }
  3843. static int wcd9378_resume(struct device *dev)
  3844. {
  3845. struct wcd9378_priv *wcd9378 = NULL;
  3846. struct wcd9378_pdata *pdata = NULL;
  3847. if (!dev)
  3848. return -ENODEV;
  3849. wcd9378 = dev_get_drvdata(dev);
  3850. if (!wcd9378)
  3851. return -EINVAL;
  3852. pdata = dev_get_platdata(wcd9378->dev);
  3853. if (!pdata) {
  3854. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3855. return -EINVAL;
  3856. }
  3857. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  3858. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3859. wcd9378->supplies,
  3860. pdata->regulator,
  3861. pdata->num_supplies,
  3862. false);
  3863. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3864. }
  3865. return 0;
  3866. }
  3867. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  3868. .suspend_late = wcd9378_suspend,
  3869. .resume_early = wcd9378_resume,
  3870. };
  3871. #endif
  3872. static struct platform_driver wcd9378_codec_driver = {
  3873. .probe = wcd9378_probe,
  3874. .remove = wcd9378_remove,
  3875. .driver = {
  3876. .name = "wcd9378_codec",
  3877. .of_match_table = of_match_ptr(wcd9378_dt_match),
  3878. #ifdef CONFIG_PM_SLEEP
  3879. .pm = &wcd9378_dev_pm_ops,
  3880. #endif
  3881. .suppress_bind_attrs = true,
  3882. },
  3883. };
  3884. module_platform_driver(wcd9378_codec_driver);
  3885. MODULE_DESCRIPTION("WCD9378 Codec driver");
  3886. MODULE_LICENSE("GPL");