dp_tx.c 156 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779578057815782578357845785578657875788578957905791579257935794579557965797579857995800580158025803580458055806580758085809581058115812581358145815581658175818581958205821582258235824582558265827582858295830583158325833583458355836583758385839584058415842584358445845584658475848584958505851585258535854585558565857585858595860586158625863586458655866586758685869587058715872587358745875587658775878587958805881588258835884588558865887588858895890589158925893589458955896589758985899590059015902590359045905590659075908590959105911591259135914591559165917591859195920592159225923592459255926592759285929
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef QCA_DP_TX_FW_METADATA_V2
  66. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  67. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  68. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  69. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  78. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  79. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  80. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  82. #else
  83. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  84. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  85. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  86. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  95. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  96. HTT_TCL_METADATA_TYPE_PEER_BASED
  97. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  98. HTT_TCL_METADATA_TYPE_VDEV_BASED
  99. #endif
  100. /*mapping between hal encrypt type and cdp_sec_type*/
  101. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  102. HAL_TX_ENCRYPT_TYPE_WEP_128,
  103. HAL_TX_ENCRYPT_TYPE_WEP_104,
  104. HAL_TX_ENCRYPT_TYPE_WEP_40,
  105. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  106. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  107. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  108. HAL_TX_ENCRYPT_TYPE_WAPI,
  109. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  110. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  111. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  112. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  113. qdf_export_symbol(sec_type_map);
  114. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  115. /**
  116. * dp_update_tx_desc_stats - Update the increase or decrease in
  117. * outstanding tx desc count
  118. * values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  125. {
  126. int32_t tx_descs_cnt =
  127. qdf_atomic_read(&pdev->num_tx_outstanding);
  128. if (pdev->tx_descs_max < tx_descs_cnt)
  129. pdev->tx_descs_max = tx_descs_cnt;
  130. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  131. pdev->tx_descs_max);
  132. }
  133. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  134. static inline void
  135. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  136. {
  137. }
  138. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  139. #ifdef QCA_TX_LIMIT_CHECK
  140. /**
  141. * dp_tx_limit_check - Check if allocated tx descriptors reached
  142. * soc max limit and pdev max limit
  143. * @vdev: DP vdev handle
  144. *
  145. * Return: true if allocated tx descriptors reached max configured value, else
  146. * false
  147. */
  148. static inline bool
  149. dp_tx_limit_check(struct dp_vdev *vdev)
  150. {
  151. struct dp_pdev *pdev = vdev->pdev;
  152. struct dp_soc *soc = pdev->soc;
  153. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  154. soc->num_tx_allowed) {
  155. dp_tx_info("queued packets are more than max tx, drop the frame");
  156. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  157. return true;
  158. }
  159. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  160. pdev->num_tx_allowed) {
  161. dp_tx_info("queued packets are more than max tx, drop the frame");
  162. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  163. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  164. return true;
  165. }
  166. return false;
  167. }
  168. /**
  169. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  170. * reached soc max limit
  171. * @vdev: DP vdev handle
  172. *
  173. * Return: true if allocated tx descriptors reached max configured value, else
  174. * false
  175. */
  176. static inline bool
  177. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  178. {
  179. struct dp_pdev *pdev = vdev->pdev;
  180. struct dp_soc *soc = pdev->soc;
  181. if (qdf_atomic_read(&soc->num_tx_exception) >=
  182. soc->num_msdu_exception_desc) {
  183. dp_info("exc packets are more than max drop the exc pkt");
  184. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  185. return true;
  186. }
  187. return false;
  188. }
  189. /**
  190. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  191. * @vdev: DP pdev handle
  192. *
  193. * Return: void
  194. */
  195. static inline void
  196. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  197. {
  198. struct dp_soc *soc = pdev->soc;
  199. qdf_atomic_inc(&pdev->num_tx_outstanding);
  200. qdf_atomic_inc(&soc->num_tx_outstanding);
  201. dp_update_tx_desc_stats(pdev);
  202. }
  203. /**
  204. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  205. * @vdev: DP pdev handle
  206. *
  207. * Return: void
  208. */
  209. static inline void
  210. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  211. {
  212. struct dp_soc *soc = pdev->soc;
  213. qdf_atomic_dec(&pdev->num_tx_outstanding);
  214. qdf_atomic_dec(&soc->num_tx_outstanding);
  215. dp_update_tx_desc_stats(pdev);
  216. }
  217. #else //QCA_TX_LIMIT_CHECK
  218. static inline bool
  219. dp_tx_limit_check(struct dp_vdev *vdev)
  220. {
  221. return false;
  222. }
  223. static inline bool
  224. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  225. {
  226. return false;
  227. }
  228. static inline void
  229. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  230. {
  231. qdf_atomic_inc(&pdev->num_tx_outstanding);
  232. dp_update_tx_desc_stats(pdev);
  233. }
  234. static inline void
  235. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  236. {
  237. qdf_atomic_dec(&pdev->num_tx_outstanding);
  238. dp_update_tx_desc_stats(pdev);
  239. }
  240. #endif //QCA_TX_LIMIT_CHECK
  241. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  242. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  243. {
  244. enum dp_tx_event_type type;
  245. if (flags & DP_TX_DESC_FLAG_FLUSH)
  246. type = DP_TX_DESC_FLUSH;
  247. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  248. type = DP_TX_COMP_UNMAP_ERR;
  249. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  250. type = DP_TX_COMP_UNMAP;
  251. else
  252. type = DP_TX_DESC_UNMAP;
  253. return type;
  254. }
  255. static inline void
  256. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  257. qdf_nbuf_t skb, uint32_t sw_cookie,
  258. enum dp_tx_event_type type)
  259. {
  260. struct dp_tx_desc_event *entry;
  261. uint32_t idx;
  262. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  263. return;
  264. switch (type) {
  265. case DP_TX_COMP_UNMAP:
  266. case DP_TX_COMP_UNMAP_ERR:
  267. case DP_TX_COMP_MSDU_EXT:
  268. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  269. DP_TX_COMP_HISTORY_SIZE);
  270. entry = &soc->tx_comp_history->entry[idx];
  271. break;
  272. case DP_TX_DESC_MAP:
  273. case DP_TX_DESC_UNMAP:
  274. case DP_TX_DESC_COOKIE:
  275. case DP_TX_DESC_FLUSH:
  276. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  277. DP_TX_TCL_HISTORY_SIZE);
  278. entry = &soc->tx_tcl_history->entry[idx];
  279. break;
  280. default:
  281. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  282. return;
  283. }
  284. entry->skb = skb;
  285. entry->paddr = paddr;
  286. entry->sw_cookie = sw_cookie;
  287. entry->type = type;
  288. entry->ts = qdf_get_log_timestamp();
  289. }
  290. static inline void
  291. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  292. struct qdf_tso_seg_elem_t *tso_seg,
  293. qdf_nbuf_t skb, uint32_t sw_cookie,
  294. enum dp_tx_event_type type)
  295. {
  296. int i;
  297. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  298. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  299. skb, sw_cookie, type);
  300. }
  301. if (!tso_seg->next)
  302. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  303. skb, 0xFFFFFFFF, type);
  304. }
  305. static inline void
  306. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  307. qdf_nbuf_t skb, uint32_t sw_cookie,
  308. enum dp_tx_event_type type)
  309. {
  310. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  311. uint32_t num_segs = tso_info.num_segs;
  312. while (num_segs) {
  313. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  314. curr_seg = curr_seg->next;
  315. num_segs--;
  316. }
  317. }
  318. #else
  319. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  320. {
  321. return DP_TX_DESC_INVAL_EVT;
  322. }
  323. static inline void
  324. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  325. qdf_nbuf_t skb, uint32_t sw_cookie,
  326. enum dp_tx_event_type type)
  327. {
  328. }
  329. static inline void
  330. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  331. struct qdf_tso_seg_elem_t *tso_seg,
  332. qdf_nbuf_t skb, uint32_t sw_cookie,
  333. enum dp_tx_event_type type)
  334. {
  335. }
  336. static inline void
  337. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  338. qdf_nbuf_t skb, uint32_t sw_cookie,
  339. enum dp_tx_event_type type)
  340. {
  341. }
  342. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  343. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  344. /**
  345. * dp_is_tput_high() - Check if throughput is high
  346. *
  347. * @soc - core txrx main context
  348. *
  349. * The current function is based of the RTPM tput policy variable where RTPM is
  350. * avoided based on throughput.
  351. */
  352. static inline int dp_is_tput_high(struct dp_soc *soc)
  353. {
  354. return dp_get_rtpm_tput_policy_requirement(soc);
  355. }
  356. #if defined(FEATURE_TSO)
  357. /**
  358. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  359. *
  360. * @soc - core txrx main context
  361. * @seg_desc - tso segment descriptor
  362. * @num_seg_desc - tso number segment descriptor
  363. */
  364. static void dp_tx_tso_unmap_segment(
  365. struct dp_soc *soc,
  366. struct qdf_tso_seg_elem_t *seg_desc,
  367. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  368. {
  369. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  370. if (qdf_unlikely(!seg_desc)) {
  371. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  372. __func__, __LINE__);
  373. qdf_assert(0);
  374. } else if (qdf_unlikely(!num_seg_desc)) {
  375. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  376. __func__, __LINE__);
  377. qdf_assert(0);
  378. } else {
  379. bool is_last_seg;
  380. /* no tso segment left to do dma unmap */
  381. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  382. return;
  383. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  384. true : false;
  385. qdf_nbuf_unmap_tso_segment(soc->osdev,
  386. seg_desc, is_last_seg);
  387. num_seg_desc->num_seg.tso_cmn_num_seg--;
  388. }
  389. }
  390. /**
  391. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  392. * back to the freelist
  393. *
  394. * @soc - soc device handle
  395. * @tx_desc - Tx software descriptor
  396. */
  397. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  398. struct dp_tx_desc_s *tx_desc)
  399. {
  400. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  401. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  402. dp_tx_err("SO desc is NULL!");
  403. qdf_assert(0);
  404. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  405. dp_tx_err("TSO num desc is NULL!");
  406. qdf_assert(0);
  407. } else {
  408. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  409. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  410. msdu_ext_desc->tso_num_desc;
  411. /* Add the tso num segment into the free list */
  412. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  413. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  414. tx_desc->msdu_ext_desc->
  415. tso_num_desc);
  416. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  417. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  418. }
  419. /* Add the tso segment into the free list*/
  420. dp_tx_tso_desc_free(soc,
  421. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  422. tso_desc);
  423. tx_desc->msdu_ext_desc->tso_desc = NULL;
  424. }
  425. }
  426. #else
  427. static void dp_tx_tso_unmap_segment(
  428. struct dp_soc *soc,
  429. struct qdf_tso_seg_elem_t *seg_desc,
  430. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  431. {
  432. }
  433. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  434. struct dp_tx_desc_s *tx_desc)
  435. {
  436. }
  437. #endif
  438. /**
  439. * dp_tx_desc_release() - Release Tx Descriptor
  440. * @tx_desc : Tx Descriptor
  441. * @desc_pool_id: Descriptor Pool ID
  442. *
  443. * Deallocate all resources attached to Tx descriptor and free the Tx
  444. * descriptor.
  445. *
  446. * Return:
  447. */
  448. void
  449. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  450. {
  451. struct dp_pdev *pdev = tx_desc->pdev;
  452. struct dp_soc *soc;
  453. uint8_t comp_status = 0;
  454. qdf_assert(pdev);
  455. soc = pdev->soc;
  456. dp_tx_outstanding_dec(pdev);
  457. if (tx_desc->msdu_ext_desc) {
  458. if (tx_desc->frm_type == dp_tx_frm_tso)
  459. dp_tx_tso_desc_release(soc, tx_desc);
  460. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  461. dp_tx_me_free_buf(tx_desc->pdev,
  462. tx_desc->msdu_ext_desc->me_buffer);
  463. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  464. }
  465. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  466. qdf_atomic_dec(&soc->num_tx_exception);
  467. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  468. tx_desc->buffer_src)
  469. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  470. soc->hal_soc);
  471. else
  472. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  473. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  474. tx_desc->id, comp_status,
  475. qdf_atomic_read(&pdev->num_tx_outstanding));
  476. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  477. return;
  478. }
  479. /**
  480. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  481. * @vdev: DP vdev Handle
  482. * @nbuf: skb
  483. * @msdu_info: msdu_info required to create HTT metadata
  484. *
  485. * Prepares and fills HTT metadata in the frame pre-header for special frames
  486. * that should be transmitted using varying transmit parameters.
  487. * There are 2 VDEV modes that currently needs this special metadata -
  488. * 1) Mesh Mode
  489. * 2) DSRC Mode
  490. *
  491. * Return: HTT metadata size
  492. *
  493. */
  494. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  495. struct dp_tx_msdu_info_s *msdu_info)
  496. {
  497. uint32_t *meta_data = msdu_info->meta_data;
  498. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  499. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  500. uint8_t htt_desc_size;
  501. /* Size rounded of multiple of 8 bytes */
  502. uint8_t htt_desc_size_aligned;
  503. uint8_t *hdr = NULL;
  504. /*
  505. * Metadata - HTT MSDU Extension header
  506. */
  507. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  508. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  509. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  510. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  511. meta_data[0])) {
  512. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  513. htt_desc_size_aligned)) {
  514. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  515. htt_desc_size_aligned);
  516. if (!nbuf) {
  517. /*
  518. * qdf_nbuf_realloc_headroom won't do skb_clone
  519. * as skb_realloc_headroom does. so, no free is
  520. * needed here.
  521. */
  522. DP_STATS_INC(vdev,
  523. tx_i.dropped.headroom_insufficient,
  524. 1);
  525. qdf_print(" %s[%d] skb_realloc_headroom failed",
  526. __func__, __LINE__);
  527. return 0;
  528. }
  529. }
  530. /* Fill and add HTT metaheader */
  531. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  532. if (!hdr) {
  533. dp_tx_err("Error in filling HTT metadata");
  534. return 0;
  535. }
  536. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  537. } else if (vdev->opmode == wlan_op_mode_ocb) {
  538. /* Todo - Add support for DSRC */
  539. }
  540. return htt_desc_size_aligned;
  541. }
  542. /**
  543. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  544. * @tso_seg: TSO segment to process
  545. * @ext_desc: Pointer to MSDU extension descriptor
  546. *
  547. * Return: void
  548. */
  549. #if defined(FEATURE_TSO)
  550. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  551. void *ext_desc)
  552. {
  553. uint8_t num_frag;
  554. uint32_t tso_flags;
  555. /*
  556. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  557. * tcp_flag_mask
  558. *
  559. * Checksum enable flags are set in TCL descriptor and not in Extension
  560. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  561. */
  562. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  563. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  564. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  565. tso_seg->tso_flags.ip_len);
  566. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  567. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  568. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  569. uint32_t lo = 0;
  570. uint32_t hi = 0;
  571. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  572. (tso_seg->tso_frags[num_frag].length));
  573. qdf_dmaaddr_to_32s(
  574. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  575. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  576. tso_seg->tso_frags[num_frag].length);
  577. }
  578. return;
  579. }
  580. #else
  581. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  582. void *ext_desc)
  583. {
  584. return;
  585. }
  586. #endif
  587. #if defined(FEATURE_TSO)
  588. /**
  589. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  590. * allocated and free them
  591. *
  592. * @soc: soc handle
  593. * @free_seg: list of tso segments
  594. * @msdu_info: msdu descriptor
  595. *
  596. * Return - void
  597. */
  598. static void dp_tx_free_tso_seg_list(
  599. struct dp_soc *soc,
  600. struct qdf_tso_seg_elem_t *free_seg,
  601. struct dp_tx_msdu_info_s *msdu_info)
  602. {
  603. struct qdf_tso_seg_elem_t *next_seg;
  604. while (free_seg) {
  605. next_seg = free_seg->next;
  606. dp_tx_tso_desc_free(soc,
  607. msdu_info->tx_queue.desc_pool_id,
  608. free_seg);
  609. free_seg = next_seg;
  610. }
  611. }
  612. /**
  613. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  614. * allocated and free them
  615. *
  616. * @soc: soc handle
  617. * @free_num_seg: list of tso number segments
  618. * @msdu_info: msdu descriptor
  619. * Return - void
  620. */
  621. static void dp_tx_free_tso_num_seg_list(
  622. struct dp_soc *soc,
  623. struct qdf_tso_num_seg_elem_t *free_num_seg,
  624. struct dp_tx_msdu_info_s *msdu_info)
  625. {
  626. struct qdf_tso_num_seg_elem_t *next_num_seg;
  627. while (free_num_seg) {
  628. next_num_seg = free_num_seg->next;
  629. dp_tso_num_seg_free(soc,
  630. msdu_info->tx_queue.desc_pool_id,
  631. free_num_seg);
  632. free_num_seg = next_num_seg;
  633. }
  634. }
  635. /**
  636. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  637. * do dma unmap for each segment
  638. *
  639. * @soc: soc handle
  640. * @free_seg: list of tso segments
  641. * @num_seg_desc: tso number segment descriptor
  642. *
  643. * Return - void
  644. */
  645. static void dp_tx_unmap_tso_seg_list(
  646. struct dp_soc *soc,
  647. struct qdf_tso_seg_elem_t *free_seg,
  648. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  649. {
  650. struct qdf_tso_seg_elem_t *next_seg;
  651. if (qdf_unlikely(!num_seg_desc)) {
  652. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  653. return;
  654. }
  655. while (free_seg) {
  656. next_seg = free_seg->next;
  657. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  658. free_seg = next_seg;
  659. }
  660. }
  661. #ifdef FEATURE_TSO_STATS
  662. /**
  663. * dp_tso_get_stats_idx: Retrieve the tso packet id
  664. * @pdev - pdev handle
  665. *
  666. * Return: id
  667. */
  668. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  669. {
  670. uint32_t stats_idx;
  671. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  672. % CDP_MAX_TSO_PACKETS);
  673. return stats_idx;
  674. }
  675. #else
  676. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  677. {
  678. return 0;
  679. }
  680. #endif /* FEATURE_TSO_STATS */
  681. /**
  682. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  683. * free the tso segments descriptor and
  684. * tso num segments descriptor
  685. *
  686. * @soc: soc handle
  687. * @msdu_info: msdu descriptor
  688. * @tso_seg_unmap: flag to show if dma unmap is necessary
  689. *
  690. * Return - void
  691. */
  692. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  693. struct dp_tx_msdu_info_s *msdu_info,
  694. bool tso_seg_unmap)
  695. {
  696. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  697. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  698. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  699. tso_info->tso_num_seg_list;
  700. /* do dma unmap for each segment */
  701. if (tso_seg_unmap)
  702. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  703. /* free all tso number segment descriptor though looks only have 1 */
  704. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  705. /* free all tso segment descriptor */
  706. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  707. }
  708. /**
  709. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  710. * @vdev: virtual device handle
  711. * @msdu: network buffer
  712. * @msdu_info: meta data associated with the msdu
  713. *
  714. * Return: QDF_STATUS_SUCCESS success
  715. */
  716. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  717. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  718. {
  719. struct qdf_tso_seg_elem_t *tso_seg;
  720. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  721. struct dp_soc *soc = vdev->pdev->soc;
  722. struct dp_pdev *pdev = vdev->pdev;
  723. struct qdf_tso_info_t *tso_info;
  724. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  725. tso_info = &msdu_info->u.tso_info;
  726. tso_info->curr_seg = NULL;
  727. tso_info->tso_seg_list = NULL;
  728. tso_info->num_segs = num_seg;
  729. msdu_info->frm_type = dp_tx_frm_tso;
  730. tso_info->tso_num_seg_list = NULL;
  731. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  732. while (num_seg) {
  733. tso_seg = dp_tx_tso_desc_alloc(
  734. soc, msdu_info->tx_queue.desc_pool_id);
  735. if (tso_seg) {
  736. tso_seg->next = tso_info->tso_seg_list;
  737. tso_info->tso_seg_list = tso_seg;
  738. num_seg--;
  739. } else {
  740. dp_err_rl("Failed to alloc tso seg desc");
  741. DP_STATS_INC_PKT(vdev->pdev,
  742. tso_stats.tso_no_mem_dropped, 1,
  743. qdf_nbuf_len(msdu));
  744. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  745. return QDF_STATUS_E_NOMEM;
  746. }
  747. }
  748. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  749. tso_num_seg = dp_tso_num_seg_alloc(soc,
  750. msdu_info->tx_queue.desc_pool_id);
  751. if (tso_num_seg) {
  752. tso_num_seg->next = tso_info->tso_num_seg_list;
  753. tso_info->tso_num_seg_list = tso_num_seg;
  754. } else {
  755. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  756. __func__);
  757. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  758. return QDF_STATUS_E_NOMEM;
  759. }
  760. msdu_info->num_seg =
  761. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  762. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  763. msdu_info->num_seg);
  764. if (!(msdu_info->num_seg)) {
  765. /*
  766. * Free allocated TSO seg desc and number seg desc,
  767. * do unmap for segments if dma map has done.
  768. */
  769. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  770. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  771. return QDF_STATUS_E_INVAL;
  772. }
  773. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  774. msdu, 0, DP_TX_DESC_MAP);
  775. tso_info->curr_seg = tso_info->tso_seg_list;
  776. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  777. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  778. msdu, msdu_info->num_seg);
  779. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  780. tso_info->msdu_stats_idx);
  781. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  782. return QDF_STATUS_SUCCESS;
  783. }
  784. #else
  785. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  786. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  787. {
  788. return QDF_STATUS_E_NOMEM;
  789. }
  790. #endif
  791. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  792. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  793. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  794. /**
  795. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  796. * @vdev: DP Vdev handle
  797. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  798. * @desc_pool_id: Descriptor Pool ID
  799. *
  800. * Return:
  801. */
  802. static
  803. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  804. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  805. {
  806. uint8_t i;
  807. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  808. struct dp_tx_seg_info_s *seg_info;
  809. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  810. struct dp_soc *soc = vdev->pdev->soc;
  811. /* Allocate an extension descriptor */
  812. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  813. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  814. if (!msdu_ext_desc) {
  815. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  816. return NULL;
  817. }
  818. if (msdu_info->exception_fw &&
  819. qdf_unlikely(vdev->mesh_vdev)) {
  820. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  821. &msdu_info->meta_data[0],
  822. sizeof(struct htt_tx_msdu_desc_ext2_t));
  823. qdf_atomic_inc(&soc->num_tx_exception);
  824. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  825. }
  826. switch (msdu_info->frm_type) {
  827. case dp_tx_frm_sg:
  828. case dp_tx_frm_me:
  829. case dp_tx_frm_raw:
  830. seg_info = msdu_info->u.sg_info.curr_seg;
  831. /* Update the buffer pointers in MSDU Extension Descriptor */
  832. for (i = 0; i < seg_info->frag_cnt; i++) {
  833. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  834. seg_info->frags[i].paddr_lo,
  835. seg_info->frags[i].paddr_hi,
  836. seg_info->frags[i].len);
  837. }
  838. break;
  839. case dp_tx_frm_tso:
  840. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  841. &cached_ext_desc[0]);
  842. break;
  843. default:
  844. break;
  845. }
  846. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  847. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  848. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  849. msdu_ext_desc->vaddr);
  850. return msdu_ext_desc;
  851. }
  852. /**
  853. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  854. *
  855. * @skb: skb to be traced
  856. * @msdu_id: msdu_id of the packet
  857. * @vdev_id: vdev_id of the packet
  858. *
  859. * Return: None
  860. */
  861. #ifdef DP_DISABLE_TX_PKT_TRACE
  862. static void dp_tx_trace_pkt(struct dp_soc *soc,
  863. qdf_nbuf_t skb, uint16_t msdu_id,
  864. uint8_t vdev_id)
  865. {
  866. }
  867. #else
  868. static void dp_tx_trace_pkt(struct dp_soc *soc,
  869. qdf_nbuf_t skb, uint16_t msdu_id,
  870. uint8_t vdev_id)
  871. {
  872. if (dp_is_tput_high(soc))
  873. return;
  874. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  875. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  876. DPTRACE(qdf_dp_trace_ptr(skb,
  877. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  878. QDF_TRACE_DEFAULT_PDEV_ID,
  879. qdf_nbuf_data_addr(skb),
  880. sizeof(qdf_nbuf_data(skb)),
  881. msdu_id, vdev_id, 0));
  882. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  883. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  884. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  885. msdu_id, QDF_TX));
  886. }
  887. #endif
  888. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  889. /**
  890. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  891. * exception by the upper layer (OS_IF)
  892. * @soc: DP soc handle
  893. * @nbuf: packet to be transmitted
  894. *
  895. * Returns: 1 if the packet is marked as exception,
  896. * 0, if the packet is not marked as exception.
  897. */
  898. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  899. qdf_nbuf_t nbuf)
  900. {
  901. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  902. }
  903. #else
  904. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  905. qdf_nbuf_t nbuf)
  906. {
  907. return 0;
  908. }
  909. #endif
  910. /**
  911. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  912. * @vdev: DP vdev handle
  913. * @nbuf: skb
  914. * @desc_pool_id: Descriptor pool ID
  915. * @meta_data: Metadata to the fw
  916. * @tx_exc_metadata: Handle that holds exception path metadata
  917. * Allocate and prepare Tx descriptor with msdu information.
  918. *
  919. * Return: Pointer to Tx Descriptor on success,
  920. * NULL on failure
  921. */
  922. static
  923. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  924. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  925. struct dp_tx_msdu_info_s *msdu_info,
  926. struct cdp_tx_exception_metadata *tx_exc_metadata)
  927. {
  928. uint8_t align_pad;
  929. uint8_t is_exception = 0;
  930. uint8_t htt_hdr_size;
  931. struct dp_tx_desc_s *tx_desc;
  932. struct dp_pdev *pdev = vdev->pdev;
  933. struct dp_soc *soc = pdev->soc;
  934. if (dp_tx_limit_check(vdev))
  935. return NULL;
  936. /* Allocate software Tx descriptor */
  937. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  938. if (qdf_unlikely(!tx_desc)) {
  939. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  940. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  941. return NULL;
  942. }
  943. dp_tx_outstanding_inc(pdev);
  944. /* Initialize the SW tx descriptor */
  945. tx_desc->nbuf = nbuf;
  946. tx_desc->frm_type = dp_tx_frm_std;
  947. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  948. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  949. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  950. tx_desc->vdev_id = vdev->vdev_id;
  951. tx_desc->pdev = pdev;
  952. tx_desc->msdu_ext_desc = NULL;
  953. tx_desc->pkt_offset = 0;
  954. tx_desc->length = qdf_nbuf_headlen(nbuf);
  955. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  956. if (qdf_unlikely(vdev->multipass_en)) {
  957. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  958. goto failure;
  959. }
  960. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  961. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  962. is_exception = 1;
  963. /*
  964. * For special modes (vdev_type == ocb or mesh), data frames should be
  965. * transmitted using varying transmit parameters (tx spec) which include
  966. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  967. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  968. * These frames are sent as exception packets to firmware.
  969. *
  970. * HW requirement is that metadata should always point to a
  971. * 8-byte aligned address. So we add alignment pad to start of buffer.
  972. * HTT Metadata should be ensured to be multiple of 8-bytes,
  973. * to get 8-byte aligned start address along with align_pad added
  974. *
  975. * |-----------------------------|
  976. * | |
  977. * |-----------------------------| <-----Buffer Pointer Address given
  978. * | | ^ in HW descriptor (aligned)
  979. * | HTT Metadata | |
  980. * | | |
  981. * | | | Packet Offset given in descriptor
  982. * | | |
  983. * |-----------------------------| |
  984. * | Alignment Pad | v
  985. * |-----------------------------| <----- Actual buffer start address
  986. * | SKB Data | (Unaligned)
  987. * | |
  988. * | |
  989. * | |
  990. * | |
  991. * | |
  992. * |-----------------------------|
  993. */
  994. if (qdf_unlikely((msdu_info->exception_fw)) ||
  995. (vdev->opmode == wlan_op_mode_ocb) ||
  996. (tx_exc_metadata &&
  997. tx_exc_metadata->is_tx_sniffer)) {
  998. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  999. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1000. DP_STATS_INC(vdev,
  1001. tx_i.dropped.headroom_insufficient, 1);
  1002. goto failure;
  1003. }
  1004. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1005. dp_tx_err("qdf_nbuf_push_head failed");
  1006. goto failure;
  1007. }
  1008. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1009. msdu_info);
  1010. if (htt_hdr_size == 0)
  1011. goto failure;
  1012. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1013. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1014. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1015. is_exception = 1;
  1016. tx_desc->length -= tx_desc->pkt_offset;
  1017. }
  1018. #if !TQM_BYPASS_WAR
  1019. if (is_exception || tx_exc_metadata)
  1020. #endif
  1021. {
  1022. /* Temporary WAR due to TQM VP issues */
  1023. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1024. qdf_atomic_inc(&soc->num_tx_exception);
  1025. }
  1026. return tx_desc;
  1027. failure:
  1028. dp_tx_desc_release(tx_desc, desc_pool_id);
  1029. return NULL;
  1030. }
  1031. /**
  1032. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1033. * @vdev: DP vdev handle
  1034. * @nbuf: skb
  1035. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1036. * @desc_pool_id : Descriptor Pool ID
  1037. *
  1038. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1039. * information. For frames wth fragments, allocate and prepare
  1040. * an MSDU extension descriptor
  1041. *
  1042. * Return: Pointer to Tx Descriptor on success,
  1043. * NULL on failure
  1044. */
  1045. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1046. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1047. uint8_t desc_pool_id)
  1048. {
  1049. struct dp_tx_desc_s *tx_desc;
  1050. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1051. struct dp_pdev *pdev = vdev->pdev;
  1052. struct dp_soc *soc = pdev->soc;
  1053. if (dp_tx_limit_check(vdev))
  1054. return NULL;
  1055. /* Allocate software Tx descriptor */
  1056. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1057. if (!tx_desc) {
  1058. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1059. return NULL;
  1060. }
  1061. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1062. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1063. dp_tx_outstanding_inc(pdev);
  1064. /* Initialize the SW tx descriptor */
  1065. tx_desc->nbuf = nbuf;
  1066. tx_desc->frm_type = msdu_info->frm_type;
  1067. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1068. tx_desc->vdev_id = vdev->vdev_id;
  1069. tx_desc->pdev = pdev;
  1070. tx_desc->pkt_offset = 0;
  1071. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1072. /* Handle scattered frames - TSO/SG/ME */
  1073. /* Allocate and prepare an extension descriptor for scattered frames */
  1074. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1075. if (!msdu_ext_desc) {
  1076. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1077. goto failure;
  1078. }
  1079. #if TQM_BYPASS_WAR
  1080. /* Temporary WAR due to TQM VP issues */
  1081. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1082. qdf_atomic_inc(&soc->num_tx_exception);
  1083. #endif
  1084. if (qdf_unlikely(msdu_info->exception_fw))
  1085. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1086. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1087. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1088. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1089. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1090. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1091. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1092. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1093. else
  1094. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1095. return tx_desc;
  1096. failure:
  1097. dp_tx_desc_release(tx_desc, desc_pool_id);
  1098. return NULL;
  1099. }
  1100. /**
  1101. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1102. * @vdev: DP vdev handle
  1103. * @nbuf: buffer pointer
  1104. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1105. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1106. * descriptor
  1107. *
  1108. * Return:
  1109. */
  1110. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1111. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1112. {
  1113. qdf_nbuf_t curr_nbuf = NULL;
  1114. uint16_t total_len = 0;
  1115. qdf_dma_addr_t paddr;
  1116. int32_t i;
  1117. int32_t mapped_buf_num = 0;
  1118. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1119. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1120. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1121. /* Continue only if frames are of DATA type */
  1122. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1123. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1124. dp_tx_debug("Pkt. recd is of not data type");
  1125. goto error;
  1126. }
  1127. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1128. if (vdev->raw_mode_war &&
  1129. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1130. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1131. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1132. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1133. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1134. /*
  1135. * Number of nbuf's must not exceed the size of the frags
  1136. * array in seg_info.
  1137. */
  1138. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1139. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1140. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1141. goto error;
  1142. }
  1143. if (QDF_STATUS_SUCCESS !=
  1144. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1145. curr_nbuf,
  1146. QDF_DMA_TO_DEVICE,
  1147. curr_nbuf->len)) {
  1148. dp_tx_err("%s dma map error ", __func__);
  1149. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1150. goto error;
  1151. }
  1152. /* Update the count of mapped nbuf's */
  1153. mapped_buf_num++;
  1154. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1155. seg_info->frags[i].paddr_lo = paddr;
  1156. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1157. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1158. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1159. total_len += qdf_nbuf_len(curr_nbuf);
  1160. }
  1161. seg_info->frag_cnt = i;
  1162. seg_info->total_len = total_len;
  1163. seg_info->next = NULL;
  1164. sg_info->curr_seg = seg_info;
  1165. msdu_info->frm_type = dp_tx_frm_raw;
  1166. msdu_info->num_seg = 1;
  1167. return nbuf;
  1168. error:
  1169. i = 0;
  1170. while (nbuf) {
  1171. curr_nbuf = nbuf;
  1172. if (i < mapped_buf_num) {
  1173. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1174. QDF_DMA_TO_DEVICE,
  1175. curr_nbuf->len);
  1176. i++;
  1177. }
  1178. nbuf = qdf_nbuf_next(nbuf);
  1179. qdf_nbuf_free(curr_nbuf);
  1180. }
  1181. return NULL;
  1182. }
  1183. /**
  1184. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1185. * @soc: DP soc handle
  1186. * @nbuf: Buffer pointer
  1187. *
  1188. * unmap the chain of nbufs that belong to this RAW frame.
  1189. *
  1190. * Return: None
  1191. */
  1192. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1193. qdf_nbuf_t nbuf)
  1194. {
  1195. qdf_nbuf_t cur_nbuf = nbuf;
  1196. do {
  1197. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1198. QDF_DMA_TO_DEVICE,
  1199. cur_nbuf->len);
  1200. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1201. } while (cur_nbuf);
  1202. }
  1203. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1204. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1205. qdf_nbuf_t nbuf)
  1206. {
  1207. qdf_nbuf_t nbuf_local;
  1208. struct dp_vdev *vdev_local = vdev_hdl;
  1209. do {
  1210. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1211. break;
  1212. nbuf_local = nbuf;
  1213. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1214. htt_cmn_pkt_type_raw))
  1215. break;
  1216. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1217. break;
  1218. else if (qdf_nbuf_is_tso((nbuf_local)))
  1219. break;
  1220. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1221. (nbuf_local),
  1222. NULL, 1, 0);
  1223. } while (0);
  1224. }
  1225. #endif
  1226. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1227. /**
  1228. * dp_tx_update_stats() - Update soc level tx stats
  1229. * @soc: DP soc handle
  1230. * @tx_desc: TX descriptor reference
  1231. * @ring_id: TCL ring id
  1232. *
  1233. * Returns: none
  1234. */
  1235. void dp_tx_update_stats(struct dp_soc *soc,
  1236. struct dp_tx_desc_s *tx_desc,
  1237. uint8_t ring_id)
  1238. {
  1239. uint32_t stats_len = 0;
  1240. if (tx_desc->frm_type == dp_tx_frm_tso)
  1241. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1242. else
  1243. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1244. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1245. }
  1246. int
  1247. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1248. struct dp_tx_desc_s *tx_desc,
  1249. uint8_t tid,
  1250. struct dp_tx_msdu_info_s *msdu_info,
  1251. uint8_t ring_id)
  1252. {
  1253. struct dp_swlm *swlm = &soc->swlm;
  1254. union swlm_data swlm_query_data;
  1255. struct dp_swlm_tcl_data tcl_data;
  1256. QDF_STATUS status;
  1257. int ret;
  1258. if (!swlm->is_enabled)
  1259. return msdu_info->skip_hp_update;
  1260. tcl_data.nbuf = tx_desc->nbuf;
  1261. tcl_data.tid = tid;
  1262. tcl_data.ring_id = ring_id;
  1263. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1264. tcl_data.pkt_len =
  1265. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1266. } else {
  1267. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1268. }
  1269. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1270. swlm_query_data.tcl_data = &tcl_data;
  1271. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1272. if (QDF_IS_STATUS_ERROR(status)) {
  1273. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1274. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1275. return 0;
  1276. }
  1277. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1278. if (ret) {
  1279. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1280. } else {
  1281. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1282. }
  1283. return ret;
  1284. }
  1285. void
  1286. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1287. int coalesce)
  1288. {
  1289. if (coalesce)
  1290. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1291. else
  1292. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1293. }
  1294. static inline void
  1295. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1296. {
  1297. if (((i + 1) < msdu_info->num_seg))
  1298. msdu_info->skip_hp_update = 1;
  1299. else
  1300. msdu_info->skip_hp_update = 0;
  1301. }
  1302. static inline void
  1303. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1304. {
  1305. hal_ring_handle_t hal_ring_hdl =
  1306. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1307. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1308. dp_err("Fillmore: SRNG access start failed");
  1309. return;
  1310. }
  1311. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1312. }
  1313. static inline void
  1314. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1315. QDF_STATUS status,
  1316. struct dp_tx_msdu_info_s *msdu_info)
  1317. {
  1318. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1319. dp_flush_tcp_hp(soc,
  1320. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1321. }
  1322. }
  1323. #else
  1324. static inline void
  1325. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1326. {
  1327. }
  1328. static inline void
  1329. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1330. QDF_STATUS status,
  1331. struct dp_tx_msdu_info_s *msdu_info)
  1332. {
  1333. }
  1334. #endif
  1335. #ifdef FEATURE_RUNTIME_PM
  1336. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1337. {
  1338. return qdf_atomic_read(&soc->rtpm_high_tput_flag);
  1339. }
  1340. /**
  1341. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1342. * @soc: Datapath soc handle
  1343. * @hal_ring_hdl: HAL ring handle
  1344. * @coalesce: Coalesce the current write or not
  1345. *
  1346. * Wrapper for HAL ring access end for data transmission for
  1347. * FEATURE_RUNTIME_PM
  1348. *
  1349. * Returns: none
  1350. */
  1351. void
  1352. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1353. hal_ring_handle_t hal_ring_hdl,
  1354. int coalesce)
  1355. {
  1356. int ret;
  1357. /*
  1358. * Avoid runtime get and put APIs under high throughput scenarios.
  1359. */
  1360. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1361. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1362. return;
  1363. }
  1364. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1365. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1366. if (hif_system_pm_state_check(soc->hif_handle)) {
  1367. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1368. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1369. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1370. } else {
  1371. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1372. }
  1373. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1374. } else {
  1375. dp_runtime_get(soc);
  1376. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1377. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1378. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1379. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1380. dp_runtime_put(soc);
  1381. }
  1382. }
  1383. #else
  1384. #ifdef DP_POWER_SAVE
  1385. void
  1386. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1387. hal_ring_handle_t hal_ring_hdl,
  1388. int coalesce)
  1389. {
  1390. if (hif_system_pm_state_check(soc->hif_handle)) {
  1391. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1392. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1393. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1394. } else {
  1395. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1396. }
  1397. }
  1398. #endif
  1399. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1400. {
  1401. return 0;
  1402. }
  1403. #endif
  1404. /**
  1405. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1406. * @vdev: DP vdev handle
  1407. * @nbuf: skb
  1408. *
  1409. * Extract the DSCP or PCP information from frame and map into TID value.
  1410. *
  1411. * Return: void
  1412. */
  1413. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1414. struct dp_tx_msdu_info_s *msdu_info)
  1415. {
  1416. uint8_t tos = 0, dscp_tid_override = 0;
  1417. uint8_t *hdr_ptr, *L3datap;
  1418. uint8_t is_mcast = 0;
  1419. qdf_ether_header_t *eh = NULL;
  1420. qdf_ethervlan_header_t *evh = NULL;
  1421. uint16_t ether_type;
  1422. qdf_llc_t *llcHdr;
  1423. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1424. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1425. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1426. eh = (qdf_ether_header_t *)nbuf->data;
  1427. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1428. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1429. } else {
  1430. qdf_dot3_qosframe_t *qos_wh =
  1431. (qdf_dot3_qosframe_t *) nbuf->data;
  1432. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1433. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1434. return;
  1435. }
  1436. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1437. ether_type = eh->ether_type;
  1438. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1439. /*
  1440. * Check if packet is dot3 or eth2 type.
  1441. */
  1442. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1443. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1444. sizeof(*llcHdr));
  1445. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1446. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1447. sizeof(*llcHdr);
  1448. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1449. + sizeof(*llcHdr) +
  1450. sizeof(qdf_net_vlanhdr_t));
  1451. } else {
  1452. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1453. sizeof(*llcHdr);
  1454. }
  1455. } else {
  1456. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1457. evh = (qdf_ethervlan_header_t *) eh;
  1458. ether_type = evh->ether_type;
  1459. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1460. }
  1461. }
  1462. /*
  1463. * Find priority from IP TOS DSCP field
  1464. */
  1465. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1466. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1467. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1468. /* Only for unicast frames */
  1469. if (!is_mcast) {
  1470. /* send it on VO queue */
  1471. msdu_info->tid = DP_VO_TID;
  1472. }
  1473. } else {
  1474. /*
  1475. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1476. * from TOS byte.
  1477. */
  1478. tos = ip->ip_tos;
  1479. dscp_tid_override = 1;
  1480. }
  1481. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1482. /* TODO
  1483. * use flowlabel
  1484. *igmpmld cases to be handled in phase 2
  1485. */
  1486. unsigned long ver_pri_flowlabel;
  1487. unsigned long pri;
  1488. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1489. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1490. DP_IPV6_PRIORITY_SHIFT;
  1491. tos = pri;
  1492. dscp_tid_override = 1;
  1493. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1494. msdu_info->tid = DP_VO_TID;
  1495. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1496. /* Only for unicast frames */
  1497. if (!is_mcast) {
  1498. /* send ucast arp on VO queue */
  1499. msdu_info->tid = DP_VO_TID;
  1500. }
  1501. }
  1502. /*
  1503. * Assign all MCAST packets to BE
  1504. */
  1505. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1506. if (is_mcast) {
  1507. tos = 0;
  1508. dscp_tid_override = 1;
  1509. }
  1510. }
  1511. if (dscp_tid_override == 1) {
  1512. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1513. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1514. }
  1515. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1516. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1517. return;
  1518. }
  1519. /**
  1520. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1521. * @vdev: DP vdev handle
  1522. * @nbuf: skb
  1523. *
  1524. * Software based TID classification is required when more than 2 DSCP-TID
  1525. * mapping tables are needed.
  1526. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1527. *
  1528. * Return: void
  1529. */
  1530. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1531. struct dp_tx_msdu_info_s *msdu_info)
  1532. {
  1533. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1534. /*
  1535. * skip_sw_tid_classification flag will set in below cases-
  1536. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1537. * 2. hlos_tid_override enabled for vdev
  1538. * 3. mesh mode enabled for vdev
  1539. */
  1540. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1541. /* Update tid in msdu_info from skb priority */
  1542. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1543. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1544. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1545. if (tid == DP_TX_INVALID_QOS_TAG)
  1546. return;
  1547. msdu_info->tid = tid;
  1548. return;
  1549. }
  1550. return;
  1551. }
  1552. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1553. }
  1554. #ifdef FEATURE_WLAN_TDLS
  1555. /**
  1556. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1557. * @soc: datapath SOC
  1558. * @vdev: datapath vdev
  1559. * @tx_desc: TX descriptor
  1560. *
  1561. * Return: None
  1562. */
  1563. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1564. struct dp_vdev *vdev,
  1565. struct dp_tx_desc_s *tx_desc)
  1566. {
  1567. if (vdev) {
  1568. if (vdev->is_tdls_frame) {
  1569. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1570. vdev->is_tdls_frame = false;
  1571. }
  1572. }
  1573. }
  1574. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1575. {
  1576. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1577. switch (soc->arch_id) {
  1578. case CDP_ARCH_TYPE_LI:
  1579. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1580. break;
  1581. case CDP_ARCH_TYPE_BE:
  1582. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1583. break;
  1584. default:
  1585. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1586. QDF_BUG(0);
  1587. }
  1588. return tx_status;
  1589. }
  1590. /**
  1591. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1592. * @soc: dp_soc handle
  1593. * @tx_desc: TX descriptor
  1594. * @vdev: datapath vdev handle
  1595. *
  1596. * Return: None
  1597. */
  1598. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1599. struct dp_tx_desc_s *tx_desc)
  1600. {
  1601. uint8_t tx_status = 0;
  1602. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1603. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1604. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1605. DP_MOD_ID_TDLS);
  1606. if (qdf_unlikely(!vdev)) {
  1607. dp_err_rl("vdev is null!");
  1608. goto error;
  1609. }
  1610. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1611. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1612. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1613. if (vdev->tx_non_std_data_callback.func) {
  1614. qdf_nbuf_set_next(nbuf, NULL);
  1615. vdev->tx_non_std_data_callback.func(
  1616. vdev->tx_non_std_data_callback.ctxt,
  1617. nbuf, tx_status);
  1618. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1619. return;
  1620. } else {
  1621. dp_err_rl("callback func is null");
  1622. }
  1623. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1624. error:
  1625. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1626. qdf_nbuf_free(nbuf);
  1627. }
  1628. /**
  1629. * dp_tx_msdu_single_map() - do nbuf map
  1630. * @vdev: DP vdev handle
  1631. * @tx_desc: DP TX descriptor pointer
  1632. * @nbuf: skb pointer
  1633. *
  1634. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1635. * operation done in other component.
  1636. *
  1637. * Return: QDF_STATUS
  1638. */
  1639. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1640. struct dp_tx_desc_s *tx_desc,
  1641. qdf_nbuf_t nbuf)
  1642. {
  1643. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1644. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1645. nbuf,
  1646. QDF_DMA_TO_DEVICE,
  1647. nbuf->len);
  1648. else
  1649. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1650. QDF_DMA_TO_DEVICE);
  1651. }
  1652. #else
  1653. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1654. struct dp_vdev *vdev,
  1655. struct dp_tx_desc_s *tx_desc)
  1656. {
  1657. }
  1658. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1659. struct dp_tx_desc_s *tx_desc)
  1660. {
  1661. }
  1662. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1663. struct dp_tx_desc_s *tx_desc,
  1664. qdf_nbuf_t nbuf)
  1665. {
  1666. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1667. nbuf,
  1668. QDF_DMA_TO_DEVICE,
  1669. nbuf->len);
  1670. }
  1671. #endif
  1672. static inline
  1673. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1674. struct dp_tx_desc_s *tx_desc,
  1675. qdf_nbuf_t nbuf)
  1676. {
  1677. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1678. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1679. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1680. return 0;
  1681. return qdf_nbuf_mapped_paddr_get(nbuf);
  1682. }
  1683. static inline
  1684. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1685. {
  1686. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1687. desc->nbuf,
  1688. desc->dma_addr,
  1689. QDF_DMA_TO_DEVICE,
  1690. desc->length);
  1691. }
  1692. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1693. static inline
  1694. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1695. struct dp_tx_desc_s *tx_desc,
  1696. qdf_nbuf_t nbuf)
  1697. {
  1698. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1699. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1700. (void *)(nbuf->data + nbuf->len));
  1701. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1702. } else {
  1703. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1704. }
  1705. }
  1706. static inline
  1707. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1708. struct dp_tx_desc_s *desc)
  1709. {
  1710. if (qdf_unlikely(!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)))
  1711. return dp_tx_nbuf_unmap_regular(soc, desc);
  1712. }
  1713. #else
  1714. static inline
  1715. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1716. struct dp_tx_desc_s *tx_desc,
  1717. qdf_nbuf_t nbuf)
  1718. {
  1719. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1720. }
  1721. static inline
  1722. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1723. struct dp_tx_desc_s *desc)
  1724. {
  1725. return dp_tx_nbuf_unmap_regular(soc, desc);
  1726. }
  1727. #endif
  1728. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1729. static inline
  1730. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1731. {
  1732. dp_tx_nbuf_unmap(soc, desc);
  1733. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1734. }
  1735. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1736. {
  1737. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1738. dp_tx_nbuf_unmap(soc, desc);
  1739. }
  1740. #else
  1741. static inline
  1742. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1743. {
  1744. }
  1745. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1746. {
  1747. dp_tx_nbuf_unmap(soc, desc);
  1748. }
  1749. #endif
  1750. #ifdef MESH_MODE_SUPPORT
  1751. /**
  1752. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1753. * @soc: datapath SOC
  1754. * @vdev: datapath vdev
  1755. * @tx_desc: TX descriptor
  1756. *
  1757. * Return: None
  1758. */
  1759. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1760. struct dp_vdev *vdev,
  1761. struct dp_tx_desc_s *tx_desc)
  1762. {
  1763. if (qdf_unlikely(vdev->mesh_vdev))
  1764. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1765. }
  1766. /**
  1767. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1768. * @soc: dp_soc handle
  1769. * @tx_desc: TX descriptor
  1770. * @vdev: datapath vdev handle
  1771. *
  1772. * Return: None
  1773. */
  1774. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1775. struct dp_tx_desc_s *tx_desc)
  1776. {
  1777. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1778. struct dp_vdev *vdev = NULL;
  1779. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1780. qdf_nbuf_free(nbuf);
  1781. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1782. } else {
  1783. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1784. DP_MOD_ID_MESH);
  1785. if (vdev && vdev->osif_tx_free_ext)
  1786. vdev->osif_tx_free_ext((nbuf));
  1787. else
  1788. qdf_nbuf_free(nbuf);
  1789. if (vdev)
  1790. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1791. }
  1792. }
  1793. #else
  1794. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1795. struct dp_vdev *vdev,
  1796. struct dp_tx_desc_s *tx_desc)
  1797. {
  1798. }
  1799. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1800. struct dp_tx_desc_s *tx_desc)
  1801. {
  1802. }
  1803. #endif
  1804. /**
  1805. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1806. * @vdev: DP vdev handle
  1807. * @nbuf: skb
  1808. *
  1809. * Return: 1 if frame needs to be dropped else 0
  1810. */
  1811. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1812. {
  1813. struct dp_pdev *pdev = NULL;
  1814. struct dp_ast_entry *src_ast_entry = NULL;
  1815. struct dp_ast_entry *dst_ast_entry = NULL;
  1816. struct dp_soc *soc = NULL;
  1817. qdf_assert(vdev);
  1818. pdev = vdev->pdev;
  1819. qdf_assert(pdev);
  1820. soc = pdev->soc;
  1821. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1822. (soc, dstmac, vdev->pdev->pdev_id);
  1823. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1824. (soc, srcmac, vdev->pdev->pdev_id);
  1825. if (dst_ast_entry && src_ast_entry) {
  1826. if (dst_ast_entry->peer_id ==
  1827. src_ast_entry->peer_id)
  1828. return 1;
  1829. }
  1830. return 0;
  1831. }
  1832. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1833. defined(WLAN_MCAST_MLO)
  1834. /* MLO peer id for reinject*/
  1835. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1836. /* MLO vdev id inc offset */
  1837. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1838. static inline void
  1839. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1840. {
  1841. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1842. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1843. qdf_atomic_inc(&soc->num_tx_exception);
  1844. }
  1845. }
  1846. static inline void
  1847. dp_tx_update_mcast_param(uint16_t peer_id,
  1848. uint16_t *htt_tcl_metadata,
  1849. struct dp_vdev *vdev,
  1850. struct dp_tx_msdu_info_s *msdu_info)
  1851. {
  1852. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1853. *htt_tcl_metadata = 0;
  1854. DP_TX_TCL_METADATA_TYPE_SET(
  1855. *htt_tcl_metadata,
  1856. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1857. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1858. msdu_info->gsn);
  1859. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1860. if (qdf_unlikely(vdev->nawds_enabled))
  1861. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  1862. *htt_tcl_metadata, 1);
  1863. } else {
  1864. msdu_info->vdev_id = vdev->vdev_id;
  1865. }
  1866. }
  1867. #else
  1868. static inline void
  1869. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  1870. {
  1871. }
  1872. static inline void
  1873. dp_tx_update_mcast_param(uint16_t peer_id,
  1874. uint16_t *htt_tcl_metadata,
  1875. struct dp_vdev *vdev,
  1876. struct dp_tx_msdu_info_s *msdu_info)
  1877. {
  1878. }
  1879. #endif
  1880. /**
  1881. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1882. * @vdev: DP vdev handle
  1883. * @nbuf: skb
  1884. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1885. * @meta_data: Metadata to the fw
  1886. * @tx_q: Tx queue to be used for this Tx frame
  1887. * @peer_id: peer_id of the peer in case of NAWDS frames
  1888. * @tx_exc_metadata: Handle that holds exception path metadata
  1889. *
  1890. * Return: NULL on success,
  1891. * nbuf when it fails to send
  1892. */
  1893. qdf_nbuf_t
  1894. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1895. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1896. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1897. {
  1898. struct dp_pdev *pdev = vdev->pdev;
  1899. struct dp_soc *soc = pdev->soc;
  1900. struct dp_tx_desc_s *tx_desc;
  1901. QDF_STATUS status;
  1902. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1903. uint16_t htt_tcl_metadata = 0;
  1904. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1905. uint8_t tid = msdu_info->tid;
  1906. struct cdp_tid_tx_stats *tid_stats = NULL;
  1907. qdf_dma_addr_t paddr;
  1908. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1909. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1910. msdu_info, tx_exc_metadata);
  1911. if (!tx_desc) {
  1912. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1913. vdev, tx_q->desc_pool_id);
  1914. drop_code = TX_DESC_ERR;
  1915. goto fail_return;
  1916. }
  1917. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1918. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1919. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1920. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1921. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1922. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1923. DP_TCL_METADATA_TYPE_PEER_BASED);
  1924. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1925. peer_id);
  1926. dp_tx_bypass_reinjection(soc, tx_desc);
  1927. } else
  1928. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1929. if (msdu_info->exception_fw)
  1930. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1931. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1932. !pdev->enhanced_stats_en);
  1933. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1934. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  1935. if (!paddr) {
  1936. /* Handle failure */
  1937. dp_err("qdf_nbuf_map failed");
  1938. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1939. drop_code = TX_DMA_MAP_ERR;
  1940. goto release_desc;
  1941. }
  1942. tx_desc->dma_addr = paddr;
  1943. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1944. tx_desc->id, DP_TX_DESC_MAP);
  1945. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  1946. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1947. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1948. htt_tcl_metadata,
  1949. tx_exc_metadata, msdu_info);
  1950. if (status != QDF_STATUS_SUCCESS) {
  1951. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1952. tx_desc, tx_q->ring_id);
  1953. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1954. tx_desc->id, DP_TX_DESC_UNMAP);
  1955. dp_tx_nbuf_unmap(soc, tx_desc);
  1956. drop_code = TX_HW_ENQUEUE;
  1957. goto release_desc;
  1958. }
  1959. return NULL;
  1960. release_desc:
  1961. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1962. fail_return:
  1963. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1964. tid_stats = &pdev->stats.tid_stats.
  1965. tid_tx_stats[tx_q->ring_id][tid];
  1966. tid_stats->swdrop_cnt[drop_code]++;
  1967. return nbuf;
  1968. }
  1969. /**
  1970. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1971. * @soc: Soc handle
  1972. * @desc: software Tx descriptor to be processed
  1973. *
  1974. * Return: none
  1975. */
  1976. void dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1977. {
  1978. qdf_nbuf_t nbuf = desc->nbuf;
  1979. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1980. /* nbuf already freed in vdev detach path */
  1981. if (!nbuf)
  1982. return;
  1983. /* If it is TDLS mgmt, don't unmap or free the frame */
  1984. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1985. return dp_non_std_htt_tx_comp_free_buff(soc, desc);
  1986. /* 0 : MSDU buffer, 1 : MLE */
  1987. if (desc->msdu_ext_desc) {
  1988. /* TSO free */
  1989. if (hal_tx_ext_desc_get_tso_enable(
  1990. desc->msdu_ext_desc->vaddr)) {
  1991. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1992. desc->id, DP_TX_COMP_MSDU_EXT);
  1993. dp_tx_tso_seg_history_add(soc,
  1994. desc->msdu_ext_desc->tso_desc,
  1995. desc->nbuf, desc->id, type);
  1996. /* unmap eash TSO seg before free the nbuf */
  1997. dp_tx_tso_unmap_segment(soc,
  1998. desc->msdu_ext_desc->tso_desc,
  1999. desc->msdu_ext_desc->
  2000. tso_num_desc);
  2001. qdf_nbuf_free(nbuf);
  2002. return;
  2003. }
  2004. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2005. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2006. qdf_dma_addr_t iova;
  2007. uint32_t frag_len;
  2008. uint32_t i;
  2009. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2010. QDF_DMA_TO_DEVICE,
  2011. qdf_nbuf_headlen(nbuf));
  2012. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2013. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2014. &iova,
  2015. &frag_len);
  2016. if (!iova || !frag_len)
  2017. break;
  2018. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2019. QDF_DMA_TO_DEVICE);
  2020. }
  2021. qdf_nbuf_free(nbuf);
  2022. return;
  2023. }
  2024. }
  2025. /* If it's ME frame, dont unmap the cloned nbuf's */
  2026. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2027. goto nbuf_free;
  2028. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2029. dp_tx_unmap(soc, desc);
  2030. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2031. return dp_mesh_tx_comp_free_buff(soc, desc);
  2032. nbuf_free:
  2033. qdf_nbuf_free(nbuf);
  2034. }
  2035. /**
  2036. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2037. * @soc: DP soc handle
  2038. * @nbuf: skb
  2039. * @msdu_info: MSDU info
  2040. *
  2041. * Return: None
  2042. */
  2043. static inline void
  2044. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2045. struct dp_tx_msdu_info_s *msdu_info)
  2046. {
  2047. uint32_t cur_idx;
  2048. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2049. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2050. qdf_nbuf_headlen(nbuf));
  2051. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2052. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2053. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2054. seg->frags[cur_idx].paddr_hi) << 32),
  2055. seg->frags[cur_idx].len,
  2056. QDF_DMA_TO_DEVICE);
  2057. }
  2058. /**
  2059. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2060. * @vdev: DP vdev handle
  2061. * @nbuf: skb
  2062. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2063. *
  2064. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2065. *
  2066. * Return: NULL on success,
  2067. * nbuf when it fails to send
  2068. */
  2069. #if QDF_LOCK_STATS
  2070. noinline
  2071. #else
  2072. #endif
  2073. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2074. struct dp_tx_msdu_info_s *msdu_info)
  2075. {
  2076. uint32_t i;
  2077. struct dp_pdev *pdev = vdev->pdev;
  2078. struct dp_soc *soc = pdev->soc;
  2079. struct dp_tx_desc_s *tx_desc;
  2080. bool is_cce_classified = false;
  2081. QDF_STATUS status;
  2082. uint16_t htt_tcl_metadata = 0;
  2083. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2084. struct cdp_tid_tx_stats *tid_stats = NULL;
  2085. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2086. if (msdu_info->frm_type == dp_tx_frm_me)
  2087. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2088. i = 0;
  2089. /* Print statement to track i and num_seg */
  2090. /*
  2091. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2092. * descriptors using information in msdu_info
  2093. */
  2094. while (i < msdu_info->num_seg) {
  2095. /*
  2096. * Setup Tx descriptor for an MSDU, and MSDU extension
  2097. * descriptor
  2098. */
  2099. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2100. tx_q->desc_pool_id);
  2101. if (!tx_desc) {
  2102. if (msdu_info->frm_type == dp_tx_frm_me) {
  2103. prep_desc_fail++;
  2104. dp_tx_me_free_buf(pdev,
  2105. (void *)(msdu_info->u.sg_info
  2106. .curr_seg->frags[0].vaddr));
  2107. if (prep_desc_fail == msdu_info->num_seg) {
  2108. /*
  2109. * Unmap is needed only if descriptor
  2110. * preparation failed for all segments.
  2111. */
  2112. qdf_nbuf_unmap(soc->osdev,
  2113. msdu_info->u.sg_info.
  2114. curr_seg->nbuf,
  2115. QDF_DMA_TO_DEVICE);
  2116. }
  2117. /*
  2118. * Free the nbuf for the current segment
  2119. * and make it point to the next in the list.
  2120. * For me, there are as many segments as there
  2121. * are no of clients.
  2122. */
  2123. qdf_nbuf_free(msdu_info->u.sg_info
  2124. .curr_seg->nbuf);
  2125. if (msdu_info->u.sg_info.curr_seg->next) {
  2126. msdu_info->u.sg_info.curr_seg =
  2127. msdu_info->u.sg_info
  2128. .curr_seg->next;
  2129. nbuf = msdu_info->u.sg_info
  2130. .curr_seg->nbuf;
  2131. }
  2132. i++;
  2133. continue;
  2134. }
  2135. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2136. dp_tx_tso_seg_history_add(
  2137. soc,
  2138. msdu_info->u.tso_info.curr_seg,
  2139. nbuf, 0, DP_TX_DESC_UNMAP);
  2140. dp_tx_tso_unmap_segment(soc,
  2141. msdu_info->u.tso_info.
  2142. curr_seg,
  2143. msdu_info->u.tso_info.
  2144. tso_num_seg_list);
  2145. if (msdu_info->u.tso_info.curr_seg->next) {
  2146. msdu_info->u.tso_info.curr_seg =
  2147. msdu_info->u.tso_info.curr_seg->next;
  2148. i++;
  2149. continue;
  2150. }
  2151. }
  2152. if (msdu_info->frm_type == dp_tx_frm_sg)
  2153. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2154. goto done;
  2155. }
  2156. if (msdu_info->frm_type == dp_tx_frm_me) {
  2157. tx_desc->msdu_ext_desc->me_buffer =
  2158. (struct dp_tx_me_buf_t *)msdu_info->
  2159. u.sg_info.curr_seg->frags[0].vaddr;
  2160. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2161. }
  2162. if (is_cce_classified)
  2163. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2164. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2165. if (msdu_info->exception_fw) {
  2166. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2167. }
  2168. dp_tx_is_hp_update_required(i, msdu_info);
  2169. /*
  2170. * For frames with multiple segments (TSO, ME), jump to next
  2171. * segment.
  2172. */
  2173. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2174. if (msdu_info->u.tso_info.curr_seg->next) {
  2175. msdu_info->u.tso_info.curr_seg =
  2176. msdu_info->u.tso_info.curr_seg->next;
  2177. /*
  2178. * If this is a jumbo nbuf, then increment the
  2179. * number of nbuf users for each additional
  2180. * segment of the msdu. This will ensure that
  2181. * the skb is freed only after receiving tx
  2182. * completion for all segments of an nbuf
  2183. */
  2184. qdf_nbuf_inc_users(nbuf);
  2185. /* Check with MCL if this is needed */
  2186. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2187. */
  2188. }
  2189. }
  2190. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2191. &htt_tcl_metadata,
  2192. vdev,
  2193. msdu_info);
  2194. /*
  2195. * Enqueue the Tx MSDU descriptor to HW for transmit
  2196. */
  2197. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2198. htt_tcl_metadata,
  2199. NULL, msdu_info);
  2200. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2201. if (status != QDF_STATUS_SUCCESS) {
  2202. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2203. tx_desc, tx_q->ring_id);
  2204. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2205. tid_stats = &pdev->stats.tid_stats.
  2206. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2207. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2208. if (msdu_info->frm_type == dp_tx_frm_me) {
  2209. hw_enq_fail++;
  2210. if (hw_enq_fail == msdu_info->num_seg) {
  2211. /*
  2212. * Unmap is needed only if enqueue
  2213. * failed for all segments.
  2214. */
  2215. qdf_nbuf_unmap(soc->osdev,
  2216. msdu_info->u.sg_info.
  2217. curr_seg->nbuf,
  2218. QDF_DMA_TO_DEVICE);
  2219. }
  2220. /*
  2221. * Free the nbuf for the current segment
  2222. * and make it point to the next in the list.
  2223. * For me, there are as many segments as there
  2224. * are no of clients.
  2225. */
  2226. qdf_nbuf_free(msdu_info->u.sg_info
  2227. .curr_seg->nbuf);
  2228. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2229. if (msdu_info->u.sg_info.curr_seg->next) {
  2230. msdu_info->u.sg_info.curr_seg =
  2231. msdu_info->u.sg_info
  2232. .curr_seg->next;
  2233. nbuf = msdu_info->u.sg_info
  2234. .curr_seg->nbuf;
  2235. } else
  2236. break;
  2237. i++;
  2238. continue;
  2239. }
  2240. /*
  2241. * For TSO frames, the nbuf users increment done for
  2242. * the current segment has to be reverted, since the
  2243. * hw enqueue for this segment failed
  2244. */
  2245. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2246. msdu_info->u.tso_info.curr_seg) {
  2247. /*
  2248. * unmap and free current,
  2249. * retransmit remaining segments
  2250. */
  2251. dp_tx_comp_free_buf(soc, tx_desc);
  2252. i++;
  2253. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2254. continue;
  2255. }
  2256. if (msdu_info->frm_type == dp_tx_frm_sg)
  2257. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2258. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2259. goto done;
  2260. }
  2261. /*
  2262. * TODO
  2263. * if tso_info structure can be modified to have curr_seg
  2264. * as first element, following 2 blocks of code (for TSO and SG)
  2265. * can be combined into 1
  2266. */
  2267. /*
  2268. * For Multicast-Unicast converted packets,
  2269. * each converted frame (for a client) is represented as
  2270. * 1 segment
  2271. */
  2272. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2273. (msdu_info->frm_type == dp_tx_frm_me)) {
  2274. if (msdu_info->u.sg_info.curr_seg->next) {
  2275. msdu_info->u.sg_info.curr_seg =
  2276. msdu_info->u.sg_info.curr_seg->next;
  2277. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2278. } else
  2279. break;
  2280. }
  2281. i++;
  2282. }
  2283. nbuf = NULL;
  2284. done:
  2285. return nbuf;
  2286. }
  2287. /**
  2288. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2289. * for SG frames
  2290. * @vdev: DP vdev handle
  2291. * @nbuf: skb
  2292. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2293. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2294. *
  2295. * Return: NULL on success,
  2296. * nbuf when it fails to send
  2297. */
  2298. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2299. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2300. {
  2301. uint32_t cur_frag, nr_frags, i;
  2302. qdf_dma_addr_t paddr;
  2303. struct dp_tx_sg_info_s *sg_info;
  2304. sg_info = &msdu_info->u.sg_info;
  2305. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2306. if (QDF_STATUS_SUCCESS !=
  2307. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2308. QDF_DMA_TO_DEVICE,
  2309. qdf_nbuf_headlen(nbuf))) {
  2310. dp_tx_err("dma map error");
  2311. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2312. qdf_nbuf_free(nbuf);
  2313. return NULL;
  2314. }
  2315. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2316. seg_info->frags[0].paddr_lo = paddr;
  2317. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2318. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2319. seg_info->frags[0].vaddr = (void *) nbuf;
  2320. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2321. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2322. nbuf, 0,
  2323. QDF_DMA_TO_DEVICE,
  2324. cur_frag)) {
  2325. dp_tx_err("frag dma map error");
  2326. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2327. goto map_err;
  2328. }
  2329. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2330. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2331. seg_info->frags[cur_frag + 1].paddr_hi =
  2332. ((uint64_t) paddr) >> 32;
  2333. seg_info->frags[cur_frag + 1].len =
  2334. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2335. }
  2336. seg_info->frag_cnt = (cur_frag + 1);
  2337. seg_info->total_len = qdf_nbuf_len(nbuf);
  2338. seg_info->next = NULL;
  2339. sg_info->curr_seg = seg_info;
  2340. msdu_info->frm_type = dp_tx_frm_sg;
  2341. msdu_info->num_seg = 1;
  2342. return nbuf;
  2343. map_err:
  2344. /* restore paddr into nbuf before calling unmap */
  2345. qdf_nbuf_mapped_paddr_set(nbuf,
  2346. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2347. ((uint64_t)
  2348. seg_info->frags[0].paddr_hi) << 32));
  2349. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2350. QDF_DMA_TO_DEVICE,
  2351. seg_info->frags[0].len);
  2352. for (i = 1; i <= cur_frag; i++) {
  2353. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2354. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2355. seg_info->frags[i].paddr_hi) << 32),
  2356. seg_info->frags[i].len,
  2357. QDF_DMA_TO_DEVICE);
  2358. }
  2359. qdf_nbuf_free(nbuf);
  2360. return NULL;
  2361. }
  2362. /**
  2363. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2364. * @vdev: DP vdev handle
  2365. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2366. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2367. *
  2368. * Return: NULL on failure,
  2369. * nbuf when extracted successfully
  2370. */
  2371. static
  2372. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2373. struct dp_tx_msdu_info_s *msdu_info,
  2374. uint16_t ppdu_cookie)
  2375. {
  2376. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2377. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2378. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2379. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2380. (msdu_info->meta_data[5], 1);
  2381. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2382. (msdu_info->meta_data[5], 1);
  2383. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2384. (msdu_info->meta_data[6], ppdu_cookie);
  2385. msdu_info->exception_fw = 1;
  2386. msdu_info->is_tx_sniffer = 1;
  2387. }
  2388. #ifdef MESH_MODE_SUPPORT
  2389. /**
  2390. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2391. and prepare msdu_info for mesh frames.
  2392. * @vdev: DP vdev handle
  2393. * @nbuf: skb
  2394. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2395. *
  2396. * Return: NULL on failure,
  2397. * nbuf when extracted successfully
  2398. */
  2399. static
  2400. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2401. struct dp_tx_msdu_info_s *msdu_info)
  2402. {
  2403. struct meta_hdr_s *mhdr;
  2404. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2405. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2406. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2407. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2408. msdu_info->exception_fw = 0;
  2409. goto remove_meta_hdr;
  2410. }
  2411. msdu_info->exception_fw = 1;
  2412. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2413. meta_data->host_tx_desc_pool = 1;
  2414. meta_data->update_peer_cache = 1;
  2415. meta_data->learning_frame = 1;
  2416. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2417. meta_data->power = mhdr->power;
  2418. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2419. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2420. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2421. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2422. meta_data->dyn_bw = 1;
  2423. meta_data->valid_pwr = 1;
  2424. meta_data->valid_mcs_mask = 1;
  2425. meta_data->valid_nss_mask = 1;
  2426. meta_data->valid_preamble_type = 1;
  2427. meta_data->valid_retries = 1;
  2428. meta_data->valid_bw_info = 1;
  2429. }
  2430. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2431. meta_data->encrypt_type = 0;
  2432. meta_data->valid_encrypt_type = 1;
  2433. meta_data->learning_frame = 0;
  2434. }
  2435. meta_data->valid_key_flags = 1;
  2436. meta_data->key_flags = (mhdr->keyix & 0x3);
  2437. remove_meta_hdr:
  2438. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2439. dp_tx_err("qdf_nbuf_pull_head failed");
  2440. qdf_nbuf_free(nbuf);
  2441. return NULL;
  2442. }
  2443. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2444. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2445. " tid %d to_fw %d",
  2446. msdu_info->meta_data[0],
  2447. msdu_info->meta_data[1],
  2448. msdu_info->meta_data[2],
  2449. msdu_info->meta_data[3],
  2450. msdu_info->meta_data[4],
  2451. msdu_info->meta_data[5],
  2452. msdu_info->tid, msdu_info->exception_fw);
  2453. return nbuf;
  2454. }
  2455. #else
  2456. static
  2457. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2458. struct dp_tx_msdu_info_s *msdu_info)
  2459. {
  2460. return nbuf;
  2461. }
  2462. #endif
  2463. /**
  2464. * dp_check_exc_metadata() - Checks if parameters are valid
  2465. * @tx_exc - holds all exception path parameters
  2466. *
  2467. * Returns true when all the parameters are valid else false
  2468. *
  2469. */
  2470. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2471. {
  2472. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2473. HTT_INVALID_TID);
  2474. bool invalid_encap_type =
  2475. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2476. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2477. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2478. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2479. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2480. tx_exc->ppdu_cookie == 0);
  2481. if (tx_exc->is_intrabss_fwd)
  2482. return true;
  2483. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2484. invalid_cookie) {
  2485. return false;
  2486. }
  2487. return true;
  2488. }
  2489. #ifdef ATH_SUPPORT_IQUE
  2490. /**
  2491. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2492. * @vdev: vdev handle
  2493. * @nbuf: skb
  2494. *
  2495. * Return: true on success,
  2496. * false on failure
  2497. */
  2498. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2499. {
  2500. qdf_ether_header_t *eh;
  2501. /* Mcast to Ucast Conversion*/
  2502. if (qdf_likely(!vdev->mcast_enhancement_en))
  2503. return true;
  2504. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2505. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2506. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2507. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2508. qdf_nbuf_set_next(nbuf, NULL);
  2509. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2510. qdf_nbuf_len(nbuf));
  2511. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2512. QDF_STATUS_SUCCESS) {
  2513. return false;
  2514. }
  2515. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2516. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2517. QDF_STATUS_SUCCESS) {
  2518. return false;
  2519. }
  2520. }
  2521. }
  2522. return true;
  2523. }
  2524. #else
  2525. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2526. {
  2527. return true;
  2528. }
  2529. #endif
  2530. /**
  2531. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2532. * @nbuf: qdf_nbuf_t
  2533. * @vdev: struct dp_vdev *
  2534. *
  2535. * Allow packet for processing only if it is for peer client which is
  2536. * connected with same vap. Drop packet if client is connected to
  2537. * different vap.
  2538. *
  2539. * Return: QDF_STATUS
  2540. */
  2541. static inline QDF_STATUS
  2542. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2543. {
  2544. struct dp_ast_entry *dst_ast_entry = NULL;
  2545. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2546. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2547. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2548. return QDF_STATUS_SUCCESS;
  2549. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2550. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2551. eh->ether_dhost,
  2552. vdev->vdev_id);
  2553. /* If there is no ast entry, return failure */
  2554. if (qdf_unlikely(!dst_ast_entry)) {
  2555. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2556. return QDF_STATUS_E_FAILURE;
  2557. }
  2558. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2559. return QDF_STATUS_SUCCESS;
  2560. }
  2561. /**
  2562. * dp_tx_nawds_handler() - NAWDS handler
  2563. *
  2564. * @soc: DP soc handle
  2565. * @vdev_id: id of DP vdev handle
  2566. * @msdu_info: msdu_info required to create HTT metadata
  2567. * @nbuf: skb
  2568. *
  2569. * This API transfers the multicast frames with the peer id
  2570. * on NAWDS enabled peer.
  2571. * Return: none
  2572. */
  2573. static inline
  2574. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2575. struct dp_tx_msdu_info_s *msdu_info,
  2576. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2577. {
  2578. struct dp_peer *peer = NULL;
  2579. qdf_nbuf_t nbuf_clone = NULL;
  2580. uint16_t peer_id = DP_INVALID_PEER;
  2581. struct dp_txrx_peer *txrx_peer;
  2582. /* This check avoids pkt forwarding which is entered
  2583. * in the ast table but still doesn't have valid peerid.
  2584. */
  2585. if (sa_peer_id == HTT_INVALID_PEER)
  2586. return;
  2587. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2588. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2589. txrx_peer = dp_get_txrx_peer(peer);
  2590. if (!txrx_peer)
  2591. continue;
  2592. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2593. peer_id = peer->peer_id;
  2594. if (!dp_peer_is_primary_link_peer(peer))
  2595. continue;
  2596. /* Multicast packets needs to be
  2597. * dropped in case of intra bss forwarding
  2598. */
  2599. if (sa_peer_id == txrx_peer->peer_id) {
  2600. dp_tx_debug("multicast packet");
  2601. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2602. tx.nawds_mcast_drop,
  2603. 1);
  2604. continue;
  2605. }
  2606. nbuf_clone = qdf_nbuf_clone(nbuf);
  2607. if (!nbuf_clone) {
  2608. QDF_TRACE(QDF_MODULE_ID_DP,
  2609. QDF_TRACE_LEVEL_ERROR,
  2610. FL("nbuf clone failed"));
  2611. break;
  2612. }
  2613. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2614. msdu_info, peer_id,
  2615. NULL);
  2616. if (nbuf_clone) {
  2617. dp_tx_debug("pkt send failed");
  2618. qdf_nbuf_free(nbuf_clone);
  2619. } else {
  2620. if (peer_id != DP_INVALID_PEER)
  2621. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2622. tx.nawds_mcast,
  2623. 1, qdf_nbuf_len(nbuf));
  2624. }
  2625. }
  2626. }
  2627. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2628. }
  2629. /**
  2630. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2631. * @soc: DP soc handle
  2632. * @vdev_id: id of DP vdev handle
  2633. * @nbuf: skb
  2634. * @tx_exc_metadata: Handle that holds exception path meta data
  2635. *
  2636. * Entry point for Core Tx layer (DP_TX) invoked from
  2637. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2638. *
  2639. * Return: NULL on success,
  2640. * nbuf when it fails to send
  2641. */
  2642. qdf_nbuf_t
  2643. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2644. qdf_nbuf_t nbuf,
  2645. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2646. {
  2647. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2648. qdf_ether_header_t *eh = NULL;
  2649. struct dp_tx_msdu_info_s msdu_info;
  2650. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2651. DP_MOD_ID_TX_EXCEPTION);
  2652. if (qdf_unlikely(!vdev))
  2653. goto fail;
  2654. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2655. if (!tx_exc_metadata)
  2656. goto fail;
  2657. msdu_info.tid = tx_exc_metadata->tid;
  2658. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2659. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2660. QDF_MAC_ADDR_REF(nbuf->data));
  2661. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2662. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2663. dp_tx_err("Invalid parameters in exception path");
  2664. goto fail;
  2665. }
  2666. /* Basic sanity checks for unsupported packets */
  2667. /* MESH mode */
  2668. if (qdf_unlikely(vdev->mesh_vdev)) {
  2669. dp_tx_err("Mesh mode is not supported in exception path");
  2670. goto fail;
  2671. }
  2672. /*
  2673. * Classify the frame and call corresponding
  2674. * "prepare" function which extracts the segment (TSO)
  2675. * and fragmentation information (for TSO , SG, ME, or Raw)
  2676. * into MSDU_INFO structure which is later used to fill
  2677. * SW and HW descriptors.
  2678. */
  2679. if (qdf_nbuf_is_tso(nbuf)) {
  2680. dp_verbose_debug("TSO frame %pK", vdev);
  2681. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2682. qdf_nbuf_len(nbuf));
  2683. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2684. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2685. qdf_nbuf_len(nbuf));
  2686. goto fail;
  2687. }
  2688. goto send_multiple;
  2689. }
  2690. /* SG */
  2691. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2692. struct dp_tx_seg_info_s seg_info = {0};
  2693. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2694. if (!nbuf)
  2695. goto fail;
  2696. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2697. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2698. qdf_nbuf_len(nbuf));
  2699. goto send_multiple;
  2700. }
  2701. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2702. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2703. qdf_nbuf_len(nbuf));
  2704. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2705. tx_exc_metadata->ppdu_cookie);
  2706. }
  2707. /*
  2708. * Get HW Queue to use for this frame.
  2709. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2710. * dedicated for data and 1 for command.
  2711. * "queue_id" maps to one hardware ring.
  2712. * With each ring, we also associate a unique Tx descriptor pool
  2713. * to minimize lock contention for these resources.
  2714. */
  2715. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2716. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2717. if (qdf_unlikely(vdev->nawds_enabled)) {
  2718. /*
  2719. * This is a multicast packet
  2720. */
  2721. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2722. tx_exc_metadata->peer_id);
  2723. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2724. 1, qdf_nbuf_len(nbuf));
  2725. }
  2726. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2727. DP_INVALID_PEER, NULL);
  2728. } else {
  2729. /*
  2730. * Check exception descriptors
  2731. */
  2732. if (dp_tx_exception_limit_check(vdev))
  2733. goto fail;
  2734. /* Single linear frame */
  2735. /*
  2736. * If nbuf is a simple linear frame, use send_single function to
  2737. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2738. * SRNG. There is no need to setup a MSDU extension descriptor.
  2739. */
  2740. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2741. tx_exc_metadata->peer_id,
  2742. tx_exc_metadata);
  2743. }
  2744. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2745. return nbuf;
  2746. send_multiple:
  2747. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2748. fail:
  2749. if (vdev)
  2750. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2751. dp_verbose_debug("pkt send failed");
  2752. return nbuf;
  2753. }
  2754. /**
  2755. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2756. * in exception path in special case to avoid regular exception path chk.
  2757. * @soc: DP soc handle
  2758. * @vdev_id: id of DP vdev handle
  2759. * @nbuf: skb
  2760. * @tx_exc_metadata: Handle that holds exception path meta data
  2761. *
  2762. * Entry point for Core Tx layer (DP_TX) invoked from
  2763. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2764. *
  2765. * Return: NULL on success,
  2766. * nbuf when it fails to send
  2767. */
  2768. qdf_nbuf_t
  2769. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2770. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2771. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2772. {
  2773. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2774. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2775. DP_MOD_ID_TX_EXCEPTION);
  2776. if (qdf_unlikely(!vdev))
  2777. goto fail;
  2778. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2779. == QDF_STATUS_E_FAILURE)) {
  2780. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2781. goto fail;
  2782. }
  2783. /* Unref count as it will agin be taken inside dp_tx_exception */
  2784. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2785. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2786. fail:
  2787. if (vdev)
  2788. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2789. dp_verbose_debug("pkt send failed");
  2790. return nbuf;
  2791. }
  2792. /**
  2793. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2794. * @soc: DP soc handle
  2795. * @vdev_id: DP vdev handle
  2796. * @nbuf: skb
  2797. *
  2798. * Entry point for Core Tx layer (DP_TX) invoked from
  2799. * hard_start_xmit in OSIF/HDD
  2800. *
  2801. * Return: NULL on success,
  2802. * nbuf when it fails to send
  2803. */
  2804. #ifdef MESH_MODE_SUPPORT
  2805. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2806. qdf_nbuf_t nbuf)
  2807. {
  2808. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2809. struct meta_hdr_s *mhdr;
  2810. qdf_nbuf_t nbuf_mesh = NULL;
  2811. qdf_nbuf_t nbuf_clone = NULL;
  2812. struct dp_vdev *vdev;
  2813. uint8_t no_enc_frame = 0;
  2814. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2815. if (!nbuf_mesh) {
  2816. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2817. "qdf_nbuf_unshare failed");
  2818. return nbuf;
  2819. }
  2820. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2821. if (!vdev) {
  2822. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2823. "vdev is NULL for vdev_id %d", vdev_id);
  2824. return nbuf;
  2825. }
  2826. nbuf = nbuf_mesh;
  2827. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2828. if ((vdev->sec_type != cdp_sec_type_none) &&
  2829. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2830. no_enc_frame = 1;
  2831. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2832. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2833. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2834. !no_enc_frame) {
  2835. nbuf_clone = qdf_nbuf_clone(nbuf);
  2836. if (!nbuf_clone) {
  2837. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2838. "qdf_nbuf_clone failed");
  2839. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2840. return nbuf;
  2841. }
  2842. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2843. }
  2844. if (nbuf_clone) {
  2845. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2846. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2847. } else {
  2848. qdf_nbuf_free(nbuf_clone);
  2849. }
  2850. }
  2851. if (no_enc_frame)
  2852. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2853. else
  2854. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2855. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2856. if ((!nbuf) && no_enc_frame) {
  2857. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2858. }
  2859. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2860. return nbuf;
  2861. }
  2862. #else
  2863. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2864. qdf_nbuf_t nbuf)
  2865. {
  2866. return dp_tx_send(soc, vdev_id, nbuf);
  2867. }
  2868. #endif
  2869. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  2870. static inline
  2871. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2872. {
  2873. if (nbuf) {
  2874. qdf_prefetch(&nbuf->len);
  2875. qdf_prefetch(&nbuf->data);
  2876. }
  2877. }
  2878. #else
  2879. static inline
  2880. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  2881. {
  2882. }
  2883. #endif
  2884. /**
  2885. * dp_tx_send() - Transmit a frame on a given VAP
  2886. * @soc: DP soc handle
  2887. * @vdev_id: id of DP vdev handle
  2888. * @nbuf: skb
  2889. *
  2890. * Entry point for Core Tx layer (DP_TX) invoked from
  2891. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2892. * cases
  2893. *
  2894. * Return: NULL on success,
  2895. * nbuf when it fails to send
  2896. */
  2897. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2898. qdf_nbuf_t nbuf)
  2899. {
  2900. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2901. uint16_t peer_id = HTT_INVALID_PEER;
  2902. /*
  2903. * doing a memzero is causing additional function call overhead
  2904. * so doing static stack clearing
  2905. */
  2906. struct dp_tx_msdu_info_s msdu_info = {0};
  2907. struct dp_vdev *vdev = NULL;
  2908. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2909. return nbuf;
  2910. /*
  2911. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2912. * this in per packet path.
  2913. *
  2914. * As in this path vdev memory is already protected with netdev
  2915. * tx lock
  2916. */
  2917. vdev = soc->vdev_id_map[vdev_id];
  2918. if (qdf_unlikely(!vdev))
  2919. return nbuf;
  2920. /*
  2921. * Set Default Host TID value to invalid TID
  2922. * (TID override disabled)
  2923. */
  2924. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2925. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  2926. if (qdf_unlikely(vdev->mesh_vdev)) {
  2927. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2928. &msdu_info);
  2929. if (!nbuf_mesh) {
  2930. dp_verbose_debug("Extracting mesh metadata failed");
  2931. return nbuf;
  2932. }
  2933. nbuf = nbuf_mesh;
  2934. }
  2935. /*
  2936. * Get HW Queue to use for this frame.
  2937. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2938. * dedicated for data and 1 for command.
  2939. * "queue_id" maps to one hardware ring.
  2940. * With each ring, we also associate a unique Tx descriptor pool
  2941. * to minimize lock contention for these resources.
  2942. */
  2943. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2944. /*
  2945. * TCL H/W supports 2 DSCP-TID mapping tables.
  2946. * Table 1 - Default DSCP-TID mapping table
  2947. * Table 2 - 1 DSCP-TID override table
  2948. *
  2949. * If we need a different DSCP-TID mapping for this vap,
  2950. * call tid_classify to extract DSCP/ToS from frame and
  2951. * map to a TID and store in msdu_info. This is later used
  2952. * to fill in TCL Input descriptor (per-packet TID override).
  2953. */
  2954. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2955. /*
  2956. * Classify the frame and call corresponding
  2957. * "prepare" function which extracts the segment (TSO)
  2958. * and fragmentation information (for TSO , SG, ME, or Raw)
  2959. * into MSDU_INFO structure which is later used to fill
  2960. * SW and HW descriptors.
  2961. */
  2962. if (qdf_nbuf_is_tso(nbuf)) {
  2963. dp_verbose_debug("TSO frame %pK", vdev);
  2964. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2965. qdf_nbuf_len(nbuf));
  2966. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2967. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2968. qdf_nbuf_len(nbuf));
  2969. return nbuf;
  2970. }
  2971. goto send_multiple;
  2972. }
  2973. /* SG */
  2974. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2975. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  2976. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  2977. return nbuf;
  2978. } else {
  2979. struct dp_tx_seg_info_s seg_info = {0};
  2980. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  2981. &msdu_info);
  2982. if (!nbuf)
  2983. return NULL;
  2984. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2985. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2986. qdf_nbuf_len(nbuf));
  2987. goto send_multiple;
  2988. }
  2989. }
  2990. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2991. return NULL;
  2992. /* RAW */
  2993. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2994. struct dp_tx_seg_info_s seg_info = {0};
  2995. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2996. if (!nbuf)
  2997. return NULL;
  2998. dp_verbose_debug("Raw frame %pK", vdev);
  2999. goto send_multiple;
  3000. }
  3001. if (qdf_unlikely(vdev->nawds_enabled)) {
  3002. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3003. qdf_nbuf_data(nbuf);
  3004. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3005. uint16_t sa_peer_id = DP_INVALID_PEER;
  3006. if (!soc->ast_offload_support) {
  3007. struct dp_ast_entry *ast_entry = NULL;
  3008. qdf_spin_lock_bh(&soc->ast_lock);
  3009. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3010. (soc,
  3011. (uint8_t *)(eh->ether_shost),
  3012. vdev->pdev->pdev_id);
  3013. if (ast_entry)
  3014. sa_peer_id = ast_entry->peer_id;
  3015. qdf_spin_unlock_bh(&soc->ast_lock);
  3016. }
  3017. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3018. sa_peer_id);
  3019. }
  3020. peer_id = DP_INVALID_PEER;
  3021. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3022. 1, qdf_nbuf_len(nbuf));
  3023. }
  3024. /* Single linear frame */
  3025. /*
  3026. * If nbuf is a simple linear frame, use send_single function to
  3027. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3028. * SRNG. There is no need to setup a MSDU extension descriptor.
  3029. */
  3030. dp_tx_prefetch_nbuf_data(nbuf);
  3031. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  3032. return nbuf;
  3033. send_multiple:
  3034. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3035. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3036. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3037. return nbuf;
  3038. }
  3039. /**
  3040. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3041. * case to vaoid check in perpkt path.
  3042. * @soc: DP soc handle
  3043. * @vdev_id: id of DP vdev handle
  3044. * @nbuf: skb
  3045. *
  3046. * Entry point for Core Tx layer (DP_TX) invoked from
  3047. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3048. * with special condition to avoid per pkt check in dp_tx_send
  3049. *
  3050. * Return: NULL on success,
  3051. * nbuf when it fails to send
  3052. */
  3053. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3054. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3055. {
  3056. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3057. struct dp_vdev *vdev = NULL;
  3058. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3059. return nbuf;
  3060. /*
  3061. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3062. * this in per packet path.
  3063. *
  3064. * As in this path vdev memory is already protected with netdev
  3065. * tx lock
  3066. */
  3067. vdev = soc->vdev_id_map[vdev_id];
  3068. if (qdf_unlikely(!vdev))
  3069. return nbuf;
  3070. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3071. == QDF_STATUS_E_FAILURE)) {
  3072. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3073. return nbuf;
  3074. }
  3075. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3076. }
  3077. #ifdef UMAC_SUPPORT_PROXY_ARP
  3078. /**
  3079. * dp_tx_proxy_arp() - Tx proxy arp handler
  3080. * @vdev: datapath vdev handle
  3081. * @buf: sk buffer
  3082. *
  3083. * Return: status
  3084. */
  3085. static inline
  3086. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3087. {
  3088. if (vdev->osif_proxy_arp)
  3089. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3090. /*
  3091. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3092. * osif_proxy_arp has a valid function pointer assigned
  3093. * to it
  3094. */
  3095. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3096. return QDF_STATUS_NOT_INITIALIZED;
  3097. }
  3098. #else
  3099. /**
  3100. * dp_tx_proxy_arp() - Tx proxy arp handler
  3101. * @vdev: datapath vdev handle
  3102. * @buf: sk buffer
  3103. *
  3104. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3105. * is not defined.
  3106. *
  3107. * Return: status
  3108. */
  3109. static inline
  3110. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3111. {
  3112. return QDF_STATUS_SUCCESS;
  3113. }
  3114. #endif
  3115. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3116. #ifdef WLAN_MCAST_MLO
  3117. static bool
  3118. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3119. struct dp_tx_desc_s *tx_desc,
  3120. qdf_nbuf_t nbuf,
  3121. uint8_t reinject_reason)
  3122. {
  3123. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3124. if (soc->arch_ops.dp_tx_mcast_handler)
  3125. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3126. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3127. return true;
  3128. }
  3129. return false;
  3130. }
  3131. #else /* WLAN_MCAST_MLO */
  3132. static inline bool
  3133. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3134. struct dp_tx_desc_s *tx_desc,
  3135. qdf_nbuf_t nbuf,
  3136. uint8_t reinject_reason)
  3137. {
  3138. return false;
  3139. }
  3140. #endif /* WLAN_MCAST_MLO */
  3141. #else
  3142. static inline bool
  3143. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3144. struct dp_tx_desc_s *tx_desc,
  3145. qdf_nbuf_t nbuf,
  3146. uint8_t reinject_reason)
  3147. {
  3148. return false;
  3149. }
  3150. #endif
  3151. /**
  3152. * dp_tx_reinject_handler() - Tx Reinject Handler
  3153. * @soc: datapath soc handle
  3154. * @vdev: datapath vdev handle
  3155. * @tx_desc: software descriptor head pointer
  3156. * @status : Tx completion status from HTT descriptor
  3157. * @reinject_reason : reinject reason from HTT descriptor
  3158. *
  3159. * This function reinjects frames back to Target.
  3160. * Todo - Host queue needs to be added
  3161. *
  3162. * Return: none
  3163. */
  3164. void dp_tx_reinject_handler(struct dp_soc *soc,
  3165. struct dp_vdev *vdev,
  3166. struct dp_tx_desc_s *tx_desc,
  3167. uint8_t *status,
  3168. uint8_t reinject_reason)
  3169. {
  3170. struct dp_peer *peer = NULL;
  3171. uint32_t peer_id = HTT_INVALID_PEER;
  3172. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3173. qdf_nbuf_t nbuf_copy = NULL;
  3174. struct dp_tx_msdu_info_s msdu_info;
  3175. #ifdef WDS_VENDOR_EXTENSION
  3176. int is_mcast = 0, is_ucast = 0;
  3177. int num_peers_3addr = 0;
  3178. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3179. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3180. #endif
  3181. struct dp_txrx_peer *txrx_peer;
  3182. qdf_assert(vdev);
  3183. dp_tx_debug("Tx reinject path");
  3184. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3185. qdf_nbuf_len(tx_desc->nbuf));
  3186. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3187. return;
  3188. #ifdef WDS_VENDOR_EXTENSION
  3189. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3190. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3191. } else {
  3192. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3193. }
  3194. is_ucast = !is_mcast;
  3195. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3196. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3197. txrx_peer = dp_get_txrx_peer(peer);
  3198. if (!txrx_peer || txrx_peer->bss_peer)
  3199. continue;
  3200. /* Detect wds peers that use 3-addr framing for mcast.
  3201. * if there are any, the bss_peer is used to send the
  3202. * the mcast frame using 3-addr format. all wds enabled
  3203. * peers that use 4-addr framing for mcast frames will
  3204. * be duplicated and sent as 4-addr frames below.
  3205. */
  3206. if (!txrx_peer->wds_enabled ||
  3207. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3208. num_peers_3addr = 1;
  3209. break;
  3210. }
  3211. }
  3212. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3213. #endif
  3214. if (qdf_unlikely(vdev->mesh_vdev)) {
  3215. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3216. } else {
  3217. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3218. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3219. txrx_peer = dp_get_txrx_peer(peer);
  3220. if (!txrx_peer)
  3221. continue;
  3222. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3223. #ifdef WDS_VENDOR_EXTENSION
  3224. /*
  3225. * . if 3-addr STA, then send on BSS Peer
  3226. * . if Peer WDS enabled and accept 4-addr mcast,
  3227. * send mcast on that peer only
  3228. * . if Peer WDS enabled and accept 4-addr ucast,
  3229. * send ucast on that peer only
  3230. */
  3231. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3232. (txrx_peer->wds_enabled &&
  3233. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3234. (is_ucast &&
  3235. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3236. #else
  3237. (txrx_peer->bss_peer &&
  3238. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3239. #endif
  3240. peer_id = DP_INVALID_PEER;
  3241. nbuf_copy = qdf_nbuf_copy(nbuf);
  3242. if (!nbuf_copy) {
  3243. dp_tx_debug("nbuf copy failed");
  3244. break;
  3245. }
  3246. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3247. dp_tx_get_queue(vdev, nbuf,
  3248. &msdu_info.tx_queue);
  3249. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3250. nbuf_copy,
  3251. &msdu_info,
  3252. peer_id,
  3253. NULL);
  3254. if (nbuf_copy) {
  3255. dp_tx_debug("pkt send failed");
  3256. qdf_nbuf_free(nbuf_copy);
  3257. }
  3258. }
  3259. }
  3260. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3261. }
  3262. qdf_nbuf_free(nbuf);
  3263. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3264. }
  3265. /**
  3266. * dp_tx_inspect_handler() - Tx Inspect Handler
  3267. * @soc: datapath soc handle
  3268. * @vdev: datapath vdev handle
  3269. * @tx_desc: software descriptor head pointer
  3270. * @status : Tx completion status from HTT descriptor
  3271. *
  3272. * Handles Tx frames sent back to Host for inspection
  3273. * (ProxyARP)
  3274. *
  3275. * Return: none
  3276. */
  3277. void dp_tx_inspect_handler(struct dp_soc *soc,
  3278. struct dp_vdev *vdev,
  3279. struct dp_tx_desc_s *tx_desc,
  3280. uint8_t *status)
  3281. {
  3282. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3283. "%s Tx inspect path",
  3284. __func__);
  3285. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3286. qdf_nbuf_len(tx_desc->nbuf));
  3287. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3288. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3289. }
  3290. #ifdef MESH_MODE_SUPPORT
  3291. /**
  3292. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3293. * in mesh meta header
  3294. * @tx_desc: software descriptor head pointer
  3295. * @ts: pointer to tx completion stats
  3296. * Return: none
  3297. */
  3298. static
  3299. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3300. struct hal_tx_completion_status *ts)
  3301. {
  3302. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3303. if (!tx_desc->msdu_ext_desc) {
  3304. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3305. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3306. "netbuf %pK offset %d",
  3307. netbuf, tx_desc->pkt_offset);
  3308. return;
  3309. }
  3310. }
  3311. }
  3312. #else
  3313. static
  3314. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3315. struct hal_tx_completion_status *ts)
  3316. {
  3317. }
  3318. #endif
  3319. #ifdef CONFIG_SAWF
  3320. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3321. struct dp_vdev *vdev,
  3322. struct dp_txrx_peer *txrx_peer,
  3323. struct dp_tx_desc_s *tx_desc,
  3324. struct hal_tx_completion_status *ts,
  3325. uint8_t tid)
  3326. {
  3327. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3328. ts, tid);
  3329. }
  3330. #else
  3331. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3332. struct dp_vdev *vdev,
  3333. struct dp_txrx_peer *txrx_peer,
  3334. struct dp_tx_desc_s *tx_desc,
  3335. struct hal_tx_completion_status *ts,
  3336. uint8_t tid)
  3337. {
  3338. }
  3339. #endif
  3340. #ifdef QCA_PEER_EXT_STATS
  3341. /*
  3342. * dp_tx_compute_tid_delay() - Compute per TID delay
  3343. * @stats: Per TID delay stats
  3344. * @tx_desc: Software Tx descriptor
  3345. *
  3346. * Compute the software enqueue and hw enqueue delays and
  3347. * update the respective histograms
  3348. *
  3349. * Return: void
  3350. */
  3351. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3352. struct dp_tx_desc_s *tx_desc)
  3353. {
  3354. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3355. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3356. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3357. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3358. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3359. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3360. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3361. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3362. timestamp_hw_enqueue);
  3363. /*
  3364. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3365. */
  3366. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3367. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3368. }
  3369. /*
  3370. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3371. * @txrx_peer: DP peer context
  3372. * @tx_desc: Tx software descriptor
  3373. * @tid: Transmission ID
  3374. * @ring_id: Rx CPU context ID/CPU_ID
  3375. *
  3376. * Update the peer extended stats. These are enhanced other
  3377. * delay stats per msdu level.
  3378. *
  3379. * Return: void
  3380. */
  3381. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3382. struct dp_tx_desc_s *tx_desc,
  3383. uint8_t tid, uint8_t ring_id)
  3384. {
  3385. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3386. struct dp_soc *soc = NULL;
  3387. struct dp_peer_delay_stats *delay_stats = NULL;
  3388. soc = pdev->soc;
  3389. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3390. return;
  3391. delay_stats = txrx_peer->delay_stats;
  3392. qdf_assert(delay_stats);
  3393. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3394. /*
  3395. * For non-TID packets use the TID 9
  3396. */
  3397. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3398. tid = CDP_MAX_DATA_TIDS - 1;
  3399. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3400. tx_desc);
  3401. }
  3402. #else
  3403. static inline void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3404. struct dp_tx_desc_s *tx_desc,
  3405. uint8_t tid, uint8_t ring_id)
  3406. {
  3407. }
  3408. #endif
  3409. #ifdef HW_TX_DELAY_STATS_ENABLE
  3410. /**
  3411. * dp_update_tx_delay_stats() - update the delay stats
  3412. * @vdev: vdev handle
  3413. * @delay: delay in ms or us based on the flag delay_in_us
  3414. * @tid: tid value
  3415. * @mode: type of tx delay mode
  3416. * @ring id: ring number
  3417. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3418. *
  3419. * Return: none
  3420. */
  3421. static inline
  3422. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3423. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3424. {
  3425. struct cdp_tid_tx_stats *tstats =
  3426. &vdev->stats.tid_tx_stats[ring_id][tid];
  3427. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3428. delay_in_us);
  3429. }
  3430. #else
  3431. static inline
  3432. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3433. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3434. {
  3435. struct cdp_tid_tx_stats *tstats =
  3436. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3437. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3438. delay_in_us);
  3439. }
  3440. #endif
  3441. /**
  3442. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3443. * to pass in correct fields
  3444. *
  3445. * @vdev: pdev handle
  3446. * @tx_desc: tx descriptor
  3447. * @tid: tid value
  3448. * @ring_id: TCL or WBM ring number for transmit path
  3449. * Return: none
  3450. */
  3451. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3452. uint8_t tid, uint8_t ring_id)
  3453. {
  3454. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3455. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3456. uint32_t fwhw_transmit_delay_us;
  3457. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3458. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3459. return;
  3460. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3461. fwhw_transmit_delay_us =
  3462. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3463. qdf_ktime_to_us(tx_desc->timestamp);
  3464. /*
  3465. * Delay between packet enqueued to HW and Tx completion in us
  3466. */
  3467. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3468. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3469. ring_id, true);
  3470. /*
  3471. * For MCL, only enqueue to completion delay is required
  3472. * so return if the vdev flag is enabled.
  3473. */
  3474. return;
  3475. }
  3476. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3477. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3478. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3479. timestamp_hw_enqueue);
  3480. /*
  3481. * Delay between packet enqueued to HW and Tx completion in ms
  3482. */
  3483. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3484. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3485. false);
  3486. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3487. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3488. interframe_delay = (uint32_t)(timestamp_ingress -
  3489. vdev->prev_tx_enq_tstamp);
  3490. /*
  3491. * Delay in software enqueue
  3492. */
  3493. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3494. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3495. false);
  3496. /*
  3497. * Update interframe delay stats calculated at hardstart receive point.
  3498. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3499. * interframe delay will not be calculate correctly for 1st frame.
  3500. * On the other side, this will help in avoiding extra per packet check
  3501. * of !vdev->prev_tx_enq_tstamp.
  3502. */
  3503. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3504. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3505. false);
  3506. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3507. }
  3508. #ifdef DISABLE_DP_STATS
  3509. static
  3510. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3511. struct dp_txrx_peer *txrx_peer)
  3512. {
  3513. }
  3514. #else
  3515. static inline void
  3516. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  3517. {
  3518. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3519. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3520. if (subtype != QDF_PROTO_INVALID)
  3521. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3522. 1);
  3523. }
  3524. #endif
  3525. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3526. /**
  3527. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3528. *
  3529. * @ts: Tx compltion status
  3530. * @txrx_peer: datapath txrx_peer handle
  3531. *
  3532. * Return: void
  3533. */
  3534. static inline void
  3535. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3536. struct dp_txrx_peer *txrx_peer)
  3537. {
  3538. uint8_t mcs, pkt_type, dst_mcs_idx;
  3539. uint8_t retry_threshold = txrx_peer->mpdu_retry_threshold;
  3540. mcs = ts->mcs;
  3541. pkt_type = ts->pkt_type;
  3542. /* do HW to SW pkt type conversion */
  3543. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3544. hal_2_dp_pkt_type_map[pkt_type]);
  3545. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3546. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3547. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3548. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3549. 1);
  3550. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  3551. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  3552. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3553. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3554. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3555. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  3556. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  3557. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  3558. if (ts->first_msdu) {
  3559. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3560. ts->transmit_cnt > 1);
  3561. if (!retry_threshold)
  3562. return;
  3563. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3564. qdf_do_div(ts->transmit_cnt,
  3565. retry_threshold),
  3566. ts->transmit_cnt > retry_threshold);
  3567. }
  3568. }
  3569. #else
  3570. static inline void
  3571. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3572. struct dp_txrx_peer *txrx_peer)
  3573. {
  3574. }
  3575. #endif
  3576. /**
  3577. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3578. * per wbm ring
  3579. *
  3580. * @tx_desc: software descriptor head pointer
  3581. * @ts: Tx completion status
  3582. * @peer: peer handle
  3583. * @ring_id: ring number
  3584. *
  3585. * Return: None
  3586. */
  3587. static inline void
  3588. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3589. struct hal_tx_completion_status *ts,
  3590. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  3591. {
  3592. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3593. uint8_t tid = ts->tid;
  3594. uint32_t length;
  3595. struct cdp_tid_tx_stats *tid_stats;
  3596. if (!pdev)
  3597. return;
  3598. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3599. tid = CDP_MAX_DATA_TIDS - 1;
  3600. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3601. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3602. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  3603. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  3604. return;
  3605. }
  3606. length = qdf_nbuf_len(tx_desc->nbuf);
  3607. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  3608. if (qdf_unlikely(pdev->delay_stats_flag) ||
  3609. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  3610. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  3611. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3612. tid_stats->tqm_status_cnt[ts->status]++;
  3613. }
  3614. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  3615. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  3616. ts->transmit_cnt > 1);
  3617. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  3618. 1, ts->transmit_cnt > 2);
  3619. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  3620. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  3621. ts->msdu_part_of_amsdu);
  3622. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  3623. !ts->msdu_part_of_amsdu);
  3624. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  3625. qdf_system_ticks();
  3626. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  3627. return;
  3628. }
  3629. /*
  3630. * tx_failed is ideally supposed to be updated from HTT ppdu
  3631. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  3632. * hw limitation there are no completions for failed cases.
  3633. * Hence updating tx_failed from data path. Please note that
  3634. * if tx_failed is fixed to be from ppdu, then this has to be
  3635. * removed
  3636. */
  3637. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  3638. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  3639. ts->transmit_cnt > DP_RETRY_COUNT);
  3640. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  3641. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  3642. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  3643. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  3644. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  3645. length);
  3646. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  3647. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  3648. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  3649. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  3650. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  3651. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  3652. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  3653. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  3654. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  3655. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  3656. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  3657. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3658. tx.dropped.fw_rem_queue_disable, 1);
  3659. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  3660. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3661. tx.dropped.fw_rem_no_match, 1);
  3662. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  3663. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3664. tx.dropped.drop_threshold, 1);
  3665. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  3666. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3667. tx.dropped.drop_link_desc_na, 1);
  3668. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  3669. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3670. tx.dropped.invalid_drop, 1);
  3671. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  3672. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  3673. tx.dropped.mcast_vdev_drop, 1);
  3674. } else {
  3675. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  3676. }
  3677. }
  3678. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3679. /**
  3680. * dp_tx_flow_pool_lock() - take flow pool lock
  3681. * @soc: core txrx main context
  3682. * @tx_desc: tx desc
  3683. *
  3684. * Return: None
  3685. */
  3686. static inline
  3687. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3688. struct dp_tx_desc_s *tx_desc)
  3689. {
  3690. struct dp_tx_desc_pool_s *pool;
  3691. uint8_t desc_pool_id;
  3692. desc_pool_id = tx_desc->pool_id;
  3693. pool = &soc->tx_desc[desc_pool_id];
  3694. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3695. }
  3696. /**
  3697. * dp_tx_flow_pool_unlock() - release flow pool lock
  3698. * @soc: core txrx main context
  3699. * @tx_desc: tx desc
  3700. *
  3701. * Return: None
  3702. */
  3703. static inline
  3704. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3705. struct dp_tx_desc_s *tx_desc)
  3706. {
  3707. struct dp_tx_desc_pool_s *pool;
  3708. uint8_t desc_pool_id;
  3709. desc_pool_id = tx_desc->pool_id;
  3710. pool = &soc->tx_desc[desc_pool_id];
  3711. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3712. }
  3713. #else
  3714. static inline
  3715. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3716. {
  3717. }
  3718. static inline
  3719. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3720. {
  3721. }
  3722. #endif
  3723. /**
  3724. * dp_tx_notify_completion() - Notify tx completion for this desc
  3725. * @soc: core txrx main context
  3726. * @vdev: datapath vdev handle
  3727. * @tx_desc: tx desc
  3728. * @netbuf: buffer
  3729. * @status: tx status
  3730. *
  3731. * Return: none
  3732. */
  3733. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3734. struct dp_vdev *vdev,
  3735. struct dp_tx_desc_s *tx_desc,
  3736. qdf_nbuf_t netbuf,
  3737. uint8_t status)
  3738. {
  3739. void *osif_dev;
  3740. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3741. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3742. qdf_assert(tx_desc);
  3743. if (!vdev ||
  3744. !vdev->osif_vdev) {
  3745. return;
  3746. }
  3747. osif_dev = vdev->osif_vdev;
  3748. tx_compl_cbk = vdev->tx_comp;
  3749. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3750. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3751. if (tx_compl_cbk)
  3752. tx_compl_cbk(netbuf, osif_dev, flag);
  3753. }
  3754. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3755. * @pdev: pdev handle
  3756. * @tid: tid value
  3757. * @txdesc_ts: timestamp from txdesc
  3758. * @ppdu_id: ppdu id
  3759. *
  3760. * Return: none
  3761. */
  3762. #ifdef FEATURE_PERPKT_INFO
  3763. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3764. struct dp_txrx_peer *txrx_peer,
  3765. uint8_t tid,
  3766. uint64_t txdesc_ts,
  3767. uint32_t ppdu_id)
  3768. {
  3769. uint64_t delta_ms;
  3770. struct cdp_tx_sojourn_stats *sojourn_stats;
  3771. struct dp_peer *primary_link_peer = NULL;
  3772. struct dp_soc *link_peer_soc = NULL;
  3773. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3774. return;
  3775. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3776. tid >= CDP_DATA_TID_MAX))
  3777. return;
  3778. if (qdf_unlikely(!pdev->sojourn_buf))
  3779. return;
  3780. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  3781. txrx_peer->peer_id,
  3782. DP_MOD_ID_TX_COMP);
  3783. if (qdf_unlikely(!primary_link_peer))
  3784. return;
  3785. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3786. qdf_nbuf_data(pdev->sojourn_buf);
  3787. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  3788. sojourn_stats->cookie = (void *)
  3789. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  3790. primary_link_peer);
  3791. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3792. txdesc_ts;
  3793. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  3794. delta_ms);
  3795. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3796. sojourn_stats->num_msdus[tid] = 1;
  3797. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3798. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  3799. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3800. pdev->sojourn_buf, HTT_INVALID_PEER,
  3801. WDI_NO_VAL, pdev->pdev_id);
  3802. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3803. sojourn_stats->num_msdus[tid] = 0;
  3804. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3805. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  3806. }
  3807. #else
  3808. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3809. struct dp_txrx_peer *txrx_peer,
  3810. uint8_t tid,
  3811. uint64_t txdesc_ts,
  3812. uint32_t ppdu_id)
  3813. {
  3814. }
  3815. #endif
  3816. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3817. /**
  3818. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3819. * @soc: dp_soc handle
  3820. * @desc: Tx Descriptor
  3821. * @ts: HAL Tx completion descriptor contents
  3822. *
  3823. * This function is used to send tx completion to packet capture
  3824. */
  3825. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3826. struct dp_tx_desc_s *desc,
  3827. struct hal_tx_completion_status *ts)
  3828. {
  3829. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3830. desc, ts->peer_id,
  3831. WDI_NO_VAL, desc->pdev->pdev_id);
  3832. }
  3833. #endif
  3834. /**
  3835. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3836. * @soc: DP Soc handle
  3837. * @tx_desc: software Tx descriptor
  3838. * @ts : Tx completion status from HAL/HTT descriptor
  3839. *
  3840. * Return: none
  3841. */
  3842. void
  3843. dp_tx_comp_process_desc(struct dp_soc *soc,
  3844. struct dp_tx_desc_s *desc,
  3845. struct hal_tx_completion_status *ts,
  3846. struct dp_txrx_peer *txrx_peer)
  3847. {
  3848. uint64_t time_latency = 0;
  3849. uint16_t peer_id = DP_INVALID_PEER_ID;
  3850. /*
  3851. * m_copy/tx_capture modes are not supported for
  3852. * scatter gather packets
  3853. */
  3854. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3855. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3856. qdf_ktime_to_ms(desc->timestamp));
  3857. }
  3858. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3859. if (dp_tx_pkt_tracepoints_enabled())
  3860. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  3861. desc->msdu_ext_desc ?
  3862. desc->msdu_ext_desc->tso_desc : NULL,
  3863. qdf_ktime_to_ms(desc->timestamp));
  3864. if (!(desc->msdu_ext_desc)) {
  3865. dp_tx_enh_unmap(soc, desc);
  3866. if (txrx_peer)
  3867. peer_id = txrx_peer->peer_id;
  3868. if (QDF_STATUS_SUCCESS ==
  3869. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  3870. return;
  3871. }
  3872. if (QDF_STATUS_SUCCESS ==
  3873. dp_get_completion_indication_for_stack(soc,
  3874. desc->pdev,
  3875. txrx_peer, ts,
  3876. desc->nbuf,
  3877. time_latency)) {
  3878. dp_send_completion_to_stack(soc,
  3879. desc->pdev,
  3880. ts->peer_id,
  3881. ts->ppdu_id,
  3882. desc->nbuf);
  3883. return;
  3884. }
  3885. }
  3886. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3887. dp_tx_comp_free_buf(soc, desc);
  3888. }
  3889. #ifdef DISABLE_DP_STATS
  3890. /**
  3891. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3892. * @soc: core txrx main context
  3893. * @tx_desc: tx desc
  3894. * @status: tx status
  3895. *
  3896. * Return: none
  3897. */
  3898. static inline
  3899. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3900. struct dp_vdev *vdev,
  3901. struct dp_tx_desc_s *tx_desc,
  3902. uint8_t status)
  3903. {
  3904. }
  3905. #else
  3906. static inline
  3907. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3908. struct dp_vdev *vdev,
  3909. struct dp_tx_desc_s *tx_desc,
  3910. uint8_t status)
  3911. {
  3912. void *osif_dev;
  3913. ol_txrx_stats_rx_fp stats_cbk;
  3914. uint8_t pkt_type;
  3915. qdf_assert(tx_desc);
  3916. if (!vdev ||
  3917. !vdev->osif_vdev ||
  3918. !vdev->stats_cb)
  3919. return;
  3920. osif_dev = vdev->osif_vdev;
  3921. stats_cbk = vdev->stats_cb;
  3922. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3923. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3924. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3925. &pkt_type);
  3926. }
  3927. #endif
  3928. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF)
  3929. QDF_STATUS
  3930. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  3931. uint32_t delta_tsf,
  3932. uint32_t *delay_us)
  3933. {
  3934. uint32_t buffer_ts;
  3935. uint32_t delay;
  3936. if (!delay_us)
  3937. return QDF_STATUS_E_INVAL;
  3938. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3939. if (!ts->valid)
  3940. return QDF_STATUS_E_INVAL;
  3941. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3942. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3943. * valid up to 29 bits.
  3944. */
  3945. buffer_ts = ts->buffer_timestamp << 10;
  3946. delay = ts->tsf - buffer_ts - delta_tsf;
  3947. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3948. if (delay > 0x1000000) {
  3949. dp_info_rl("----------------------\n"
  3950. "Tx completion status:\n"
  3951. "----------------------\n"
  3952. "release_src = %d\n"
  3953. "ppdu_id = 0x%x\n"
  3954. "release_reason = %d\n"
  3955. "tsf = %u (0x%x)\n"
  3956. "buffer_timestamp = %u (0x%x)\n"
  3957. "delta_tsf = %u (0x%x)\n",
  3958. ts->release_src, ts->ppdu_id, ts->status,
  3959. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3960. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3961. return QDF_STATUS_E_FAILURE;
  3962. }
  3963. *delay_us = delay;
  3964. return QDF_STATUS_SUCCESS;
  3965. }
  3966. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3967. uint32_t delta_tsf)
  3968. {
  3969. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3970. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3971. DP_MOD_ID_CDP);
  3972. if (!vdev) {
  3973. dp_err_rl("vdev %d does not exist", vdev_id);
  3974. return;
  3975. }
  3976. vdev->delta_tsf = delta_tsf;
  3977. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3978. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3979. }
  3980. #endif
  3981. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3982. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3983. uint8_t vdev_id, bool enable)
  3984. {
  3985. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3986. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3987. DP_MOD_ID_CDP);
  3988. if (!vdev) {
  3989. dp_err_rl("vdev %d does not exist", vdev_id);
  3990. return QDF_STATUS_E_FAILURE;
  3991. }
  3992. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3993. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3994. return QDF_STATUS_SUCCESS;
  3995. }
  3996. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3997. uint32_t *val)
  3998. {
  3999. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4000. struct dp_vdev *vdev;
  4001. uint32_t delay_accum;
  4002. uint32_t pkts_accum;
  4003. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4004. if (!vdev) {
  4005. dp_err_rl("vdev %d does not exist", vdev_id);
  4006. return QDF_STATUS_E_FAILURE;
  4007. }
  4008. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4009. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4010. return QDF_STATUS_E_FAILURE;
  4011. }
  4012. /* Average uplink delay based on current accumulated values */
  4013. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4014. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4015. *val = delay_accum / pkts_accum;
  4016. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4017. delay_accum, pkts_accum);
  4018. /* Reset accumulated values to 0 */
  4019. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4020. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4021. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4022. return QDF_STATUS_SUCCESS;
  4023. }
  4024. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4025. struct hal_tx_completion_status *ts)
  4026. {
  4027. uint32_t ul_delay;
  4028. if (qdf_unlikely(!vdev)) {
  4029. dp_info_rl("vdev is null or delete in progrss");
  4030. return;
  4031. }
  4032. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4033. return;
  4034. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4035. vdev->delta_tsf,
  4036. &ul_delay)))
  4037. return;
  4038. ul_delay /= 1000; /* in unit of ms */
  4039. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4040. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4041. }
  4042. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4043. static inline
  4044. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4045. struct hal_tx_completion_status *ts)
  4046. {
  4047. }
  4048. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4049. /**
  4050. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4051. * @soc: DP soc handle
  4052. * @tx_desc: software descriptor head pointer
  4053. * @ts: Tx completion status
  4054. * @txrx_peer: txrx peer handle
  4055. * @ring_id: ring number
  4056. *
  4057. * Return: none
  4058. */
  4059. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4060. struct dp_tx_desc_s *tx_desc,
  4061. struct hal_tx_completion_status *ts,
  4062. struct dp_txrx_peer *txrx_peer,
  4063. uint8_t ring_id)
  4064. {
  4065. uint32_t length;
  4066. qdf_ether_header_t *eh;
  4067. struct dp_vdev *vdev = NULL;
  4068. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4069. enum qdf_dp_tx_rx_status dp_status;
  4070. if (!nbuf) {
  4071. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4072. goto out;
  4073. }
  4074. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4075. length = qdf_nbuf_len(nbuf);
  4076. dp_status = dp_tx_hw_to_qdf(ts->status);
  4077. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4078. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4079. QDF_TRACE_DEFAULT_PDEV_ID,
  4080. qdf_nbuf_data_addr(nbuf),
  4081. sizeof(qdf_nbuf_data(nbuf)),
  4082. tx_desc->id, ts->status, dp_status));
  4083. dp_tx_comp_debug("-------------------- \n"
  4084. "Tx Completion Stats: \n"
  4085. "-------------------- \n"
  4086. "ack_frame_rssi = %d \n"
  4087. "first_msdu = %d \n"
  4088. "last_msdu = %d \n"
  4089. "msdu_part_of_amsdu = %d \n"
  4090. "rate_stats valid = %d \n"
  4091. "bw = %d \n"
  4092. "pkt_type = %d \n"
  4093. "stbc = %d \n"
  4094. "ldpc = %d \n"
  4095. "sgi = %d \n"
  4096. "mcs = %d \n"
  4097. "ofdma = %d \n"
  4098. "tones_in_ru = %d \n"
  4099. "tsf = %d \n"
  4100. "ppdu_id = %d \n"
  4101. "transmit_cnt = %d \n"
  4102. "tid = %d \n"
  4103. "peer_id = %d\n"
  4104. "tx_status = %d\n",
  4105. ts->ack_frame_rssi, ts->first_msdu,
  4106. ts->last_msdu, ts->msdu_part_of_amsdu,
  4107. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4108. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4109. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4110. ts->transmit_cnt, ts->tid, ts->peer_id,
  4111. ts->status);
  4112. /* Update SoC level stats */
  4113. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4114. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4115. if (!txrx_peer) {
  4116. dp_info_rl("peer is null or deletion in progress");
  4117. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4118. goto out;
  4119. }
  4120. vdev = txrx_peer->vdev;
  4121. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4122. dp_tx_update_uplink_delay(soc, vdev, ts);
  4123. /* check tx complete notification */
  4124. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4125. dp_tx_notify_completion(soc, vdev, tx_desc,
  4126. nbuf, ts->status);
  4127. /* Update per-packet stats for mesh mode */
  4128. if (qdf_unlikely(vdev->mesh_vdev) &&
  4129. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4130. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4131. /* Update peer level stats */
  4132. if (qdf_unlikely(txrx_peer->bss_peer &&
  4133. vdev->opmode == wlan_op_mode_ap)) {
  4134. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4135. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4136. length);
  4137. if (txrx_peer->vdev->tx_encap_type ==
  4138. htt_cmn_pkt_type_ethernet &&
  4139. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4140. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4141. tx.bcast, 1,
  4142. length);
  4143. }
  4144. }
  4145. } else {
  4146. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4147. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4148. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4149. 1, length);
  4150. if (qdf_unlikely(txrx_peer->in_twt)) {
  4151. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4152. tx.tx_success_twt,
  4153. 1, length);
  4154. }
  4155. }
  4156. }
  4157. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4158. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts->tid, ring_id);
  4159. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4160. ts, ts->tid);
  4161. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4162. #ifdef QCA_SUPPORT_RDK_STATS
  4163. if (soc->peerstats_enabled)
  4164. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4165. qdf_ktime_to_ms(tx_desc->timestamp),
  4166. ts->ppdu_id);
  4167. #endif
  4168. out:
  4169. return;
  4170. }
  4171. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4172. defined(QCA_ENHANCED_STATS_SUPPORT)
  4173. /*
  4174. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4175. * @txrx_peer: Datapath txrx_peer handle
  4176. * @length: Length of the packet
  4177. * @tx_status: Tx status from TQM/FW
  4178. * @update: enhanced flag value present in dp_pdev
  4179. *
  4180. * Return: none
  4181. */
  4182. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4183. uint32_t length, uint8_t tx_status,
  4184. bool update)
  4185. {
  4186. if ((!txrx_peer->hw_txrx_stats_en) || update) {
  4187. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4188. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4189. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4190. }
  4191. }
  4192. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4193. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4194. uint32_t length, uint8_t tx_status,
  4195. bool update)
  4196. {
  4197. if (!peer->hw_txrx_stats_en) {
  4198. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4199. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4200. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4201. }
  4202. }
  4203. #else
  4204. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4205. uint32_t length, uint8_t tx_status,
  4206. bool update)
  4207. {
  4208. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4209. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4210. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4211. }
  4212. #endif
  4213. /*
  4214. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4215. * @nbuf: skb buffer
  4216. *
  4217. * Return: none
  4218. */
  4219. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4220. static inline
  4221. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4222. {
  4223. qdf_nbuf_t nbuf = NULL;
  4224. if (next)
  4225. nbuf = next->nbuf;
  4226. if (nbuf) {
  4227. /* prefetch skb->next and first few bytes of skb->cb */
  4228. qdf_prefetch(nbuf);
  4229. /* prefetch skb fields present in different cachelines */
  4230. qdf_prefetch(&nbuf->len);
  4231. qdf_prefetch(&nbuf->users);
  4232. qdf_prefetch(skb_end_pointer(nbuf));
  4233. }
  4234. }
  4235. #else
  4236. static inline
  4237. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4238. {
  4239. }
  4240. #endif
  4241. /**
  4242. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4243. * @soc: core txrx main context
  4244. * @desc: software descriptor
  4245. *
  4246. * Return: true when packet is reinjected
  4247. */
  4248. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4249. defined(WLAN_MCAST_MLO)
  4250. static inline bool
  4251. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4252. {
  4253. struct dp_vdev *vdev = NULL;
  4254. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4255. if (!soc->arch_ops.dp_tx_mcast_handler)
  4256. return false;
  4257. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4258. DP_MOD_ID_REINJECT);
  4259. if (qdf_unlikely(!vdev)) {
  4260. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4261. desc->id);
  4262. return false;
  4263. }
  4264. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4265. qdf_nbuf_len(desc->nbuf));
  4266. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4267. dp_tx_desc_release(desc, desc->pool_id);
  4268. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4269. return true;
  4270. }
  4271. return false;
  4272. }
  4273. #else
  4274. static inline bool
  4275. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4276. {
  4277. return false;
  4278. }
  4279. #endif
  4280. /**
  4281. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4282. * @soc: core txrx main context
  4283. * @comp_head: software descriptor head pointer
  4284. * @ring_id: ring number
  4285. *
  4286. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4287. * and release the software descriptors after processing is complete
  4288. *
  4289. * Return: none
  4290. */
  4291. static void
  4292. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4293. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4294. {
  4295. struct dp_tx_desc_s *desc;
  4296. struct dp_tx_desc_s *next;
  4297. struct hal_tx_completion_status ts;
  4298. struct dp_txrx_peer *txrx_peer = NULL;
  4299. uint16_t peer_id = DP_INVALID_PEER;
  4300. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4301. desc = comp_head;
  4302. while (desc) {
  4303. next = desc->next;
  4304. dp_tx_prefetch_next_nbuf_data(next);
  4305. if (peer_id != desc->peer_id) {
  4306. if (txrx_peer)
  4307. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4308. DP_MOD_ID_TX_COMP);
  4309. peer_id = desc->peer_id;
  4310. txrx_peer =
  4311. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4312. &txrx_ref_handle,
  4313. DP_MOD_ID_TX_COMP);
  4314. }
  4315. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4316. desc = next;
  4317. continue;
  4318. }
  4319. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4320. struct dp_pdev *pdev = desc->pdev;
  4321. if (qdf_likely(txrx_peer))
  4322. dp_tx_update_peer_basic_stats(txrx_peer,
  4323. desc->length,
  4324. desc->tx_status,
  4325. false);
  4326. qdf_assert(pdev);
  4327. dp_tx_outstanding_dec(pdev);
  4328. /*
  4329. * Calling a QDF WRAPPER here is creating signifcant
  4330. * performance impact so avoided the wrapper call here
  4331. */
  4332. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4333. desc->id, DP_TX_COMP_UNMAP);
  4334. dp_tx_nbuf_unmap(soc, desc);
  4335. qdf_nbuf_free_simple(desc->nbuf);
  4336. dp_tx_desc_free(soc, desc, desc->pool_id);
  4337. desc = next;
  4338. continue;
  4339. }
  4340. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4341. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4342. ring_id);
  4343. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4344. dp_tx_desc_release(desc, desc->pool_id);
  4345. desc = next;
  4346. }
  4347. if (txrx_peer)
  4348. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4349. }
  4350. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4351. static inline
  4352. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4353. int max_reap_limit)
  4354. {
  4355. bool limit_hit = false;
  4356. limit_hit =
  4357. (num_reaped >= max_reap_limit) ? true : false;
  4358. if (limit_hit)
  4359. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4360. return limit_hit;
  4361. }
  4362. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4363. {
  4364. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4365. }
  4366. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4367. {
  4368. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4369. return cfg->tx_comp_loop_pkt_limit;
  4370. }
  4371. #else
  4372. static inline
  4373. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4374. int max_reap_limit)
  4375. {
  4376. return false;
  4377. }
  4378. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4379. {
  4380. return false;
  4381. }
  4382. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4383. {
  4384. return 0;
  4385. }
  4386. #endif
  4387. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  4388. static inline int
  4389. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4390. int *max_reap_limit)
  4391. {
  4392. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  4393. max_reap_limit);
  4394. }
  4395. #else
  4396. static inline int
  4397. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  4398. int *max_reap_limit)
  4399. {
  4400. return 0;
  4401. }
  4402. #endif
  4403. #ifdef DP_TX_TRACKING
  4404. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  4405. {
  4406. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  4407. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  4408. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  4409. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  4410. }
  4411. }
  4412. #endif
  4413. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  4414. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  4415. uint32_t quota)
  4416. {
  4417. void *tx_comp_hal_desc;
  4418. void *last_prefetched_hw_desc = NULL;
  4419. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  4420. hal_soc_handle_t hal_soc;
  4421. uint8_t buffer_src;
  4422. struct dp_tx_desc_s *tx_desc = NULL;
  4423. struct dp_tx_desc_s *head_desc = NULL;
  4424. struct dp_tx_desc_s *tail_desc = NULL;
  4425. uint32_t num_processed = 0;
  4426. uint32_t count;
  4427. uint32_t num_avail_for_reap = 0;
  4428. bool force_break = false;
  4429. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4430. int max_reap_limit, ring_near_full;
  4431. DP_HIST_INIT();
  4432. more_data:
  4433. hal_soc = soc->hal_soc;
  4434. /* Re-initialize local variables to be re-used */
  4435. head_desc = NULL;
  4436. tail_desc = NULL;
  4437. count = 0;
  4438. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4439. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4440. &max_reap_limit);
  4441. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4442. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4443. return 0;
  4444. }
  4445. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  4446. if (num_avail_for_reap >= quota)
  4447. num_avail_for_reap = quota;
  4448. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4449. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  4450. num_avail_for_reap);
  4451. /* Find head descriptor from completion ring */
  4452. while (qdf_likely(num_avail_for_reap--)) {
  4453. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4454. if (qdf_unlikely(!tx_comp_hal_desc))
  4455. break;
  4456. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  4457. tx_comp_hal_desc);
  4458. /* If this buffer was not released by TQM or FW, then it is not
  4459. * Tx completion indication, assert */
  4460. if (qdf_unlikely(buffer_src !=
  4461. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4462. (qdf_unlikely(buffer_src !=
  4463. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4464. uint8_t wbm_internal_error;
  4465. dp_err_rl(
  4466. "Tx comp release_src != TQM | FW but from %d",
  4467. buffer_src);
  4468. hal_dump_comp_desc(tx_comp_hal_desc);
  4469. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4470. /* When WBM sees NULL buffer_addr_info in any of
  4471. * ingress rings it sends an error indication,
  4472. * with wbm_internal_error=1, to a specific ring.
  4473. * The WBM2SW ring used to indicate these errors is
  4474. * fixed in HW, and that ring is being used as Tx
  4475. * completion ring. These errors are not related to
  4476. * Tx completions, and should just be ignored
  4477. */
  4478. wbm_internal_error = hal_get_wbm_internal_error(
  4479. hal_soc,
  4480. tx_comp_hal_desc);
  4481. if (wbm_internal_error) {
  4482. dp_err_rl("Tx comp wbm_internal_error!!");
  4483. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4484. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4485. buffer_src)
  4486. dp_handle_wbm_internal_error(
  4487. soc,
  4488. tx_comp_hal_desc,
  4489. hal_tx_comp_get_buffer_type(
  4490. tx_comp_hal_desc));
  4491. } else {
  4492. dp_err_rl("Tx comp wbm_internal_error false");
  4493. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4494. }
  4495. continue;
  4496. }
  4497. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4498. tx_comp_hal_desc,
  4499. &tx_desc);
  4500. if (!tx_desc) {
  4501. dp_err("unable to retrieve tx_desc!");
  4502. QDF_BUG(0);
  4503. continue;
  4504. }
  4505. tx_desc->buffer_src = buffer_src;
  4506. /*
  4507. * If the release source is FW, process the HTT status
  4508. */
  4509. if (qdf_unlikely(buffer_src ==
  4510. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4511. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4512. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4513. htt_tx_status);
  4514. /* Collect hw completion contents */
  4515. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4516. &tx_desc->comp, 1);
  4517. soc->arch_ops.dp_tx_process_htt_completion(
  4518. soc,
  4519. tx_desc,
  4520. htt_tx_status,
  4521. ring_id);
  4522. } else {
  4523. tx_desc->tx_status =
  4524. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4525. tx_desc->buffer_src = buffer_src;
  4526. /*
  4527. * If the fast completion mode is enabled extended
  4528. * metadata from descriptor is not copied
  4529. */
  4530. if (qdf_likely(tx_desc->flags &
  4531. DP_TX_DESC_FLAG_SIMPLE))
  4532. goto add_to_pool;
  4533. /*
  4534. * If the descriptor is already freed in vdev_detach,
  4535. * continue to next descriptor
  4536. */
  4537. if (qdf_unlikely
  4538. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4539. !tx_desc->flags)) {
  4540. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4541. tx_desc->id);
  4542. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4543. dp_tx_desc_check_corruption(tx_desc);
  4544. continue;
  4545. }
  4546. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4547. dp_tx_comp_info_rl("pdev in down state %d",
  4548. tx_desc->id);
  4549. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4550. dp_tx_comp_free_buf(soc, tx_desc);
  4551. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4552. goto next_desc;
  4553. }
  4554. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4555. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4556. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4557. tx_desc->flags, tx_desc->id);
  4558. qdf_assert_always(0);
  4559. }
  4560. /* Collect hw completion contents */
  4561. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4562. &tx_desc->comp, 1);
  4563. add_to_pool:
  4564. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4565. /* First ring descriptor on the cycle */
  4566. if (!head_desc) {
  4567. head_desc = tx_desc;
  4568. tail_desc = tx_desc;
  4569. }
  4570. tail_desc->next = tx_desc;
  4571. tx_desc->next = NULL;
  4572. tail_desc = tx_desc;
  4573. }
  4574. next_desc:
  4575. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4576. /*
  4577. * Processed packet count is more than given quota
  4578. * stop to processing
  4579. */
  4580. count++;
  4581. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  4582. num_avail_for_reap,
  4583. hal_ring_hdl,
  4584. &last_prefetched_hw_desc,
  4585. &last_prefetched_sw_desc);
  4586. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4587. break;
  4588. }
  4589. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4590. /* Process the reaped descriptors */
  4591. if (head_desc)
  4592. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4593. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  4594. /*
  4595. * If we are processing in near-full condition, there are 3 scenario
  4596. * 1) Ring entries has reached critical state
  4597. * 2) Ring entries are still near high threshold
  4598. * 3) Ring entries are below the safe level
  4599. *
  4600. * One more loop will move te state to normal processing and yield
  4601. */
  4602. if (ring_near_full)
  4603. goto more_data;
  4604. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4605. if (num_processed >= quota)
  4606. force_break = true;
  4607. if (!force_break &&
  4608. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4609. hal_ring_hdl)) {
  4610. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4611. if (!hif_exec_should_yield(soc->hif_handle,
  4612. int_ctx->dp_intr_id))
  4613. goto more_data;
  4614. }
  4615. }
  4616. DP_TX_HIST_STATS_PER_PDEV();
  4617. return num_processed;
  4618. }
  4619. #ifdef FEATURE_WLAN_TDLS
  4620. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4621. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4622. {
  4623. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4624. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4625. DP_MOD_ID_TDLS);
  4626. if (!vdev) {
  4627. dp_err("vdev handle for id %d is NULL", vdev_id);
  4628. return NULL;
  4629. }
  4630. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4631. vdev->is_tdls_frame = true;
  4632. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4633. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4634. }
  4635. #endif
  4636. /**
  4637. * dp_tx_vdev_attach() - attach vdev to dp tx
  4638. * @vdev: virtual device instance
  4639. *
  4640. * Return: QDF_STATUS_SUCCESS: success
  4641. * QDF_STATUS_E_RESOURCES: Error return
  4642. */
  4643. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4644. {
  4645. int pdev_id;
  4646. /*
  4647. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4648. */
  4649. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4650. DP_TCL_METADATA_TYPE_VDEV_BASED);
  4651. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4652. vdev->vdev_id);
  4653. pdev_id =
  4654. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4655. vdev->pdev->pdev_id);
  4656. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4657. /*
  4658. * Set HTT Extension Valid bit to 0 by default
  4659. */
  4660. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4661. dp_tx_vdev_update_search_flags(vdev);
  4662. return QDF_STATUS_SUCCESS;
  4663. }
  4664. #ifndef FEATURE_WDS
  4665. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4666. {
  4667. return false;
  4668. }
  4669. #endif
  4670. /**
  4671. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4672. * @vdev: virtual device instance
  4673. *
  4674. * Return: void
  4675. *
  4676. */
  4677. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4678. {
  4679. struct dp_soc *soc = vdev->pdev->soc;
  4680. /*
  4681. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4682. * for TDLS link
  4683. *
  4684. * Enable AddrY (SA based search) only for non-WDS STA and
  4685. * ProxySTA VAP (in HKv1) modes.
  4686. *
  4687. * In all other VAP modes, only DA based search should be
  4688. * enabled
  4689. */
  4690. if (vdev->opmode == wlan_op_mode_sta &&
  4691. vdev->tdls_link_connected)
  4692. vdev->hal_desc_addr_search_flags =
  4693. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4694. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4695. !dp_tx_da_search_override(vdev))
  4696. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4697. else
  4698. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4699. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  4700. vdev->search_type = soc->sta_mode_search_policy;
  4701. else
  4702. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4703. }
  4704. static inline bool
  4705. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4706. struct dp_vdev *vdev,
  4707. struct dp_tx_desc_s *tx_desc)
  4708. {
  4709. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4710. return false;
  4711. /*
  4712. * if vdev is given, then only check whether desc
  4713. * vdev match. if vdev is NULL, then check whether
  4714. * desc pdev match.
  4715. */
  4716. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4717. (tx_desc->pdev == pdev);
  4718. }
  4719. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4720. /**
  4721. * dp_tx_desc_flush() - release resources associated
  4722. * to TX Desc
  4723. *
  4724. * @dp_pdev: Handle to DP pdev structure
  4725. * @vdev: virtual device instance
  4726. * NULL: no specific Vdev is required and check all allcated TX desc
  4727. * on this pdev.
  4728. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4729. *
  4730. * @force_free:
  4731. * true: flush the TX desc.
  4732. * false: only reset the Vdev in each allocated TX desc
  4733. * that associated to current Vdev.
  4734. *
  4735. * This function will go through the TX desc pool to flush
  4736. * the outstanding TX data or reset Vdev to NULL in associated TX
  4737. * Desc.
  4738. */
  4739. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4740. bool force_free)
  4741. {
  4742. uint8_t i;
  4743. uint32_t j;
  4744. uint32_t num_desc, page_id, offset;
  4745. uint16_t num_desc_per_page;
  4746. struct dp_soc *soc = pdev->soc;
  4747. struct dp_tx_desc_s *tx_desc = NULL;
  4748. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4749. if (!vdev && !force_free) {
  4750. dp_err("Reset TX desc vdev, Vdev param is required!");
  4751. return;
  4752. }
  4753. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4754. tx_desc_pool = &soc->tx_desc[i];
  4755. if (!(tx_desc_pool->pool_size) ||
  4756. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4757. !(tx_desc_pool->desc_pages.cacheable_pages))
  4758. continue;
  4759. /*
  4760. * Add flow pool lock protection in case pool is freed
  4761. * due to all tx_desc is recycled when handle TX completion.
  4762. * this is not necessary when do force flush as:
  4763. * a. double lock will happen if dp_tx_desc_release is
  4764. * also trying to acquire it.
  4765. * b. dp interrupt has been disabled before do force TX desc
  4766. * flush in dp_pdev_deinit().
  4767. */
  4768. if (!force_free)
  4769. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4770. num_desc = tx_desc_pool->pool_size;
  4771. num_desc_per_page =
  4772. tx_desc_pool->desc_pages.num_element_per_page;
  4773. for (j = 0; j < num_desc; j++) {
  4774. page_id = j / num_desc_per_page;
  4775. offset = j % num_desc_per_page;
  4776. if (qdf_unlikely(!(tx_desc_pool->
  4777. desc_pages.cacheable_pages)))
  4778. break;
  4779. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4780. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4781. /*
  4782. * Free TX desc if force free is
  4783. * required, otherwise only reset vdev
  4784. * in this TX desc.
  4785. */
  4786. if (force_free) {
  4787. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4788. dp_tx_comp_free_buf(soc, tx_desc);
  4789. dp_tx_desc_release(tx_desc, i);
  4790. } else {
  4791. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4792. }
  4793. }
  4794. }
  4795. if (!force_free)
  4796. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4797. }
  4798. }
  4799. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4800. /**
  4801. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4802. *
  4803. * @soc: Handle to DP soc structure
  4804. * @tx_desc: pointer of one TX desc
  4805. * @desc_pool_id: TX Desc pool id
  4806. */
  4807. static inline void
  4808. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4809. uint8_t desc_pool_id)
  4810. {
  4811. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4812. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4813. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4814. }
  4815. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4816. bool force_free)
  4817. {
  4818. uint8_t i, num_pool;
  4819. uint32_t j;
  4820. uint32_t num_desc, page_id, offset;
  4821. uint16_t num_desc_per_page;
  4822. struct dp_soc *soc = pdev->soc;
  4823. struct dp_tx_desc_s *tx_desc = NULL;
  4824. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4825. if (!vdev && !force_free) {
  4826. dp_err("Reset TX desc vdev, Vdev param is required!");
  4827. return;
  4828. }
  4829. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4830. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4831. for (i = 0; i < num_pool; i++) {
  4832. tx_desc_pool = &soc->tx_desc[i];
  4833. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4834. continue;
  4835. num_desc_per_page =
  4836. tx_desc_pool->desc_pages.num_element_per_page;
  4837. for (j = 0; j < num_desc; j++) {
  4838. page_id = j / num_desc_per_page;
  4839. offset = j % num_desc_per_page;
  4840. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4841. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4842. if (force_free) {
  4843. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4844. dp_tx_comp_free_buf(soc, tx_desc);
  4845. dp_tx_desc_release(tx_desc, i);
  4846. } else {
  4847. dp_tx_desc_reset_vdev(soc, tx_desc,
  4848. i);
  4849. }
  4850. }
  4851. }
  4852. }
  4853. }
  4854. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4855. /**
  4856. * dp_tx_vdev_detach() - detach vdev from dp tx
  4857. * @vdev: virtual device instance
  4858. *
  4859. * Return: QDF_STATUS_SUCCESS: success
  4860. * QDF_STATUS_E_RESOURCES: Error return
  4861. */
  4862. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4863. {
  4864. struct dp_pdev *pdev = vdev->pdev;
  4865. /* Reset TX desc associated to this Vdev as NULL */
  4866. dp_tx_desc_flush(pdev, vdev, false);
  4867. return QDF_STATUS_SUCCESS;
  4868. }
  4869. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4870. /* Pools will be allocated dynamically */
  4871. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4872. int num_desc)
  4873. {
  4874. uint8_t i;
  4875. for (i = 0; i < num_pool; i++) {
  4876. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4877. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4878. }
  4879. return QDF_STATUS_SUCCESS;
  4880. }
  4881. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4882. uint32_t num_desc)
  4883. {
  4884. return QDF_STATUS_SUCCESS;
  4885. }
  4886. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4887. {
  4888. }
  4889. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4890. {
  4891. uint8_t i;
  4892. for (i = 0; i < num_pool; i++)
  4893. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4894. }
  4895. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4896. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4897. uint32_t num_desc)
  4898. {
  4899. uint8_t i, count;
  4900. /* Allocate software Tx descriptor pools */
  4901. for (i = 0; i < num_pool; i++) {
  4902. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4903. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4904. FL("Tx Desc Pool alloc %d failed %pK"),
  4905. i, soc);
  4906. goto fail;
  4907. }
  4908. }
  4909. return QDF_STATUS_SUCCESS;
  4910. fail:
  4911. for (count = 0; count < i; count++)
  4912. dp_tx_desc_pool_free(soc, count);
  4913. return QDF_STATUS_E_NOMEM;
  4914. }
  4915. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4916. uint32_t num_desc)
  4917. {
  4918. uint8_t i;
  4919. for (i = 0; i < num_pool; i++) {
  4920. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4922. FL("Tx Desc Pool init %d failed %pK"),
  4923. i, soc);
  4924. return QDF_STATUS_E_NOMEM;
  4925. }
  4926. }
  4927. return QDF_STATUS_SUCCESS;
  4928. }
  4929. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4930. {
  4931. uint8_t i;
  4932. for (i = 0; i < num_pool; i++)
  4933. dp_tx_desc_pool_deinit(soc, i);
  4934. }
  4935. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4936. {
  4937. uint8_t i;
  4938. for (i = 0; i < num_pool; i++)
  4939. dp_tx_desc_pool_free(soc, i);
  4940. }
  4941. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4942. /**
  4943. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4944. * @soc: core txrx main context
  4945. * @num_pool: number of pools
  4946. *
  4947. */
  4948. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4949. {
  4950. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4951. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4952. }
  4953. /**
  4954. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4955. * @soc: core txrx main context
  4956. * @num_pool: number of pools
  4957. *
  4958. */
  4959. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4960. {
  4961. dp_tx_tso_desc_pool_free(soc, num_pool);
  4962. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4963. }
  4964. /**
  4965. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4966. * @soc: core txrx main context
  4967. *
  4968. * This function frees all tx related descriptors as below
  4969. * 1. Regular TX descriptors (static pools)
  4970. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4971. * 3. TSO descriptors
  4972. *
  4973. */
  4974. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4975. {
  4976. uint8_t num_pool;
  4977. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4978. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4979. dp_tx_ext_desc_pool_free(soc, num_pool);
  4980. dp_tx_delete_static_pools(soc, num_pool);
  4981. }
  4982. /**
  4983. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4984. * @soc: core txrx main context
  4985. *
  4986. * This function de-initializes all tx related descriptors as below
  4987. * 1. Regular TX descriptors (static pools)
  4988. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4989. * 3. TSO descriptors
  4990. *
  4991. */
  4992. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4993. {
  4994. uint8_t num_pool;
  4995. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4996. dp_tx_flow_control_deinit(soc);
  4997. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4998. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4999. dp_tx_deinit_static_pools(soc, num_pool);
  5000. }
  5001. /**
  5002. * dp_tso_attach() - TSO attach handler
  5003. * @txrx_soc: Opaque Dp handle
  5004. *
  5005. * Reserve TSO descriptor buffers
  5006. *
  5007. * Return: QDF_STATUS_E_FAILURE on failure or
  5008. * QDF_STATUS_SUCCESS on success
  5009. */
  5010. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5011. uint8_t num_pool,
  5012. uint32_t num_desc)
  5013. {
  5014. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5015. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5016. return QDF_STATUS_E_FAILURE;
  5017. }
  5018. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5019. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5020. num_pool, soc);
  5021. return QDF_STATUS_E_FAILURE;
  5022. }
  5023. return QDF_STATUS_SUCCESS;
  5024. }
  5025. /**
  5026. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5027. * @soc: DP soc handle
  5028. * @num_pool: Number of pools
  5029. * @num_desc: Number of descriptors
  5030. *
  5031. * Initialize TSO descriptor pools
  5032. *
  5033. * Return: QDF_STATUS_E_FAILURE on failure or
  5034. * QDF_STATUS_SUCCESS on success
  5035. */
  5036. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5037. uint8_t num_pool,
  5038. uint32_t num_desc)
  5039. {
  5040. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5041. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5042. return QDF_STATUS_E_FAILURE;
  5043. }
  5044. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5045. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5046. num_pool, soc);
  5047. return QDF_STATUS_E_FAILURE;
  5048. }
  5049. return QDF_STATUS_SUCCESS;
  5050. }
  5051. /**
  5052. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5053. * @soc: core txrx main context
  5054. *
  5055. * This function allocates memory for following descriptor pools
  5056. * 1. regular sw tx descriptor pools (static pools)
  5057. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5058. * 3. TSO descriptor pools
  5059. *
  5060. * Return: QDF_STATUS_SUCCESS: success
  5061. * QDF_STATUS_E_RESOURCES: Error return
  5062. */
  5063. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5064. {
  5065. uint8_t num_pool;
  5066. uint32_t num_desc;
  5067. uint32_t num_ext_desc;
  5068. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5069. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5070. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5071. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5072. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5073. __func__, num_pool, num_desc);
  5074. if ((num_pool > MAX_TXDESC_POOLS) ||
  5075. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5076. goto fail1;
  5077. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5078. goto fail1;
  5079. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5080. goto fail2;
  5081. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5082. return QDF_STATUS_SUCCESS;
  5083. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5084. goto fail3;
  5085. return QDF_STATUS_SUCCESS;
  5086. fail3:
  5087. dp_tx_ext_desc_pool_free(soc, num_pool);
  5088. fail2:
  5089. dp_tx_delete_static_pools(soc, num_pool);
  5090. fail1:
  5091. return QDF_STATUS_E_RESOURCES;
  5092. }
  5093. /**
  5094. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5095. * @soc: core txrx main context
  5096. *
  5097. * This function initializes the following TX descriptor pools
  5098. * 1. regular sw tx descriptor pools (static pools)
  5099. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5100. * 3. TSO descriptor pools
  5101. *
  5102. * Return: QDF_STATUS_SUCCESS: success
  5103. * QDF_STATUS_E_RESOURCES: Error return
  5104. */
  5105. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5106. {
  5107. uint8_t num_pool;
  5108. uint32_t num_desc;
  5109. uint32_t num_ext_desc;
  5110. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5111. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5112. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5113. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5114. goto fail1;
  5115. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5116. goto fail2;
  5117. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5118. return QDF_STATUS_SUCCESS;
  5119. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5120. goto fail3;
  5121. dp_tx_flow_control_init(soc);
  5122. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5123. return QDF_STATUS_SUCCESS;
  5124. fail3:
  5125. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5126. fail2:
  5127. dp_tx_deinit_static_pools(soc, num_pool);
  5128. fail1:
  5129. return QDF_STATUS_E_RESOURCES;
  5130. }
  5131. /**
  5132. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5133. * @txrx_soc: dp soc handle
  5134. *
  5135. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5136. * QDF_STATUS_E_FAILURE
  5137. */
  5138. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5139. {
  5140. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5141. uint8_t num_pool;
  5142. uint32_t num_desc;
  5143. uint32_t num_ext_desc;
  5144. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5145. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5146. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5147. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5148. return QDF_STATUS_E_FAILURE;
  5149. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5150. return QDF_STATUS_E_FAILURE;
  5151. return QDF_STATUS_SUCCESS;
  5152. }
  5153. /**
  5154. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5155. * @txrx_soc: dp soc handle
  5156. *
  5157. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5158. */
  5159. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5160. {
  5161. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5162. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5163. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5164. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5165. return QDF_STATUS_SUCCESS;
  5166. }