dp_main.c 163 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. bool rx_hash = 1;
  71. qdf_declare_param(rx_hash, bool);
  72. #define STR_MAXLEN 64
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  252. };
  253. /**
  254. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  255. * @ring_num: ring num of the ring being queried
  256. * @grp_mask: the grp_mask array for the ring type in question.
  257. *
  258. * The grp_mask array is indexed by group number and the bit fields correspond
  259. * to ring numbers. We are finding which interrupt group a ring belongs to.
  260. *
  261. * Return: the index in the grp_mask array with the ring number.
  262. * -QDF_STATUS_E_NOENT if no entry is found
  263. */
  264. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  265. {
  266. int ext_group_num;
  267. int mask = 1 << ring_num;
  268. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  269. ext_group_num++) {
  270. if (mask & grp_mask[ext_group_num])
  271. return ext_group_num;
  272. }
  273. return -QDF_STATUS_E_NOENT;
  274. }
  275. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  276. enum hal_ring_type ring_type,
  277. int ring_num)
  278. {
  279. int *grp_mask;
  280. switch (ring_type) {
  281. case WBM2SW_RELEASE:
  282. /* dp_tx_comp_handler - soc->tx_comp_ring */
  283. if (ring_num < 3)
  284. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  285. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  286. else if (ring_num == 3) {
  287. /* sw treats this as a separate ring type */
  288. grp_mask = &soc->wlan_cfg_ctx->
  289. int_rx_wbm_rel_ring_mask[0];
  290. ring_num = 0;
  291. } else {
  292. qdf_assert(0);
  293. return -QDF_STATUS_E_NOENT;
  294. }
  295. break;
  296. case REO_EXCEPTION:
  297. /* dp_rx_err_process - &soc->reo_exception_ring */
  298. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  299. break;
  300. case REO_DST:
  301. /* dp_rx_process - soc->reo_dest_ring */
  302. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  303. break;
  304. case REO_STATUS:
  305. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  306. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  307. break;
  308. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  309. case RXDMA_MONITOR_STATUS:
  310. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  311. case RXDMA_MONITOR_DST:
  312. /* dp_mon_process */
  313. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  314. break;
  315. case RXDMA_DST:
  316. /* dp_rxdma_err_process */
  317. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  318. break;
  319. case RXDMA_MONITOR_BUF:
  320. case RXDMA_BUF:
  321. /* TODO: support low_thresh interrupt */
  322. return -QDF_STATUS_E_NOENT;
  323. break;
  324. case TCL_DATA:
  325. case TCL_CMD:
  326. case REO_CMD:
  327. case SW2WBM_RELEASE:
  328. case WBM_IDLE_LINK:
  329. /* normally empty SW_TO_HW rings */
  330. return -QDF_STATUS_E_NOENT;
  331. break;
  332. case TCL_STATUS:
  333. case REO_REINJECT:
  334. /* misc unused rings */
  335. return -QDF_STATUS_E_NOENT;
  336. break;
  337. case CE_SRC:
  338. case CE_DST:
  339. case CE_DST_STATUS:
  340. /* CE_rings - currently handled by hif */
  341. default:
  342. return -QDF_STATUS_E_NOENT;
  343. break;
  344. }
  345. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  346. }
  347. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  348. *ring_params, int ring_type, int ring_num)
  349. {
  350. int msi_group_number;
  351. int msi_data_count;
  352. int ret;
  353. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  354. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  355. &msi_data_count, &msi_data_start,
  356. &msi_irq_start);
  357. if (ret)
  358. return;
  359. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  360. ring_num);
  361. if (msi_group_number < 0) {
  362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  363. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  364. ring_type, ring_num);
  365. ring_params->msi_addr = 0;
  366. ring_params->msi_data = 0;
  367. return;
  368. }
  369. if (msi_group_number > msi_data_count) {
  370. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  371. FL("2 msi_groups will share an msi; msi_group_num %d"),
  372. msi_group_number);
  373. QDF_ASSERT(0);
  374. }
  375. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  376. ring_params->msi_addr = addr_low;
  377. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  378. ring_params->msi_data = (msi_group_number % msi_data_count)
  379. + msi_data_start;
  380. ring_params->flags |= HAL_SRNG_MSI_INTR;
  381. }
  382. /**
  383. * dp_print_ast_stats() - Dump AST table contents
  384. * @soc: Datapath soc handle
  385. *
  386. * return void
  387. */
  388. #ifdef FEATURE_WDS
  389. static void dp_print_ast_stats(struct dp_soc *soc)
  390. {
  391. uint8_t i;
  392. uint8_t num_entries = 0;
  393. struct dp_vdev *vdev;
  394. struct dp_pdev *pdev;
  395. struct dp_peer *peer;
  396. struct dp_ast_entry *ase, *tmp_ase;
  397. DP_PRINT_STATS("AST Stats:");
  398. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  399. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  400. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  401. DP_PRINT_STATS("AST Table:");
  402. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  403. pdev = soc->pdev_list[i];
  404. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  405. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  406. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  407. DP_PRINT_STATS("%6d mac_addr = %pM"
  408. " peer_mac_addr = %pM"
  409. " type = %d"
  410. " next_hop = %d"
  411. " is_active = %d"
  412. " is_bss = %d",
  413. ++num_entries,
  414. ase->mac_addr.raw,
  415. ase->peer->mac_addr.raw,
  416. ase->type,
  417. ase->next_hop,
  418. ase->is_active,
  419. ase->is_bss);
  420. }
  421. }
  422. }
  423. }
  424. }
  425. #else
  426. static void dp_print_ast_stats(struct dp_soc *soc)
  427. {
  428. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  429. return;
  430. }
  431. #endif
  432. /*
  433. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  434. */
  435. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  436. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  437. {
  438. void *hal_soc = soc->hal_soc;
  439. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  440. /* TODO: See if we should get align size from hal */
  441. uint32_t ring_base_align = 8;
  442. struct hal_srng_params ring_params;
  443. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  444. /* TODO: Currently hal layer takes care of endianness related settings.
  445. * See if these settings need to passed from DP layer
  446. */
  447. ring_params.flags = 0;
  448. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  449. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  450. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  451. srng->hal_srng = NULL;
  452. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  453. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  454. soc->osdev, soc->osdev->dev, srng->alloc_size,
  455. &(srng->base_paddr_unaligned));
  456. if (!srng->base_vaddr_unaligned) {
  457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  458. FL("alloc failed - ring_type: %d, ring_num %d"),
  459. ring_type, ring_num);
  460. return QDF_STATUS_E_NOMEM;
  461. }
  462. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  463. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  464. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  465. ((unsigned long)(ring_params.ring_base_vaddr) -
  466. (unsigned long)srng->base_vaddr_unaligned);
  467. ring_params.num_entries = num_entries;
  468. if (soc->intr_mode == DP_INTR_MSI) {
  469. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  471. FL("Using MSI for ring_type: %d, ring_num %d"),
  472. ring_type, ring_num);
  473. } else {
  474. ring_params.msi_data = 0;
  475. ring_params.msi_addr = 0;
  476. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  477. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  478. ring_type, ring_num);
  479. }
  480. /*
  481. * Setup interrupt timer and batch counter thresholds for
  482. * interrupt mitigation based on ring type
  483. */
  484. if (ring_type == REO_DST) {
  485. ring_params.intr_timer_thres_us =
  486. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  487. ring_params.intr_batch_cntr_thres_entries =
  488. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  489. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  490. ring_params.intr_timer_thres_us =
  491. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  492. ring_params.intr_batch_cntr_thres_entries =
  493. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  494. } else {
  495. ring_params.intr_timer_thres_us =
  496. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  497. ring_params.intr_batch_cntr_thres_entries =
  498. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  499. }
  500. /* Enable low threshold interrupts for rx buffer rings (regular and
  501. * monitor buffer rings.
  502. * TODO: See if this is required for any other ring
  503. */
  504. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  505. /* TODO: Setting low threshold to 1/8th of ring size
  506. * see if this needs to be configurable
  507. */
  508. ring_params.low_threshold = num_entries >> 3;
  509. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  510. ring_params.intr_timer_thres_us = 0x1000;
  511. }
  512. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  513. mac_id, &ring_params);
  514. return 0;
  515. }
  516. /**
  517. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  518. * Any buffers allocated and attached to ring entries are expected to be freed
  519. * before calling this function.
  520. */
  521. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  522. int ring_type, int ring_num)
  523. {
  524. if (!srng->hal_srng) {
  525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  526. FL("Ring type: %d, num:%d not setup"),
  527. ring_type, ring_num);
  528. return;
  529. }
  530. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  531. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  532. srng->alloc_size,
  533. srng->base_vaddr_unaligned,
  534. srng->base_paddr_unaligned, 0);
  535. srng->hal_srng = NULL;
  536. }
  537. #ifdef IPA_OFFLOAD
  538. /**
  539. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  540. * @soc: data path instance
  541. * @pdev: core txrx pdev context
  542. *
  543. * Free allocated TX buffers with WBM SRNG
  544. *
  545. * Return: none
  546. */
  547. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  548. {
  549. int idx;
  550. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  551. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  552. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  553. }
  554. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  555. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  556. }
  557. /**
  558. * dp_rx_ipa_uc_detach - free autonomy RX resources
  559. * @soc: data path instance
  560. * @pdev: core txrx pdev context
  561. *
  562. * This function will detach DP RX into main device context
  563. * will free DP Rx resources.
  564. *
  565. * Return: none
  566. */
  567. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  568. {
  569. }
  570. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  571. {
  572. /* TX resource detach */
  573. dp_tx_ipa_uc_detach(soc, pdev);
  574. /* RX resource detach */
  575. dp_rx_ipa_uc_detach(soc, pdev);
  576. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  577. return QDF_STATUS_SUCCESS; /* success */
  578. }
  579. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  580. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  581. /**
  582. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  583. * @soc: data path instance
  584. * @pdev: Physical device handle
  585. *
  586. * Allocate TX buffer from non-cacheable memory
  587. * Attache allocated TX buffers with WBM SRNG
  588. *
  589. * Return: int
  590. */
  591. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  592. {
  593. uint32_t tx_buffer_count;
  594. uint32_t ring_base_align = 8;
  595. void *buffer_vaddr_unaligned;
  596. void *buffer_vaddr;
  597. qdf_dma_addr_t buffer_paddr_unaligned;
  598. qdf_dma_addr_t buffer_paddr;
  599. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  600. uint32_t paddr_lo;
  601. uint32_t paddr_hi;
  602. void *ring_entry;
  603. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  604. int retval = QDF_STATUS_SUCCESS;
  605. /*
  606. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  607. * unsigned int uc_tx_buf_sz =
  608. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  609. */
  610. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  611. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  613. "requested %d buffers to be posted to wbm ring",
  614. ring_size);
  615. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  616. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  617. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  618. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  619. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  620. return -ENOMEM;
  621. }
  622. hal_srng_access_start(soc->hal_soc, wbm_srng);
  623. /* Allocate TX buffers as many as possible */
  624. for (tx_buffer_count = 0;
  625. tx_buffer_count < ring_size; tx_buffer_count++) {
  626. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  627. if (!ring_entry) {
  628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  629. "Failed to get WBM ring entry\n");
  630. goto fail;
  631. }
  632. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  633. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  634. if (!buffer_vaddr_unaligned) {
  635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  636. "IPA WDI TX buffer alloc fail %d allocated\n",
  637. tx_buffer_count);
  638. break;
  639. }
  640. buffer_vaddr = buffer_vaddr_unaligned +
  641. ((unsigned long)buffer_vaddr_unaligned %
  642. ring_base_align);
  643. buffer_paddr = buffer_paddr_unaligned +
  644. ((unsigned long)(buffer_vaddr) -
  645. (unsigned long)buffer_vaddr_unaligned);
  646. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  647. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  648. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  649. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  650. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  651. buffer_vaddr;
  652. }
  653. hal_srng_access_end(soc->hal_soc, wbm_srng);
  654. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  655. return retval;
  656. fail:
  657. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  658. return retval;
  659. }
  660. /**
  661. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  662. * @soc: data path instance
  663. * @pdev: core txrx pdev context
  664. *
  665. * This function will attach a DP RX instance into the main
  666. * device (SOC) context.
  667. *
  668. * Return: QDF_STATUS_SUCCESS: success
  669. * QDF_STATUS_E_RESOURCES: Error return
  670. */
  671. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  672. {
  673. return QDF_STATUS_SUCCESS;
  674. }
  675. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  676. {
  677. int error;
  678. /* TX resource attach */
  679. error = dp_tx_ipa_uc_attach(soc, pdev);
  680. if (error) {
  681. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  682. "DP IPA UC TX attach fail code %d\n", error);
  683. return error;
  684. }
  685. /* RX resource attach */
  686. error = dp_rx_ipa_uc_attach(soc, pdev);
  687. if (error) {
  688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  689. "DP IPA UC RX attach fail code %d\n", error);
  690. dp_tx_ipa_uc_detach(soc, pdev);
  691. return error;
  692. }
  693. return QDF_STATUS_SUCCESS; /* success */
  694. }
  695. #else
  696. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  697. {
  698. return QDF_STATUS_SUCCESS;
  699. }
  700. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  701. {
  702. return QDF_STATUS_SUCCESS;
  703. }
  704. #endif
  705. /* TODO: Need this interface from HIF */
  706. void *hif_get_hal_handle(void *hif_handle);
  707. /*
  708. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  709. * @dp_ctx: DP SOC handle
  710. * @budget: Number of frames/descriptors that can be processed in one shot
  711. *
  712. * Return: remaining budget/quota for the soc device
  713. */
  714. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  715. {
  716. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  717. struct dp_soc *soc = int_ctx->soc;
  718. int ring = 0;
  719. uint32_t work_done = 0;
  720. int budget = dp_budget;
  721. uint8_t tx_mask = int_ctx->tx_ring_mask;
  722. uint8_t rx_mask = int_ctx->rx_ring_mask;
  723. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  724. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  725. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  726. uint32_t remaining_quota = dp_budget;
  727. /* Process Tx completion interrupts first to return back buffers */
  728. while (tx_mask) {
  729. if (tx_mask & 0x1) {
  730. work_done = dp_tx_comp_handler(soc,
  731. soc->tx_comp_ring[ring].hal_srng,
  732. remaining_quota);
  733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  734. "tx mask 0x%x ring %d, budget %d, work_done %d",
  735. tx_mask, ring, budget, work_done);
  736. budget -= work_done;
  737. if (budget <= 0)
  738. goto budget_done;
  739. remaining_quota = budget;
  740. }
  741. tx_mask = tx_mask >> 1;
  742. ring++;
  743. }
  744. /* Process REO Exception ring interrupt */
  745. if (rx_err_mask) {
  746. work_done = dp_rx_err_process(soc,
  747. soc->reo_exception_ring.hal_srng,
  748. remaining_quota);
  749. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  750. "REO Exception Ring: work_done %d budget %d",
  751. work_done, budget);
  752. budget -= work_done;
  753. if (budget <= 0) {
  754. goto budget_done;
  755. }
  756. remaining_quota = budget;
  757. }
  758. /* Process Rx WBM release ring interrupt */
  759. if (rx_wbm_rel_mask) {
  760. work_done = dp_rx_wbm_err_process(soc,
  761. soc->rx_rel_ring.hal_srng, remaining_quota);
  762. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  763. "WBM Release Ring: work_done %d budget %d",
  764. work_done, budget);
  765. budget -= work_done;
  766. if (budget <= 0) {
  767. goto budget_done;
  768. }
  769. remaining_quota = budget;
  770. }
  771. /* Process Rx interrupts */
  772. if (rx_mask) {
  773. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  774. if (rx_mask & (1 << ring)) {
  775. work_done = dp_rx_process(int_ctx,
  776. soc->reo_dest_ring[ring].hal_srng,
  777. remaining_quota);
  778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  779. "rx mask 0x%x ring %d, work_done %d budget %d",
  780. rx_mask, ring, work_done, budget);
  781. budget -= work_done;
  782. if (budget <= 0)
  783. goto budget_done;
  784. remaining_quota = budget;
  785. }
  786. }
  787. }
  788. if (reo_status_mask)
  789. dp_reo_status_ring_handler(soc);
  790. /* Process LMAC interrupts */
  791. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  792. if (soc->pdev_list[ring] == NULL)
  793. continue;
  794. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  795. work_done = dp_mon_process(soc, ring, remaining_quota);
  796. budget -= work_done;
  797. remaining_quota = budget;
  798. }
  799. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  800. work_done = dp_rxdma_err_process(soc, ring,
  801. remaining_quota);
  802. budget -= work_done;
  803. }
  804. }
  805. qdf_lro_flush(int_ctx->lro_ctx);
  806. budget_done:
  807. return dp_budget - budget;
  808. }
  809. #ifdef DP_INTR_POLL_BASED
  810. /* dp_interrupt_timer()- timer poll for interrupts
  811. *
  812. * @arg: SoC Handle
  813. *
  814. * Return:
  815. *
  816. */
  817. static void dp_interrupt_timer(void *arg)
  818. {
  819. struct dp_soc *soc = (struct dp_soc *) arg;
  820. int i;
  821. if (qdf_atomic_read(&soc->cmn_init_done)) {
  822. for (i = 0;
  823. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  824. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  825. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  826. }
  827. }
  828. /*
  829. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  830. * @txrx_soc: DP SOC handle
  831. *
  832. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  833. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  834. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  835. *
  836. * Return: 0 for success. nonzero for failure.
  837. */
  838. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  839. {
  840. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  841. int i;
  842. soc->intr_mode = DP_INTR_POLL;
  843. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  844. soc->intr_ctx[i].dp_intr_id = i;
  845. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  846. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  847. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  848. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  849. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  850. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  851. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  852. soc->intr_ctx[i].soc = soc;
  853. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  854. }
  855. qdf_timer_init(soc->osdev, &soc->int_timer,
  856. dp_interrupt_timer, (void *)soc,
  857. QDF_TIMER_TYPE_WAKE_APPS);
  858. return QDF_STATUS_SUCCESS;
  859. }
  860. #if defined(CONFIG_MCL)
  861. extern int con_mode_monitor;
  862. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  863. /*
  864. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  865. * @txrx_soc: DP SOC handle
  866. *
  867. * Call the appropriate attach function based on the mode of operation.
  868. * This is a WAR for enabling monitor mode.
  869. *
  870. * Return: 0 for success. nonzero for failure.
  871. */
  872. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  873. {
  874. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  875. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  876. con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  877. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  878. "%s: Poll mode", __func__);
  879. return dp_soc_interrupt_attach_poll(txrx_soc);
  880. } else {
  881. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  882. "%s: Interrupt mode", __func__);
  883. return dp_soc_interrupt_attach(txrx_soc);
  884. }
  885. }
  886. #else
  887. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  888. {
  889. return dp_soc_interrupt_attach_poll(txrx_soc);
  890. }
  891. #endif
  892. #endif
  893. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  894. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  895. {
  896. int j;
  897. int num_irq = 0;
  898. int tx_mask =
  899. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  900. int rx_mask =
  901. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  902. int rx_mon_mask =
  903. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  904. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  905. soc->wlan_cfg_ctx, intr_ctx_num);
  906. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  907. soc->wlan_cfg_ctx, intr_ctx_num);
  908. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  909. soc->wlan_cfg_ctx, intr_ctx_num);
  910. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  911. soc->wlan_cfg_ctx, intr_ctx_num);
  912. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  913. if (tx_mask & (1 << j)) {
  914. irq_id_map[num_irq++] =
  915. (wbm2host_tx_completions_ring1 - j);
  916. }
  917. if (rx_mask & (1 << j)) {
  918. irq_id_map[num_irq++] =
  919. (reo2host_destination_ring1 - j);
  920. }
  921. if (rxdma2host_ring_mask & (1 << j)) {
  922. irq_id_map[num_irq++] =
  923. rxdma2host_destination_ring_mac1 -
  924. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  925. }
  926. if (rx_mon_mask & (1 << j)) {
  927. irq_id_map[num_irq++] =
  928. ppdu_end_interrupts_mac1 -
  929. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  930. }
  931. if (rx_wbm_rel_ring_mask & (1 << j))
  932. irq_id_map[num_irq++] = wbm2host_rx_release;
  933. if (rx_err_ring_mask & (1 << j))
  934. irq_id_map[num_irq++] = reo2host_exception;
  935. if (reo_status_ring_mask & (1 << j))
  936. irq_id_map[num_irq++] = reo2host_status;
  937. }
  938. *num_irq_r = num_irq;
  939. }
  940. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  941. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  942. int msi_vector_count, int msi_vector_start)
  943. {
  944. int tx_mask = wlan_cfg_get_tx_ring_mask(
  945. soc->wlan_cfg_ctx, intr_ctx_num);
  946. int rx_mask = wlan_cfg_get_rx_ring_mask(
  947. soc->wlan_cfg_ctx, intr_ctx_num);
  948. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  949. soc->wlan_cfg_ctx, intr_ctx_num);
  950. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  951. soc->wlan_cfg_ctx, intr_ctx_num);
  952. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  953. soc->wlan_cfg_ctx, intr_ctx_num);
  954. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  955. soc->wlan_cfg_ctx, intr_ctx_num);
  956. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  957. soc->wlan_cfg_ctx, intr_ctx_num);
  958. unsigned int vector =
  959. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  960. int num_irq = 0;
  961. soc->intr_mode = DP_INTR_MSI;
  962. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  963. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  964. irq_id_map[num_irq++] =
  965. pld_get_msi_irq(soc->osdev->dev, vector);
  966. *num_irq_r = num_irq;
  967. }
  968. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  969. int *irq_id_map, int *num_irq)
  970. {
  971. int msi_vector_count, ret;
  972. uint32_t msi_base_data, msi_vector_start;
  973. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  974. &msi_vector_count,
  975. &msi_base_data,
  976. &msi_vector_start);
  977. if (ret)
  978. return dp_soc_interrupt_map_calculate_integrated(soc,
  979. intr_ctx_num, irq_id_map, num_irq);
  980. else
  981. dp_soc_interrupt_map_calculate_msi(soc,
  982. intr_ctx_num, irq_id_map, num_irq,
  983. msi_vector_count, msi_vector_start);
  984. }
  985. /*
  986. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  987. * @txrx_soc: DP SOC handle
  988. *
  989. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  990. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  991. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  992. *
  993. * Return: 0 for success. nonzero for failure.
  994. */
  995. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  996. {
  997. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  998. int i = 0;
  999. int num_irq = 0;
  1000. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1001. int ret = 0;
  1002. /* Map of IRQ ids registered with one interrupt context */
  1003. int irq_id_map[HIF_MAX_GRP_IRQ];
  1004. int tx_mask =
  1005. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1006. int rx_mask =
  1007. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1008. int rx_mon_mask =
  1009. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1010. int rx_err_ring_mask =
  1011. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1012. int rx_wbm_rel_ring_mask =
  1013. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1014. int reo_status_ring_mask =
  1015. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1016. int rxdma2host_ring_mask =
  1017. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1018. soc->intr_ctx[i].dp_intr_id = i;
  1019. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1020. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1021. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1022. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1023. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1024. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1025. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1026. soc->intr_ctx[i].soc = soc;
  1027. num_irq = 0;
  1028. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1029. &num_irq);
  1030. ret = hif_register_ext_group(soc->hif_handle,
  1031. num_irq, irq_id_map, dp_service_srngs,
  1032. &soc->intr_ctx[i], "dp_intr",
  1033. HIF_EXEC_NAPI_TYPE, 2);
  1034. if (ret) {
  1035. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1036. FL("failed, ret = %d"), ret);
  1037. return QDF_STATUS_E_FAILURE;
  1038. }
  1039. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1040. }
  1041. hif_configure_ext_group_interrupts(soc->hif_handle);
  1042. return QDF_STATUS_SUCCESS;
  1043. }
  1044. /*
  1045. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1046. * @txrx_soc: DP SOC handle
  1047. *
  1048. * Return: void
  1049. */
  1050. static void dp_soc_interrupt_detach(void *txrx_soc)
  1051. {
  1052. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1053. int i;
  1054. if (soc->intr_mode == DP_INTR_POLL) {
  1055. qdf_timer_stop(&soc->int_timer);
  1056. qdf_timer_free(&soc->int_timer);
  1057. } else {
  1058. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1059. }
  1060. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1061. soc->intr_ctx[i].tx_ring_mask = 0;
  1062. soc->intr_ctx[i].rx_ring_mask = 0;
  1063. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1064. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1065. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1066. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1067. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1068. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1069. }
  1070. }
  1071. #define AVG_MAX_MPDUS_PER_TID 128
  1072. #define AVG_TIDS_PER_CLIENT 2
  1073. #define AVG_FLOWS_PER_TID 2
  1074. #define AVG_MSDUS_PER_FLOW 128
  1075. #define AVG_MSDUS_PER_MPDU 4
  1076. /*
  1077. * Allocate and setup link descriptor pool that will be used by HW for
  1078. * various link and queue descriptors and managed by WBM
  1079. */
  1080. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1081. {
  1082. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1083. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1084. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1085. uint32_t num_mpdus_per_link_desc =
  1086. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1087. uint32_t num_msdus_per_link_desc =
  1088. hal_num_msdus_per_link_desc(soc->hal_soc);
  1089. uint32_t num_mpdu_links_per_queue_desc =
  1090. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1091. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1092. uint32_t total_link_descs, total_mem_size;
  1093. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1094. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1095. uint32_t num_link_desc_banks;
  1096. uint32_t last_bank_size = 0;
  1097. uint32_t entry_size, num_entries;
  1098. int i;
  1099. uint32_t desc_id = 0;
  1100. /* Only Tx queue descriptors are allocated from common link descriptor
  1101. * pool Rx queue descriptors are not included in this because (REO queue
  1102. * extension descriptors) they are expected to be allocated contiguously
  1103. * with REO queue descriptors
  1104. */
  1105. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1106. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1107. num_mpdu_queue_descs = num_mpdu_link_descs /
  1108. num_mpdu_links_per_queue_desc;
  1109. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1110. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1111. num_msdus_per_link_desc;
  1112. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1113. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1114. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1115. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1116. /* Round up to power of 2 */
  1117. total_link_descs = 1;
  1118. while (total_link_descs < num_entries)
  1119. total_link_descs <<= 1;
  1120. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1121. FL("total_link_descs: %u, link_desc_size: %d"),
  1122. total_link_descs, link_desc_size);
  1123. total_mem_size = total_link_descs * link_desc_size;
  1124. total_mem_size += link_desc_align;
  1125. if (total_mem_size <= max_alloc_size) {
  1126. num_link_desc_banks = 0;
  1127. last_bank_size = total_mem_size;
  1128. } else {
  1129. num_link_desc_banks = (total_mem_size) /
  1130. (max_alloc_size - link_desc_align);
  1131. last_bank_size = total_mem_size %
  1132. (max_alloc_size - link_desc_align);
  1133. }
  1134. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1135. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1136. total_mem_size, num_link_desc_banks);
  1137. for (i = 0; i < num_link_desc_banks; i++) {
  1138. soc->link_desc_banks[i].base_vaddr_unaligned =
  1139. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1140. max_alloc_size,
  1141. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1142. soc->link_desc_banks[i].size = max_alloc_size;
  1143. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1144. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1145. ((unsigned long)(
  1146. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1147. link_desc_align));
  1148. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1149. soc->link_desc_banks[i].base_paddr_unaligned) +
  1150. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1151. (unsigned long)(
  1152. soc->link_desc_banks[i].base_vaddr_unaligned));
  1153. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1154. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1155. FL("Link descriptor memory alloc failed"));
  1156. goto fail;
  1157. }
  1158. }
  1159. if (last_bank_size) {
  1160. /* Allocate last bank in case total memory required is not exact
  1161. * multiple of max_alloc_size
  1162. */
  1163. soc->link_desc_banks[i].base_vaddr_unaligned =
  1164. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1165. last_bank_size,
  1166. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1167. soc->link_desc_banks[i].size = last_bank_size;
  1168. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1169. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1170. ((unsigned long)(
  1171. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1172. link_desc_align));
  1173. soc->link_desc_banks[i].base_paddr =
  1174. (unsigned long)(
  1175. soc->link_desc_banks[i].base_paddr_unaligned) +
  1176. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1177. (unsigned long)(
  1178. soc->link_desc_banks[i].base_vaddr_unaligned));
  1179. }
  1180. /* Allocate and setup link descriptor idle list for HW internal use */
  1181. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1182. total_mem_size = entry_size * total_link_descs;
  1183. if (total_mem_size <= max_alloc_size) {
  1184. void *desc;
  1185. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1186. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1187. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1188. FL("Link desc idle ring setup failed"));
  1189. goto fail;
  1190. }
  1191. hal_srng_access_start_unlocked(soc->hal_soc,
  1192. soc->wbm_idle_link_ring.hal_srng);
  1193. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1194. soc->link_desc_banks[i].base_paddr; i++) {
  1195. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1196. ((unsigned long)(
  1197. soc->link_desc_banks[i].base_vaddr) -
  1198. (unsigned long)(
  1199. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1200. / link_desc_size;
  1201. unsigned long paddr = (unsigned long)(
  1202. soc->link_desc_banks[i].base_paddr);
  1203. while (num_entries && (desc = hal_srng_src_get_next(
  1204. soc->hal_soc,
  1205. soc->wbm_idle_link_ring.hal_srng))) {
  1206. hal_set_link_desc_addr(desc,
  1207. LINK_DESC_COOKIE(desc_id, i), paddr);
  1208. num_entries--;
  1209. desc_id++;
  1210. paddr += link_desc_size;
  1211. }
  1212. }
  1213. hal_srng_access_end_unlocked(soc->hal_soc,
  1214. soc->wbm_idle_link_ring.hal_srng);
  1215. } else {
  1216. uint32_t num_scatter_bufs;
  1217. uint32_t num_entries_per_buf;
  1218. uint32_t rem_entries;
  1219. uint8_t *scatter_buf_ptr;
  1220. uint16_t scatter_buf_num;
  1221. soc->wbm_idle_scatter_buf_size =
  1222. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1223. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1224. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1225. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1226. soc->hal_soc, total_mem_size,
  1227. soc->wbm_idle_scatter_buf_size);
  1228. for (i = 0; i < num_scatter_bufs; i++) {
  1229. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1230. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1231. soc->wbm_idle_scatter_buf_size,
  1232. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1233. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1234. QDF_TRACE(QDF_MODULE_ID_DP,
  1235. QDF_TRACE_LEVEL_ERROR,
  1236. FL("Scatter list memory alloc failed"));
  1237. goto fail;
  1238. }
  1239. }
  1240. /* Populate idle list scatter buffers with link descriptor
  1241. * pointers
  1242. */
  1243. scatter_buf_num = 0;
  1244. scatter_buf_ptr = (uint8_t *)(
  1245. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1246. rem_entries = num_entries_per_buf;
  1247. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1248. soc->link_desc_banks[i].base_paddr; i++) {
  1249. uint32_t num_link_descs =
  1250. (soc->link_desc_banks[i].size -
  1251. ((unsigned long)(
  1252. soc->link_desc_banks[i].base_vaddr) -
  1253. (unsigned long)(
  1254. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1255. / link_desc_size;
  1256. unsigned long paddr = (unsigned long)(
  1257. soc->link_desc_banks[i].base_paddr);
  1258. while (num_link_descs) {
  1259. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1260. LINK_DESC_COOKIE(desc_id, i), paddr);
  1261. num_link_descs--;
  1262. desc_id++;
  1263. paddr += link_desc_size;
  1264. rem_entries--;
  1265. if (rem_entries) {
  1266. scatter_buf_ptr += entry_size;
  1267. } else {
  1268. rem_entries = num_entries_per_buf;
  1269. scatter_buf_num++;
  1270. if (scatter_buf_num >= num_scatter_bufs)
  1271. break;
  1272. scatter_buf_ptr = (uint8_t *)(
  1273. soc->wbm_idle_scatter_buf_base_vaddr[
  1274. scatter_buf_num]);
  1275. }
  1276. }
  1277. }
  1278. /* Setup link descriptor idle list in HW */
  1279. hal_setup_link_idle_list(soc->hal_soc,
  1280. soc->wbm_idle_scatter_buf_base_paddr,
  1281. soc->wbm_idle_scatter_buf_base_vaddr,
  1282. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1283. (uint32_t)(scatter_buf_ptr -
  1284. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1285. scatter_buf_num-1])), total_link_descs);
  1286. }
  1287. return 0;
  1288. fail:
  1289. if (soc->wbm_idle_link_ring.hal_srng) {
  1290. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1291. WBM_IDLE_LINK, 0);
  1292. }
  1293. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1294. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1295. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1296. soc->wbm_idle_scatter_buf_size,
  1297. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1298. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1299. }
  1300. }
  1301. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1302. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1303. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1304. soc->link_desc_banks[i].size,
  1305. soc->link_desc_banks[i].base_vaddr_unaligned,
  1306. soc->link_desc_banks[i].base_paddr_unaligned,
  1307. 0);
  1308. }
  1309. }
  1310. return QDF_STATUS_E_FAILURE;
  1311. }
  1312. /*
  1313. * Free link descriptor pool that was setup HW
  1314. */
  1315. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1316. {
  1317. int i;
  1318. if (soc->wbm_idle_link_ring.hal_srng) {
  1319. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1320. WBM_IDLE_LINK, 0);
  1321. }
  1322. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1323. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1324. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1325. soc->wbm_idle_scatter_buf_size,
  1326. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1327. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1328. }
  1329. }
  1330. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1331. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1332. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1333. soc->link_desc_banks[i].size,
  1334. soc->link_desc_banks[i].base_vaddr_unaligned,
  1335. soc->link_desc_banks[i].base_paddr_unaligned,
  1336. 0);
  1337. }
  1338. }
  1339. }
  1340. /* TODO: Following should be configurable */
  1341. #define WBM_RELEASE_RING_SIZE 64
  1342. #define TCL_CMD_RING_SIZE 32
  1343. #define TCL_STATUS_RING_SIZE 32
  1344. #if defined(QCA_WIFI_QCA6290)
  1345. #define REO_DST_RING_SIZE 1024
  1346. #else
  1347. #define REO_DST_RING_SIZE 2048
  1348. #endif
  1349. #define REO_REINJECT_RING_SIZE 32
  1350. #define RX_RELEASE_RING_SIZE 1024
  1351. #define REO_EXCEPTION_RING_SIZE 128
  1352. #define REO_CMD_RING_SIZE 32
  1353. #define REO_STATUS_RING_SIZE 32
  1354. #define RXDMA_BUF_RING_SIZE 1024
  1355. #define RXDMA_REFILL_RING_SIZE 2048
  1356. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1357. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1358. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1359. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1360. #define RXDMA_ERR_DST_RING_SIZE 1024
  1361. /*
  1362. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1363. * @soc: Datapath SOC handle
  1364. *
  1365. * This is a timer function used to age out stale WDS nodes from
  1366. * AST table
  1367. */
  1368. #ifdef FEATURE_WDS
  1369. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1370. {
  1371. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1372. struct dp_pdev *pdev;
  1373. struct dp_vdev *vdev;
  1374. struct dp_peer *peer;
  1375. struct dp_ast_entry *ase, *temp_ase;
  1376. int i;
  1377. qdf_spin_lock_bh(&soc->ast_lock);
  1378. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1379. pdev = soc->pdev_list[i];
  1380. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1381. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1382. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1383. /*
  1384. * Do not expire static ast entries
  1385. */
  1386. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1387. continue;
  1388. if (ase->is_active) {
  1389. ase->is_active = FALSE;
  1390. continue;
  1391. }
  1392. DP_STATS_INC(soc, ast.aged_out, 1);
  1393. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1394. pdev->osif_pdev,
  1395. ase->mac_addr.raw);
  1396. dp_peer_del_ast(soc, ase);
  1397. }
  1398. }
  1399. }
  1400. }
  1401. qdf_spin_unlock_bh(&soc->ast_lock);
  1402. if (qdf_atomic_read(&soc->cmn_init_done))
  1403. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1404. }
  1405. /*
  1406. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1407. * @soc: Datapath SOC handle
  1408. *
  1409. * Return: None
  1410. */
  1411. static void dp_soc_wds_attach(struct dp_soc *soc)
  1412. {
  1413. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1414. dp_wds_aging_timer_fn, (void *)soc,
  1415. QDF_TIMER_TYPE_WAKE_APPS);
  1416. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1417. }
  1418. /*
  1419. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1420. * @txrx_soc: DP SOC handle
  1421. *
  1422. * Return: None
  1423. */
  1424. static void dp_soc_wds_detach(struct dp_soc *soc)
  1425. {
  1426. qdf_timer_stop(&soc->wds_aging_timer);
  1427. qdf_timer_free(&soc->wds_aging_timer);
  1428. }
  1429. #else
  1430. static void dp_soc_wds_attach(struct dp_soc *soc)
  1431. {
  1432. }
  1433. static void dp_soc_wds_detach(struct dp_soc *soc)
  1434. {
  1435. }
  1436. #endif
  1437. /*
  1438. * dp_soc_reset_ring_map() - Reset cpu ring map
  1439. * @soc: Datapath soc handler
  1440. *
  1441. * This api resets the default cpu ring map
  1442. */
  1443. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1444. {
  1445. uint8_t i;
  1446. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1447. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1448. if (nss_config == 1) {
  1449. /*
  1450. * Setting Tx ring map for one nss offloaded radio
  1451. */
  1452. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1453. } else if (nss_config == 2) {
  1454. /*
  1455. * Setting Tx ring for two nss offloaded radios
  1456. */
  1457. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1458. } else {
  1459. /*
  1460. * Setting Tx ring map for all nss offloaded radios
  1461. */
  1462. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1463. }
  1464. }
  1465. }
  1466. /*
  1467. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1468. * @dp_soc - DP soc handle
  1469. * @ring_type - ring type
  1470. * @ring_num - ring_num
  1471. *
  1472. * return 0 or 1
  1473. */
  1474. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1475. {
  1476. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1477. uint8_t status = 0;
  1478. switch (ring_type) {
  1479. case WBM2SW_RELEASE:
  1480. case REO_DST:
  1481. status = ((nss_config) & (1 << ring_num));
  1482. break;
  1483. default:
  1484. break;
  1485. }
  1486. return status;
  1487. }
  1488. /*
  1489. * dp_soc_reset_intr_mask() - reset interrupt mask
  1490. * @dp_soc - DP Soc handle
  1491. *
  1492. * Return: Return void
  1493. */
  1494. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1495. {
  1496. uint8_t j;
  1497. int *grp_mask = NULL;
  1498. int group_number, mask, num_ring;
  1499. /* number of tx ring */
  1500. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1501. /*
  1502. * group mask for tx completion ring.
  1503. */
  1504. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1505. /* loop and reset the mask for only offloaded ring */
  1506. for (j = 0; j < num_ring; j++) {
  1507. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1508. continue;
  1509. }
  1510. /*
  1511. * Group number corresponding to tx offloaded ring.
  1512. */
  1513. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1514. if (group_number < 0) {
  1515. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1516. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1517. WBM2SW_RELEASE, j);
  1518. return;
  1519. }
  1520. /* reset the tx mask for offloaded ring */
  1521. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1522. mask &= (~(1 << j));
  1523. /*
  1524. * reset the interrupt mask for offloaded ring.
  1525. */
  1526. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1527. }
  1528. /* number of rx rings */
  1529. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1530. /*
  1531. * group mask for reo destination ring.
  1532. */
  1533. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1534. /* loop and reset the mask for only offloaded ring */
  1535. for (j = 0; j < num_ring; j++) {
  1536. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1537. continue;
  1538. }
  1539. /*
  1540. * Group number corresponding to rx offloaded ring.
  1541. */
  1542. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1543. if (group_number < 0) {
  1544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1545. FL("ring not part of an group; ring_type: %d,ring_num %d"),
  1546. REO_DST, j);
  1547. return;
  1548. }
  1549. /* set the interrupt mask for offloaded ring */
  1550. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1551. mask &= (~(1 << j));
  1552. /*
  1553. * set the interrupt mask to zero for rx offloaded radio.
  1554. */
  1555. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1556. }
  1557. }
  1558. #ifdef IPA_OFFLOAD
  1559. /**
  1560. * dp_reo_remap_config() - configure reo remap register value based
  1561. * nss configuration.
  1562. * based on offload_radio value below remap configuration
  1563. * get applied.
  1564. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1565. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1566. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1567. * 3 - both Radios handled by NSS (remap not required)
  1568. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1569. *
  1570. * @remap1: output parameter indicates reo remap 1 register value
  1571. * @remap2: output parameter indicates reo remap 2 register value
  1572. * Return: bool type, true if remap is configured else false.
  1573. */
  1574. static bool dp_reo_remap_config(struct dp_soc *soc,
  1575. uint32_t *remap1,
  1576. uint32_t *remap2)
  1577. {
  1578. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1579. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1580. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1581. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1582. return true;
  1583. }
  1584. #else
  1585. static bool dp_reo_remap_config(struct dp_soc *soc,
  1586. uint32_t *remap1,
  1587. uint32_t *remap2)
  1588. {
  1589. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1590. switch (offload_radio) {
  1591. case 0:
  1592. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1593. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1594. (0x3 << 18) | (0x4 << 21)) << 8;
  1595. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1596. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1597. (0x3 << 18) | (0x4 << 21)) << 8;
  1598. break;
  1599. case 1:
  1600. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1601. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1602. (0x2 << 18) | (0x3 << 21)) << 8;
  1603. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1604. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1605. (0x4 << 18) | (0x2 << 21)) << 8;
  1606. break;
  1607. case 2:
  1608. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1609. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1610. (0x1 << 18) | (0x3 << 21)) << 8;
  1611. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1612. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1613. (0x4 << 18) | (0x1 << 21)) << 8;
  1614. break;
  1615. case 3:
  1616. /* return false if both radios are offloaded to NSS */
  1617. return false;
  1618. }
  1619. return true;
  1620. }
  1621. #endif
  1622. /*
  1623. * dp_soc_cmn_setup() - Common SoC level initializion
  1624. * @soc: Datapath SOC handle
  1625. *
  1626. * This is an internal function used to setup common SOC data structures,
  1627. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1628. */
  1629. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1630. {
  1631. int i;
  1632. struct hal_reo_params reo_params;
  1633. int tx_ring_size;
  1634. int tx_comp_ring_size;
  1635. if (qdf_atomic_read(&soc->cmn_init_done))
  1636. return 0;
  1637. if (dp_peer_find_attach(soc))
  1638. goto fail0;
  1639. if (dp_hw_link_desc_pool_setup(soc))
  1640. goto fail1;
  1641. /* Setup SRNG rings */
  1642. /* Common rings */
  1643. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1644. WBM_RELEASE_RING_SIZE)) {
  1645. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1646. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1647. goto fail1;
  1648. }
  1649. soc->num_tcl_data_rings = 0;
  1650. /* Tx data rings */
  1651. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1652. soc->num_tcl_data_rings =
  1653. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1654. tx_comp_ring_size =
  1655. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1656. tx_ring_size =
  1657. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1658. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1659. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1660. TCL_DATA, i, 0, tx_ring_size)) {
  1661. QDF_TRACE(QDF_MODULE_ID_DP,
  1662. QDF_TRACE_LEVEL_ERROR,
  1663. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1664. goto fail1;
  1665. }
  1666. /*
  1667. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1668. * count
  1669. */
  1670. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1671. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1672. QDF_TRACE(QDF_MODULE_ID_DP,
  1673. QDF_TRACE_LEVEL_ERROR,
  1674. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1675. goto fail1;
  1676. }
  1677. }
  1678. } else {
  1679. /* This will be incremented during per pdev ring setup */
  1680. soc->num_tcl_data_rings = 0;
  1681. }
  1682. if (dp_tx_soc_attach(soc)) {
  1683. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1684. FL("dp_tx_soc_attach failed"));
  1685. goto fail1;
  1686. }
  1687. /* TCL command and status rings */
  1688. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1689. TCL_CMD_RING_SIZE)) {
  1690. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1691. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1692. goto fail1;
  1693. }
  1694. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1695. TCL_STATUS_RING_SIZE)) {
  1696. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1697. FL("dp_srng_setup failed for tcl_status_ring"));
  1698. goto fail1;
  1699. }
  1700. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1701. * descriptors
  1702. */
  1703. /* Rx data rings */
  1704. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1705. soc->num_reo_dest_rings =
  1706. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1707. QDF_TRACE(QDF_MODULE_ID_DP,
  1708. QDF_TRACE_LEVEL_ERROR,
  1709. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1710. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1711. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1712. i, 0, REO_DST_RING_SIZE)) {
  1713. QDF_TRACE(QDF_MODULE_ID_DP,
  1714. QDF_TRACE_LEVEL_ERROR,
  1715. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1716. goto fail1;
  1717. }
  1718. }
  1719. } else {
  1720. /* This will be incremented during per pdev ring setup */
  1721. soc->num_reo_dest_rings = 0;
  1722. }
  1723. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1724. /* REO reinjection ring */
  1725. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1726. REO_REINJECT_RING_SIZE)) {
  1727. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1728. FL("dp_srng_setup failed for reo_reinject_ring"));
  1729. goto fail1;
  1730. }
  1731. /* Rx release ring */
  1732. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1733. RX_RELEASE_RING_SIZE)) {
  1734. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1735. FL("dp_srng_setup failed for rx_rel_ring"));
  1736. goto fail1;
  1737. }
  1738. /* Rx exception ring */
  1739. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1740. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1741. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1742. FL("dp_srng_setup failed for reo_exception_ring"));
  1743. goto fail1;
  1744. }
  1745. /* REO command and status rings */
  1746. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1747. REO_CMD_RING_SIZE)) {
  1748. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1749. FL("dp_srng_setup failed for reo_cmd_ring"));
  1750. goto fail1;
  1751. }
  1752. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1753. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1754. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1755. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1756. REO_STATUS_RING_SIZE)) {
  1757. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1758. FL("dp_srng_setup failed for reo_status_ring"));
  1759. goto fail1;
  1760. }
  1761. qdf_spinlock_create(&soc->ast_lock);
  1762. dp_soc_wds_attach(soc);
  1763. /* Reset the cpu ring map if radio is NSS offloaded */
  1764. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1765. dp_soc_reset_cpu_ring_map(soc);
  1766. dp_soc_reset_intr_mask(soc);
  1767. }
  1768. /* Setup HW REO */
  1769. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1770. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1771. /*
  1772. * Reo ring remap is not required if both radios
  1773. * are offloaded to NSS
  1774. */
  1775. if (!dp_reo_remap_config(soc,
  1776. &reo_params.remap1,
  1777. &reo_params.remap2))
  1778. goto out;
  1779. reo_params.rx_hash_enabled = true;
  1780. }
  1781. out:
  1782. hal_reo_setup(soc->hal_soc, &reo_params);
  1783. qdf_atomic_set(&soc->cmn_init_done, 1);
  1784. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1785. return 0;
  1786. fail1:
  1787. /*
  1788. * Cleanup will be done as part of soc_detach, which will
  1789. * be called on pdev attach failure
  1790. */
  1791. fail0:
  1792. return QDF_STATUS_E_FAILURE;
  1793. }
  1794. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1795. static void dp_lro_hash_setup(struct dp_soc *soc)
  1796. {
  1797. struct cdp_lro_hash_config lro_hash;
  1798. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1799. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1800. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1801. FL("LRO disabled RX hash disabled"));
  1802. return;
  1803. }
  1804. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1805. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1806. lro_hash.lro_enable = 1;
  1807. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1808. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1809. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1810. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1811. }
  1812. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW, FL("enabled"));
  1813. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1814. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1815. LRO_IPV4_SEED_ARR_SZ));
  1816. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1817. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1818. LRO_IPV6_SEED_ARR_SZ));
  1819. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  1820. "lro_hash: lro_enable: 0x%x tcp_flag 0x%x tcp_flag_mask 0x%x",
  1821. lro_hash.lro_enable, lro_hash.tcp_flag,
  1822. lro_hash.tcp_flag_mask);
  1823. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1824. QDF_TRACE_LEVEL_ERROR,
  1825. (void *)lro_hash.toeplitz_hash_ipv4,
  1826. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1827. LRO_IPV4_SEED_ARR_SZ));
  1828. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1829. QDF_TRACE_LEVEL_ERROR,
  1830. (void *)lro_hash.toeplitz_hash_ipv6,
  1831. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1832. LRO_IPV6_SEED_ARR_SZ));
  1833. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1834. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1835. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1836. (soc->osif_soc, &lro_hash);
  1837. }
  1838. /*
  1839. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1840. * @soc: data path SoC handle
  1841. * @pdev: Physical device handle
  1842. *
  1843. * Return: 0 - success, > 0 - failure
  1844. */
  1845. #ifdef QCA_HOST2FW_RXBUF_RING
  1846. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1847. struct dp_pdev *pdev)
  1848. {
  1849. int max_mac_rings =
  1850. wlan_cfg_get_num_mac_rings
  1851. (pdev->wlan_cfg_ctx);
  1852. int i;
  1853. for (i = 0; i < max_mac_rings; i++) {
  1854. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1855. "%s: pdev_id %d mac_id %d\n",
  1856. __func__, pdev->pdev_id, i);
  1857. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1858. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1859. QDF_TRACE(QDF_MODULE_ID_DP,
  1860. QDF_TRACE_LEVEL_ERROR,
  1861. FL("failed rx mac ring setup"));
  1862. return QDF_STATUS_E_FAILURE;
  1863. }
  1864. }
  1865. return QDF_STATUS_SUCCESS;
  1866. }
  1867. #else
  1868. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1869. struct dp_pdev *pdev)
  1870. {
  1871. return QDF_STATUS_SUCCESS;
  1872. }
  1873. #endif
  1874. /**
  1875. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1876. * @pdev - DP_PDEV handle
  1877. *
  1878. * Return: void
  1879. */
  1880. static inline void
  1881. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1882. {
  1883. uint8_t map_id;
  1884. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1885. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1886. sizeof(default_dscp_tid_map));
  1887. }
  1888. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1889. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1890. pdev->dscp_tid_map[map_id],
  1891. map_id);
  1892. }
  1893. }
  1894. /*
  1895. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1896. * @soc: data path SoC handle
  1897. *
  1898. * Return: none
  1899. */
  1900. #ifdef IPA_OFFLOAD
  1901. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1902. struct dp_pdev *pdev)
  1903. {
  1904. void *hal_srng;
  1905. struct hal_srng_params srng_params;
  1906. qdf_dma_addr_t hp_addr, tp_addr;
  1907. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1908. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1909. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1910. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1911. srng_params.ring_base_paddr;
  1912. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1913. srng_params.ring_base_vaddr;
  1914. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1915. srng_params.num_entries * srng_params.entry_size;
  1916. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1917. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1918. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1919. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1920. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1921. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1922. srng_params.ring_base_paddr;
  1923. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1924. srng_params.ring_base_vaddr;
  1925. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1926. srng_params.num_entries * srng_params.entry_size;
  1927. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1928. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1929. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1930. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1931. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1932. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1933. srng_params.ring_base_paddr;
  1934. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1935. srng_params.ring_base_vaddr;
  1936. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1937. srng_params.num_entries * srng_params.entry_size;
  1938. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1939. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1940. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1941. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1942. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1943. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1944. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1945. __func__);
  1946. return -EFAULT;
  1947. }
  1948. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1949. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1950. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1951. srng_params.ring_base_paddr;
  1952. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1953. srng_params.ring_base_vaddr;
  1954. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1955. srng_params.num_entries * srng_params.entry_size;
  1956. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1957. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1958. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1959. "%s: ring_base_paddr:%pK, ring_base_vaddr:%pK"
  1960. "_entries:%d, hp_addr:%pK\n",
  1961. __func__,
  1962. (void *)srng_params.ring_base_paddr,
  1963. (void *)srng_params.ring_base_vaddr,
  1964. srng_params.num_entries,
  1965. (void *)hp_addr);
  1966. return 0;
  1967. }
  1968. #else
  1969. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1970. struct dp_pdev *pdev)
  1971. {
  1972. return 0;
  1973. }
  1974. #endif
  1975. /*
  1976. * dp_pdev_attach_wifi3() - attach txrx pdev
  1977. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1978. * @txrx_soc: Datapath SOC handle
  1979. * @htc_handle: HTC handle for host-target interface
  1980. * @qdf_osdev: QDF OS device
  1981. * @pdev_id: PDEV ID
  1982. *
  1983. * Return: DP PDEV handle on success, NULL on failure
  1984. */
  1985. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1986. struct cdp_cfg *ctrl_pdev,
  1987. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1988. {
  1989. int tx_ring_size;
  1990. int tx_comp_ring_size;
  1991. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1992. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1993. if (!pdev) {
  1994. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1995. FL("DP PDEV memory allocation failed"));
  1996. goto fail0;
  1997. }
  1998. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1999. if (!pdev->wlan_cfg_ctx) {
  2000. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2001. FL("pdev cfg_attach failed"));
  2002. qdf_mem_free(pdev);
  2003. goto fail0;
  2004. }
  2005. /*
  2006. * set nss pdev config based on soc config
  2007. */
  2008. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  2009. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  2010. pdev->soc = soc;
  2011. pdev->osif_pdev = ctrl_pdev;
  2012. pdev->pdev_id = pdev_id;
  2013. soc->pdev_list[pdev_id] = pdev;
  2014. soc->pdev_count++;
  2015. TAILQ_INIT(&pdev->vdev_list);
  2016. pdev->vdev_count = 0;
  2017. qdf_spinlock_create(&pdev->tx_mutex);
  2018. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  2019. TAILQ_INIT(&pdev->neighbour_peers_list);
  2020. if (dp_soc_cmn_setup(soc)) {
  2021. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2022. FL("dp_soc_cmn_setup failed"));
  2023. goto fail1;
  2024. }
  2025. /* Setup per PDEV TCL rings if configured */
  2026. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2027. tx_ring_size =
  2028. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2029. tx_comp_ring_size =
  2030. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  2031. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  2032. pdev_id, pdev_id, tx_ring_size)) {
  2033. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2034. FL("dp_srng_setup failed for tcl_data_ring"));
  2035. goto fail1;
  2036. }
  2037. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  2038. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  2039. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2040. FL("dp_srng_setup failed for tx_comp_ring"));
  2041. goto fail1;
  2042. }
  2043. soc->num_tcl_data_rings++;
  2044. }
  2045. /* Tx specific init */
  2046. if (dp_tx_pdev_attach(pdev)) {
  2047. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2048. FL("dp_tx_pdev_attach failed"));
  2049. goto fail1;
  2050. }
  2051. /* Setup per PDEV REO rings if configured */
  2052. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2053. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  2054. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  2055. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2056. FL("dp_srng_setup failed for reo_dest_ringn"));
  2057. goto fail1;
  2058. }
  2059. soc->num_reo_dest_rings++;
  2060. }
  2061. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  2062. RXDMA_REFILL_RING_SIZE)) {
  2063. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2064. FL("dp_srng_setup failed rx refill ring"));
  2065. goto fail1;
  2066. }
  2067. if (dp_rxdma_ring_setup(soc, pdev)) {
  2068. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2069. FL("RXDMA ring config failed"));
  2070. goto fail1;
  2071. }
  2072. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  2073. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  2074. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2075. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  2076. goto fail1;
  2077. }
  2078. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  2079. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  2080. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2081. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2082. goto fail1;
  2083. }
  2084. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2085. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2086. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2087. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2088. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2089. goto fail1;
  2090. }
  2091. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2092. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2093. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2094. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2095. goto fail1;
  2096. }
  2097. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2098. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2099. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2100. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2101. goto fail1;
  2102. }
  2103. if (dp_ipa_ring_resource_setup(soc, pdev))
  2104. goto fail1;
  2105. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2106. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2107. "%s: dp_ipa_uc_attach failed\n", __func__);
  2108. goto fail1;
  2109. }
  2110. /* Rx specific init */
  2111. if (dp_rx_pdev_attach(pdev)) {
  2112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2113. FL("dp_rx_pdev_attach failed "));
  2114. goto fail0;
  2115. }
  2116. DP_STATS_INIT(pdev);
  2117. #ifndef CONFIG_WIN
  2118. /* MCL */
  2119. dp_local_peer_id_pool_init(pdev);
  2120. #endif
  2121. dp_dscp_tid_map_setup(pdev);
  2122. /* Rx monitor mode specific init */
  2123. if (dp_rx_pdev_mon_attach(pdev)) {
  2124. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2125. "dp_rx_pdev_attach failed\n");
  2126. goto fail1;
  2127. }
  2128. if (dp_wdi_event_attach(pdev)) {
  2129. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2130. "dp_wdi_evet_attach failed\n");
  2131. goto fail1;
  2132. }
  2133. /* set the reo destination during initialization */
  2134. pdev->reo_dest = pdev->pdev_id + 1;
  2135. return (struct cdp_pdev *)pdev;
  2136. fail1:
  2137. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2138. fail0:
  2139. return NULL;
  2140. }
  2141. /*
  2142. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2143. * @soc: data path SoC handle
  2144. * @pdev: Physical device handle
  2145. *
  2146. * Return: void
  2147. */
  2148. #ifdef QCA_HOST2FW_RXBUF_RING
  2149. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2150. struct dp_pdev *pdev)
  2151. {
  2152. int max_mac_rings =
  2153. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2154. int i;
  2155. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2156. max_mac_rings : MAX_RX_MAC_RINGS;
  2157. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2158. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2159. RXDMA_BUF, 1);
  2160. }
  2161. #else
  2162. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2163. struct dp_pdev *pdev)
  2164. {
  2165. }
  2166. #endif
  2167. /*
  2168. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2169. * @pdev: device object
  2170. *
  2171. * Return: void
  2172. */
  2173. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2174. {
  2175. struct dp_neighbour_peer *peer = NULL;
  2176. struct dp_neighbour_peer *temp_peer = NULL;
  2177. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2178. neighbour_peer_list_elem, temp_peer) {
  2179. /* delete this peer from the list */
  2180. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2181. peer, neighbour_peer_list_elem);
  2182. qdf_mem_free(peer);
  2183. }
  2184. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2185. }
  2186. /*
  2187. * dp_pdev_detach_wifi3() - detach txrx pdev
  2188. * @txrx_pdev: Datapath PDEV handle
  2189. * @force: Force detach
  2190. *
  2191. */
  2192. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2193. {
  2194. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2195. struct dp_soc *soc = pdev->soc;
  2196. dp_wdi_event_detach(pdev);
  2197. dp_tx_pdev_detach(pdev);
  2198. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2199. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2200. TCL_DATA, pdev->pdev_id);
  2201. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2202. WBM2SW_RELEASE, pdev->pdev_id);
  2203. }
  2204. dp_rx_pdev_detach(pdev);
  2205. dp_rx_pdev_mon_detach(pdev);
  2206. dp_neighbour_peers_detach(pdev);
  2207. qdf_spinlock_destroy(&pdev->tx_mutex);
  2208. dp_ipa_uc_detach(soc, pdev);
  2209. /* Cleanup per PDEV REO rings if configured */
  2210. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2211. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2212. REO_DST, pdev->pdev_id);
  2213. }
  2214. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2215. dp_rxdma_ring_cleanup(soc, pdev);
  2216. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2217. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2218. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2219. RXDMA_MONITOR_STATUS, 0);
  2220. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2221. RXDMA_MONITOR_DESC, 0);
  2222. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2223. soc->pdev_list[pdev->pdev_id] = NULL;
  2224. soc->pdev_count--;
  2225. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2226. qdf_mem_free(pdev);
  2227. }
  2228. /*
  2229. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2230. * @soc: DP SOC handle
  2231. */
  2232. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2233. {
  2234. struct reo_desc_list_node *desc;
  2235. struct dp_rx_tid *rx_tid;
  2236. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2237. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2238. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2239. rx_tid = &desc->rx_tid;
  2240. qdf_mem_unmap_nbytes_single(soc->osdev,
  2241. rx_tid->hw_qdesc_paddr,
  2242. QDF_DMA_BIDIRECTIONAL,
  2243. rx_tid->hw_qdesc_alloc_size);
  2244. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2245. qdf_mem_free(desc);
  2246. }
  2247. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2248. qdf_list_destroy(&soc->reo_desc_freelist);
  2249. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2250. }
  2251. /*
  2252. * dp_soc_detach_wifi3() - Detach txrx SOC
  2253. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2254. */
  2255. static void dp_soc_detach_wifi3(void *txrx_soc)
  2256. {
  2257. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2258. int i;
  2259. qdf_atomic_set(&soc->cmn_init_done, 0);
  2260. qdf_flush_work(&soc->htt_stats.work);
  2261. qdf_disable_work(&soc->htt_stats.work);
  2262. /* Free pending htt stats messages */
  2263. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2264. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2265. if (soc->pdev_list[i])
  2266. dp_pdev_detach_wifi3(
  2267. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2268. }
  2269. dp_peer_find_detach(soc);
  2270. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2271. * SW descriptors
  2272. */
  2273. /* Free the ring memories */
  2274. /* Common rings */
  2275. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2276. dp_tx_soc_detach(soc);
  2277. /* Tx data rings */
  2278. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2279. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2280. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2281. TCL_DATA, i);
  2282. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2283. WBM2SW_RELEASE, i);
  2284. }
  2285. }
  2286. /* TCL command and status rings */
  2287. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2288. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2289. /* Rx data rings */
  2290. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2291. soc->num_reo_dest_rings =
  2292. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2293. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2294. /* TODO: Get number of rings and ring sizes
  2295. * from wlan_cfg
  2296. */
  2297. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2298. REO_DST, i);
  2299. }
  2300. }
  2301. /* REO reinjection ring */
  2302. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2303. /* Rx release ring */
  2304. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2305. /* Rx exception ring */
  2306. /* TODO: Better to store ring_type and ring_num in
  2307. * dp_srng during setup
  2308. */
  2309. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2310. /* REO command and status rings */
  2311. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2312. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2313. dp_hw_link_desc_pool_cleanup(soc);
  2314. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2315. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2316. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2317. htt_soc_detach(soc->htt_handle);
  2318. dp_reo_cmdlist_destroy(soc);
  2319. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2320. dp_reo_desc_freelist_destroy(soc);
  2321. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2322. dp_soc_wds_detach(soc);
  2323. qdf_spinlock_destroy(&soc->ast_lock);
  2324. qdf_mem_free(soc);
  2325. }
  2326. /*
  2327. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2328. * @soc: data path SoC handle
  2329. * @pdev: physical device handle
  2330. *
  2331. * Return: void
  2332. */
  2333. #ifdef IPA_OFFLOAD
  2334. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2335. struct dp_pdev *pdev)
  2336. {
  2337. htt_srng_setup(soc->htt_handle, 0,
  2338. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2339. }
  2340. #else
  2341. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2342. struct dp_pdev *pdev)
  2343. {
  2344. }
  2345. #endif
  2346. /*
  2347. * dp_rxdma_ring_config() - configure the RX DMA rings
  2348. *
  2349. * This function is used to configure the MAC rings.
  2350. * On MCL host provides buffers in Host2FW ring
  2351. * FW refills (copies) buffers to the ring and updates
  2352. * ring_idx in register
  2353. *
  2354. * @soc: data path SoC handle
  2355. *
  2356. * Return: void
  2357. */
  2358. #ifdef QCA_HOST2FW_RXBUF_RING
  2359. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2360. {
  2361. int i;
  2362. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2363. struct dp_pdev *pdev = soc->pdev_list[i];
  2364. if (pdev) {
  2365. int mac_id = 0;
  2366. int j;
  2367. bool dbs_enable = 0;
  2368. int max_mac_rings =
  2369. wlan_cfg_get_num_mac_rings
  2370. (pdev->wlan_cfg_ctx);
  2371. htt_srng_setup(soc->htt_handle, 0,
  2372. pdev->rx_refill_buf_ring.hal_srng,
  2373. RXDMA_BUF);
  2374. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2375. if (soc->cdp_soc.ol_ops->
  2376. is_hw_dbs_2x2_capable) {
  2377. dbs_enable = soc->cdp_soc.ol_ops->
  2378. is_hw_dbs_2x2_capable(soc->psoc);
  2379. }
  2380. if (dbs_enable) {
  2381. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2382. QDF_TRACE_LEVEL_ERROR,
  2383. FL("DBS enabled max_mac_rings %d\n"),
  2384. max_mac_rings);
  2385. } else {
  2386. max_mac_rings = 1;
  2387. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2388. QDF_TRACE_LEVEL_ERROR,
  2389. FL("DBS disabled, max_mac_rings %d\n"),
  2390. max_mac_rings);
  2391. }
  2392. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2393. FL("pdev_id %d max_mac_rings %d\n"),
  2394. pdev->pdev_id, max_mac_rings);
  2395. for (j = 0; j < max_mac_rings; j++) {
  2396. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2397. QDF_TRACE_LEVEL_ERROR,
  2398. FL("mac_id %d\n"), mac_id);
  2399. htt_srng_setup(soc->htt_handle, mac_id,
  2400. pdev->rx_mac_buf_ring[j]
  2401. .hal_srng,
  2402. RXDMA_BUF);
  2403. mac_id++;
  2404. }
  2405. /* Configure monitor mode rings */
  2406. htt_srng_setup(soc->htt_handle, i,
  2407. pdev->rxdma_mon_buf_ring.hal_srng,
  2408. RXDMA_MONITOR_BUF);
  2409. htt_srng_setup(soc->htt_handle, i,
  2410. pdev->rxdma_mon_dst_ring.hal_srng,
  2411. RXDMA_MONITOR_DST);
  2412. htt_srng_setup(soc->htt_handle, i,
  2413. pdev->rxdma_mon_status_ring.hal_srng,
  2414. RXDMA_MONITOR_STATUS);
  2415. htt_srng_setup(soc->htt_handle, i,
  2416. pdev->rxdma_mon_desc_ring.hal_srng,
  2417. RXDMA_MONITOR_DESC);
  2418. htt_srng_setup(soc->htt_handle, i,
  2419. pdev->rxdma_err_dst_ring.hal_srng,
  2420. RXDMA_DST);
  2421. }
  2422. }
  2423. }
  2424. #else
  2425. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2426. {
  2427. int i;
  2428. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2429. struct dp_pdev *pdev = soc->pdev_list[i];
  2430. if (pdev) {
  2431. htt_srng_setup(soc->htt_handle, i,
  2432. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2433. htt_srng_setup(soc->htt_handle, i,
  2434. pdev->rxdma_mon_buf_ring.hal_srng,
  2435. RXDMA_MONITOR_BUF);
  2436. htt_srng_setup(soc->htt_handle, i,
  2437. pdev->rxdma_mon_dst_ring.hal_srng,
  2438. RXDMA_MONITOR_DST);
  2439. htt_srng_setup(soc->htt_handle, i,
  2440. pdev->rxdma_mon_status_ring.hal_srng,
  2441. RXDMA_MONITOR_STATUS);
  2442. htt_srng_setup(soc->htt_handle, i,
  2443. pdev->rxdma_mon_desc_ring.hal_srng,
  2444. RXDMA_MONITOR_DESC);
  2445. htt_srng_setup(soc->htt_handle, i,
  2446. pdev->rxdma_err_dst_ring.hal_srng,
  2447. RXDMA_DST);
  2448. }
  2449. }
  2450. }
  2451. #endif
  2452. /*
  2453. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2454. * @txrx_soc: Datapath SOC handle
  2455. */
  2456. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2457. {
  2458. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2459. htt_soc_attach_target(soc->htt_handle);
  2460. dp_rxdma_ring_config(soc);
  2461. DP_STATS_INIT(soc);
  2462. /* initialize work queue for stats processing */
  2463. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2464. return 0;
  2465. }
  2466. /*
  2467. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2468. * @txrx_soc: Datapath SOC handle
  2469. */
  2470. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2471. {
  2472. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2473. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2474. }
  2475. /*
  2476. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2477. * @txrx_soc: Datapath SOC handle
  2478. * @nss_cfg: nss config
  2479. */
  2480. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2481. {
  2482. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2483. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2484. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2485. FL("nss-wifi<0> nss config is enabled"));
  2486. }
  2487. /*
  2488. * dp_vdev_attach_wifi3() - attach txrx vdev
  2489. * @txrx_pdev: Datapath PDEV handle
  2490. * @vdev_mac_addr: MAC address of the virtual interface
  2491. * @vdev_id: VDEV Id
  2492. * @wlan_op_mode: VDEV operating mode
  2493. *
  2494. * Return: DP VDEV handle on success, NULL on failure
  2495. */
  2496. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2497. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2498. {
  2499. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2500. struct dp_soc *soc = pdev->soc;
  2501. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2502. int tx_ring_size;
  2503. if (!vdev) {
  2504. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2505. FL("DP VDEV memory allocation failed"));
  2506. goto fail0;
  2507. }
  2508. vdev->pdev = pdev;
  2509. vdev->vdev_id = vdev_id;
  2510. vdev->opmode = op_mode;
  2511. vdev->osdev = soc->osdev;
  2512. vdev->osif_rx = NULL;
  2513. vdev->osif_rsim_rx_decap = NULL;
  2514. vdev->osif_get_key = NULL;
  2515. vdev->osif_rx_mon = NULL;
  2516. vdev->osif_tx_free_ext = NULL;
  2517. vdev->osif_vdev = NULL;
  2518. vdev->delete.pending = 0;
  2519. vdev->safemode = 0;
  2520. vdev->drop_unenc = 1;
  2521. #ifdef notyet
  2522. vdev->filters_num = 0;
  2523. #endif
  2524. qdf_mem_copy(
  2525. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2526. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2527. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2528. vdev->dscp_tid_map_id = 0;
  2529. vdev->mcast_enhancement_en = 0;
  2530. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2531. /* TODO: Initialize default HTT meta data that will be used in
  2532. * TCL descriptors for packets transmitted from this VDEV
  2533. */
  2534. TAILQ_INIT(&vdev->peer_list);
  2535. /* add this vdev into the pdev's list */
  2536. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2537. pdev->vdev_count++;
  2538. dp_tx_vdev_attach(vdev);
  2539. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2540. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2541. goto fail1;
  2542. if ((soc->intr_mode == DP_INTR_POLL) &&
  2543. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2544. if (pdev->vdev_count == 1)
  2545. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2546. }
  2547. dp_lro_hash_setup(soc);
  2548. /* LRO */
  2549. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2550. wlan_op_mode_sta == vdev->opmode)
  2551. vdev->lro_enable = true;
  2552. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2553. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2554. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2555. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2556. DP_STATS_INIT(vdev);
  2557. return (struct cdp_vdev *)vdev;
  2558. fail1:
  2559. dp_tx_vdev_detach(vdev);
  2560. qdf_mem_free(vdev);
  2561. fail0:
  2562. return NULL;
  2563. }
  2564. /**
  2565. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2566. * @vdev: Datapath VDEV handle
  2567. * @osif_vdev: OSIF vdev handle
  2568. * @txrx_ops: Tx and Rx operations
  2569. *
  2570. * Return: DP VDEV handle on success, NULL on failure
  2571. */
  2572. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2573. void *osif_vdev,
  2574. struct ol_txrx_ops *txrx_ops)
  2575. {
  2576. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2577. vdev->osif_vdev = osif_vdev;
  2578. vdev->osif_rx = txrx_ops->rx.rx;
  2579. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2580. vdev->osif_get_key = txrx_ops->get_key;
  2581. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2582. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2583. #ifdef notyet
  2584. #if ATH_SUPPORT_WAPI
  2585. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2586. #endif
  2587. #endif
  2588. #ifdef UMAC_SUPPORT_PROXY_ARP
  2589. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2590. #endif
  2591. vdev->me_convert = txrx_ops->me_convert;
  2592. /* TODO: Enable the following once Tx code is integrated */
  2593. txrx_ops->tx.tx = dp_tx_send;
  2594. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2595. "DP Vdev Register success");
  2596. }
  2597. /*
  2598. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2599. * @txrx_vdev: Datapath VDEV handle
  2600. * @callback: Callback OL_IF on completion of detach
  2601. * @cb_context: Callback context
  2602. *
  2603. */
  2604. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2605. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2606. {
  2607. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2608. struct dp_pdev *pdev = vdev->pdev;
  2609. struct dp_soc *soc = pdev->soc;
  2610. /* preconditions */
  2611. qdf_assert(vdev);
  2612. /* remove the vdev from its parent pdev's list */
  2613. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2614. /*
  2615. * Use peer_ref_mutex while accessing peer_list, in case
  2616. * a peer is in the process of being removed from the list.
  2617. */
  2618. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2619. /* check that the vdev has no peers allocated */
  2620. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2621. /* debug print - will be removed later */
  2622. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2623. FL("not deleting vdev object %pK (%pM)"
  2624. "until deletion finishes for all its peers"),
  2625. vdev, vdev->mac_addr.raw);
  2626. /* indicate that the vdev needs to be deleted */
  2627. vdev->delete.pending = 1;
  2628. vdev->delete.callback = callback;
  2629. vdev->delete.context = cb_context;
  2630. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2631. return;
  2632. }
  2633. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2634. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2635. vdev->vdev_id);
  2636. dp_tx_vdev_detach(vdev);
  2637. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2638. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2639. qdf_mem_free(vdev);
  2640. if (callback)
  2641. callback(cb_context);
  2642. }
  2643. /*
  2644. * dp_peer_create_wifi3() - attach txrx peer
  2645. * @txrx_vdev: Datapath VDEV handle
  2646. * @peer_mac_addr: Peer MAC address
  2647. *
  2648. * Return: DP peeer handle on success, NULL on failure
  2649. */
  2650. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2651. uint8_t *peer_mac_addr)
  2652. {
  2653. struct dp_peer *peer;
  2654. int i;
  2655. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2656. struct dp_pdev *pdev;
  2657. struct dp_soc *soc;
  2658. /* preconditions */
  2659. qdf_assert(vdev);
  2660. qdf_assert(peer_mac_addr);
  2661. pdev = vdev->pdev;
  2662. soc = pdev->soc;
  2663. #ifdef notyet
  2664. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2665. soc->mempool_ol_ath_peer);
  2666. #else
  2667. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2668. #endif
  2669. if (!peer)
  2670. return NULL; /* failure */
  2671. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2672. TAILQ_INIT(&peer->ast_entry_list);
  2673. /* store provided params */
  2674. peer->vdev = vdev;
  2675. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2676. qdf_spinlock_create(&peer->peer_info_lock);
  2677. qdf_mem_copy(
  2678. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2679. /* TODO: See of rx_opt_proc is really required */
  2680. peer->rx_opt_proc = soc->rx_opt_proc;
  2681. /* initialize the peer_id */
  2682. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2683. peer->peer_ids[i] = HTT_INVALID_PEER;
  2684. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2685. qdf_atomic_init(&peer->ref_cnt);
  2686. /* keep one reference for attach */
  2687. qdf_atomic_inc(&peer->ref_cnt);
  2688. /* add this peer into the vdev's list */
  2689. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2690. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2691. /* TODO: See if hash based search is required */
  2692. dp_peer_find_hash_add(soc, peer);
  2693. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2694. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2695. vdev, peer, peer->mac_addr.raw,
  2696. qdf_atomic_read(&peer->ref_cnt));
  2697. /*
  2698. * For every peer MAp message search and set if bss_peer
  2699. */
  2700. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2701. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2702. "vdev bss_peer!!!!");
  2703. peer->bss_peer = 1;
  2704. vdev->vap_bss_peer = peer;
  2705. }
  2706. #ifndef CONFIG_WIN
  2707. dp_local_peer_id_alloc(pdev, peer);
  2708. #endif
  2709. DP_STATS_INIT(peer);
  2710. return (void *)peer;
  2711. }
  2712. /*
  2713. * dp_peer_setup_wifi3() - initialize the peer
  2714. * @vdev_hdl: virtual device object
  2715. * @peer: Peer object
  2716. *
  2717. * Return: void
  2718. */
  2719. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2720. {
  2721. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2722. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2723. struct dp_pdev *pdev;
  2724. struct dp_soc *soc;
  2725. bool hash_based = 0;
  2726. enum cdp_host_reo_dest_ring reo_dest;
  2727. /* preconditions */
  2728. qdf_assert(vdev);
  2729. qdf_assert(peer);
  2730. pdev = vdev->pdev;
  2731. soc = pdev->soc;
  2732. dp_peer_rx_init(pdev, peer);
  2733. peer->last_assoc_rcvd = 0;
  2734. peer->last_disassoc_rcvd = 0;
  2735. peer->last_deauth_rcvd = 0;
  2736. /*
  2737. * hash based steering is disabled for Radios which are offloaded
  2738. * to NSS
  2739. */
  2740. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2741. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2742. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2743. FL("hash based steering for pdev: %d is %d\n"),
  2744. pdev->pdev_id, hash_based);
  2745. /*
  2746. * Below line of code will ensure the proper reo_dest ring is choosen
  2747. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2748. */
  2749. reo_dest = pdev->reo_dest;
  2750. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2751. /* TODO: Check the destination ring number to be passed to FW */
  2752. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2753. pdev->osif_pdev, peer->mac_addr.raw,
  2754. peer->vdev->vdev_id, hash_based, reo_dest);
  2755. }
  2756. return;
  2757. }
  2758. /*
  2759. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2760. * @vdev_handle: virtual device object
  2761. * @htt_pkt_type: type of pkt
  2762. *
  2763. * Return: void
  2764. */
  2765. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2766. enum htt_cmn_pkt_type val)
  2767. {
  2768. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2769. vdev->tx_encap_type = val;
  2770. }
  2771. /*
  2772. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2773. * @vdev_handle: virtual device object
  2774. * @htt_pkt_type: type of pkt
  2775. *
  2776. * Return: void
  2777. */
  2778. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2779. enum htt_cmn_pkt_type val)
  2780. {
  2781. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2782. vdev->rx_decap_type = val;
  2783. }
  2784. /*
  2785. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2786. * @pdev_handle: physical device object
  2787. * @val: reo destination ring index (1 - 4)
  2788. *
  2789. * Return: void
  2790. */
  2791. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2792. enum cdp_host_reo_dest_ring val)
  2793. {
  2794. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2795. if (pdev)
  2796. pdev->reo_dest = val;
  2797. }
  2798. /*
  2799. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2800. * @pdev_handle: physical device object
  2801. *
  2802. * Return: reo destination ring index
  2803. */
  2804. static enum cdp_host_reo_dest_ring
  2805. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2806. {
  2807. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2808. if (pdev)
  2809. return pdev->reo_dest;
  2810. else
  2811. return cdp_host_reo_dest_ring_unknown;
  2812. }
  2813. #ifdef QCA_SUPPORT_SON
  2814. static void dp_son_peer_authorize(struct dp_peer *peer)
  2815. {
  2816. struct dp_soc *soc;
  2817. soc = peer->vdev->pdev->soc;
  2818. peer->peer_bs_inact_flag = 0;
  2819. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2820. return;
  2821. }
  2822. #else
  2823. static void dp_son_peer_authorize(struct dp_peer *peer)
  2824. {
  2825. return;
  2826. }
  2827. #endif
  2828. /*
  2829. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2830. * @pdev_handle: device object
  2831. * @val: value to be set
  2832. *
  2833. * Return: void
  2834. */
  2835. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2836. uint32_t val)
  2837. {
  2838. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2839. /* Enable/Disable smart mesh filtering. This flag will be checked
  2840. * during rx processing to check if packets are from NAC clients.
  2841. */
  2842. pdev->filter_neighbour_peers = val;
  2843. return 0;
  2844. }
  2845. /*
  2846. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2847. * address for smart mesh filtering
  2848. * @pdev_handle: device object
  2849. * @cmd: Add/Del command
  2850. * @macaddr: nac client mac address
  2851. *
  2852. * Return: void
  2853. */
  2854. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2855. uint32_t cmd, uint8_t *macaddr)
  2856. {
  2857. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2858. struct dp_neighbour_peer *peer = NULL;
  2859. if (!macaddr)
  2860. goto fail0;
  2861. /* Store address of NAC (neighbour peer) which will be checked
  2862. * against TA of received packets.
  2863. */
  2864. if (cmd == DP_NAC_PARAM_ADD) {
  2865. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2866. sizeof(*peer));
  2867. if (!peer) {
  2868. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2869. FL("DP neighbour peer node memory allocation failed"));
  2870. goto fail0;
  2871. }
  2872. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2873. macaddr, DP_MAC_ADDR_LEN);
  2874. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2875. /* add this neighbour peer into the list */
  2876. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2877. neighbour_peer_list_elem);
  2878. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2879. return 1;
  2880. } else if (cmd == DP_NAC_PARAM_DEL) {
  2881. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2882. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2883. neighbour_peer_list_elem) {
  2884. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2885. macaddr, DP_MAC_ADDR_LEN)) {
  2886. /* delete this peer from the list */
  2887. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2888. peer, neighbour_peer_list_elem);
  2889. qdf_mem_free(peer);
  2890. break;
  2891. }
  2892. }
  2893. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2894. return 1;
  2895. }
  2896. fail0:
  2897. return 0;
  2898. }
  2899. /*
  2900. * dp_get_sec_type() - Get the security type
  2901. * @peer: Datapath peer handle
  2902. * @sec_idx: Security id (mcast, ucast)
  2903. *
  2904. * return sec_type: Security type
  2905. */
  2906. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2907. {
  2908. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2909. return dpeer->security[sec_idx].sec_type;
  2910. }
  2911. /*
  2912. * dp_peer_authorize() - authorize txrx peer
  2913. * @peer_handle: Datapath peer handle
  2914. * @authorize
  2915. *
  2916. */
  2917. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2918. {
  2919. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2920. struct dp_soc *soc;
  2921. if (peer != NULL) {
  2922. soc = peer->vdev->pdev->soc;
  2923. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2924. dp_son_peer_authorize(peer);
  2925. peer->authorize = authorize ? 1 : 0;
  2926. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2927. }
  2928. }
  2929. /*
  2930. * dp_peer_unref_delete() - unref and delete peer
  2931. * @peer_handle: Datapath peer handle
  2932. *
  2933. */
  2934. void dp_peer_unref_delete(void *peer_handle)
  2935. {
  2936. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2937. struct dp_vdev *vdev = peer->vdev;
  2938. struct dp_pdev *pdev = vdev->pdev;
  2939. struct dp_soc *soc = pdev->soc;
  2940. struct dp_peer *tmppeer;
  2941. int found = 0;
  2942. uint16_t peer_id;
  2943. /*
  2944. * Hold the lock all the way from checking if the peer ref count
  2945. * is zero until the peer references are removed from the hash
  2946. * table and vdev list (if the peer ref count is zero).
  2947. * This protects against a new HL tx operation starting to use the
  2948. * peer object just after this function concludes it's done being used.
  2949. * Furthermore, the lock needs to be held while checking whether the
  2950. * vdev's list of peers is empty, to make sure that list is not modified
  2951. * concurrently with the empty check.
  2952. */
  2953. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2954. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2955. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2956. peer, qdf_atomic_read(&peer->ref_cnt));
  2957. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2958. peer_id = peer->peer_ids[0];
  2959. /*
  2960. * Make sure that the reference to the peer in
  2961. * peer object map is removed
  2962. */
  2963. if (peer_id != HTT_INVALID_PEER)
  2964. soc->peer_id_to_obj_map[peer_id] = NULL;
  2965. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2966. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2967. /* remove the reference to the peer from the hash table */
  2968. dp_peer_find_hash_remove(soc, peer);
  2969. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2970. if (tmppeer == peer) {
  2971. found = 1;
  2972. break;
  2973. }
  2974. }
  2975. if (found) {
  2976. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2977. peer_list_elem);
  2978. } else {
  2979. /*Ignoring the remove operation as peer not found*/
  2980. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2981. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2982. peer, vdev, &peer->vdev->peer_list);
  2983. }
  2984. /* cleanup the peer data */
  2985. dp_peer_cleanup(vdev, peer);
  2986. /* check whether the parent vdev has no peers left */
  2987. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2988. /*
  2989. * Now that there are no references to the peer, we can
  2990. * release the peer reference lock.
  2991. */
  2992. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2993. /*
  2994. * Check if the parent vdev was waiting for its peers
  2995. * to be deleted, in order for it to be deleted too.
  2996. */
  2997. if (vdev->delete.pending) {
  2998. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2999. vdev->delete.callback;
  3000. void *vdev_delete_context =
  3001. vdev->delete.context;
  3002. QDF_TRACE(QDF_MODULE_ID_DP,
  3003. QDF_TRACE_LEVEL_INFO_HIGH,
  3004. FL("deleting vdev object %pK (%pM)"
  3005. " - its last peer is done"),
  3006. vdev, vdev->mac_addr.raw);
  3007. /* all peers are gone, go ahead and delete it */
  3008. qdf_mem_free(vdev);
  3009. if (vdev_delete_cb)
  3010. vdev_delete_cb(vdev_delete_context);
  3011. }
  3012. } else {
  3013. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3014. }
  3015. #ifdef notyet
  3016. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  3017. #else
  3018. qdf_mem_free(peer);
  3019. #endif
  3020. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  3021. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  3022. vdev->vdev_id, peer->mac_addr.raw);
  3023. }
  3024. } else {
  3025. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  3026. }
  3027. }
  3028. /*
  3029. * dp_peer_detach_wifi3() – Detach txrx peer
  3030. * @peer_handle: Datapath peer handle
  3031. *
  3032. */
  3033. static void dp_peer_delete_wifi3(void *peer_handle)
  3034. {
  3035. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  3036. /* redirect the peer's rx delivery function to point to a
  3037. * discard func
  3038. */
  3039. peer->rx_opt_proc = dp_rx_discard;
  3040. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  3041. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  3042. #ifndef CONFIG_WIN
  3043. dp_local_peer_id_free(peer->vdev->pdev, peer);
  3044. #endif
  3045. qdf_spinlock_destroy(&peer->peer_info_lock);
  3046. /*
  3047. * Remove the reference added during peer_attach.
  3048. * The peer will still be left allocated until the
  3049. * PEER_UNMAP message arrives to remove the other
  3050. * reference, added by the PEER_MAP message.
  3051. */
  3052. dp_peer_unref_delete(peer_handle);
  3053. }
  3054. /*
  3055. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  3056. * @peer_handle: Datapath peer handle
  3057. *
  3058. */
  3059. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  3060. {
  3061. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3062. return vdev->mac_addr.raw;
  3063. }
  3064. /*
  3065. * dp_vdev_set_wds() - Enable per packet stats
  3066. * @vdev_handle: DP VDEV handle
  3067. * @val: value
  3068. *
  3069. * Return: none
  3070. */
  3071. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  3072. {
  3073. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3074. vdev->wds_enabled = val;
  3075. return 0;
  3076. }
  3077. /*
  3078. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  3079. * @peer_handle: Datapath peer handle
  3080. *
  3081. */
  3082. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3083. uint8_t vdev_id)
  3084. {
  3085. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3086. struct dp_vdev *vdev = NULL;
  3087. if (qdf_unlikely(!pdev))
  3088. return NULL;
  3089. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3090. if (vdev->vdev_id == vdev_id)
  3091. break;
  3092. }
  3093. return (struct cdp_vdev *)vdev;
  3094. }
  3095. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3096. {
  3097. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3098. return vdev->opmode;
  3099. }
  3100. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3101. {
  3102. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3103. struct dp_pdev *pdev = vdev->pdev;
  3104. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3105. }
  3106. /**
  3107. * dp_reset_monitor_mode() - Disable monitor mode
  3108. * @pdev_handle: Datapath PDEV handle
  3109. *
  3110. * Return: 0 on success, not 0 on failure
  3111. */
  3112. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3113. {
  3114. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3115. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3116. struct dp_soc *soc;
  3117. uint8_t pdev_id;
  3118. pdev_id = pdev->pdev_id;
  3119. soc = pdev->soc;
  3120. pdev->monitor_vdev = NULL;
  3121. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3122. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3123. pdev->rxdma_mon_buf_ring.hal_srng,
  3124. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3125. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3126. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3127. RX_BUFFER_SIZE, &htt_tlv_filter);
  3128. return 0;
  3129. }
  3130. /**
  3131. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3132. * @vdev_handle: Datapath VDEV handle
  3133. * @smart_monitor: Flag to denote if its smart monitor mode
  3134. *
  3135. * Return: 0 on success, not 0 on failure
  3136. */
  3137. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3138. uint8_t smart_monitor)
  3139. {
  3140. /* Many monitor VAPs can exists in a system but only one can be up at
  3141. * anytime
  3142. */
  3143. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3144. struct dp_pdev *pdev;
  3145. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3146. struct dp_soc *soc;
  3147. uint8_t pdev_id;
  3148. qdf_assert(vdev);
  3149. pdev = vdev->pdev;
  3150. pdev_id = pdev->pdev_id;
  3151. soc = pdev->soc;
  3152. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3153. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3154. pdev, pdev_id, soc, vdev);
  3155. /*Check if current pdev's monitor_vdev exists */
  3156. if (pdev->monitor_vdev) {
  3157. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3158. "vdev=%pK\n", vdev);
  3159. qdf_assert(vdev);
  3160. }
  3161. pdev->monitor_vdev = vdev;
  3162. /* If smart monitor mode, do not configure monitor ring */
  3163. if (smart_monitor)
  3164. return QDF_STATUS_SUCCESS;
  3165. htt_tlv_filter.mpdu_start = 1;
  3166. htt_tlv_filter.msdu_start = 1;
  3167. htt_tlv_filter.packet = 1;
  3168. htt_tlv_filter.msdu_end = 1;
  3169. htt_tlv_filter.mpdu_end = 1;
  3170. htt_tlv_filter.packet_header = 1;
  3171. htt_tlv_filter.attention = 1;
  3172. htt_tlv_filter.ppdu_start = 0;
  3173. htt_tlv_filter.ppdu_end = 0;
  3174. htt_tlv_filter.ppdu_end_user_stats = 0;
  3175. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3176. htt_tlv_filter.ppdu_end_status_done = 0;
  3177. htt_tlv_filter.header_per_msdu = 1;
  3178. htt_tlv_filter.enable_fp = 1;
  3179. htt_tlv_filter.enable_md = 0;
  3180. htt_tlv_filter.enable_mo = 1;
  3181. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3182. pdev->rxdma_mon_buf_ring.hal_srng,
  3183. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3184. htt_tlv_filter.mpdu_start = 1;
  3185. htt_tlv_filter.msdu_start = 1;
  3186. htt_tlv_filter.packet = 0;
  3187. htt_tlv_filter.msdu_end = 1;
  3188. htt_tlv_filter.mpdu_end = 1;
  3189. htt_tlv_filter.packet_header = 1;
  3190. htt_tlv_filter.attention = 1;
  3191. htt_tlv_filter.ppdu_start = 1;
  3192. htt_tlv_filter.ppdu_end = 1;
  3193. htt_tlv_filter.ppdu_end_user_stats = 1;
  3194. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3195. htt_tlv_filter.ppdu_end_status_done = 1;
  3196. htt_tlv_filter.header_per_msdu = 0;
  3197. htt_tlv_filter.enable_fp = 1;
  3198. htt_tlv_filter.enable_md = 0;
  3199. htt_tlv_filter.enable_mo = 1;
  3200. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3201. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3202. RX_BUFFER_SIZE, &htt_tlv_filter);
  3203. return QDF_STATUS_SUCCESS;
  3204. }
  3205. #ifdef MESH_MODE_SUPPORT
  3206. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3207. {
  3208. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3210. FL("val %d"), val);
  3211. vdev->mesh_vdev = val;
  3212. }
  3213. /*
  3214. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3215. * @vdev_hdl: virtual device object
  3216. * @val: value to be set
  3217. *
  3218. * Return: void
  3219. */
  3220. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3221. {
  3222. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3223. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3224. FL("val %d"), val);
  3225. vdev->mesh_rx_filter = val;
  3226. }
  3227. #endif
  3228. /*
  3229. * dp_aggregate_pdev_ctrl_frames_stats()- function to agreegate peer stats
  3230. * Current scope is bar recieved count
  3231. *
  3232. * @pdev_handle: DP_PDEV handle
  3233. *
  3234. * Return: void
  3235. */
  3236. #define STATS_PROC_TIMEOUT (HZ/10)
  3237. static void
  3238. dp_aggregate_pdev_ctrl_frames_stats(struct dp_pdev *pdev)
  3239. {
  3240. struct dp_vdev *vdev;
  3241. struct dp_peer *peer;
  3242. uint32_t waitcnt;
  3243. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3244. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3245. if (!peer) {
  3246. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3247. FL("DP Invalid Peer refernce"));
  3248. return;
  3249. }
  3250. waitcnt = 0;
  3251. dp_peer_rxtid_stats(peer, dp_rx_bar_stats_cb, pdev);
  3252. while (!(qdf_atomic_read(&(pdev->stats.cmd_complete)))
  3253. && waitcnt < 10) {
  3254. schedule_timeout_interruptible(
  3255. STATS_PROC_TIMEOUT);
  3256. waitcnt++;
  3257. }
  3258. qdf_atomic_set(&(pdev->stats.cmd_complete), 0);
  3259. }
  3260. }
  3261. }
  3262. /**
  3263. * dp_rx_bar_stats_cb(): BAR received stats callback
  3264. * @soc: SOC handle
  3265. * @cb_ctxt: Call back context
  3266. * @reo_status: Reo status
  3267. *
  3268. * return: void
  3269. */
  3270. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3271. union hal_reo_status *reo_status)
  3272. {
  3273. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3274. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3275. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3276. DP_TRACE_STATS(FATAL, "REO stats failure %d \n",
  3277. queue_status->header.status);
  3278. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3279. return;
  3280. }
  3281. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3282. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3283. }
  3284. /**
  3285. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3286. * @vdev: DP VDEV handle
  3287. *
  3288. * return: void
  3289. */
  3290. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3291. {
  3292. struct dp_peer *peer = NULL;
  3293. struct dp_soc *soc = vdev->pdev->soc;
  3294. int i;
  3295. uint8_t pream_type;
  3296. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3297. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3298. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3299. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3300. for (i = 0; i < MAX_MCS; i++) {
  3301. DP_STATS_AGGR(vdev, peer,
  3302. tx.pkt_type[pream_type].mcs_count[i]);
  3303. DP_STATS_AGGR(vdev, peer,
  3304. rx.pkt_type[pream_type].mcs_count[i]);
  3305. }
  3306. }
  3307. for (i = 0; i < MAX_BW; i++) {
  3308. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3309. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3310. }
  3311. for (i = 0; i < SS_COUNT; i++)
  3312. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3313. for (i = 0; i < WME_AC_MAX; i++) {
  3314. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3315. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3316. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3317. }
  3318. for (i = 0; i < MAX_GI; i++) {
  3319. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3320. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3321. }
  3322. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3323. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3324. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3325. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3326. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3327. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3328. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3329. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3330. DP_STATS_AGGR(vdev, peer, tx.retries);
  3331. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3332. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3333. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3334. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3335. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3336. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3337. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3338. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3339. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3340. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3341. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3342. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3343. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3344. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3345. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3346. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3347. peer->stats.rx.multicast.num;
  3348. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3349. peer->stats.rx.multicast.bytes;
  3350. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3351. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3352. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3353. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3354. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3355. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3356. vdev->stats.tx.last_ack_rssi =
  3357. peer->stats.tx.last_ack_rssi;
  3358. }
  3359. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3360. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3361. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3362. }
  3363. /**
  3364. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3365. * @pdev: DP PDEV handle
  3366. *
  3367. * return: void
  3368. */
  3369. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3370. {
  3371. struct dp_vdev *vdev = NULL;
  3372. uint8_t i;
  3373. uint8_t pream_type;
  3374. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3375. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3376. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3377. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3378. dp_aggregate_vdev_stats(vdev);
  3379. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3380. for (i = 0; i < MAX_MCS; i++) {
  3381. DP_STATS_AGGR(pdev, vdev,
  3382. tx.pkt_type[pream_type].mcs_count[i]);
  3383. DP_STATS_AGGR(pdev, vdev,
  3384. rx.pkt_type[pream_type].mcs_count[i]);
  3385. }
  3386. }
  3387. for (i = 0; i < MAX_BW; i++) {
  3388. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3389. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3390. }
  3391. for (i = 0; i < SS_COUNT; i++)
  3392. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3393. for (i = 0; i < WME_AC_MAX; i++) {
  3394. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3395. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3396. DP_STATS_AGGR(pdev, vdev,
  3397. tx.excess_retries_ac[i]);
  3398. }
  3399. for (i = 0; i < MAX_GI; i++) {
  3400. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3401. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3402. }
  3403. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3404. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3405. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3406. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3407. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3408. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3409. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3410. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3411. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3412. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3413. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3414. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3415. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3416. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3417. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3418. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3419. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3420. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3421. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3422. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3423. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3424. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3425. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3426. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3427. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3428. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3429. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3430. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3431. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3432. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3433. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3434. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3435. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3436. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3437. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3438. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3439. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3440. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3441. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3442. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3443. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3444. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3445. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3446. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3447. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3448. DP_STATS_AGGR(pdev, vdev,
  3449. tx_i.mcast_en.dropped_map_error);
  3450. DP_STATS_AGGR(pdev, vdev,
  3451. tx_i.mcast_en.dropped_self_mac);
  3452. DP_STATS_AGGR(pdev, vdev,
  3453. tx_i.mcast_en.dropped_send_fail);
  3454. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3455. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3456. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3457. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3458. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3459. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3460. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3461. pdev->stats.tx_i.dropped.dma_error +
  3462. pdev->stats.tx_i.dropped.ring_full +
  3463. pdev->stats.tx_i.dropped.enqueue_fail +
  3464. pdev->stats.tx_i.dropped.desc_na +
  3465. pdev->stats.tx_i.dropped.res_full;
  3466. pdev->stats.tx.last_ack_rssi =
  3467. vdev->stats.tx.last_ack_rssi;
  3468. pdev->stats.tx_i.tso.num_seg =
  3469. vdev->stats.tx_i.tso.num_seg;
  3470. }
  3471. }
  3472. /**
  3473. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3474. * @pdev: DP_PDEV Handle
  3475. *
  3476. * Return:void
  3477. */
  3478. static inline void
  3479. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3480. {
  3481. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3482. DP_PRINT_STATS("Received From Stack:");
  3483. DP_PRINT_STATS(" Packets = %d",
  3484. pdev->stats.tx_i.rcvd.num);
  3485. DP_PRINT_STATS(" Bytes = %d",
  3486. pdev->stats.tx_i.rcvd.bytes);
  3487. DP_PRINT_STATS("Processed:");
  3488. DP_PRINT_STATS(" Packets = %d",
  3489. pdev->stats.tx_i.processed.num);
  3490. DP_PRINT_STATS(" Bytes = %d",
  3491. pdev->stats.tx_i.processed.bytes);
  3492. DP_PRINT_STATS("Completions:");
  3493. DP_PRINT_STATS(" Packets = %d",
  3494. pdev->stats.tx.comp_pkt.num);
  3495. DP_PRINT_STATS(" Bytes = %d",
  3496. pdev->stats.tx.comp_pkt.bytes);
  3497. DP_PRINT_STATS("Dropped:");
  3498. DP_PRINT_STATS(" Total = %d",
  3499. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3500. DP_PRINT_STATS(" Dma_map_error = %d",
  3501. pdev->stats.tx_i.dropped.dma_error);
  3502. DP_PRINT_STATS(" Ring Full = %d",
  3503. pdev->stats.tx_i.dropped.ring_full);
  3504. DP_PRINT_STATS(" Descriptor Not available = %d",
  3505. pdev->stats.tx_i.dropped.desc_na);
  3506. DP_PRINT_STATS(" HW enqueue failed= %d",
  3507. pdev->stats.tx_i.dropped.enqueue_fail);
  3508. DP_PRINT_STATS(" Resources Full = %d",
  3509. pdev->stats.tx_i.dropped.res_full);
  3510. DP_PRINT_STATS(" FW removed = %d",
  3511. pdev->stats.tx.dropped.fw_rem);
  3512. DP_PRINT_STATS(" FW removed transmitted = %d",
  3513. pdev->stats.tx.dropped.fw_rem_tx);
  3514. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3515. pdev->stats.tx.dropped.fw_rem_notx);
  3516. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3517. pdev->stats.tx.dropped.age_out);
  3518. DP_PRINT_STATS("Scatter Gather:");
  3519. DP_PRINT_STATS(" Packets = %d",
  3520. pdev->stats.tx_i.sg.sg_pkt.num);
  3521. DP_PRINT_STATS(" Bytes = %d",
  3522. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3523. DP_PRINT_STATS(" Dropped By Host = %d",
  3524. pdev->stats.tx_i.sg.dropped_host);
  3525. DP_PRINT_STATS(" Dropped By Target = %d",
  3526. pdev->stats.tx_i.sg.dropped_target);
  3527. DP_PRINT_STATS("TSO:");
  3528. DP_PRINT_STATS(" Number of Segments = %d",
  3529. pdev->stats.tx_i.tso.num_seg);
  3530. DP_PRINT_STATS(" Packets = %d",
  3531. pdev->stats.tx_i.tso.tso_pkt.num);
  3532. DP_PRINT_STATS(" Bytes = %d",
  3533. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3534. DP_PRINT_STATS(" Dropped By Host = %d",
  3535. pdev->stats.tx_i.tso.dropped_host);
  3536. DP_PRINT_STATS("Mcast Enhancement:");
  3537. DP_PRINT_STATS(" Packets = %d",
  3538. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3539. DP_PRINT_STATS(" Bytes = %d",
  3540. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3541. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3542. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3543. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3544. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3545. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3546. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3547. DP_PRINT_STATS(" Unicast sent = %d",
  3548. pdev->stats.tx_i.mcast_en.ucast);
  3549. DP_PRINT_STATS("Raw:");
  3550. DP_PRINT_STATS(" Packets = %d",
  3551. pdev->stats.tx_i.raw.raw_pkt.num);
  3552. DP_PRINT_STATS(" Bytes = %d",
  3553. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3554. DP_PRINT_STATS(" DMA map error = %d",
  3555. pdev->stats.tx_i.raw.dma_map_error);
  3556. DP_PRINT_STATS("Reinjected:");
  3557. DP_PRINT_STATS(" Packets = %d",
  3558. pdev->stats.tx_i.reinject_pkts.num);
  3559. DP_PRINT_STATS("Bytes = %d\n",
  3560. pdev->stats.tx_i.reinject_pkts.bytes);
  3561. DP_PRINT_STATS("Inspected:");
  3562. DP_PRINT_STATS(" Packets = %d",
  3563. pdev->stats.tx_i.inspect_pkts.num);
  3564. DP_PRINT_STATS(" Bytes = %d",
  3565. pdev->stats.tx_i.inspect_pkts.bytes);
  3566. }
  3567. /**
  3568. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3569. * @pdev: DP_PDEV Handle
  3570. *
  3571. * Return: void
  3572. */
  3573. static inline void
  3574. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3575. {
  3576. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3577. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3578. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3579. pdev->stats.rx.rcvd_reo[0].num,
  3580. pdev->stats.rx.rcvd_reo[1].num,
  3581. pdev->stats.rx.rcvd_reo[2].num,
  3582. pdev->stats.rx.rcvd_reo[3].num);
  3583. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3584. pdev->stats.rx.rcvd_reo[0].bytes,
  3585. pdev->stats.rx.rcvd_reo[1].bytes,
  3586. pdev->stats.rx.rcvd_reo[2].bytes,
  3587. pdev->stats.rx.rcvd_reo[3].bytes);
  3588. DP_PRINT_STATS("Replenished:");
  3589. DP_PRINT_STATS(" Packets = %d",
  3590. pdev->stats.replenish.pkts.num);
  3591. DP_PRINT_STATS(" Bytes = %d",
  3592. pdev->stats.replenish.pkts.bytes);
  3593. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3594. pdev->stats.buf_freelist);
  3595. DP_PRINT_STATS("Dropped:");
  3596. DP_PRINT_STATS(" msdu_not_done = %d",
  3597. pdev->stats.dropped.msdu_not_done);
  3598. DP_PRINT_STATS("Sent To Stack:");
  3599. DP_PRINT_STATS(" Packets = %d",
  3600. pdev->stats.rx.to_stack.num);
  3601. DP_PRINT_STATS(" Bytes = %d",
  3602. pdev->stats.rx.to_stack.bytes);
  3603. DP_PRINT_STATS("Multicast/Broadcast:");
  3604. DP_PRINT_STATS(" Packets = %d",
  3605. pdev->stats.rx.multicast.num);
  3606. DP_PRINT_STATS(" Bytes = %d",
  3607. pdev->stats.rx.multicast.bytes);
  3608. DP_PRINT_STATS("Errors:");
  3609. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3610. pdev->stats.replenish.rxdma_err);
  3611. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3612. pdev->stats.err.desc_alloc_fail);
  3613. /* Get bar_recv_cnt */
  3614. dp_aggregate_pdev_ctrl_frames_stats(pdev);
  3615. DP_PRINT_STATS("BAR Received Count: = %d",
  3616. pdev->stats.rx.bar_recv_cnt);
  3617. }
  3618. /**
  3619. * dp_print_soc_tx_stats(): Print SOC level stats
  3620. * @soc DP_SOC Handle
  3621. *
  3622. * Return: void
  3623. */
  3624. static inline void
  3625. dp_print_soc_tx_stats(struct dp_soc *soc)
  3626. {
  3627. DP_PRINT_STATS("SOC Tx Stats:\n");
  3628. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3629. soc->stats.tx.desc_in_use);
  3630. DP_PRINT_STATS("Invalid peer:");
  3631. DP_PRINT_STATS(" Packets = %d",
  3632. soc->stats.tx.tx_invalid_peer.num);
  3633. DP_PRINT_STATS(" Bytes = %d",
  3634. soc->stats.tx.tx_invalid_peer.bytes);
  3635. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3636. soc->stats.tx.tcl_ring_full[0],
  3637. soc->stats.tx.tcl_ring_full[1],
  3638. soc->stats.tx.tcl_ring_full[2]);
  3639. }
  3640. /**
  3641. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3642. * @soc: DP_SOC Handle
  3643. *
  3644. * Return:void
  3645. */
  3646. static inline void
  3647. dp_print_soc_rx_stats(struct dp_soc *soc)
  3648. {
  3649. uint32_t i;
  3650. char reo_error[DP_REO_ERR_LENGTH];
  3651. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3652. uint8_t index = 0;
  3653. DP_PRINT_STATS("SOC Rx Stats:\n");
  3654. DP_PRINT_STATS("Errors:\n");
  3655. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3656. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3657. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3658. DP_PRINT_STATS("Invalid RBM = %d",
  3659. soc->stats.rx.err.invalid_rbm);
  3660. DP_PRINT_STATS("Invalid Vdev = %d",
  3661. soc->stats.rx.err.invalid_vdev);
  3662. DP_PRINT_STATS("Invalid Pdev = %d",
  3663. soc->stats.rx.err.invalid_pdev);
  3664. DP_PRINT_STATS("Invalid Peer = %d",
  3665. soc->stats.rx.err.rx_invalid_peer.num);
  3666. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3667. soc->stats.rx.err.hal_ring_access_fail);
  3668. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3669. index += qdf_snprint(&rxdma_error[index],
  3670. DP_RXDMA_ERR_LENGTH - index,
  3671. " %d", soc->stats.rx.err.rxdma_error[i]);
  3672. }
  3673. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3674. rxdma_error);
  3675. index = 0;
  3676. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3677. index += qdf_snprint(&reo_error[index],
  3678. DP_REO_ERR_LENGTH - index,
  3679. " %d", soc->stats.rx.err.reo_error[i]);
  3680. }
  3681. DP_PRINT_STATS("REO Error(0-14):%s",
  3682. reo_error);
  3683. }
  3684. /**
  3685. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3686. * @soc: DP_SOC handle
  3687. * @srng: DP_SRNG handle
  3688. * @ring_name: SRNG name
  3689. *
  3690. * Return: void
  3691. */
  3692. static inline void
  3693. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3694. char *ring_name)
  3695. {
  3696. uint32_t tailp;
  3697. uint32_t headp;
  3698. if (srng->hal_srng != NULL) {
  3699. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3700. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3701. ring_name, headp, tailp);
  3702. }
  3703. }
  3704. /**
  3705. * dp_print_ring_stats(): Print tail and head pointer
  3706. * @pdev: DP_PDEV handle
  3707. *
  3708. * Return:void
  3709. */
  3710. static inline void
  3711. dp_print_ring_stats(struct dp_pdev *pdev)
  3712. {
  3713. uint32_t i;
  3714. char ring_name[STR_MAXLEN + 1];
  3715. dp_print_ring_stat_from_hal(pdev->soc,
  3716. &pdev->soc->reo_exception_ring,
  3717. "Reo Exception Ring");
  3718. dp_print_ring_stat_from_hal(pdev->soc,
  3719. &pdev->soc->reo_reinject_ring,
  3720. "Reo Inject Ring");
  3721. dp_print_ring_stat_from_hal(pdev->soc,
  3722. &pdev->soc->reo_cmd_ring,
  3723. "Reo Command Ring");
  3724. dp_print_ring_stat_from_hal(pdev->soc,
  3725. &pdev->soc->reo_status_ring,
  3726. "Reo Status Ring");
  3727. dp_print_ring_stat_from_hal(pdev->soc,
  3728. &pdev->soc->rx_rel_ring,
  3729. "Rx Release ring");
  3730. dp_print_ring_stat_from_hal(pdev->soc,
  3731. &pdev->soc->tcl_cmd_ring,
  3732. "Tcl command Ring");
  3733. dp_print_ring_stat_from_hal(pdev->soc,
  3734. &pdev->soc->tcl_status_ring,
  3735. "Tcl Status Ring");
  3736. dp_print_ring_stat_from_hal(pdev->soc,
  3737. &pdev->soc->wbm_desc_rel_ring,
  3738. "Wbm Desc Rel Ring");
  3739. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3740. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3741. dp_print_ring_stat_from_hal(pdev->soc,
  3742. &pdev->soc->reo_dest_ring[i],
  3743. ring_name);
  3744. }
  3745. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3746. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3747. dp_print_ring_stat_from_hal(pdev->soc,
  3748. &pdev->soc->tcl_data_ring[i],
  3749. ring_name);
  3750. }
  3751. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3752. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3753. dp_print_ring_stat_from_hal(pdev->soc,
  3754. &pdev->soc->tx_comp_ring[i],
  3755. ring_name);
  3756. }
  3757. dp_print_ring_stat_from_hal(pdev->soc,
  3758. &pdev->rx_refill_buf_ring,
  3759. "Rx Refill Buf Ring");
  3760. #ifdef IPA_OFFLOAD
  3761. dp_print_ring_stat_from_hal(pdev->soc,
  3762. &pdev->ipa_rx_refill_buf_ring,
  3763. "IPA Rx Refill Buf Ring");
  3764. #endif
  3765. dp_print_ring_stat_from_hal(pdev->soc,
  3766. &pdev->rxdma_mon_buf_ring,
  3767. "Rxdma Mon Buf Ring");
  3768. dp_print_ring_stat_from_hal(pdev->soc,
  3769. &pdev->rxdma_mon_dst_ring,
  3770. "Rxdma Mon Dst Ring");
  3771. dp_print_ring_stat_from_hal(pdev->soc,
  3772. &pdev->rxdma_mon_status_ring,
  3773. "Rxdma Mon Status Ring");
  3774. dp_print_ring_stat_from_hal(pdev->soc,
  3775. &pdev->rxdma_mon_desc_ring,
  3776. "Rxdma mon desc Ring");
  3777. dp_print_ring_stat_from_hal(pdev->soc,
  3778. &pdev->rxdma_err_dst_ring,
  3779. "Rxdma err dst ring");
  3780. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3781. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3782. dp_print_ring_stat_from_hal(pdev->soc,
  3783. &pdev->rx_mac_buf_ring[i],
  3784. ring_name);
  3785. }
  3786. }
  3787. /**
  3788. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3789. * @vdev: DP_VDEV handle
  3790. *
  3791. * Return:void
  3792. */
  3793. static inline void
  3794. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3795. {
  3796. struct dp_peer *peer = NULL;
  3797. DP_STATS_CLR(vdev->pdev);
  3798. DP_STATS_CLR(vdev->pdev->soc);
  3799. DP_STATS_CLR(vdev);
  3800. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3801. if (!peer)
  3802. return;
  3803. DP_STATS_CLR(peer);
  3804. }
  3805. }
  3806. /**
  3807. * dp_print_rx_rates(): Print Rx rate stats
  3808. * @vdev: DP_VDEV handle
  3809. *
  3810. * Return:void
  3811. */
  3812. static inline void
  3813. dp_print_rx_rates(struct dp_vdev *vdev)
  3814. {
  3815. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3816. uint8_t i, mcs, pkt_type;
  3817. uint8_t index = 0;
  3818. char nss[DP_NSS_LENGTH];
  3819. DP_PRINT_STATS("Rx Rate Info:\n");
  3820. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3821. index = 0;
  3822. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3823. if (!dp_rate_string[pkt_type][mcs].valid)
  3824. continue;
  3825. DP_PRINT_STATS(" %s = %d",
  3826. dp_rate_string[pkt_type][mcs].mcs_type,
  3827. pdev->stats.rx.pkt_type[pkt_type].
  3828. mcs_count[mcs]);
  3829. }
  3830. DP_PRINT_STATS("\n");
  3831. }
  3832. index = 0;
  3833. for (i = 0; i < SS_COUNT; i++) {
  3834. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3835. " %d", pdev->stats.rx.nss[i]);
  3836. }
  3837. DP_PRINT_STATS("NSS(0-7) = %s",
  3838. nss);
  3839. DP_PRINT_STATS("SGI ="
  3840. " 0.8us %d,"
  3841. " 0.4us %d,"
  3842. " 1.6us %d,"
  3843. " 3.2us %d,",
  3844. pdev->stats.rx.sgi_count[0],
  3845. pdev->stats.rx.sgi_count[1],
  3846. pdev->stats.rx.sgi_count[2],
  3847. pdev->stats.rx.sgi_count[3]);
  3848. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3849. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3850. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3851. DP_PRINT_STATS("Reception Type ="
  3852. " SU: %d,"
  3853. " MU_MIMO:%d,"
  3854. " MU_OFDMA:%d,"
  3855. " MU_OFDMA_MIMO:%d\n",
  3856. pdev->stats.rx.reception_type[0],
  3857. pdev->stats.rx.reception_type[1],
  3858. pdev->stats.rx.reception_type[2],
  3859. pdev->stats.rx.reception_type[3]);
  3860. DP_PRINT_STATS("Aggregation:\n");
  3861. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3862. pdev->stats.rx.ampdu_cnt);
  3863. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3864. pdev->stats.rx.non_ampdu_cnt);
  3865. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3866. pdev->stats.rx.amsdu_cnt);
  3867. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3868. pdev->stats.rx.non_amsdu_cnt);
  3869. }
  3870. /**
  3871. * dp_print_tx_rates(): Print tx rates
  3872. * @vdev: DP_VDEV handle
  3873. *
  3874. * Return:void
  3875. */
  3876. static inline void
  3877. dp_print_tx_rates(struct dp_vdev *vdev)
  3878. {
  3879. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3880. uint8_t mcs, pkt_type;
  3881. uint32_t index;
  3882. DP_PRINT_STATS("Tx Rate Info:\n");
  3883. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3884. index = 0;
  3885. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3886. if (!dp_rate_string[pkt_type][mcs].valid)
  3887. continue;
  3888. DP_PRINT_STATS(" %s = %d",
  3889. dp_rate_string[pkt_type][mcs].mcs_type,
  3890. pdev->stats.tx.pkt_type[pkt_type].
  3891. mcs_count[mcs]);
  3892. }
  3893. DP_PRINT_STATS("\n");
  3894. }
  3895. DP_PRINT_STATS("SGI ="
  3896. " 0.8us %d"
  3897. " 0.4us %d"
  3898. " 1.6us %d"
  3899. " 3.2us %d",
  3900. pdev->stats.tx.sgi_count[0],
  3901. pdev->stats.tx.sgi_count[1],
  3902. pdev->stats.tx.sgi_count[2],
  3903. pdev->stats.tx.sgi_count[3]);
  3904. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3905. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3906. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3907. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3908. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3909. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3910. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3911. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3912. DP_PRINT_STATS("Aggregation:\n");
  3913. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3914. pdev->stats.tx.amsdu_cnt);
  3915. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3916. pdev->stats.tx.non_amsdu_cnt);
  3917. }
  3918. /**
  3919. * dp_print_peer_stats():print peer stats
  3920. * @peer: DP_PEER handle
  3921. *
  3922. * return void
  3923. */
  3924. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3925. {
  3926. uint8_t i, mcs, pkt_type;
  3927. uint32_t index;
  3928. char nss[DP_NSS_LENGTH];
  3929. DP_PRINT_STATS("Node Tx Stats:\n");
  3930. DP_PRINT_STATS("Total Packet Completions = %d",
  3931. peer->stats.tx.comp_pkt.num);
  3932. DP_PRINT_STATS("Total Bytes Completions = %d",
  3933. peer->stats.tx.comp_pkt.bytes);
  3934. DP_PRINT_STATS("Success Packets = %d",
  3935. peer->stats.tx.tx_success.num);
  3936. DP_PRINT_STATS("Success Bytes = %d",
  3937. peer->stats.tx.tx_success.bytes);
  3938. DP_PRINT_STATS("Packets Failed = %d",
  3939. peer->stats.tx.tx_failed);
  3940. DP_PRINT_STATS("Packets In OFDMA = %d",
  3941. peer->stats.tx.ofdma);
  3942. DP_PRINT_STATS("Packets In STBC = %d",
  3943. peer->stats.tx.stbc);
  3944. DP_PRINT_STATS("Packets In LDPC = %d",
  3945. peer->stats.tx.ldpc);
  3946. DP_PRINT_STATS("Packet Retries = %d",
  3947. peer->stats.tx.retries);
  3948. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3949. peer->stats.tx.amsdu_cnt);
  3950. DP_PRINT_STATS("Last Packet RSSI = %d",
  3951. peer->stats.tx.last_ack_rssi);
  3952. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3953. peer->stats.tx.dropped.fw_rem);
  3954. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3955. peer->stats.tx.dropped.fw_rem_tx);
  3956. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3957. peer->stats.tx.dropped.fw_rem_notx);
  3958. DP_PRINT_STATS("Dropped : Age Out = %d",
  3959. peer->stats.tx.dropped.age_out);
  3960. DP_PRINT_STATS("Rate Info:");
  3961. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3962. index = 0;
  3963. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3964. if (!dp_rate_string[pkt_type][mcs].valid)
  3965. continue;
  3966. DP_PRINT_STATS(" %s = %d",
  3967. dp_rate_string[pkt_type][mcs].mcs_type,
  3968. peer->stats.tx.pkt_type[pkt_type].
  3969. mcs_count[mcs]);
  3970. }
  3971. DP_PRINT_STATS("\n");
  3972. }
  3973. DP_PRINT_STATS("SGI = "
  3974. " 0.8us %d"
  3975. " 0.4us %d"
  3976. " 1.6us %d"
  3977. " 3.2us %d",
  3978. peer->stats.tx.sgi_count[0],
  3979. peer->stats.tx.sgi_count[1],
  3980. peer->stats.tx.sgi_count[2],
  3981. peer->stats.tx.sgi_count[3]);
  3982. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3983. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3984. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3985. DP_PRINT_STATS("Aggregation:");
  3986. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3987. peer->stats.tx.amsdu_cnt);
  3988. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3989. peer->stats.tx.non_amsdu_cnt);
  3990. DP_PRINT_STATS("Node Rx Stats:");
  3991. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3992. peer->stats.rx.to_stack.num);
  3993. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3994. peer->stats.rx.to_stack.bytes);
  3995. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3996. DP_PRINT_STATS("Packets Received = %d",
  3997. peer->stats.rx.rcvd_reo[i].num);
  3998. DP_PRINT_STATS("Bytes Received = %d",
  3999. peer->stats.rx.rcvd_reo[i].bytes);
  4000. }
  4001. DP_PRINT_STATS("Multicast Packets Received = %d",
  4002. peer->stats.rx.multicast.num);
  4003. DP_PRINT_STATS("Multicast Bytes Received = %d",
  4004. peer->stats.rx.multicast.bytes);
  4005. DP_PRINT_STATS("WDS Packets Received = %d",
  4006. peer->stats.rx.wds.num);
  4007. DP_PRINT_STATS("WDS Bytes Received = %d",
  4008. peer->stats.rx.wds.bytes);
  4009. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  4010. peer->stats.rx.intra_bss.pkts.num);
  4011. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  4012. peer->stats.rx.intra_bss.pkts.bytes);
  4013. DP_PRINT_STATS("Raw Packets Received = %d",
  4014. peer->stats.rx.raw.num);
  4015. DP_PRINT_STATS("Raw Bytes Received = %d",
  4016. peer->stats.rx.raw.bytes);
  4017. DP_PRINT_STATS("Errors: MIC Errors = %d",
  4018. peer->stats.rx.err.mic_err);
  4019. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  4020. peer->stats.rx.err.decrypt_err);
  4021. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  4022. peer->stats.rx.non_ampdu_cnt);
  4023. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  4024. peer->stats.rx.ampdu_cnt);
  4025. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  4026. peer->stats.rx.non_amsdu_cnt);
  4027. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  4028. peer->stats.rx.amsdu_cnt);
  4029. DP_PRINT_STATS("SGI ="
  4030. " 0.8us %d"
  4031. " 0.4us %d"
  4032. " 1.6us %d"
  4033. " 3.2us %d",
  4034. peer->stats.rx.sgi_count[0],
  4035. peer->stats.rx.sgi_count[1],
  4036. peer->stats.rx.sgi_count[2],
  4037. peer->stats.rx.sgi_count[3]);
  4038. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  4039. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  4040. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  4041. DP_PRINT_STATS("Reception Type ="
  4042. " SU %d,"
  4043. " MU_MIMO %d,"
  4044. " MU_OFDMA %d,"
  4045. " MU_OFDMA_MIMO %d",
  4046. peer->stats.rx.reception_type[0],
  4047. peer->stats.rx.reception_type[1],
  4048. peer->stats.rx.reception_type[2],
  4049. peer->stats.rx.reception_type[3]);
  4050. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  4051. index = 0;
  4052. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  4053. if (!dp_rate_string[pkt_type][mcs].valid)
  4054. continue;
  4055. DP_PRINT_STATS(" %s = %d",
  4056. dp_rate_string[pkt_type][mcs].mcs_type,
  4057. peer->stats.rx.pkt_type[pkt_type].
  4058. mcs_count[mcs]);
  4059. }
  4060. DP_PRINT_STATS("\n");
  4061. }
  4062. index = 0;
  4063. for (i = 0; i < SS_COUNT; i++) {
  4064. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  4065. " %d", peer->stats.rx.nss[i]);
  4066. }
  4067. DP_PRINT_STATS("NSS(0-7) = %s",
  4068. nss);
  4069. DP_PRINT_STATS("Aggregation:");
  4070. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  4071. peer->stats.rx.ampdu_cnt);
  4072. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  4073. peer->stats.rx.non_ampdu_cnt);
  4074. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  4075. peer->stats.rx.amsdu_cnt);
  4076. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  4077. peer->stats.rx.non_amsdu_cnt);
  4078. }
  4079. /**
  4080. * dp_print_host_stats()- Function to print the stats aggregated at host
  4081. * @vdev_handle: DP_VDEV handle
  4082. * @type: host stats type
  4083. *
  4084. * Available Stat types
  4085. * TXRX_CLEAR_STATS : Clear the stats
  4086. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  4087. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  4088. * TXRX_TX_HOST_STATS: Print Tx Stats
  4089. * TXRX_RX_HOST_STATS: Print Rx Stats
  4090. * TXRX_AST_STATS: Print AST Stats
  4091. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  4092. *
  4093. * Return: 0 on success, print error message in case of failure
  4094. */
  4095. static int
  4096. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  4097. {
  4098. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4099. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  4100. dp_aggregate_pdev_stats(pdev);
  4101. switch (type) {
  4102. case TXRX_CLEAR_STATS:
  4103. dp_txrx_host_stats_clr(vdev);
  4104. break;
  4105. case TXRX_RX_RATE_STATS:
  4106. dp_print_rx_rates(vdev);
  4107. break;
  4108. case TXRX_TX_RATE_STATS:
  4109. dp_print_tx_rates(vdev);
  4110. break;
  4111. case TXRX_TX_HOST_STATS:
  4112. dp_print_pdev_tx_stats(pdev);
  4113. dp_print_soc_tx_stats(pdev->soc);
  4114. break;
  4115. case TXRX_RX_HOST_STATS:
  4116. dp_print_pdev_rx_stats(pdev);
  4117. dp_print_soc_rx_stats(pdev->soc);
  4118. break;
  4119. case TXRX_AST_STATS:
  4120. dp_print_ast_stats(pdev->soc);
  4121. break;
  4122. case TXRX_SRNG_PTR_STATS:
  4123. dp_print_ring_stats(pdev);
  4124. break;
  4125. default:
  4126. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  4127. break;
  4128. }
  4129. return 0;
  4130. }
  4131. /*
  4132. * dp_get_host_peer_stats()- function to print peer stats
  4133. * @pdev_handle: DP_PDEV handle
  4134. * @mac_addr: mac address of the peer
  4135. *
  4136. * Return: void
  4137. */
  4138. static void
  4139. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  4140. {
  4141. struct dp_peer *peer;
  4142. uint8_t local_id;
  4143. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4144. &local_id);
  4145. if (!peer) {
  4146. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4147. "%s: Invalid peer\n", __func__);
  4148. return;
  4149. }
  4150. dp_print_peer_stats(peer);
  4151. dp_peer_rxtid_stats(peer, dp_rx_tid_stats_cb, NULL);
  4152. return;
  4153. }
  4154. /*
  4155. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4156. * @pdev: DP_PDEV handle
  4157. *
  4158. * Return: void
  4159. */
  4160. static void
  4161. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4162. {
  4163. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4164. htt_tlv_filter.mpdu_start = 0;
  4165. htt_tlv_filter.msdu_start = 0;
  4166. htt_tlv_filter.packet = 0;
  4167. htt_tlv_filter.msdu_end = 0;
  4168. htt_tlv_filter.mpdu_end = 0;
  4169. htt_tlv_filter.packet_header = 1;
  4170. htt_tlv_filter.attention = 1;
  4171. htt_tlv_filter.ppdu_start = 1;
  4172. htt_tlv_filter.ppdu_end = 1;
  4173. htt_tlv_filter.ppdu_end_user_stats = 1;
  4174. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4175. htt_tlv_filter.ppdu_end_status_done = 1;
  4176. htt_tlv_filter.enable_fp = 1;
  4177. htt_tlv_filter.enable_md = 0;
  4178. htt_tlv_filter.enable_mo = 0;
  4179. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4180. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4181. RX_BUFFER_SIZE, &htt_tlv_filter);
  4182. }
  4183. /*
  4184. * dp_config_tx_capture()- API to enable/disable tx capture
  4185. * @pdev_handle: DP_PDEV handle
  4186. * @val: user provided value
  4187. *
  4188. * Return: void
  4189. */
  4190. static void
  4191. dp_config_tx_capture(struct cdp_pdev *pdev_handle, int val)
  4192. {
  4193. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4194. if (val) {
  4195. pdev->tx_sniffer_enable = 1;
  4196. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4197. } else {
  4198. pdev->tx_sniffer_enable = 0;
  4199. if (!pdev->enhanced_stats_en)
  4200. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4201. }
  4202. }
  4203. /*
  4204. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4205. * @pdev_handle: DP_PDEV handle
  4206. *
  4207. * Return: void
  4208. */
  4209. static void
  4210. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4211. {
  4212. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4213. pdev->enhanced_stats_en = 1;
  4214. dp_ppdu_ring_cfg(pdev);
  4215. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4216. }
  4217. /*
  4218. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4219. * @pdev_handle: DP_PDEV handle
  4220. *
  4221. * Return: void
  4222. */
  4223. static void
  4224. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4225. {
  4226. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4227. pdev->enhanced_stats_en = 0;
  4228. if (!pdev->tx_sniffer_enable)
  4229. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4230. }
  4231. /*
  4232. * dp_get_fw_peer_stats()- function to print peer stats
  4233. * @pdev_handle: DP_PDEV handle
  4234. * @mac_addr: mac address of the peer
  4235. * @cap: Type of htt stats requested
  4236. *
  4237. * Currently Supporting only MAC ID based requests Only
  4238. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4239. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4240. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4241. *
  4242. * Return: void
  4243. */
  4244. static void
  4245. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4246. uint32_t cap)
  4247. {
  4248. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4249. uint32_t config_param0 = 0;
  4250. uint32_t config_param1 = 0;
  4251. uint32_t config_param2 = 0;
  4252. uint32_t config_param3 = 0;
  4253. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4254. config_param0 |= (1 << (cap + 1));
  4255. config_param1 = 0x8f;
  4256. config_param2 |= (mac_addr[0] & 0x000000ff);
  4257. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4258. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4259. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4260. config_param3 |= (mac_addr[4] & 0x000000ff);
  4261. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4262. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4263. config_param0, config_param1, config_param2,
  4264. config_param3);
  4265. }
  4266. /*
  4267. * dp_set_pdev_param: function to set parameters in pdev
  4268. * @pdev_handle: DP pdev handle
  4269. * @param: parameter type to be set
  4270. * @val: value of parameter to be set
  4271. *
  4272. * return: void
  4273. */
  4274. static void dp_set_pdev_param(struct cdp_pdev *pdev_handle,
  4275. enum cdp_pdev_param_type param, uint8_t val)
  4276. {
  4277. switch (param) {
  4278. case CDP_CONFIG_TX_CAPTURE:
  4279. dp_config_tx_capture(pdev_handle, val);
  4280. break;
  4281. default:
  4282. break;
  4283. }
  4284. }
  4285. /*
  4286. * dp_set_vdev_param: function to set parameters in vdev
  4287. * @param: parameter type to be set
  4288. * @val: value of parameter to be set
  4289. *
  4290. * return: void
  4291. */
  4292. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4293. enum cdp_vdev_param_type param, uint32_t val)
  4294. {
  4295. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4296. switch (param) {
  4297. case CDP_ENABLE_WDS:
  4298. vdev->wds_enabled = val;
  4299. break;
  4300. case CDP_ENABLE_NAWDS:
  4301. vdev->nawds_enabled = val;
  4302. break;
  4303. case CDP_ENABLE_MCAST_EN:
  4304. vdev->mcast_enhancement_en = val;
  4305. break;
  4306. case CDP_ENABLE_PROXYSTA:
  4307. vdev->proxysta_vdev = val;
  4308. break;
  4309. case CDP_UPDATE_TDLS_FLAGS:
  4310. vdev->tdls_link_connected = val;
  4311. break;
  4312. case CDP_CFG_WDS_AGING_TIMER:
  4313. if (val == 0)
  4314. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4315. else if (val != vdev->wds_aging_timer_val)
  4316. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4317. vdev->wds_aging_timer_val = val;
  4318. break;
  4319. case CDP_ENABLE_AP_BRIDGE:
  4320. if (wlan_op_mode_sta != vdev->opmode)
  4321. vdev->ap_bridge_enabled = val;
  4322. else
  4323. vdev->ap_bridge_enabled = false;
  4324. break;
  4325. default:
  4326. break;
  4327. }
  4328. dp_tx_vdev_update_search_flags(vdev);
  4329. }
  4330. /**
  4331. * dp_peer_set_nawds: set nawds bit in peer
  4332. * @peer_handle: pointer to peer
  4333. * @value: enable/disable nawds
  4334. *
  4335. * return: void
  4336. */
  4337. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4338. {
  4339. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4340. peer->nawds_enabled = value;
  4341. }
  4342. /*
  4343. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4344. * @vdev_handle: DP_VDEV handle
  4345. * @map_id:ID of map that needs to be updated
  4346. *
  4347. * Return: void
  4348. */
  4349. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4350. uint8_t map_id)
  4351. {
  4352. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4353. vdev->dscp_tid_map_id = map_id;
  4354. return;
  4355. }
  4356. /**
  4357. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4358. * @pdev: DP_PDEV handle
  4359. * @map_id: ID of map that needs to be updated
  4360. * @tos: index value in map
  4361. * @tid: tid value passed by the user
  4362. *
  4363. * Return: void
  4364. */
  4365. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4366. uint8_t map_id, uint8_t tos, uint8_t tid)
  4367. {
  4368. uint8_t dscp;
  4369. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4370. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4371. pdev->dscp_tid_map[map_id][dscp] = tid;
  4372. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4373. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4374. map_id, dscp);
  4375. return;
  4376. }
  4377. /**
  4378. * dp_fw_stats_process(): Process TxRX FW stats request
  4379. * @vdev_handle: DP VDEV handle
  4380. * @val: value passed by user
  4381. *
  4382. * return: int
  4383. */
  4384. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4385. {
  4386. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4387. struct dp_pdev *pdev = NULL;
  4388. if (!vdev) {
  4389. DP_TRACE(NONE, "VDEV not found");
  4390. return 1;
  4391. }
  4392. pdev = vdev->pdev;
  4393. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4394. }
  4395. /*
  4396. * dp_txrx_stats() - function to map to firmware and host stats
  4397. * @vdev: virtual handle
  4398. * @stats: type of statistics requested
  4399. *
  4400. * Return: integer
  4401. */
  4402. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4403. {
  4404. int host_stats;
  4405. int fw_stats;
  4406. if (stats >= CDP_TXRX_MAX_STATS)
  4407. return 0;
  4408. /*
  4409. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4410. * has to be updated if new FW HTT stats added
  4411. */
  4412. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4413. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4414. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4415. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4416. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4417. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4418. stats, fw_stats, host_stats);
  4419. if (fw_stats != TXRX_FW_STATS_INVALID)
  4420. return dp_fw_stats_process(vdev, fw_stats);
  4421. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4422. (host_stats <= TXRX_HOST_STATS_MAX))
  4423. return dp_print_host_stats(vdev, host_stats);
  4424. else
  4425. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4426. "Wrong Input for TxRx Stats");
  4427. return 0;
  4428. }
  4429. /*
  4430. * dp_print_napi_stats(): NAPI stats
  4431. * @soc - soc handle
  4432. */
  4433. static void dp_print_napi_stats(struct dp_soc *soc)
  4434. {
  4435. hif_print_napi_stats(soc->hif_handle);
  4436. }
  4437. /*
  4438. * dp_print_per_ring_stats(): Packet count per ring
  4439. * @soc - soc handle
  4440. */
  4441. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4442. {
  4443. uint8_t core, ring;
  4444. uint64_t total_packets;
  4445. DP_TRACE(FATAL, "Reo packets per ring:");
  4446. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4447. total_packets = 0;
  4448. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4449. for (core = 0; core < NR_CPUS; core++) {
  4450. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4451. core, soc->stats.rx.ring_packets[core][ring]);
  4452. total_packets += soc->stats.rx.ring_packets[core][ring];
  4453. }
  4454. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4455. ring, total_packets);
  4456. }
  4457. }
  4458. /*
  4459. * dp_txrx_path_stats() - Function to display dump stats
  4460. * @soc - soc handle
  4461. *
  4462. * return: none
  4463. */
  4464. static void dp_txrx_path_stats(struct dp_soc *soc)
  4465. {
  4466. uint8_t error_code;
  4467. uint8_t loop_pdev;
  4468. struct dp_pdev *pdev;
  4469. uint8_t i;
  4470. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4471. pdev = soc->pdev_list[loop_pdev];
  4472. dp_aggregate_pdev_stats(pdev);
  4473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4474. "Tx path Statistics:");
  4475. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4476. pdev->stats.tx_i.rcvd.num,
  4477. pdev->stats.tx_i.rcvd.bytes);
  4478. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4479. pdev->stats.tx_i.processed.num,
  4480. pdev->stats.tx_i.processed.bytes);
  4481. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4482. pdev->stats.tx.tx_success.num,
  4483. pdev->stats.tx.tx_success.bytes);
  4484. DP_TRACE(FATAL, "Dropped in host:");
  4485. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4486. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4487. DP_TRACE(FATAL, "Descriptor not available: %u",
  4488. pdev->stats.tx_i.dropped.desc_na);
  4489. DP_TRACE(FATAL, "Ring full: %u",
  4490. pdev->stats.tx_i.dropped.ring_full);
  4491. DP_TRACE(FATAL, "Enqueue fail: %u",
  4492. pdev->stats.tx_i.dropped.enqueue_fail);
  4493. DP_TRACE(FATAL, "DMA Error: %u",
  4494. pdev->stats.tx_i.dropped.dma_error);
  4495. DP_TRACE(FATAL, "Dropped in hardware:");
  4496. DP_TRACE(FATAL, "total packets dropped: %u",
  4497. pdev->stats.tx.tx_failed);
  4498. DP_TRACE(FATAL, "mpdu age out: %u",
  4499. pdev->stats.tx.dropped.age_out);
  4500. DP_TRACE(FATAL, "firmware removed: %u",
  4501. pdev->stats.tx.dropped.fw_rem);
  4502. DP_TRACE(FATAL, "firmware removed tx: %u",
  4503. pdev->stats.tx.dropped.fw_rem_tx);
  4504. DP_TRACE(FATAL, "firmware removed notx %u",
  4505. pdev->stats.tx.dropped.fw_rem_notx);
  4506. DP_TRACE(FATAL, "peer_invalid: %u",
  4507. pdev->soc->stats.tx.tx_invalid_peer.num);
  4508. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4509. DP_TRACE(FATAL, "Single Packet: %u",
  4510. pdev->stats.tx_comp_histogram.pkts_1);
  4511. DP_TRACE(FATAL, "2-20 Packets: %u",
  4512. pdev->stats.tx_comp_histogram.pkts_2_20);
  4513. DP_TRACE(FATAL, "21-40 Packets: %u",
  4514. pdev->stats.tx_comp_histogram.pkts_21_40);
  4515. DP_TRACE(FATAL, "41-60 Packets: %u",
  4516. pdev->stats.tx_comp_histogram.pkts_41_60);
  4517. DP_TRACE(FATAL, "61-80 Packets: %u",
  4518. pdev->stats.tx_comp_histogram.pkts_61_80);
  4519. DP_TRACE(FATAL, "81-100 Packets: %u",
  4520. pdev->stats.tx_comp_histogram.pkts_81_100);
  4521. DP_TRACE(FATAL, "101-200 Packets: %u",
  4522. pdev->stats.tx_comp_histogram.pkts_101_200);
  4523. DP_TRACE(FATAL, " 201+ Packets: %u",
  4524. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4525. DP_TRACE(FATAL, "Rx path statistics");
  4526. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4527. pdev->stats.rx.to_stack.num,
  4528. pdev->stats.rx.to_stack.bytes);
  4529. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4530. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4531. i, pdev->stats.rx.rcvd_reo[i].num,
  4532. pdev->stats.rx.rcvd_reo[i].bytes);
  4533. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4534. pdev->stats.rx.intra_bss.pkts.num,
  4535. pdev->stats.rx.intra_bss.pkts.bytes);
  4536. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4537. pdev->stats.rx.intra_bss.fail.num,
  4538. pdev->stats.rx.intra_bss.fail.bytes);
  4539. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4540. pdev->stats.rx.raw.num,
  4541. pdev->stats.rx.raw.bytes);
  4542. DP_TRACE(FATAL, "dropped: error %u msdus",
  4543. pdev->stats.rx.err.mic_err);
  4544. DP_TRACE(FATAL, "peer invalid %u",
  4545. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4546. DP_TRACE(FATAL, "Reo Statistics");
  4547. DP_TRACE(FATAL, "rbm error: %u msdus",
  4548. pdev->soc->stats.rx.err.invalid_rbm);
  4549. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4550. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4551. DP_TRACE(FATAL, "Reo errors");
  4552. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4553. error_code++) {
  4554. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4555. error_code,
  4556. pdev->soc->stats.rx.err.reo_error[error_code]);
  4557. }
  4558. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4559. error_code++) {
  4560. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4561. error_code,
  4562. pdev->soc->stats.rx.err
  4563. .rxdma_error[error_code]);
  4564. }
  4565. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4566. DP_TRACE(FATAL, "Single Packet: %u",
  4567. pdev->stats.rx_ind_histogram.pkts_1);
  4568. DP_TRACE(FATAL, "2-20 Packets: %u",
  4569. pdev->stats.rx_ind_histogram.pkts_2_20);
  4570. DP_TRACE(FATAL, "21-40 Packets: %u",
  4571. pdev->stats.rx_ind_histogram.pkts_21_40);
  4572. DP_TRACE(FATAL, "41-60 Packets: %u",
  4573. pdev->stats.rx_ind_histogram.pkts_41_60);
  4574. DP_TRACE(FATAL, "61-80 Packets: %u",
  4575. pdev->stats.rx_ind_histogram.pkts_61_80);
  4576. DP_TRACE(FATAL, "81-100 Packets: %u",
  4577. pdev->stats.rx_ind_histogram.pkts_81_100);
  4578. DP_TRACE(FATAL, "101-200 Packets: %u",
  4579. pdev->stats.rx_ind_histogram.pkts_101_200);
  4580. DP_TRACE(FATAL, " 201+ Packets: %u",
  4581. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4582. DP_TRACE_STATS(ERROR, "%s: tso_enable: %u lro_enable: %u rx_hash: %u napi_enable: %u",
  4583. __func__,
  4584. pdev->soc->wlan_cfg_ctx->tso_enabled,
  4585. pdev->soc->wlan_cfg_ctx->lro_enabled,
  4586. pdev->soc->wlan_cfg_ctx->rx_hash,
  4587. pdev->soc->wlan_cfg_ctx->napi_enabled);
  4588. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4589. DP_TRACE_STATS(ERROR, "%s: Tx flow stop queue: %u tx flow start queue offset: %u",
  4590. __func__,
  4591. pdev->soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold,
  4592. pdev->soc->wlan_cfg_ctx->tx_flow_start_queue_offset);
  4593. #endif
  4594. }
  4595. }
  4596. /*
  4597. * dp_txrx_dump_stats() - Dump statistics
  4598. * @value - Statistics option
  4599. */
  4600. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4601. {
  4602. struct dp_soc *soc =
  4603. (struct dp_soc *)psoc;
  4604. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4605. if (!soc) {
  4606. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4607. "%s: soc is NULL", __func__);
  4608. return QDF_STATUS_E_INVAL;
  4609. }
  4610. switch (value) {
  4611. case CDP_TXRX_PATH_STATS:
  4612. dp_txrx_path_stats(soc);
  4613. break;
  4614. case CDP_RX_RING_STATS:
  4615. dp_print_per_ring_stats(soc);
  4616. break;
  4617. case CDP_TXRX_TSO_STATS:
  4618. /* TODO: NOT IMPLEMENTED */
  4619. break;
  4620. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4621. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4622. break;
  4623. case CDP_DP_NAPI_STATS:
  4624. dp_print_napi_stats(soc);
  4625. break;
  4626. case CDP_TXRX_DESC_STATS:
  4627. /* TODO: NOT IMPLEMENTED */
  4628. break;
  4629. default:
  4630. status = QDF_STATUS_E_INVAL;
  4631. break;
  4632. }
  4633. return status;
  4634. }
  4635. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4636. /**
  4637. * dp_update_flow_control_parameters() - API to store datapath
  4638. * config parameters
  4639. * @soc: soc handle
  4640. * @cfg: ini parameter handle
  4641. *
  4642. * Return: void
  4643. */
  4644. static inline
  4645. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4646. struct cdp_config_params *params)
  4647. {
  4648. soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold =
  4649. params->tx_flow_stop_queue_threshold;
  4650. soc->wlan_cfg_ctx->tx_flow_start_queue_offset =
  4651. params->tx_flow_start_queue_offset;
  4652. }
  4653. #else
  4654. static inline
  4655. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4656. struct cdp_config_params *params)
  4657. {
  4658. }
  4659. #endif
  4660. /**
  4661. * dp_update_config_parameters() - API to store datapath
  4662. * config parameters
  4663. * @soc: soc handle
  4664. * @cfg: ini parameter handle
  4665. *
  4666. * Return: status
  4667. */
  4668. static
  4669. QDF_STATUS dp_update_config_parameters(struct cdp_soc *psoc,
  4670. struct cdp_config_params *params)
  4671. {
  4672. struct dp_soc *soc = (struct dp_soc *)psoc;
  4673. if (!(soc)) {
  4674. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4675. "%s: Invalid handle", __func__);
  4676. return QDF_STATUS_E_INVAL;
  4677. }
  4678. soc->wlan_cfg_ctx->tso_enabled = params->tso_enable;
  4679. soc->wlan_cfg_ctx->lro_enabled = params->lro_enable;
  4680. soc->wlan_cfg_ctx->rx_hash = params->flow_steering_enable;
  4681. soc->wlan_cfg_ctx->tcp_udp_checksumoffload =
  4682. params->tcp_udp_checksumoffload;
  4683. soc->wlan_cfg_ctx->napi_enabled = params->napi_enable;
  4684. dp_update_flow_control_parameters(soc, params);
  4685. return QDF_STATUS_SUCCESS;
  4686. }
  4687. static struct cdp_wds_ops dp_ops_wds = {
  4688. .vdev_set_wds = dp_vdev_set_wds,
  4689. };
  4690. /*
  4691. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4692. * @soc - datapath soc handle
  4693. * @peer - datapath peer handle
  4694. *
  4695. * Delete the AST entries belonging to a peer
  4696. */
  4697. #ifdef FEATURE_WDS
  4698. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4699. struct dp_peer *peer)
  4700. {
  4701. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4702. qdf_spin_lock_bh(&soc->ast_lock);
  4703. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4704. if (ast_entry->next_hop) {
  4705. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4706. peer->vdev->pdev->osif_pdev,
  4707. ast_entry->mac_addr.raw);
  4708. }
  4709. dp_peer_del_ast(soc, ast_entry);
  4710. }
  4711. qdf_spin_unlock_bh(&soc->ast_lock);
  4712. }
  4713. #else
  4714. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4715. struct dp_peer *peer)
  4716. {
  4717. }
  4718. #endif
  4719. /*
  4720. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4721. * @vdev_handle - datapath vdev handle
  4722. * @callback - callback function
  4723. * @ctxt: callback context
  4724. *
  4725. */
  4726. static void
  4727. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4728. ol_txrx_data_tx_cb callback, void *ctxt)
  4729. {
  4730. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4731. vdev->tx_non_std_data_callback.func = callback;
  4732. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4733. }
  4734. #ifdef CONFIG_WIN
  4735. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4736. {
  4737. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4738. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4739. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4740. dp_peer_delete_ast_entries(soc, peer);
  4741. }
  4742. #endif
  4743. static struct cdp_cmn_ops dp_ops_cmn = {
  4744. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4745. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4746. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4747. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4748. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4749. .txrx_peer_create = dp_peer_create_wifi3,
  4750. .txrx_peer_setup = dp_peer_setup_wifi3,
  4751. #ifdef CONFIG_WIN
  4752. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4753. #else
  4754. .txrx_peer_teardown = NULL,
  4755. #endif
  4756. .txrx_peer_delete = dp_peer_delete_wifi3,
  4757. .txrx_vdev_register = dp_vdev_register_wifi3,
  4758. .txrx_soc_detach = dp_soc_detach_wifi3,
  4759. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4760. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4761. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4762. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4763. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4764. .delba_process = dp_delba_process_wifi3,
  4765. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4766. .flush_cache_rx_queue = NULL,
  4767. /* TODO: get API's for dscp-tid need to be added*/
  4768. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4769. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4770. .txrx_stats = dp_txrx_stats,
  4771. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4772. .display_stats = dp_txrx_dump_stats,
  4773. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4774. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4775. #ifdef DP_INTR_POLL_BASED
  4776. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4777. #else
  4778. .txrx_intr_attach = dp_soc_interrupt_attach,
  4779. #endif
  4780. .txrx_intr_detach = dp_soc_interrupt_detach,
  4781. .set_pn_check = dp_set_pn_check_wifi3,
  4782. .update_config_parameters = dp_update_config_parameters,
  4783. /* TODO: Add other functions */
  4784. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4785. };
  4786. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4787. .txrx_peer_authorize = dp_peer_authorize,
  4788. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4789. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4790. #ifdef MESH_MODE_SUPPORT
  4791. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4792. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4793. #endif
  4794. .txrx_set_vdev_param = dp_set_vdev_param,
  4795. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4796. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4797. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4798. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4799. .txrx_update_filter_neighbour_peers =
  4800. dp_update_filter_neighbour_peers,
  4801. .txrx_get_sec_type = dp_get_sec_type,
  4802. /* TODO: Add other functions */
  4803. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4804. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4805. .txrx_set_pdev_param = dp_set_pdev_param,
  4806. };
  4807. static struct cdp_me_ops dp_ops_me = {
  4808. #ifdef ATH_SUPPORT_IQUE
  4809. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4810. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4811. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4812. #endif
  4813. };
  4814. static struct cdp_mon_ops dp_ops_mon = {
  4815. .txrx_monitor_set_filter_ucast_data = NULL,
  4816. .txrx_monitor_set_filter_mcast_data = NULL,
  4817. .txrx_monitor_set_filter_non_data = NULL,
  4818. .txrx_monitor_get_filter_ucast_data = NULL,
  4819. .txrx_monitor_get_filter_mcast_data = NULL,
  4820. .txrx_monitor_get_filter_non_data = NULL,
  4821. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4822. };
  4823. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4824. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4825. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4826. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4827. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4828. /* TODO */
  4829. };
  4830. static struct cdp_raw_ops dp_ops_raw = {
  4831. /* TODO */
  4832. };
  4833. #ifdef CONFIG_WIN
  4834. static struct cdp_pflow_ops dp_ops_pflow = {
  4835. /* TODO */
  4836. };
  4837. #endif /* CONFIG_WIN */
  4838. #ifdef FEATURE_RUNTIME_PM
  4839. /**
  4840. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4841. * @opaque_pdev: DP pdev context
  4842. *
  4843. * DP is ready to runtime suspend if there are no pending TX packets.
  4844. *
  4845. * Return: QDF_STATUS
  4846. */
  4847. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4848. {
  4849. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4850. struct dp_soc *soc = pdev->soc;
  4851. /* Call DP TX flow control API to check if there is any
  4852. pending packets */
  4853. if (soc->intr_mode == DP_INTR_POLL)
  4854. qdf_timer_stop(&soc->int_timer);
  4855. return QDF_STATUS_SUCCESS;
  4856. }
  4857. /**
  4858. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4859. * @opaque_pdev: DP pdev context
  4860. *
  4861. * Resume DP for runtime PM.
  4862. *
  4863. * Return: QDF_STATUS
  4864. */
  4865. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4866. {
  4867. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4868. struct dp_soc *soc = pdev->soc;
  4869. void *hal_srng;
  4870. int i;
  4871. if (soc->intr_mode == DP_INTR_POLL)
  4872. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4873. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4874. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4875. if (hal_srng) {
  4876. /* We actually only need to acquire the lock */
  4877. hal_srng_access_start(soc->hal_soc, hal_srng);
  4878. /* Update SRC ring head pointer for HW to send
  4879. all pending packets */
  4880. hal_srng_access_end(soc->hal_soc, hal_srng);
  4881. }
  4882. }
  4883. return QDF_STATUS_SUCCESS;
  4884. }
  4885. #endif /* FEATURE_RUNTIME_PM */
  4886. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4887. {
  4888. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4889. struct dp_soc *soc = pdev->soc;
  4890. if (soc->intr_mode == DP_INTR_POLL)
  4891. qdf_timer_stop(&soc->int_timer);
  4892. return QDF_STATUS_SUCCESS;
  4893. }
  4894. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4895. {
  4896. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4897. struct dp_soc *soc = pdev->soc;
  4898. if (soc->intr_mode == DP_INTR_POLL)
  4899. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4900. return QDF_STATUS_SUCCESS;
  4901. }
  4902. #ifndef CONFIG_WIN
  4903. static struct cdp_misc_ops dp_ops_misc = {
  4904. .tx_non_std = dp_tx_non_std,
  4905. .get_opmode = dp_get_opmode,
  4906. #ifdef FEATURE_RUNTIME_PM
  4907. .runtime_suspend = dp_runtime_suspend,
  4908. .runtime_resume = dp_runtime_resume,
  4909. #endif /* FEATURE_RUNTIME_PM */
  4910. };
  4911. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4912. /* WIFI 3.0 DP implement as required. */
  4913. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4914. .register_pause_cb = dp_txrx_register_pause_cb,
  4915. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4916. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4917. };
  4918. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4919. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4920. };
  4921. #ifdef IPA_OFFLOAD
  4922. static struct cdp_ipa_ops dp_ops_ipa = {
  4923. .ipa_get_resource = dp_ipa_get_resource,
  4924. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4925. .ipa_op_response = dp_ipa_op_response,
  4926. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4927. .ipa_get_stat = dp_ipa_get_stat,
  4928. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4929. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4930. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4931. .ipa_setup = dp_ipa_setup,
  4932. .ipa_cleanup = dp_ipa_cleanup,
  4933. .ipa_setup_iface = dp_ipa_setup_iface,
  4934. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4935. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4936. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4937. .ipa_set_perf_level = dp_ipa_set_perf_level
  4938. };
  4939. #endif
  4940. static struct cdp_bus_ops dp_ops_bus = {
  4941. .bus_suspend = dp_bus_suspend,
  4942. .bus_resume = dp_bus_resume
  4943. };
  4944. static struct cdp_ocb_ops dp_ops_ocb = {
  4945. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4946. };
  4947. static struct cdp_throttle_ops dp_ops_throttle = {
  4948. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4949. };
  4950. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4951. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4952. };
  4953. static struct cdp_cfg_ops dp_ops_cfg = {
  4954. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4955. };
  4956. static struct cdp_peer_ops dp_ops_peer = {
  4957. .register_peer = dp_register_peer,
  4958. .clear_peer = dp_clear_peer,
  4959. .find_peer_by_addr = dp_find_peer_by_addr,
  4960. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4961. .local_peer_id = dp_local_peer_id,
  4962. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4963. .peer_state_update = dp_peer_state_update,
  4964. .get_vdevid = dp_get_vdevid,
  4965. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4966. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4967. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4968. .get_peer_state = dp_get_peer_state,
  4969. .last_assoc_received = dp_get_last_assoc_received,
  4970. .last_disassoc_received = dp_get_last_disassoc_received,
  4971. .last_deauth_received = dp_get_last_deauth_received,
  4972. };
  4973. #endif
  4974. static struct cdp_ops dp_txrx_ops = {
  4975. .cmn_drv_ops = &dp_ops_cmn,
  4976. .ctrl_ops = &dp_ops_ctrl,
  4977. .me_ops = &dp_ops_me,
  4978. .mon_ops = &dp_ops_mon,
  4979. .host_stats_ops = &dp_ops_host_stats,
  4980. .wds_ops = &dp_ops_wds,
  4981. .raw_ops = &dp_ops_raw,
  4982. #ifdef CONFIG_WIN
  4983. .pflow_ops = &dp_ops_pflow,
  4984. #endif /* CONFIG_WIN */
  4985. #ifndef CONFIG_WIN
  4986. .misc_ops = &dp_ops_misc,
  4987. .cfg_ops = &dp_ops_cfg,
  4988. .flowctl_ops = &dp_ops_flowctl,
  4989. .l_flowctl_ops = &dp_ops_l_flowctl,
  4990. #ifdef IPA_OFFLOAD
  4991. .ipa_ops = &dp_ops_ipa,
  4992. #endif
  4993. .bus_ops = &dp_ops_bus,
  4994. .ocb_ops = &dp_ops_ocb,
  4995. .peer_ops = &dp_ops_peer,
  4996. .throttle_ops = &dp_ops_throttle,
  4997. .mob_stats_ops = &dp_ops_mob_stats,
  4998. #endif
  4999. };
  5000. /*
  5001. * dp_soc_set_txrx_ring_map()
  5002. * @dp_soc: DP handler for soc
  5003. *
  5004. * Return: Void
  5005. */
  5006. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  5007. {
  5008. uint32_t i;
  5009. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  5010. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  5011. }
  5012. }
  5013. /*
  5014. * dp_soc_attach_wifi3() - Attach txrx SOC
  5015. * @osif_soc: Opaque SOC handle from OSIF/HDD
  5016. * @htc_handle: Opaque HTC handle
  5017. * @hif_handle: Opaque HIF handle
  5018. * @qdf_osdev: QDF device
  5019. *
  5020. * Return: DP SOC handle on success, NULL on failure
  5021. */
  5022. /*
  5023. * Local prototype added to temporarily address warning caused by
  5024. * -Wmissing-prototypes. A more correct solution, namely to expose
  5025. * a prototype in an appropriate header file, will come later.
  5026. */
  5027. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  5028. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  5029. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  5030. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  5031. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  5032. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  5033. {
  5034. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  5035. if (!soc) {
  5036. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5037. FL("DP SOC memory allocation failed"));
  5038. goto fail0;
  5039. }
  5040. soc->cdp_soc.ops = &dp_txrx_ops;
  5041. soc->cdp_soc.ol_ops = ol_ops;
  5042. soc->osif_soc = osif_soc;
  5043. soc->osdev = qdf_osdev;
  5044. soc->hif_handle = hif_handle;
  5045. soc->psoc = psoc;
  5046. soc->hal_soc = hif_get_hal_handle(hif_handle);
  5047. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  5048. soc->hal_soc, qdf_osdev);
  5049. if (!soc->htt_handle) {
  5050. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5051. FL("HTT attach failed"));
  5052. goto fail1;
  5053. }
  5054. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  5055. if (!soc->wlan_cfg_ctx) {
  5056. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5057. FL("wlan_cfg_soc_attach failed"));
  5058. goto fail2;
  5059. }
  5060. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  5061. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  5062. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  5063. CDP_CFG_MAX_PEER_ID);
  5064. if (ret != -EINVAL) {
  5065. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  5066. }
  5067. }
  5068. qdf_spinlock_create(&soc->peer_ref_mutex);
  5069. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  5070. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  5071. /* fill the tx/rx cpu ring map*/
  5072. dp_soc_set_txrx_ring_map(soc);
  5073. qdf_spinlock_create(&soc->htt_stats.lock);
  5074. /* initialize work queue for stats processing */
  5075. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  5076. return (void *)soc;
  5077. fail2:
  5078. htt_soc_detach(soc->htt_handle);
  5079. fail1:
  5080. qdf_mem_free(soc);
  5081. fail0:
  5082. return NULL;
  5083. }
  5084. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  5085. /*
  5086. * dp_set_pktlog_wifi3() - attach txrx vdev
  5087. * @pdev: Datapath PDEV handle
  5088. * @event: which event's notifications are being subscribed to
  5089. * @enable: WDI event subscribe or not. (True or False)
  5090. *
  5091. * Return: Success, NULL on failure
  5092. */
  5093. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  5094. bool enable)
  5095. {
  5096. struct dp_soc *soc = pdev->soc;
  5097. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  5098. if (enable) {
  5099. switch (event) {
  5100. case WDI_EVENT_RX_DESC:
  5101. if (pdev->monitor_vdev) {
  5102. /* Nothing needs to be done if monitor mode is
  5103. * enabled
  5104. */
  5105. return 0;
  5106. }
  5107. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  5108. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  5109. htt_tlv_filter.mpdu_start = 1;
  5110. htt_tlv_filter.msdu_start = 1;
  5111. htt_tlv_filter.msdu_end = 1;
  5112. htt_tlv_filter.mpdu_end = 1;
  5113. htt_tlv_filter.packet_header = 1;
  5114. htt_tlv_filter.attention = 1;
  5115. htt_tlv_filter.ppdu_start = 1;
  5116. htt_tlv_filter.ppdu_end = 1;
  5117. htt_tlv_filter.ppdu_end_user_stats = 1;
  5118. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5119. htt_tlv_filter.ppdu_end_status_done = 1;
  5120. htt_tlv_filter.enable_fp = 1;
  5121. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5122. pdev->pdev_id,
  5123. pdev->rxdma_mon_status_ring.hal_srng,
  5124. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  5125. &htt_tlv_filter);
  5126. }
  5127. break;
  5128. case WDI_EVENT_LITE_RX:
  5129. if (pdev->monitor_vdev) {
  5130. /* Nothing needs to be done if monitor mode is
  5131. * enabled
  5132. */
  5133. return 0;
  5134. }
  5135. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  5136. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  5137. htt_tlv_filter.ppdu_start = 1;
  5138. htt_tlv_filter.ppdu_end = 1;
  5139. htt_tlv_filter.ppdu_end_user_stats = 1;
  5140. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  5141. htt_tlv_filter.ppdu_end_status_done = 1;
  5142. htt_tlv_filter.enable_fp = 1;
  5143. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5144. pdev->pdev_id,
  5145. pdev->rxdma_mon_status_ring.hal_srng,
  5146. RXDMA_MONITOR_STATUS,
  5147. RX_BUFFER_SIZE_PKTLOG_LITE,
  5148. &htt_tlv_filter);
  5149. }
  5150. break;
  5151. case WDI_EVENT_LITE_T2H:
  5152. if (pdev->monitor_vdev) {
  5153. /* Nothing needs to be done if monitor mode is
  5154. * enabled
  5155. */
  5156. return 0;
  5157. }
  5158. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5159. * passing value 0xffff. Once these macros will define in htt
  5160. * header file will use proper macros
  5161. */
  5162. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  5163. break;
  5164. default:
  5165. /* Nothing needs to be done for other pktlog types */
  5166. break;
  5167. }
  5168. } else {
  5169. switch (event) {
  5170. case WDI_EVENT_RX_DESC:
  5171. case WDI_EVENT_LITE_RX:
  5172. if (pdev->monitor_vdev) {
  5173. /* Nothing needs to be done if monitor mode is
  5174. * enabled
  5175. */
  5176. return 0;
  5177. }
  5178. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  5179. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  5180. /* htt_tlv_filter is initialized to 0 */
  5181. htt_h2t_rx_ring_cfg(soc->htt_handle,
  5182. pdev->pdev_id,
  5183. pdev->rxdma_mon_status_ring.hal_srng,
  5184. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  5185. &htt_tlv_filter);
  5186. }
  5187. break;
  5188. case WDI_EVENT_LITE_T2H:
  5189. if (pdev->monitor_vdev) {
  5190. /* Nothing needs to be done if monitor mode is
  5191. * enabled
  5192. */
  5193. return 0;
  5194. }
  5195. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5196. * passing value 0. Once these macros will define in htt
  5197. * header file will use proper macros
  5198. */
  5199. dp_h2t_cfg_stats_msg_send(pdev, 0);
  5200. break;
  5201. default:
  5202. /* Nothing needs to be done for other pktlog types */
  5203. break;
  5204. }
  5205. }
  5206. return 0;
  5207. }
  5208. #endif