cam_soc_util.c 95 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of.h>
  6. #include <linux/clk.h>
  7. #include <linux/slab.h>
  8. #include <linux/gpio.h>
  9. #include <linux/of_gpio.h>
  10. #include "cam_soc_util.h"
  11. #include "cam_debug_util.h"
  12. #include "cam_cx_ipeak.h"
  13. #include "cam_mem_mgr.h"
  14. #include "cam_presil_hw_access.h"
  15. #define CAM_TO_MASK(bitn) (1 << (int)(bitn))
  16. #define CAM_IS_BIT_SET(mask, bit) ((mask) & CAM_TO_MASK(bit))
  17. #define CAM_SET_BIT(mask, bit) ((mask) |= CAM_TO_MASK(bit))
  18. #define CAM_CLEAR_BIT(mask, bit) ((mask) &= ~CAM_TO_MASK(bit))
  19. #define CAM_SS_START_PRESIL 0x08c00000
  20. #define CAM_SS_START 0x0ac00000
  21. static uint skip_mmrm_set_rate;
  22. module_param(skip_mmrm_set_rate, uint, 0644);
  23. /**
  24. * struct cam_clk_wrapper_clk: This represents an entry corresponding to a
  25. * shared clock in Clk wrapper. Clients that share
  26. * the same clock are registered to this clk entry
  27. * and set rate from them is consolidated before
  28. * setting it to clk driver.
  29. *
  30. * @list: List pointer to point to next shared clk entry
  31. * @clk_id: Clk Id of this clock
  32. * @curr_clk_rate: Current clock rate set for this clock
  33. * @client_list: List of clients registered to this shared clock entry
  34. * @num_clients: Number of registered clients
  35. * @active_clients: Number of active clients
  36. * @mmrm_client: MMRM Client handle for src clock
  37. * @soc_info: soc_info of client with which mmrm handle is created.
  38. * This is used as unique identifier for a client and mmrm
  39. * callback data. When client corresponds to this soc_info is
  40. * unregistered, need to unregister mmrm handle as well.
  41. * @is_nrt_dev: Whether this clock corresponds to NRT device
  42. * @min_clk_rate: Minimum clk rate that this clock supports
  43. **/
  44. struct cam_clk_wrapper_clk {
  45. struct list_head list;
  46. uint32_t clk_id;
  47. int64_t curr_clk_rate;
  48. struct list_head client_list;
  49. uint32_t num_clients;
  50. uint32_t active_clients;
  51. void *mmrm_handle;
  52. struct cam_hw_soc_info *soc_info;
  53. bool is_nrt_dev;
  54. int64_t min_clk_rate;
  55. };
  56. /**
  57. * struct cam_clk_wrapper_client: This represents a client (device) that wants
  58. * to share the clock with some other client.
  59. *
  60. * @list: List pointer to point to next client that share the
  61. * same clock
  62. * @soc_info: soc_info of client. This is used as unique identifier
  63. * for a client
  64. * @clk: Clk handle
  65. * @curr_clk_rate: Current clock rate set for this client
  66. **/
  67. struct cam_clk_wrapper_client {
  68. struct list_head list;
  69. struct cam_hw_soc_info *soc_info;
  70. struct clk *clk;
  71. int64_t curr_clk_rate;
  72. };
  73. static char supported_clk_info[256];
  74. static DEFINE_MUTEX(wrapper_lock);
  75. static LIST_HEAD(wrapper_clk_list);
  76. #if IS_REACHABLE(CONFIG_MSM_MMRM)
  77. bool cam_is_mmrm_supported_on_current_chip(void)
  78. {
  79. bool is_supported;
  80. is_supported = mmrm_client_check_scaling_supported(MMRM_CLIENT_CLOCK,
  81. MMRM_CLIENT_DOMAIN_CAMERA);
  82. CAM_DBG(CAM_UTIL, "is mmrm supported: %s",
  83. CAM_BOOL_TO_YESNO(is_supported));;
  84. return is_supported;
  85. }
  86. int cam_mmrm_notifier_callback(
  87. struct mmrm_client_notifier_data *notifier_data)
  88. {
  89. if (!notifier_data) {
  90. CAM_ERR(CAM_UTIL, "Invalid notifier data");
  91. return -EBADR;
  92. }
  93. if (notifier_data->cb_type == MMRM_CLIENT_RESOURCE_VALUE_CHANGE) {
  94. struct cam_hw_soc_info *soc_info = notifier_data->pvt_data;
  95. CAM_WARN(CAM_UTIL, "Dev %s Clk %s value change from %ld to %ld",
  96. soc_info->dev_name,
  97. (soc_info->src_clk_idx == -1) ? "No src clk" :
  98. soc_info->clk_name[soc_info->src_clk_idx],
  99. notifier_data->cb_data.val_chng.old_val,
  100. notifier_data->cb_data.val_chng.new_val);
  101. }
  102. return 0;
  103. }
  104. int cam_soc_util_register_mmrm_client(
  105. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  106. struct cam_hw_soc_info *soc_info, const char *clk_name,
  107. void **mmrm_handle)
  108. {
  109. struct mmrm_client *mmrm_client;
  110. struct mmrm_client_desc desc = { };
  111. if (!mmrm_handle) {
  112. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  113. return -EINVAL;
  114. }
  115. *mmrm_handle = (void *)NULL;
  116. if (!cam_is_mmrm_supported_on_current_chip())
  117. return 0;
  118. desc.client_type = MMRM_CLIENT_CLOCK;
  119. desc.client_info.desc.client_domain = MMRM_CLIENT_DOMAIN_CAMERA;
  120. desc.client_info.desc.client_id = clk_id;
  121. desc.client_info.desc.clk = clk;
  122. snprintf((char *)desc.client_info.desc.name,
  123. sizeof(desc.client_info.desc.name), "%s_%s",
  124. soc_info->dev_name, clk_name);
  125. desc.priority = is_nrt_dev ?
  126. MMRM_CLIENT_PRIOR_LOW : MMRM_CLIENT_PRIOR_HIGH;
  127. desc.pvt_data = soc_info;
  128. desc.notifier_callback_fn = cam_mmrm_notifier_callback;
  129. mmrm_client = mmrm_client_register(&desc);
  130. if (!mmrm_client) {
  131. CAM_ERR(CAM_UTIL, "MMRM Register failed Dev %s clk %s id %d",
  132. soc_info->dev_name, clk_name, clk_id);
  133. return -EINVAL;
  134. }
  135. CAM_DBG(CAM_UTIL,
  136. "MMRM Register success Dev %s is_nrt_dev %d clk %s id %d handle=%pK",
  137. soc_info->dev_name, is_nrt_dev, clk_name, clk_id, mmrm_client);
  138. *mmrm_handle = (void *)mmrm_client;
  139. return 0;
  140. }
  141. int cam_soc_util_unregister_mmrm_client(
  142. void *mmrm_handle)
  143. {
  144. int rc = 0;
  145. CAM_DBG(CAM_UTIL, "MMRM UnRegister handle=%pK", mmrm_handle);
  146. if (mmrm_handle) {
  147. rc = mmrm_client_deregister((struct mmrm_client *)mmrm_handle);
  148. if (rc)
  149. CAM_ERR(CAM_UTIL,
  150. "Failed in deregister handle=%pK, rc %d",
  151. mmrm_handle, rc);
  152. }
  153. return rc;
  154. }
  155. static int cam_soc_util_set_rate_through_mmrm(
  156. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  157. long req_rate, uint32_t num_hw_blocks)
  158. {
  159. int rc = 0;
  160. struct mmrm_client_data client_data;
  161. struct mmrm_client_res_value val;
  162. client_data.num_hw_blocks = num_hw_blocks;
  163. client_data.flags = 0;
  164. CAM_DBG(CAM_UTIL,
  165. "mmrm=%pK, nrt=%d, min_rate=%ld req_rate %ld, num_blocks=%d",
  166. mmrm_handle, is_nrt_dev, min_rate, req_rate, num_hw_blocks);
  167. if (is_nrt_dev) {
  168. val.min = min_rate;
  169. val.cur = req_rate;
  170. rc = mmrm_client_set_value_in_range(
  171. (struct mmrm_client *)mmrm_handle, &client_data, &val);
  172. } else {
  173. rc = mmrm_client_set_value(
  174. (struct mmrm_client *)mmrm_handle,
  175. &client_data, req_rate);
  176. }
  177. if (rc)
  178. CAM_ERR(CAM_UTIL, "Set rate failed rate %ld rc %d",
  179. req_rate, rc);
  180. return rc;
  181. }
  182. #else
  183. int cam_soc_util_register_mmrm_client(
  184. uint32_t clk_id, struct clk *clk, bool is_nrt_dev,
  185. struct cam_hw_soc_info *soc_info, const char *clk_name,
  186. void **mmrm_handle)
  187. {
  188. if (!mmrm_handle) {
  189. CAM_ERR(CAM_UTIL, "Invalid mmrm input");
  190. return -EINVAL;
  191. }
  192. *mmrm_handle = NULL;
  193. return 0;
  194. }
  195. int cam_soc_util_unregister_mmrm_client(
  196. void *mmrm_handle)
  197. {
  198. return 0;
  199. }
  200. static int cam_soc_util_set_rate_through_mmrm(
  201. void *mmrm_handle, bool is_nrt_dev, long min_rate,
  202. long req_rate, uint32_t num_hw_blocks)
  203. {
  204. return 0;
  205. }
  206. #endif
  207. static int cam_soc_util_clk_wrapper_register_entry(
  208. uint32_t clk_id, struct clk *clk, bool is_src_clk,
  209. struct cam_hw_soc_info *soc_info, int64_t min_clk_rate,
  210. const char *clk_name)
  211. {
  212. struct cam_clk_wrapper_clk *wrapper_clk;
  213. struct cam_clk_wrapper_client *wrapper_client;
  214. bool clock_found = false;
  215. int rc = 0;
  216. mutex_lock(&wrapper_lock);
  217. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  218. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  219. wrapper_clk->clk_id, wrapper_clk->num_clients);
  220. if (wrapper_clk->clk_id == clk_id) {
  221. clock_found = true;
  222. list_for_each_entry(wrapper_client,
  223. &wrapper_clk->client_list, list) {
  224. CAM_DBG(CAM_UTIL,
  225. "Clk id %d entry client %s",
  226. wrapper_clk->clk_id,
  227. wrapper_client->soc_info->dev_name);
  228. if (wrapper_client->soc_info == soc_info) {
  229. CAM_ERR(CAM_UTIL,
  230. "Register with same soc info, clk id %d, client %s",
  231. clk_id, soc_info->dev_name);
  232. rc = -EINVAL;
  233. goto end;
  234. }
  235. }
  236. break;
  237. }
  238. }
  239. if (!clock_found) {
  240. CAM_DBG(CAM_UTIL, "Adding new entry for clk id %d", clk_id);
  241. wrapper_clk = kzalloc(sizeof(struct cam_clk_wrapper_clk),
  242. GFP_KERNEL);
  243. if (!wrapper_clk) {
  244. CAM_ERR(CAM_UTIL,
  245. "Failed in allocating new clk entry %d",
  246. clk_id);
  247. rc = -ENOMEM;
  248. goto end;
  249. }
  250. wrapper_clk->clk_id = clk_id;
  251. INIT_LIST_HEAD(&wrapper_clk->list);
  252. INIT_LIST_HEAD(&wrapper_clk->client_list);
  253. list_add_tail(&wrapper_clk->list, &wrapper_clk_list);
  254. }
  255. wrapper_client = kzalloc(sizeof(struct cam_clk_wrapper_client),
  256. GFP_KERNEL);
  257. if (!wrapper_client) {
  258. CAM_ERR(CAM_UTIL, "Failed in allocating new client entry %d",
  259. clk_id);
  260. rc = -ENOMEM;
  261. goto end;
  262. }
  263. wrapper_client->soc_info = soc_info;
  264. wrapper_client->clk = clk;
  265. if (is_src_clk && !wrapper_clk->mmrm_handle) {
  266. wrapper_clk->is_nrt_dev = soc_info->is_nrt_dev;
  267. wrapper_clk->min_clk_rate = min_clk_rate;
  268. wrapper_clk->soc_info = soc_info;
  269. rc = cam_soc_util_register_mmrm_client(clk_id, clk,
  270. wrapper_clk->is_nrt_dev, soc_info, clk_name,
  271. &wrapper_clk->mmrm_handle);
  272. if (rc) {
  273. CAM_ERR(CAM_UTIL,
  274. "Failed in register mmrm client Dev %s clk id %d",
  275. soc_info->dev_name, clk_id);
  276. kfree(wrapper_client);
  277. goto end;
  278. }
  279. }
  280. INIT_LIST_HEAD(&wrapper_client->list);
  281. list_add_tail(&wrapper_client->list, &wrapper_clk->client_list);
  282. wrapper_clk->num_clients++;
  283. CAM_DBG(CAM_UTIL,
  284. "Adding new client %s for clk[%s] id %d, num clients %d",
  285. soc_info->dev_name, clk_name, clk_id, wrapper_clk->num_clients);
  286. end:
  287. mutex_unlock(&wrapper_lock);
  288. return rc;
  289. }
  290. static int cam_soc_util_clk_wrapper_unregister_entry(
  291. uint32_t clk_id, struct cam_hw_soc_info *soc_info)
  292. {
  293. struct cam_clk_wrapper_clk *wrapper_clk;
  294. struct cam_clk_wrapper_client *wrapper_client;
  295. bool clock_found = false;
  296. bool client_found = false;
  297. int rc = 0;
  298. mutex_lock(&wrapper_lock);
  299. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  300. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  301. wrapper_clk->clk_id, wrapper_clk->num_clients);
  302. if (wrapper_clk->clk_id == clk_id) {
  303. clock_found = true;
  304. list_for_each_entry(wrapper_client,
  305. &wrapper_clk->client_list, list) {
  306. CAM_DBG(CAM_UTIL, "Clk id %d entry client %s",
  307. wrapper_clk->clk_id,
  308. wrapper_client->soc_info->dev_name);
  309. if (wrapper_client->soc_info == soc_info) {
  310. client_found = true;
  311. break;
  312. }
  313. }
  314. break;
  315. }
  316. }
  317. if (!clock_found) {
  318. CAM_ERR(CAM_UTIL, "Shared clk id %d entry not found", clk_id);
  319. rc = -EINVAL;
  320. goto end;
  321. }
  322. if (!client_found) {
  323. CAM_ERR(CAM_UTIL,
  324. "Client %pK for Shared clk id %d entry not found",
  325. soc_info, clk_id);
  326. rc = -EINVAL;
  327. goto end;
  328. }
  329. wrapper_clk->num_clients--;
  330. if (wrapper_clk->mmrm_handle && (wrapper_clk->soc_info == soc_info)) {
  331. cam_soc_util_unregister_mmrm_client(wrapper_clk->mmrm_handle);
  332. wrapper_clk->mmrm_handle = NULL;
  333. wrapper_clk->soc_info = NULL;
  334. }
  335. list_del_init(&wrapper_client->list);
  336. kfree(wrapper_client);
  337. CAM_DBG(CAM_UTIL, "Unregister client %s for clk id %d, num clients %d",
  338. soc_info->dev_name, clk_id, wrapper_clk->num_clients);
  339. if (!wrapper_clk->num_clients) {
  340. list_del_init(&wrapper_clk->list);
  341. kfree(wrapper_clk);
  342. }
  343. end:
  344. mutex_unlock(&wrapper_lock);
  345. return rc;
  346. }
  347. static int cam_soc_util_clk_wrapper_set_clk_rate(
  348. uint32_t clk_id, struct cam_hw_soc_info *soc_info,
  349. struct clk *clk, int64_t clk_rate)
  350. {
  351. struct cam_clk_wrapper_clk *wrapper_clk;
  352. struct cam_clk_wrapper_client *wrapper_client;
  353. bool clk_found = false;
  354. bool client_found = false;
  355. int rc = 0;
  356. int64_t final_clk_rate = 0;
  357. uint32_t active_clients = 0;
  358. if (!soc_info || !clk) {
  359. CAM_ERR(CAM_UTIL, "Invalid param soc_info %pK clk %pK",
  360. soc_info, clk);
  361. return -EINVAL;
  362. }
  363. mutex_lock(&wrapper_lock);
  364. list_for_each_entry(wrapper_clk, &wrapper_clk_list, list) {
  365. CAM_DBG(CAM_UTIL, "Clk list id %d num clients %d",
  366. wrapper_clk->clk_id, wrapper_clk->num_clients);
  367. if (wrapper_clk->clk_id == clk_id) {
  368. clk_found = true;
  369. break;
  370. }
  371. }
  372. if (!clk_found) {
  373. CAM_ERR(CAM_UTIL, "Clk entry not found id %d client %s",
  374. clk_id, soc_info->dev_name);
  375. rc = -EINVAL;
  376. goto end;
  377. }
  378. list_for_each_entry(wrapper_client, &wrapper_clk->client_list, list) {
  379. CAM_DBG(CAM_UTIL, "Clk id %d client %s, clk rate %lld",
  380. wrapper_clk->clk_id, wrapper_client->soc_info->dev_name,
  381. wrapper_client->curr_clk_rate);
  382. if (wrapper_client->soc_info == soc_info) {
  383. client_found = true;
  384. CAM_DBG(CAM_UTIL,
  385. "Clk enable clk id %d, client %s curr %ld new %ld",
  386. clk_id, wrapper_client->soc_info->dev_name,
  387. wrapper_client->curr_clk_rate, clk_rate);
  388. wrapper_client->curr_clk_rate = clk_rate;
  389. }
  390. if (wrapper_client->curr_clk_rate > 0)
  391. active_clients++;
  392. if (final_clk_rate < wrapper_client->curr_clk_rate)
  393. final_clk_rate = wrapper_client->curr_clk_rate;
  394. }
  395. if (!client_found) {
  396. CAM_ERR(CAM_UTIL,
  397. "Wrapper clk enable without client entry clk id %d client %s",
  398. clk_id, soc_info->dev_name);
  399. rc = -EINVAL;
  400. goto end;
  401. }
  402. CAM_DBG(CAM_UTIL,
  403. "Clk id %d, client %s, clients rate %ld, curr %ld final %ld",
  404. wrapper_clk->clk_id, soc_info->dev_name, clk_rate,
  405. wrapper_clk->curr_clk_rate, final_clk_rate);
  406. if ((final_clk_rate != wrapper_clk->curr_clk_rate) ||
  407. (active_clients != wrapper_clk->active_clients)) {
  408. bool set_rate_finish = false;
  409. if (!skip_mmrm_set_rate && wrapper_clk->mmrm_handle) {
  410. rc = cam_soc_util_set_rate_through_mmrm(
  411. wrapper_clk->mmrm_handle,
  412. wrapper_clk->is_nrt_dev,
  413. wrapper_clk->min_clk_rate,
  414. final_clk_rate, active_clients);
  415. if (rc) {
  416. CAM_ERR(CAM_UTIL,
  417. "set_rate through mmrm failed clk_id %d, rate=%ld",
  418. wrapper_clk->clk_id, final_clk_rate);
  419. goto end;
  420. }
  421. set_rate_finish = true;
  422. }
  423. if (!set_rate_finish && final_clk_rate &&
  424. (final_clk_rate != wrapper_clk->curr_clk_rate)) {
  425. rc = clk_set_rate(clk, final_clk_rate);
  426. if (rc) {
  427. CAM_ERR(CAM_UTIL, "set_rate failed on clk %d",
  428. wrapper_clk->clk_id);
  429. goto end;
  430. }
  431. }
  432. wrapper_clk->curr_clk_rate = final_clk_rate;
  433. wrapper_clk->active_clients = active_clients;
  434. }
  435. end:
  436. mutex_unlock(&wrapper_lock);
  437. return rc;
  438. }
  439. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  440. int64_t clk_rate, int clk_idx, int32_t *clk_lvl)
  441. {
  442. int i;
  443. long clk_rate_round;
  444. if (!soc_info || (clk_idx < 0) || (clk_idx >= CAM_SOC_MAX_CLK)) {
  445. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d", clk_idx);
  446. *clk_lvl = -1;
  447. return -EINVAL;
  448. }
  449. clk_rate_round = clk_round_rate(soc_info->clk[clk_idx], clk_rate);
  450. if (clk_rate_round < 0) {
  451. CAM_ERR(CAM_UTIL, "round failed rc = %ld",
  452. clk_rate_round);
  453. *clk_lvl = -1;
  454. return -EINVAL;
  455. }
  456. for (i = 0; i < CAM_MAX_VOTE; i++) {
  457. if ((soc_info->clk_level_valid[i]) &&
  458. (soc_info->clk_rate[i][clk_idx] >=
  459. clk_rate_round)) {
  460. CAM_DBG(CAM_UTIL,
  461. "soc = %d round rate = %ld actual = %lld",
  462. soc_info->clk_rate[i][clk_idx],
  463. clk_rate_round, clk_rate);
  464. *clk_lvl = i;
  465. return 0;
  466. }
  467. }
  468. CAM_WARN(CAM_UTIL, "Invalid clock rate %ld", clk_rate_round);
  469. *clk_lvl = -1;
  470. return -EINVAL;
  471. }
  472. /**
  473. * cam_soc_util_get_string_from_level()
  474. *
  475. * @brief: Returns the string for a given clk level
  476. *
  477. * @level: Clock level
  478. *
  479. * @return: String corresponding to the clk level
  480. */
  481. static const char *cam_soc_util_get_string_from_level(
  482. enum cam_vote_level level)
  483. {
  484. switch (level) {
  485. case CAM_SUSPEND_VOTE:
  486. return "";
  487. case CAM_MINSVS_VOTE:
  488. return "MINSVS[1]";
  489. case CAM_LOWSVS_VOTE:
  490. return "LOWSVS[2]";
  491. case CAM_SVS_VOTE:
  492. return "SVS[3]";
  493. case CAM_SVSL1_VOTE:
  494. return "SVSL1[4]";
  495. case CAM_NOMINAL_VOTE:
  496. return "NOM[5]";
  497. case CAM_NOMINALL1_VOTE:
  498. return "NOML1[6]";
  499. case CAM_TURBO_VOTE:
  500. return "TURBO[7]";
  501. default:
  502. return "";
  503. }
  504. }
  505. /**
  506. * cam_soc_util_get_supported_clk_levels()
  507. *
  508. * @brief: Returns the string of all the supported clk levels for
  509. * the given device
  510. *
  511. * @soc_info: Device soc information
  512. *
  513. * @return: String containing all supported clk levels
  514. */
  515. static const char *cam_soc_util_get_supported_clk_levels(
  516. struct cam_hw_soc_info *soc_info)
  517. {
  518. int i = 0;
  519. memset(supported_clk_info, 0, sizeof(supported_clk_info));
  520. strlcat(supported_clk_info, "Supported levels: ",
  521. sizeof(supported_clk_info));
  522. for (i = 0; i < CAM_MAX_VOTE; i++) {
  523. if (soc_info->clk_level_valid[i] == true) {
  524. strlcat(supported_clk_info,
  525. cam_soc_util_get_string_from_level(i),
  526. sizeof(supported_clk_info));
  527. strlcat(supported_clk_info, " ",
  528. sizeof(supported_clk_info));
  529. }
  530. }
  531. strlcat(supported_clk_info, "\n", sizeof(supported_clk_info));
  532. return supported_clk_info;
  533. }
  534. static int cam_soc_util_clk_lvl_options_open(struct inode *inode,
  535. struct file *file)
  536. {
  537. file->private_data = inode->i_private;
  538. return 0;
  539. }
  540. static ssize_t cam_soc_util_clk_lvl_options_read(struct file *file,
  541. char __user *clk_info, size_t size_t, loff_t *loff_t)
  542. {
  543. struct cam_hw_soc_info *soc_info =
  544. (struct cam_hw_soc_info *)file->private_data;
  545. const char *display_string =
  546. cam_soc_util_get_supported_clk_levels(soc_info);
  547. return simple_read_from_buffer(clk_info, size_t, loff_t, display_string,
  548. strlen(display_string));
  549. }
  550. static const struct file_operations cam_soc_util_clk_lvl_options = {
  551. .open = cam_soc_util_clk_lvl_options_open,
  552. .read = cam_soc_util_clk_lvl_options_read,
  553. };
  554. static int cam_soc_util_set_clk_lvl(void *data, u64 val)
  555. {
  556. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  557. if (val <= CAM_SUSPEND_VOTE || val >= CAM_MAX_VOTE)
  558. return 0;
  559. if (soc_info->clk_level_valid[val] == true)
  560. soc_info->clk_level_override = val;
  561. else
  562. soc_info->clk_level_override = 0;
  563. return 0;
  564. }
  565. static int cam_soc_util_get_clk_lvl(void *data, u64 *val)
  566. {
  567. struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data;
  568. *val = soc_info->clk_level_override;
  569. return 0;
  570. }
  571. DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control,
  572. cam_soc_util_get_clk_lvl, cam_soc_util_set_clk_lvl, "%08llu");
  573. /**
  574. * cam_soc_util_create_clk_lvl_debugfs()
  575. *
  576. * @brief: Creates debugfs files to view/control device clk rates
  577. *
  578. * @soc_info: Device soc information
  579. *
  580. * @return: Success or failure
  581. */
  582. static int cam_soc_util_create_clk_lvl_debugfs(struct cam_hw_soc_info *soc_info)
  583. {
  584. char debugfs_dir_name[64];
  585. int rc = 0;
  586. struct dentry *dbgfileptr = NULL;
  587. if (soc_info->dentry) {
  588. CAM_DBG(CAM_UTIL, "Debugfs entry for %s already exist",
  589. soc_info->dev_name);
  590. goto end;
  591. }
  592. memset(debugfs_dir_name, 0, sizeof(debugfs_dir_name));
  593. strlcat(debugfs_dir_name, "clk_dir_", sizeof(debugfs_dir_name));
  594. strlcat(debugfs_dir_name, soc_info->dev_name, sizeof(debugfs_dir_name));
  595. dbgfileptr = debugfs_create_dir(debugfs_dir_name, NULL);
  596. if (!dbgfileptr) {
  597. CAM_ERR(CAM_UTIL,"DebugFS could not create directory!");
  598. rc = -ENOENT;
  599. goto end;
  600. }
  601. /* Store parent inode for cleanup in caller */
  602. soc_info->dentry = dbgfileptr;
  603. dbgfileptr = debugfs_create_file("clk_lvl_options", 0444,
  604. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_options);
  605. dbgfileptr = debugfs_create_file("clk_lvl_control", 0644,
  606. soc_info->dentry, soc_info, &cam_soc_util_clk_lvl_control);
  607. if (IS_ERR(dbgfileptr)) {
  608. if (PTR_ERR(dbgfileptr) == -ENODEV)
  609. CAM_WARN(CAM_UTIL, "DebugFS not enabled in kernel!");
  610. else
  611. rc = PTR_ERR(dbgfileptr);
  612. }
  613. end:
  614. return rc;
  615. }
  616. /**
  617. * cam_soc_util_remove_clk_lvl_debugfs()
  618. *
  619. * @brief: Removes the debugfs files used to view/control
  620. * device clk rates
  621. *
  622. * @soc_info: Device soc information
  623. *
  624. */
  625. static void cam_soc_util_remove_clk_lvl_debugfs(
  626. struct cam_hw_soc_info *soc_info)
  627. {
  628. debugfs_remove_recursive(soc_info->dentry);
  629. soc_info->dentry = NULL;
  630. }
  631. int cam_soc_util_get_level_from_string(const char *string,
  632. enum cam_vote_level *level)
  633. {
  634. if (!level)
  635. return -EINVAL;
  636. if (!strcmp(string, "suspend")) {
  637. *level = CAM_SUSPEND_VOTE;
  638. } else if (!strcmp(string, "minsvs")) {
  639. *level = CAM_MINSVS_VOTE;
  640. } else if (!strcmp(string, "lowsvs")) {
  641. *level = CAM_LOWSVS_VOTE;
  642. } else if (!strcmp(string, "svs")) {
  643. *level = CAM_SVS_VOTE;
  644. } else if (!strcmp(string, "svs_l1")) {
  645. *level = CAM_SVSL1_VOTE;
  646. } else if (!strcmp(string, "nominal")) {
  647. *level = CAM_NOMINAL_VOTE;
  648. } else if (!strcmp(string, "nominal_l1")) {
  649. *level = CAM_NOMINALL1_VOTE;
  650. } else if (!strcmp(string, "turbo")) {
  651. *level = CAM_TURBO_VOTE;
  652. } else {
  653. CAM_ERR(CAM_UTIL, "Invalid string %s", string);
  654. return -EINVAL;
  655. }
  656. return 0;
  657. }
  658. /**
  659. * cam_soc_util_get_clk_level_to_apply()
  660. *
  661. * @brief: Get the clock level to apply. If the requested level
  662. * is not valid, bump the level to next available valid
  663. * level. If no higher level found, return failure.
  664. *
  665. * @soc_info: Device soc struct to be populated
  666. * @req_level: Requested level
  667. * @apply_level Level to apply
  668. *
  669. * @return: success or failure
  670. */
  671. static int cam_soc_util_get_clk_level_to_apply(
  672. struct cam_hw_soc_info *soc_info, enum cam_vote_level req_level,
  673. enum cam_vote_level *apply_level)
  674. {
  675. if (req_level >= CAM_MAX_VOTE) {
  676. CAM_ERR(CAM_UTIL, "Invalid clock level parameter %d",
  677. req_level);
  678. return -EINVAL;
  679. }
  680. if (soc_info->clk_level_valid[req_level] == true) {
  681. *apply_level = req_level;
  682. } else {
  683. int i;
  684. for (i = (req_level + 1); i < CAM_MAX_VOTE; i++)
  685. if (soc_info->clk_level_valid[i] == true) {
  686. *apply_level = i;
  687. break;
  688. }
  689. if (i == CAM_MAX_VOTE) {
  690. CAM_ERR(CAM_UTIL,
  691. "No valid clock level found to apply, req=%d",
  692. req_level);
  693. return -EINVAL;
  694. }
  695. }
  696. CAM_DBG(CAM_UTIL, "Req level %d, Applying %d",
  697. req_level, *apply_level);
  698. return 0;
  699. }
  700. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info)
  701. {
  702. if (!soc_info) {
  703. CAM_ERR(CAM_UTIL, "Invalid arguments");
  704. return -EINVAL;
  705. }
  706. if (!soc_info->irq_line) {
  707. CAM_ERR(CAM_UTIL, "No IRQ line available");
  708. return -ENODEV;
  709. }
  710. enable_irq(soc_info->irq_line->start);
  711. return 0;
  712. }
  713. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info)
  714. {
  715. if (!soc_info) {
  716. CAM_ERR(CAM_UTIL, "Invalid arguments");
  717. return -EINVAL;
  718. }
  719. if (!soc_info->irq_line) {
  720. CAM_ERR(CAM_UTIL, "No IRQ line available");
  721. return -ENODEV;
  722. }
  723. disable_irq(soc_info->irq_line->start);
  724. return 0;
  725. }
  726. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  727. uint32_t clk_index, unsigned long clk_rate)
  728. {
  729. if (!soc_info || (clk_index >= soc_info->num_clk) || (clk_rate == 0)) {
  730. CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d %lu",
  731. soc_info, clk_index, clk_rate);
  732. return clk_rate;
  733. }
  734. return clk_round_rate(soc_info->clk[clk_index], clk_rate);
  735. }
  736. /**
  737. * cam_soc_util_set_clk_rate()
  738. *
  739. * @brief: Sets the given rate for the clk requested for
  740. *
  741. * @clk: Clock structure information for which rate is to be set
  742. * @clk_name: Name of the clock for which rate is being set
  743. * @clk_rate: Clock rate to be set
  744. * @shared_clk: Whether this is a shared clk
  745. * @is_src_clk: Whether this is source clk
  746. * @clk_id: Clock ID
  747. * @applied_clk_rate: Final clock rate set to the clk
  748. *
  749. * @return: Success or failure
  750. */
  751. static int cam_soc_util_set_clk_rate(struct cam_hw_soc_info *soc_info,
  752. struct clk *clk, const char *clk_name,
  753. int64_t clk_rate, bool shared_clk, bool is_src_clk, uint32_t clk_id,
  754. unsigned long *applied_clk_rate)
  755. {
  756. int rc = 0;
  757. long clk_rate_round = -1;
  758. bool set_rate = false;
  759. if (!clk || !clk_name) {
  760. CAM_ERR(CAM_UTIL, "Invalid input clk %pK clk_name %pK",
  761. clk, clk_name);
  762. return -EINVAL;
  763. }
  764. CAM_DBG(CAM_UTIL, "set %s, rate %lld", clk_name, clk_rate);
  765. if (clk_rate > 0) {
  766. clk_rate_round = clk_round_rate(clk, clk_rate);
  767. CAM_DBG(CAM_UTIL, "new_rate %ld", clk_rate_round);
  768. if (clk_rate_round < 0) {
  769. CAM_ERR(CAM_UTIL, "round failed for clock %s rc = %ld",
  770. clk_name, clk_rate_round);
  771. return clk_rate_round;
  772. }
  773. set_rate = true;
  774. } else if (clk_rate == INIT_RATE) {
  775. clk_rate_round = clk_get_rate(clk);
  776. CAM_DBG(CAM_UTIL, "init new_rate %ld", clk_rate_round);
  777. if (clk_rate_round == 0) {
  778. clk_rate_round = clk_round_rate(clk, 0);
  779. if (clk_rate_round <= 0) {
  780. CAM_ERR(CAM_UTIL, "round rate failed on %s",
  781. clk_name);
  782. return clk_rate_round;
  783. }
  784. }
  785. set_rate = true;
  786. }
  787. if (set_rate) {
  788. if (shared_clk) {
  789. CAM_DBG(CAM_UTIL,
  790. "Dev %s clk %s id %d Set Shared clk %ld",
  791. soc_info->dev_name, clk_name, clk_id,
  792. clk_rate_round);
  793. cam_soc_util_clk_wrapper_set_clk_rate(
  794. clk_id, soc_info, clk, clk_rate_round);
  795. } else {
  796. bool set_rate_finish = false;
  797. CAM_DBG(CAM_UTIL,
  798. "Dev %s clk %s clk_id %d src_idx %d src_clk_id %d",
  799. soc_info->dev_name, clk_name, clk_id,
  800. soc_info->src_clk_idx,
  801. (soc_info->src_clk_idx == -1) ? -1 :
  802. soc_info->clk_id[soc_info->src_clk_idx]);
  803. if (is_src_clk && soc_info->mmrm_handle &&
  804. !skip_mmrm_set_rate) {
  805. uint32_t idx = soc_info->src_clk_idx;
  806. uint32_t min_level = soc_info->lowest_clk_level;
  807. rc = cam_soc_util_set_rate_through_mmrm(
  808. soc_info->mmrm_handle,
  809. soc_info->is_nrt_dev,
  810. soc_info->clk_rate[min_level][idx],
  811. clk_rate_round, 1);
  812. if (rc) {
  813. CAM_ERR(CAM_UTIL,
  814. "set_rate through mmrm failed on %s clk_id %d, rate=%ld",
  815. clk_name, clk_id,
  816. clk_rate_round);
  817. return rc;
  818. }
  819. set_rate_finish = true;
  820. }
  821. if (!set_rate_finish) {
  822. rc = clk_set_rate(clk, clk_rate_round);
  823. if (rc) {
  824. CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name);
  825. return rc;
  826. }
  827. }
  828. }
  829. }
  830. if (applied_clk_rate)
  831. *applied_clk_rate = clk_rate_round;
  832. return rc;
  833. }
  834. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
  835. int64_t clk_rate)
  836. {
  837. int rc = 0;
  838. int i = 0;
  839. int32_t src_clk_idx;
  840. int32_t scl_clk_idx;
  841. struct clk *clk = NULL;
  842. int32_t apply_level;
  843. uint32_t clk_level_override = 0;
  844. if (!soc_info || (soc_info->src_clk_idx < 0) ||
  845. (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) {
  846. CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d",
  847. soc_info ? soc_info->src_clk_idx : -1);
  848. return -EINVAL;
  849. }
  850. src_clk_idx = soc_info->src_clk_idx;
  851. clk_level_override = soc_info->clk_level_override;
  852. if (clk_level_override && clk_rate)
  853. clk_rate =
  854. soc_info->clk_rate[clk_level_override][src_clk_idx];
  855. clk = soc_info->clk[src_clk_idx];
  856. rc = cam_soc_util_get_clk_level(soc_info, clk_rate, src_clk_idx,
  857. &apply_level);
  858. if (rc || (apply_level < 0) || (apply_level >= CAM_MAX_VOTE)) {
  859. CAM_ERR(CAM_UTIL,
  860. "set %s, rate %lld dev_name = %s apply level = %d",
  861. soc_info->clk_name[src_clk_idx], clk_rate,
  862. soc_info->dev_name, apply_level);
  863. return -EINVAL;
  864. }
  865. CAM_DBG(CAM_UTIL, "set %s, rate %lld dev_name = %s apply level = %d",
  866. soc_info->clk_name[src_clk_idx], clk_rate,
  867. soc_info->dev_name, apply_level);
  868. if ((soc_info->cam_cx_ipeak_enable) && (clk_rate >= 0)) {
  869. cam_cx_ipeak_update_vote_cx_ipeak(soc_info,
  870. apply_level);
  871. }
  872. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  873. soc_info->clk_name[src_clk_idx], clk_rate,
  874. CAM_IS_BIT_SET(soc_info->shared_clk_mask, src_clk_idx),
  875. true, soc_info->clk_id[src_clk_idx],
  876. &soc_info->applied_src_clk_rate);
  877. if (rc) {
  878. CAM_ERR(CAM_UTIL,
  879. "SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d",
  880. soc_info->clk_name[src_clk_idx], clk_rate,
  881. soc_info->dev_name, rc);
  882. return rc;
  883. }
  884. /* set clk rate for scalable clk if available */
  885. for (i = 0; i < soc_info->scl_clk_count; i++) {
  886. scl_clk_idx = soc_info->scl_clk_idx[i];
  887. if (scl_clk_idx < 0) {
  888. CAM_DBG(CAM_UTIL, "Scl clk index invalid");
  889. continue;
  890. }
  891. clk = soc_info->clk[scl_clk_idx];
  892. rc = cam_soc_util_set_clk_rate(soc_info, clk,
  893. soc_info->clk_name[scl_clk_idx],
  894. soc_info->clk_rate[apply_level][scl_clk_idx],
  895. CAM_IS_BIT_SET(soc_info->shared_clk_mask, scl_clk_idx),
  896. false, soc_info->clk_id[scl_clk_idx],
  897. NULL);
  898. if (rc) {
  899. CAM_WARN(CAM_UTIL,
  900. "SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d",
  901. soc_info->clk_name[scl_clk_idx],
  902. soc_info->clk_rate[apply_level][scl_clk_idx],
  903. soc_info->dev_name, rc);
  904. }
  905. }
  906. return 0;
  907. }
  908. int cam_soc_util_put_optional_clk(struct cam_hw_soc_info *soc_info,
  909. int32_t clk_indx)
  910. {
  911. if (clk_indx < 0) {
  912. CAM_ERR(CAM_UTIL, "Invalid params clk %d", clk_indx);
  913. return -EINVAL;
  914. }
  915. if (CAM_IS_BIT_SET(soc_info->optional_shared_clk_mask, clk_indx))
  916. cam_soc_util_clk_wrapper_unregister_entry(
  917. soc_info->optional_clk_id[clk_indx], soc_info);
  918. clk_put(soc_info->optional_clk[clk_indx]);
  919. soc_info->optional_clk[clk_indx] = NULL;
  920. return 0;
  921. }
  922. static struct clk *cam_soc_util_option_clk_get(struct device_node *np,
  923. int index, uint32_t *clk_id)
  924. {
  925. struct of_phandle_args clkspec;
  926. struct clk *clk;
  927. int rc;
  928. if (index < 0)
  929. return ERR_PTR(-EINVAL);
  930. rc = of_parse_phandle_with_args(np, "clocks-option", "#clock-cells",
  931. index, &clkspec);
  932. if (rc)
  933. return ERR_PTR(rc);
  934. clk = of_clk_get_from_provider(&clkspec);
  935. *clk_id = clkspec.args[0];
  936. of_node_put(clkspec.np);
  937. return clk;
  938. }
  939. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  940. const char *clk_name, int32_t *clk_index)
  941. {
  942. int index = 0;
  943. int rc = 0;
  944. struct device_node *of_node = NULL;
  945. uint32_t shared_clk_val;
  946. if (!soc_info || !clk_name || !clk_index) {
  947. CAM_ERR(CAM_UTIL,
  948. "Invalid params soc_info %pK clk_name %s clk_index %pK",
  949. soc_info, clk_name, clk_index);
  950. return -EINVAL;
  951. }
  952. of_node = soc_info->dev->of_node;
  953. index = of_property_match_string(of_node, "clock-names-option",
  954. clk_name);
  955. if (index < 0) {
  956. CAM_DBG(CAM_UTIL, "No clk data for %s", clk_name);
  957. *clk_index = -1;
  958. return -EINVAL;
  959. }
  960. if (index >= CAM_SOC_MAX_OPT_CLK) {
  961. CAM_ERR(CAM_UTIL, "Insufficient optional clk entries %d %d",
  962. index, CAM_SOC_MAX_OPT_CLK);
  963. return -EINVAL;
  964. }
  965. of_property_read_string_index(of_node, "clock-names-option",
  966. index, &(soc_info->optional_clk_name[index]));
  967. soc_info->optional_clk[index] = cam_soc_util_option_clk_get(of_node,
  968. index, &soc_info->optional_clk_id[index]);
  969. if (IS_ERR(soc_info->optional_clk[index])) {
  970. CAM_ERR(CAM_UTIL, "No clk named %s found. Dev %s", clk_name,
  971. soc_info->dev_name);
  972. *clk_index = -1;
  973. return -EFAULT;
  974. }
  975. *clk_index = index;
  976. rc = of_property_read_u32_index(of_node, "clock-rates-option",
  977. index, &soc_info->optional_clk_rate[index]);
  978. if (rc) {
  979. CAM_ERR(CAM_UTIL,
  980. "Error reading clock-rates clk_name %s index %d",
  981. clk_name, index);
  982. goto error;
  983. }
  984. /*
  985. * Option clocks are assumed to be available to single Device here.
  986. * Hence use INIT_RATE instead of NO_SET_RATE.
  987. */
  988. soc_info->optional_clk_rate[index] =
  989. (soc_info->optional_clk_rate[index] == 0) ?
  990. (int32_t)INIT_RATE : soc_info->optional_clk_rate[index];
  991. CAM_DBG(CAM_UTIL, "clk_name %s index %d clk_rate %d",
  992. clk_name, *clk_index, soc_info->optional_clk_rate[index]);
  993. rc = of_property_read_u32_index(of_node, "shared-clks-option",
  994. index, &shared_clk_val);
  995. if (rc) {
  996. CAM_DBG(CAM_UTIL, "Not shared clk %s index %d",
  997. clk_name, index);
  998. } else if (shared_clk_val > 1) {
  999. CAM_WARN(CAM_UTIL, "Invalid shared clk val %d", shared_clk_val);
  1000. } else {
  1001. CAM_DBG(CAM_UTIL,
  1002. "Dev %s shared clk %s index %d, clk id %d, shared_clk_val %d",
  1003. soc_info->dev_name, clk_name, index,
  1004. soc_info->optional_clk_id[index], shared_clk_val);
  1005. if (shared_clk_val) {
  1006. CAM_SET_BIT(soc_info->optional_shared_clk_mask, index);
  1007. /* Create a wrapper entry if this is a shared clock */
  1008. CAM_DBG(CAM_UTIL,
  1009. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  1010. soc_info->dev_name,
  1011. soc_info->optional_clk_name[index],
  1012. soc_info->optional_clk_id[index]);
  1013. rc = cam_soc_util_clk_wrapper_register_entry(
  1014. soc_info->optional_clk_id[index],
  1015. soc_info->optional_clk[index], false,
  1016. soc_info,
  1017. soc_info->optional_clk_rate[index],
  1018. soc_info->optional_clk_name[index]);
  1019. if (rc) {
  1020. CAM_ERR(CAM_UTIL,
  1021. "Failed in registering shared clk Dev %s id %d",
  1022. soc_info->dev_name,
  1023. soc_info->optional_clk_id[index]);
  1024. goto error;
  1025. }
  1026. }
  1027. }
  1028. return 0;
  1029. error:
  1030. clk_put(soc_info->optional_clk[index]);
  1031. soc_info->optional_clk_rate[index] = 0;
  1032. soc_info->optional_clk[index] = NULL;
  1033. *clk_index = -1;
  1034. return rc;
  1035. }
  1036. int cam_soc_util_clk_enable(struct cam_hw_soc_info *soc_info,
  1037. bool optional_clk, int32_t clk_idx, int32_t apply_level,
  1038. unsigned long *applied_clock_rate)
  1039. {
  1040. int rc = 0;
  1041. struct clk *clk;
  1042. const char *clk_name;
  1043. int32_t clk_rate;
  1044. uint32_t shared_clk_mask;
  1045. uint32_t clk_id;
  1046. bool is_src_clk = false;
  1047. if (!soc_info || (clk_idx < 0) || (apply_level >= CAM_MAX_VOTE)) {
  1048. CAM_ERR(CAM_UTIL, "Invalid param %d %d", clk_idx, apply_level);
  1049. return -EINVAL;
  1050. }
  1051. if (optional_clk) {
  1052. clk = soc_info->optional_clk[clk_idx];
  1053. clk_name = soc_info->optional_clk_name[clk_idx];
  1054. clk_rate = (apply_level == -1) ?
  1055. 0 : soc_info->optional_clk_rate[clk_idx];
  1056. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1057. clk_id = soc_info->optional_clk_id[clk_idx];
  1058. } else {
  1059. clk = soc_info->clk[clk_idx];
  1060. clk_name = soc_info->clk_name[clk_idx];
  1061. clk_rate = (apply_level == -1) ?
  1062. 0 : soc_info->clk_rate[apply_level][clk_idx];
  1063. shared_clk_mask = soc_info->shared_clk_mask;
  1064. clk_id = soc_info->clk_id[clk_idx];
  1065. if (clk_idx == soc_info->src_clk_idx)
  1066. is_src_clk = true;
  1067. }
  1068. rc = cam_soc_util_set_clk_rate(soc_info, clk, clk_name, clk_rate,
  1069. CAM_IS_BIT_SET(shared_clk_mask, clk_idx), is_src_clk, clk_id,
  1070. applied_clock_rate);
  1071. if (rc)
  1072. return rc;
  1073. rc = clk_prepare_enable(clk);
  1074. if (rc) {
  1075. CAM_ERR(CAM_UTIL, "enable failed for %s: rc(%d)", clk_name, rc);
  1076. return rc;
  1077. }
  1078. return rc;
  1079. }
  1080. int cam_soc_util_clk_disable(struct cam_hw_soc_info *soc_info,
  1081. bool optional_clk, int32_t clk_idx)
  1082. {
  1083. struct clk *clk;
  1084. const char *clk_name;
  1085. uint32_t shared_clk_mask;
  1086. uint32_t clk_id;
  1087. if (!soc_info || (clk_idx < 0)) {
  1088. CAM_ERR(CAM_UTIL, "Invalid param %d", clk_idx);
  1089. return -EINVAL;
  1090. }
  1091. if (optional_clk) {
  1092. clk = soc_info->optional_clk[clk_idx];
  1093. clk_name = soc_info->optional_clk_name[clk_idx];
  1094. shared_clk_mask = soc_info->optional_shared_clk_mask;
  1095. clk_id = soc_info->optional_clk_id[clk_idx];
  1096. } else {
  1097. clk = soc_info->clk[clk_idx];
  1098. clk_name = soc_info->clk_name[clk_idx];
  1099. shared_clk_mask = soc_info->shared_clk_mask;
  1100. clk_id = soc_info->clk_id[clk_idx];
  1101. }
  1102. CAM_DBG(CAM_UTIL, "disable %s", clk_name);
  1103. clk_disable_unprepare(clk);
  1104. if (CAM_IS_BIT_SET(shared_clk_mask, clk_idx)) {
  1105. CAM_DBG(CAM_UTIL,
  1106. "Dev %s clk %s Disabling Shared clk, set 0 rate",
  1107. soc_info->dev_name, clk_name);
  1108. cam_soc_util_clk_wrapper_set_clk_rate(clk_id, soc_info, clk, 0);
  1109. } else if (soc_info->mmrm_handle && (!skip_mmrm_set_rate) &&
  1110. (soc_info->src_clk_idx == clk_idx)) {
  1111. CAM_DBG(CAM_UTIL,
  1112. "Dev %s Disabling %s clk, set 0 rate", soc_info->dev_name, clk_name);
  1113. cam_soc_util_set_rate_through_mmrm(
  1114. soc_info->mmrm_handle,
  1115. soc_info->is_nrt_dev,
  1116. 0, 0, 1);
  1117. }
  1118. return 0;
  1119. }
  1120. /**
  1121. * cam_soc_util_clk_enable_default()
  1122. *
  1123. * @brief: This function enables the default clocks present
  1124. * in soc_info
  1125. *
  1126. * @soc_info: Device soc struct to be populated
  1127. * @clk_level: Clk level to apply while enabling
  1128. *
  1129. * @return: success or failure
  1130. */
  1131. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  1132. enum cam_vote_level clk_level)
  1133. {
  1134. int i, rc = 0;
  1135. enum cam_vote_level apply_level;
  1136. unsigned long applied_clk_rate;
  1137. if ((soc_info->num_clk == 0) ||
  1138. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1139. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  1140. soc_info->num_clk);
  1141. return -EINVAL;
  1142. }
  1143. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  1144. &apply_level);
  1145. if (rc)
  1146. return rc;
  1147. if (soc_info->cam_cx_ipeak_enable)
  1148. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  1149. for (i = 0; i < soc_info->num_clk; i++) {
  1150. rc = cam_soc_util_clk_enable(soc_info, false, i, apply_level,
  1151. &applied_clk_rate);
  1152. if (rc)
  1153. goto clk_disable;
  1154. if (i == soc_info->src_clk_idx)
  1155. soc_info->applied_src_clk_rate = applied_clk_rate;
  1156. if (soc_info->cam_cx_ipeak_enable) {
  1157. CAM_DBG(CAM_UTIL,
  1158. "dev name = %s clk name = %s idx = %d\n"
  1159. "apply_level = %d clc idx = %d",
  1160. soc_info->dev_name, soc_info->clk_name[i], i,
  1161. apply_level, i);
  1162. }
  1163. }
  1164. return rc;
  1165. clk_disable:
  1166. if (soc_info->cam_cx_ipeak_enable)
  1167. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1168. for (i--; i >= 0; i--) {
  1169. cam_soc_util_clk_disable(soc_info, false, i);
  1170. }
  1171. return rc;
  1172. }
  1173. /**
  1174. * cam_soc_util_clk_disable_default()
  1175. *
  1176. * @brief: This function disables the default clocks present
  1177. * in soc_info
  1178. *
  1179. * @soc_info: device soc struct to be populated
  1180. *
  1181. * @return: success or failure
  1182. */
  1183. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info)
  1184. {
  1185. int i;
  1186. if (soc_info->num_clk == 0)
  1187. return;
  1188. if (soc_info->cam_cx_ipeak_enable)
  1189. cam_cx_ipeak_unvote_cx_ipeak(soc_info);
  1190. for (i = soc_info->num_clk - 1; i >= 0; i--)
  1191. cam_soc_util_clk_disable(soc_info, false, i);
  1192. }
  1193. /**
  1194. * cam_soc_util_get_dt_clk_info()
  1195. *
  1196. * @brief: Parse the DT and populate the Clock properties
  1197. *
  1198. * @soc_info: device soc struct to be populated
  1199. * @src_clk_str name of src clock that has rate control
  1200. *
  1201. * @return: success or failure
  1202. */
  1203. static int cam_soc_util_get_dt_clk_info(struct cam_hw_soc_info *soc_info)
  1204. {
  1205. struct device_node *of_node = NULL;
  1206. int count;
  1207. int num_clk_rates, num_clk_levels;
  1208. int i, j, rc;
  1209. int32_t num_clk_level_strings;
  1210. const char *src_clk_str = NULL;
  1211. const char *scl_clk_str = NULL;
  1212. const char *clk_control_debugfs = NULL;
  1213. const char *clk_cntl_lvl_string = NULL;
  1214. enum cam_vote_level level;
  1215. int shared_clk_cnt;
  1216. struct of_phandle_args clk_args = {0};
  1217. if (!soc_info || !soc_info->dev)
  1218. return -EINVAL;
  1219. of_node = soc_info->dev->of_node;
  1220. if (!of_property_read_bool(of_node, "use-shared-clk")) {
  1221. CAM_DBG(CAM_UTIL, "No shared clk parameter defined");
  1222. soc_info->use_shared_clk = false;
  1223. } else {
  1224. soc_info->use_shared_clk = true;
  1225. }
  1226. count = of_property_count_strings(of_node, "clock-names");
  1227. CAM_DBG(CAM_UTIL, "E: dev_name = %s count = %d",
  1228. soc_info->dev_name, count);
  1229. if (count > CAM_SOC_MAX_CLK) {
  1230. CAM_ERR(CAM_UTIL, "invalid count of clocks, count=%d", count);
  1231. rc = -EINVAL;
  1232. return rc;
  1233. }
  1234. if (count <= 0) {
  1235. CAM_DBG(CAM_UTIL, "No clock-names found");
  1236. count = 0;
  1237. soc_info->num_clk = count;
  1238. return 0;
  1239. }
  1240. soc_info->num_clk = count;
  1241. for (i = 0; i < count; i++) {
  1242. rc = of_property_read_string_index(of_node, "clock-names",
  1243. i, &(soc_info->clk_name[i]));
  1244. CAM_DBG(CAM_UTIL, "clock-names[%d] = %s",
  1245. i, soc_info->clk_name[i]);
  1246. if (rc) {
  1247. CAM_ERR(CAM_UTIL,
  1248. "i= %d count= %d reading clock-names failed",
  1249. i, count);
  1250. return rc;
  1251. }
  1252. }
  1253. num_clk_rates = of_property_count_u32_elems(of_node, "clock-rates");
  1254. if (num_clk_rates <= 0) {
  1255. CAM_ERR(CAM_UTIL, "reading clock-rates count failed");
  1256. return -EINVAL;
  1257. }
  1258. if ((num_clk_rates % soc_info->num_clk) != 0) {
  1259. CAM_ERR(CAM_UTIL,
  1260. "mismatch clk/rates, No of clocks=%d, No of rates=%d",
  1261. soc_info->num_clk, num_clk_rates);
  1262. return -EINVAL;
  1263. }
  1264. num_clk_levels = (num_clk_rates / soc_info->num_clk);
  1265. num_clk_level_strings = of_property_count_strings(of_node,
  1266. "clock-cntl-level");
  1267. if (num_clk_level_strings != num_clk_levels) {
  1268. CAM_ERR(CAM_UTIL,
  1269. "Mismatch No of levels=%d, No of level string=%d",
  1270. num_clk_levels, num_clk_level_strings);
  1271. return -EINVAL;
  1272. }
  1273. soc_info->lowest_clk_level = CAM_TURBO_VOTE;
  1274. for (i = 0; i < num_clk_levels; i++) {
  1275. rc = of_property_read_string_index(of_node,
  1276. "clock-cntl-level", i, &clk_cntl_lvl_string);
  1277. if (rc) {
  1278. CAM_ERR(CAM_UTIL,
  1279. "Error reading clock-cntl-level, rc=%d", rc);
  1280. return rc;
  1281. }
  1282. rc = cam_soc_util_get_level_from_string(clk_cntl_lvl_string,
  1283. &level);
  1284. if (rc)
  1285. return rc;
  1286. CAM_DBG(CAM_UTIL,
  1287. "[%d] : %s %d", i, clk_cntl_lvl_string, level);
  1288. soc_info->clk_level_valid[level] = true;
  1289. for (j = 0; j < soc_info->num_clk; j++) {
  1290. rc = of_property_read_u32_index(of_node, "clock-rates",
  1291. ((i * soc_info->num_clk) + j),
  1292. &soc_info->clk_rate[level][j]);
  1293. if (rc) {
  1294. CAM_ERR(CAM_UTIL,
  1295. "Error reading clock-rates, rc=%d",
  1296. rc);
  1297. return rc;
  1298. }
  1299. soc_info->clk_rate[level][j] =
  1300. (soc_info->clk_rate[level][j] == 0) ?
  1301. (int32_t)NO_SET_RATE :
  1302. soc_info->clk_rate[level][j];
  1303. CAM_DBG(CAM_UTIL, "soc_info->clk_rate[%d][%d] = %d",
  1304. level, j,
  1305. soc_info->clk_rate[level][j]);
  1306. }
  1307. if ((level > CAM_MINSVS_VOTE) &&
  1308. (level < soc_info->lowest_clk_level))
  1309. soc_info->lowest_clk_level = level;
  1310. }
  1311. soc_info->src_clk_idx = -1;
  1312. rc = of_property_read_string_index(of_node, "src-clock-name", 0,
  1313. &src_clk_str);
  1314. if (rc || !src_clk_str) {
  1315. CAM_DBG(CAM_UTIL, "No src_clk_str found");
  1316. rc = 0;
  1317. goto end;
  1318. }
  1319. for (i = 0; i < soc_info->num_clk; i++) {
  1320. if (strcmp(soc_info->clk_name[i], src_clk_str) == 0) {
  1321. soc_info->src_clk_idx = i;
  1322. CAM_DBG(CAM_UTIL, "src clock = %s, index = %d",
  1323. src_clk_str, i);
  1324. }
  1325. rc = of_parse_phandle_with_args(of_node, "clocks",
  1326. "#clock-cells", i, &clk_args);
  1327. if (rc) {
  1328. CAM_ERR(CAM_CPAS,
  1329. "failed to clock info rc=%d", rc);
  1330. rc = -EINVAL;
  1331. goto end;
  1332. }
  1333. soc_info->clk_id[i] = clk_args.args[0];
  1334. of_node_put(clk_args.np);
  1335. CAM_DBG(CAM_UTIL, "Dev %s clk %s id %d",
  1336. soc_info->dev_name, soc_info->clk_name[i],
  1337. soc_info->clk_id[i]);
  1338. }
  1339. CAM_DBG(CAM_UTIL, "Dev %s src_clk_idx %d, lowest_clk_level %d",
  1340. soc_info->dev_name, soc_info->src_clk_idx,
  1341. soc_info->lowest_clk_level);
  1342. soc_info->shared_clk_mask = 0;
  1343. shared_clk_cnt = of_property_count_u32_elems(of_node, "shared-clks");
  1344. if (shared_clk_cnt <= 0) {
  1345. CAM_DBG(CAM_UTIL, "Dev %s, no shared clks", soc_info->dev_name);
  1346. } else if (shared_clk_cnt != count) {
  1347. CAM_ERR(CAM_UTIL, "Dev %s, incorrect shared clock count %d %d",
  1348. soc_info->dev_name, shared_clk_cnt, count);
  1349. rc = -EINVAL;
  1350. goto end;
  1351. } else {
  1352. uint32_t shared_clk_val;
  1353. for (i = 0; i < shared_clk_cnt; i++) {
  1354. rc = of_property_read_u32_index(of_node,
  1355. "shared-clks", i, &shared_clk_val);
  1356. if (rc || (shared_clk_val > 1)) {
  1357. CAM_ERR(CAM_UTIL,
  1358. "Incorrect shared clk info at %d, val=%d, count=%d",
  1359. i, shared_clk_val, shared_clk_cnt);
  1360. rc = -EINVAL;
  1361. goto end;
  1362. }
  1363. if (shared_clk_val)
  1364. CAM_SET_BIT(soc_info->shared_clk_mask, i);
  1365. }
  1366. CAM_DBG(CAM_UTIL, "Dev %s shared clk mask 0x%x",
  1367. soc_info->dev_name, soc_info->shared_clk_mask);
  1368. }
  1369. /* scalable clk info parsing */
  1370. soc_info->scl_clk_count = 0;
  1371. soc_info->scl_clk_count = of_property_count_strings(of_node,
  1372. "scl-clk-names");
  1373. if ((soc_info->scl_clk_count <= 0) ||
  1374. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1375. if (soc_info->scl_clk_count == -EINVAL) {
  1376. CAM_DBG(CAM_UTIL, "scl_clk_name prop not avialable");
  1377. } else if ((soc_info->scl_clk_count == -ENODATA) ||
  1378. (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) {
  1379. CAM_ERR(CAM_UTIL, "Invalid scl_clk_count: %d",
  1380. soc_info->scl_clk_count);
  1381. return -EINVAL;
  1382. }
  1383. CAM_DBG(CAM_UTIL, "Invalid scl_clk count: %d",
  1384. soc_info->scl_clk_count);
  1385. soc_info->scl_clk_count = -1;
  1386. } else {
  1387. CAM_DBG(CAM_UTIL, "No of scalable clocks: %d",
  1388. soc_info->scl_clk_count);
  1389. for (i = 0; i < soc_info->scl_clk_count; i++) {
  1390. rc = of_property_read_string_index(of_node,
  1391. "scl-clk-names", i,
  1392. (const char **)&scl_clk_str);
  1393. if (rc || !scl_clk_str) {
  1394. CAM_WARN(CAM_UTIL, "scl_clk_str is NULL");
  1395. soc_info->scl_clk_idx[i] = -1;
  1396. continue;
  1397. }
  1398. for (j = 0; j < soc_info->num_clk; j++) {
  1399. if (strnstr(scl_clk_str, soc_info->clk_name[j],
  1400. strlen(scl_clk_str))) {
  1401. soc_info->scl_clk_idx[i] = j;
  1402. CAM_DBG(CAM_UTIL,
  1403. "scl clock = %s, index = %d",
  1404. scl_clk_str, j);
  1405. break;
  1406. }
  1407. }
  1408. }
  1409. }
  1410. rc = of_property_read_string_index(of_node,
  1411. "clock-control-debugfs", 0, &clk_control_debugfs);
  1412. if (rc || !clk_control_debugfs) {
  1413. CAM_DBG(CAM_UTIL, "No clock_control_debugfs property found");
  1414. rc = 0;
  1415. goto end;
  1416. }
  1417. if (strcmp("true", clk_control_debugfs) == 0)
  1418. soc_info->clk_control_enable = true;
  1419. CAM_DBG(CAM_UTIL, "X: dev_name = %s count = %d",
  1420. soc_info->dev_name, count);
  1421. end:
  1422. return rc;
  1423. }
  1424. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  1425. enum cam_vote_level clk_level, bool do_not_set_src_clk)
  1426. {
  1427. int i, rc = 0;
  1428. enum cam_vote_level apply_level;
  1429. unsigned long applied_clk_rate;
  1430. if ((soc_info->num_clk == 0) ||
  1431. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  1432. CAM_ERR(CAM_UTIL, "Invalid number of clock %d",
  1433. soc_info->num_clk);
  1434. return -EINVAL;
  1435. }
  1436. rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level,
  1437. &apply_level);
  1438. if (rc)
  1439. return rc;
  1440. if (soc_info->cam_cx_ipeak_enable)
  1441. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level);
  1442. for (i = 0; i < soc_info->num_clk; i++) {
  1443. if (do_not_set_src_clk && (i == soc_info->src_clk_idx)) {
  1444. CAM_DBG(CAM_UTIL, "Skipping set rate for src clk %s",
  1445. soc_info->clk_name[i]);
  1446. continue;
  1447. }
  1448. CAM_DBG(CAM_UTIL, "Set rate for clk %s rate %d",
  1449. soc_info->clk_name[i],
  1450. soc_info->clk_rate[apply_level][i]);
  1451. rc = cam_soc_util_set_clk_rate(soc_info, soc_info->clk[i],
  1452. soc_info->clk_name[i],
  1453. soc_info->clk_rate[apply_level][i],
  1454. CAM_IS_BIT_SET(soc_info->shared_clk_mask, i),
  1455. (i == soc_info->src_clk_idx) ? true : false,
  1456. soc_info->clk_id[i],
  1457. &applied_clk_rate);
  1458. if (rc < 0) {
  1459. CAM_DBG(CAM_UTIL,
  1460. "dev name = %s clk_name = %s idx = %d\n"
  1461. "apply_level = %d",
  1462. soc_info->dev_name, soc_info->clk_name[i],
  1463. i, apply_level);
  1464. if (soc_info->cam_cx_ipeak_enable)
  1465. cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0);
  1466. break;
  1467. }
  1468. if (i == soc_info->src_clk_idx)
  1469. soc_info->applied_src_clk_rate = applied_clk_rate;
  1470. }
  1471. return rc;
  1472. };
  1473. static int cam_soc_util_get_dt_gpio_req_tbl(struct device_node *of_node,
  1474. struct cam_soc_gpio_data *gconf, uint16_t *gpio_array,
  1475. uint16_t gpio_array_size)
  1476. {
  1477. int32_t rc = 0, i = 0;
  1478. uint32_t count = 0;
  1479. uint32_t *val_array = NULL;
  1480. if (!of_get_property(of_node, "gpio-req-tbl-num", &count))
  1481. return 0;
  1482. count /= sizeof(uint32_t);
  1483. if (!count) {
  1484. CAM_ERR(CAM_UTIL, "gpio-req-tbl-num 0");
  1485. return 0;
  1486. }
  1487. val_array = kcalloc(count, sizeof(uint32_t), GFP_KERNEL);
  1488. if (!val_array)
  1489. return -ENOMEM;
  1490. gconf->cam_gpio_req_tbl = kcalloc(count, sizeof(struct gpio),
  1491. GFP_KERNEL);
  1492. if (!gconf->cam_gpio_req_tbl) {
  1493. rc = -ENOMEM;
  1494. goto free_val_array;
  1495. }
  1496. gconf->cam_gpio_req_tbl_size = count;
  1497. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-num",
  1498. val_array, count);
  1499. if (rc) {
  1500. CAM_ERR(CAM_UTIL, "failed in reading gpio-req-tbl-num, rc = %d",
  1501. rc);
  1502. goto free_gpio_req_tbl;
  1503. }
  1504. for (i = 0; i < count; i++) {
  1505. if (val_array[i] >= gpio_array_size) {
  1506. CAM_ERR(CAM_UTIL, "gpio req tbl index %d invalid",
  1507. val_array[i]);
  1508. goto free_gpio_req_tbl;
  1509. }
  1510. gconf->cam_gpio_req_tbl[i].gpio = gpio_array[val_array[i]];
  1511. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].gpio = %d", i,
  1512. gconf->cam_gpio_req_tbl[i].gpio);
  1513. }
  1514. rc = of_property_read_u32_array(of_node, "gpio-req-tbl-flags",
  1515. val_array, count);
  1516. if (rc) {
  1517. CAM_ERR(CAM_UTIL, "Failed in gpio-req-tbl-flags, rc %d", rc);
  1518. goto free_gpio_req_tbl;
  1519. }
  1520. for (i = 0; i < count; i++) {
  1521. gconf->cam_gpio_req_tbl[i].flags = val_array[i];
  1522. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].flags = %ld", i,
  1523. gconf->cam_gpio_req_tbl[i].flags);
  1524. }
  1525. for (i = 0; i < count; i++) {
  1526. rc = of_property_read_string_index(of_node,
  1527. "gpio-req-tbl-label", i,
  1528. &gconf->cam_gpio_req_tbl[i].label);
  1529. if (rc) {
  1530. CAM_ERR(CAM_UTIL, "Failed rc %d", rc);
  1531. goto free_gpio_req_tbl;
  1532. }
  1533. CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].label = %s", i,
  1534. gconf->cam_gpio_req_tbl[i].label);
  1535. }
  1536. kfree(val_array);
  1537. return rc;
  1538. free_gpio_req_tbl:
  1539. kfree(gconf->cam_gpio_req_tbl);
  1540. free_val_array:
  1541. kfree(val_array);
  1542. gconf->cam_gpio_req_tbl_size = 0;
  1543. return rc;
  1544. }
  1545. static int cam_soc_util_get_gpio_info(struct cam_hw_soc_info *soc_info)
  1546. {
  1547. int32_t rc = 0, i = 0;
  1548. uint16_t *gpio_array = NULL;
  1549. int16_t gpio_array_size = 0;
  1550. struct cam_soc_gpio_data *gconf = NULL;
  1551. struct device_node *of_node = NULL;
  1552. if (!soc_info || !soc_info->dev)
  1553. return -EINVAL;
  1554. of_node = soc_info->dev->of_node;
  1555. /* Validate input parameters */
  1556. if (!of_node) {
  1557. CAM_ERR(CAM_UTIL, "Invalid param of_node");
  1558. return -EINVAL;
  1559. }
  1560. gpio_array_size = of_gpio_count(of_node);
  1561. if (gpio_array_size <= 0)
  1562. return 0;
  1563. CAM_DBG(CAM_UTIL, "gpio count %d", gpio_array_size);
  1564. gpio_array = kcalloc(gpio_array_size, sizeof(uint16_t), GFP_KERNEL);
  1565. if (!gpio_array)
  1566. goto free_gpio_conf;
  1567. for (i = 0; i < gpio_array_size; i++) {
  1568. gpio_array[i] = of_get_gpio(of_node, i);
  1569. CAM_DBG(CAM_UTIL, "gpio_array[%d] = %d", i, gpio_array[i]);
  1570. }
  1571. gconf = kzalloc(sizeof(*gconf), GFP_KERNEL);
  1572. if (!gconf)
  1573. return -ENOMEM;
  1574. rc = cam_soc_util_get_dt_gpio_req_tbl(of_node, gconf, gpio_array,
  1575. gpio_array_size);
  1576. if (rc) {
  1577. CAM_ERR(CAM_UTIL, "failed in msm_camera_get_dt_gpio_req_tbl");
  1578. goto free_gpio_array;
  1579. }
  1580. gconf->cam_gpio_common_tbl = kcalloc(gpio_array_size,
  1581. sizeof(struct gpio), GFP_KERNEL);
  1582. if (!gconf->cam_gpio_common_tbl) {
  1583. rc = -ENOMEM;
  1584. goto free_gpio_array;
  1585. }
  1586. for (i = 0; i < gpio_array_size; i++)
  1587. gconf->cam_gpio_common_tbl[i].gpio = gpio_array[i];
  1588. gconf->cam_gpio_common_tbl_size = gpio_array_size;
  1589. soc_info->gpio_data = gconf;
  1590. kfree(gpio_array);
  1591. return rc;
  1592. free_gpio_array:
  1593. kfree(gpio_array);
  1594. free_gpio_conf:
  1595. kfree(gconf);
  1596. soc_info->gpio_data = NULL;
  1597. return rc;
  1598. }
  1599. static int cam_soc_util_request_gpio_table(
  1600. struct cam_hw_soc_info *soc_info, bool gpio_en)
  1601. {
  1602. int rc = 0, i = 0;
  1603. uint8_t size = 0;
  1604. struct cam_soc_gpio_data *gpio_conf =
  1605. soc_info->gpio_data;
  1606. struct gpio *gpio_tbl = NULL;
  1607. if (!gpio_conf) {
  1608. CAM_DBG(CAM_UTIL, "No GPIO entry");
  1609. return 0;
  1610. }
  1611. if (gpio_conf->cam_gpio_common_tbl_size <= 0) {
  1612. CAM_ERR(CAM_UTIL, "GPIO table size is invalid");
  1613. return -EINVAL;
  1614. }
  1615. size = gpio_conf->cam_gpio_req_tbl_size;
  1616. gpio_tbl = gpio_conf->cam_gpio_req_tbl;
  1617. if (!gpio_tbl || !size) {
  1618. CAM_ERR(CAM_UTIL, "Invalid gpio_tbl %pK / size %d",
  1619. gpio_tbl, size);
  1620. return -EINVAL;
  1621. }
  1622. for (i = 0; i < size; i++) {
  1623. CAM_DBG(CAM_UTIL, "i=%d, gpio=%d dir=%ld", i,
  1624. gpio_tbl[i].gpio, gpio_tbl[i].flags);
  1625. }
  1626. if (gpio_en) {
  1627. for (i = 0; i < size; i++) {
  1628. rc = gpio_request_one(gpio_tbl[i].gpio,
  1629. gpio_tbl[i].flags, gpio_tbl[i].label);
  1630. if (rc) {
  1631. /*
  1632. * After GPIO request fails, contine to
  1633. * apply new gpios, outout a error message
  1634. * for driver bringup debug
  1635. */
  1636. CAM_ERR(CAM_UTIL, "gpio %d:%s request fails",
  1637. gpio_tbl[i].gpio, gpio_tbl[i].label);
  1638. }
  1639. }
  1640. } else {
  1641. gpio_free_array(gpio_tbl, size);
  1642. }
  1643. return rc;
  1644. }
  1645. static int cam_soc_util_get_dt_regulator_info
  1646. (struct cam_hw_soc_info *soc_info)
  1647. {
  1648. int rc = 0, count = 0, i = 0;
  1649. struct device_node *of_node = NULL;
  1650. if (!soc_info || !soc_info->dev) {
  1651. CAM_ERR(CAM_UTIL, "Invalid parameters");
  1652. return -EINVAL;
  1653. }
  1654. of_node = soc_info->dev->of_node;
  1655. soc_info->num_rgltr = 0;
  1656. count = of_property_count_strings(of_node, "regulator-names");
  1657. if (count != -EINVAL) {
  1658. if (count <= 0) {
  1659. CAM_ERR(CAM_UTIL, "no regulators found");
  1660. count = 0;
  1661. return -EINVAL;
  1662. }
  1663. soc_info->num_rgltr = count;
  1664. } else {
  1665. CAM_DBG(CAM_UTIL, "No regulators node found");
  1666. return 0;
  1667. }
  1668. for (i = 0; i < soc_info->num_rgltr; i++) {
  1669. rc = of_property_read_string_index(of_node,
  1670. "regulator-names", i, &soc_info->rgltr_name[i]);
  1671. CAM_DBG(CAM_UTIL, "rgltr_name[%d] = %s",
  1672. i, soc_info->rgltr_name[i]);
  1673. if (rc) {
  1674. CAM_ERR(CAM_UTIL, "no regulator resource at cnt=%d", i);
  1675. return -ENODEV;
  1676. }
  1677. }
  1678. if (!of_property_read_bool(of_node, "rgltr-cntrl-support")) {
  1679. CAM_DBG(CAM_UTIL, "No regulator control parameter defined");
  1680. soc_info->rgltr_ctrl_support = false;
  1681. return 0;
  1682. }
  1683. soc_info->rgltr_ctrl_support = true;
  1684. rc = of_property_read_u32_array(of_node, "rgltr-min-voltage",
  1685. soc_info->rgltr_min_volt, soc_info->num_rgltr);
  1686. if (rc) {
  1687. CAM_ERR(CAM_UTIL, "No minimum volatage value found, rc=%d", rc);
  1688. return -EINVAL;
  1689. }
  1690. rc = of_property_read_u32_array(of_node, "rgltr-max-voltage",
  1691. soc_info->rgltr_max_volt, soc_info->num_rgltr);
  1692. if (rc) {
  1693. CAM_ERR(CAM_UTIL, "No maximum volatage value found, rc=%d", rc);
  1694. return -EINVAL;
  1695. }
  1696. rc = of_property_read_u32_array(of_node, "rgltr-load-current",
  1697. soc_info->rgltr_op_mode, soc_info->num_rgltr);
  1698. if (rc) {
  1699. CAM_ERR(CAM_UTIL, "No Load curent found rc=%d", rc);
  1700. return -EINVAL;
  1701. }
  1702. return rc;
  1703. }
  1704. #ifdef CONFIG_CAM_PRESIL
  1705. static uint32_t next_dummy_irq_line_num = 0x000f;
  1706. struct resource dummy_irq_line[512];
  1707. #endif
  1708. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info)
  1709. {
  1710. struct device_node *of_node = NULL;
  1711. int count = 0, i = 0, rc = 0;
  1712. if (!soc_info || !soc_info->dev)
  1713. return -EINVAL;
  1714. of_node = soc_info->dev->of_node;
  1715. rc = of_property_read_u32(of_node, "cell-index", &soc_info->index);
  1716. if (rc) {
  1717. CAM_ERR(CAM_UTIL, "device %s failed to read cell-index",
  1718. soc_info->dev_name);
  1719. return rc;
  1720. }
  1721. count = of_property_count_strings(of_node, "reg-names");
  1722. if (count <= 0) {
  1723. CAM_DBG(CAM_UTIL, "no reg-names found for: %s",
  1724. soc_info->dev_name);
  1725. count = 0;
  1726. }
  1727. soc_info->num_mem_block = count;
  1728. for (i = 0; i < soc_info->num_mem_block; i++) {
  1729. rc = of_property_read_string_index(of_node, "reg-names", i,
  1730. &soc_info->mem_block_name[i]);
  1731. if (rc) {
  1732. CAM_ERR(CAM_UTIL, "failed to read reg-names at %d", i);
  1733. return rc;
  1734. }
  1735. soc_info->mem_block[i] =
  1736. platform_get_resource_byname(soc_info->pdev,
  1737. IORESOURCE_MEM, soc_info->mem_block_name[i]);
  1738. if (!soc_info->mem_block[i]) {
  1739. CAM_ERR(CAM_UTIL, "no mem resource by name %s",
  1740. soc_info->mem_block_name[i]);
  1741. rc = -ENODEV;
  1742. return rc;
  1743. }
  1744. }
  1745. rc = of_property_read_string(of_node, "label", &soc_info->label_name);
  1746. if (rc)
  1747. CAM_DBG(CAM_UTIL, "Label is not available in the node: %d", rc);
  1748. if (soc_info->num_mem_block > 0) {
  1749. rc = of_property_read_u32_array(of_node, "reg-cam-base",
  1750. soc_info->mem_block_cam_base, soc_info->num_mem_block);
  1751. if (rc) {
  1752. CAM_ERR(CAM_UTIL, "Error reading register offsets");
  1753. return rc;
  1754. }
  1755. }
  1756. rc = of_property_read_string_index(of_node, "interrupt-names", 0,
  1757. &soc_info->irq_name);
  1758. if (rc) {
  1759. CAM_DBG(CAM_UTIL, "No interrupt line preset for: %s",
  1760. soc_info->dev_name);
  1761. rc = 0;
  1762. } else {
  1763. soc_info->irq_line =
  1764. platform_get_resource_byname(soc_info->pdev,
  1765. IORESOURCE_IRQ, soc_info->irq_name);
  1766. if (!soc_info->irq_line) {
  1767. CAM_ERR(CAM_UTIL, "no irq resource");
  1768. #ifndef CONFIG_CAM_PRESIL
  1769. rc = -ENODEV;
  1770. return rc;
  1771. #else
  1772. /* Pre-sil for new devices not present on old */
  1773. soc_info->irq_line =
  1774. &dummy_irq_line[next_dummy_irq_line_num++];
  1775. CAM_DBG(CAM_PRESIL, "interrupt line for dev %s irq name %s number %d",
  1776. soc_info->dev_name, soc_info->irq_name,
  1777. soc_info->irq_line->start);
  1778. #endif
  1779. }
  1780. }
  1781. rc = of_property_read_string_index(of_node, "compatible", 0,
  1782. (const char **)&soc_info->compatible);
  1783. if (rc) {
  1784. CAM_DBG(CAM_UTIL, "No compatible string present for: %s",
  1785. soc_info->dev_name);
  1786. rc = 0;
  1787. }
  1788. soc_info->is_nrt_dev = false;
  1789. if (of_property_read_bool(of_node, "nrt-device"))
  1790. soc_info->is_nrt_dev = true;
  1791. CAM_DBG(CAM_UTIL, "Dev %s, nrt_dev %d",
  1792. soc_info->dev_name, soc_info->is_nrt_dev);
  1793. rc = cam_soc_util_get_dt_regulator_info(soc_info);
  1794. if (rc)
  1795. return rc;
  1796. rc = cam_soc_util_get_dt_clk_info(soc_info);
  1797. if (rc)
  1798. return rc;
  1799. rc = cam_soc_util_get_gpio_info(soc_info);
  1800. if (rc)
  1801. return rc;
  1802. if (of_find_property(of_node, "qcom,cam-cx-ipeak", NULL))
  1803. rc = cam_cx_ipeak_register_cx_ipeak(soc_info);
  1804. return rc;
  1805. }
  1806. /**
  1807. * cam_soc_util_get_regulator()
  1808. *
  1809. * @brief: Get regulator resource named vdd
  1810. *
  1811. * @dev: Device associated with regulator
  1812. * @reg: Return pointer to be filled with regulator on success
  1813. * @rgltr_name: Name of regulator to get
  1814. *
  1815. * @return: 0 for Success, negative value for failure
  1816. */
  1817. static int cam_soc_util_get_regulator(struct device *dev,
  1818. struct regulator **reg, const char *rgltr_name)
  1819. {
  1820. int rc = 0;
  1821. *reg = regulator_get(dev, rgltr_name);
  1822. if (IS_ERR_OR_NULL(*reg)) {
  1823. rc = PTR_ERR(*reg);
  1824. rc = rc ? rc : -EINVAL;
  1825. CAM_ERR(CAM_UTIL, "Regulator %s get failed %d", rgltr_name, rc);
  1826. *reg = NULL;
  1827. }
  1828. return rc;
  1829. }
  1830. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  1831. const char *rgltr_name, uint32_t rgltr_min_volt,
  1832. uint32_t rgltr_max_volt, uint32_t rgltr_op_mode,
  1833. uint32_t rgltr_delay_ms)
  1834. {
  1835. int32_t rc = 0;
  1836. if (!rgltr) {
  1837. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  1838. return -EINVAL;
  1839. }
  1840. rc = regulator_disable(rgltr);
  1841. if (rc) {
  1842. CAM_ERR(CAM_UTIL, "%s regulator disable failed", rgltr_name);
  1843. return rc;
  1844. }
  1845. if (rgltr_delay_ms > 20)
  1846. msleep(rgltr_delay_ms);
  1847. else if (rgltr_delay_ms)
  1848. usleep_range(rgltr_delay_ms * 1000,
  1849. (rgltr_delay_ms * 1000) + 1000);
  1850. if (regulator_count_voltages(rgltr) > 0) {
  1851. regulator_set_load(rgltr, 0);
  1852. regulator_set_voltage(rgltr, 0, rgltr_max_volt);
  1853. }
  1854. return rc;
  1855. }
  1856. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  1857. const char *rgltr_name,
  1858. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  1859. uint32_t rgltr_op_mode, uint32_t rgltr_delay)
  1860. {
  1861. int32_t rc = 0;
  1862. if (!rgltr) {
  1863. CAM_ERR(CAM_UTIL, "Invalid NULL parameter");
  1864. return -EINVAL;
  1865. }
  1866. if (regulator_count_voltages(rgltr) > 0) {
  1867. CAM_DBG(CAM_UTIL, "voltage min=%d, max=%d",
  1868. rgltr_min_volt, rgltr_max_volt);
  1869. rc = regulator_set_voltage(
  1870. rgltr, rgltr_min_volt, rgltr_max_volt);
  1871. if (rc) {
  1872. CAM_ERR(CAM_UTIL, "%s set voltage failed", rgltr_name);
  1873. return rc;
  1874. }
  1875. rc = regulator_set_load(rgltr, rgltr_op_mode);
  1876. if (rc) {
  1877. CAM_ERR(CAM_UTIL, "%s set optimum mode failed",
  1878. rgltr_name);
  1879. return rc;
  1880. }
  1881. }
  1882. rc = regulator_enable(rgltr);
  1883. if (rc) {
  1884. CAM_ERR(CAM_UTIL, "%s regulator_enable failed", rgltr_name);
  1885. return rc;
  1886. }
  1887. if (rgltr_delay > 20)
  1888. msleep(rgltr_delay);
  1889. else if (rgltr_delay)
  1890. usleep_range(rgltr_delay * 1000,
  1891. (rgltr_delay * 1000) + 1000);
  1892. return rc;
  1893. }
  1894. int cam_soc_util_select_pinctrl_state(struct cam_hw_soc_info *soc_info,
  1895. int pctrl_idx, bool active)
  1896. {
  1897. int rc = 0;
  1898. struct cam_soc_pinctrl_info *pctrl_info = &soc_info->pinctrl_info;
  1899. if (pctrl_idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  1900. CAM_ERR(CAM_UTIL, "Invalid Map idx: %d max supported: %d",
  1901. pctrl_idx, CAM_SOC_MAX_PINCTRL_MAP);
  1902. return -EINVAL;
  1903. }
  1904. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_active &&
  1905. active &&
  1906. !pctrl_info->pctrl_state[pctrl_idx].is_active) {
  1907. rc = pinctrl_select_state(pctrl_info->pinctrl,
  1908. pctrl_info->pctrl_state[pctrl_idx].gpio_state_active);
  1909. if (rc)
  1910. CAM_ERR(CAM_UTIL,
  1911. "Pinctrl active state transition failed: rc: %d",
  1912. rc);
  1913. else {
  1914. pctrl_info->pctrl_state[pctrl_idx].is_active = true;
  1915. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in active state",
  1916. pctrl_idx);
  1917. }
  1918. }
  1919. if (pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend &&
  1920. !active &&
  1921. pctrl_info->pctrl_state[pctrl_idx].is_active) {
  1922. rc = pinctrl_select_state(pctrl_info->pinctrl,
  1923. pctrl_info->pctrl_state[pctrl_idx].gpio_state_suspend);
  1924. if (rc)
  1925. CAM_ERR(CAM_UTIL,
  1926. "Pinctrl suspend state transition failed: rc: %d",
  1927. rc);
  1928. else {
  1929. pctrl_info->pctrl_state[pctrl_idx].is_active = false;
  1930. CAM_DBG(CAM_UTIL, "Pctrl_idx: %d is in suspend state",
  1931. pctrl_idx);
  1932. }
  1933. }
  1934. return rc;
  1935. }
  1936. static int cam_soc_util_request_pinctrl(
  1937. struct cam_hw_soc_info *soc_info)
  1938. {
  1939. struct cam_soc_pinctrl_info *device_pctrl = &soc_info->pinctrl_info;
  1940. struct device *dev = soc_info->dev;
  1941. struct device_node *of_node = dev->of_node;
  1942. uint32_t i = 0;
  1943. int rc = 0;
  1944. const char *name;
  1945. uint32_t idx;
  1946. char pctrl_active[50];
  1947. char pctrl_suspend[50];
  1948. int32_t num_of_map_idx = 0;
  1949. int32_t num_of_string = 0;
  1950. device_pctrl->pinctrl = devm_pinctrl_get(dev);
  1951. if (IS_ERR_OR_NULL(device_pctrl->pinctrl)) {
  1952. CAM_DBG(CAM_UTIL, "Pinctrl not available");
  1953. device_pctrl->pinctrl = NULL;
  1954. return 0;
  1955. }
  1956. num_of_map_idx = of_property_count_u32_elems(
  1957. of_node, "pctrl-idx-mapping");
  1958. if (num_of_map_idx <= 0) {
  1959. CAM_ERR(CAM_UTIL,
  1960. "Reading pctrl-idx-mapping failed");
  1961. return -EINVAL;
  1962. }
  1963. num_of_string = of_property_count_strings(
  1964. of_node, "pctrl-map-names");
  1965. if (num_of_string <= 0) {
  1966. CAM_ERR(CAM_UTIL, "no pinctrl-mapping found for: %s",
  1967. soc_info->dev_name);
  1968. device_pctrl->pinctrl = NULL;
  1969. return -EINVAL;
  1970. }
  1971. if (num_of_map_idx != num_of_string) {
  1972. CAM_ERR(CAM_UTIL,
  1973. "Incorrect inputs mapping-idx count: %d mapping-names: %d",
  1974. num_of_map_idx, num_of_string);
  1975. device_pctrl->pinctrl = NULL;
  1976. return -EINVAL;
  1977. }
  1978. if (num_of_map_idx > CAM_SOC_MAX_PINCTRL_MAP) {
  1979. CAM_ERR(CAM_UTIL, "Invalid mapping %u max supported: %d",
  1980. num_of_map_idx, CAM_SOC_MAX_PINCTRL_MAP);
  1981. return -EINVAL;
  1982. }
  1983. for (i = 0; i < num_of_map_idx; i++) {
  1984. memset(pctrl_active, '\0', sizeof(pctrl_active));
  1985. memset(pctrl_suspend, '\0', sizeof(pctrl_suspend));
  1986. of_property_read_u32_index(of_node,
  1987. "pctrl-idx-mapping", i, &idx);
  1988. if (idx >= CAM_SOC_MAX_PINCTRL_MAP) {
  1989. CAM_ERR(CAM_UTIL, "Invalid Index: %d max supported: %d",
  1990. idx, CAM_SOC_MAX_PINCTRL_MAP);
  1991. return -EINVAL;
  1992. }
  1993. rc = of_property_read_string_index(
  1994. of_node, "pctrl-map-names", i, &name);
  1995. if (rc) {
  1996. CAM_ERR(CAM_UTIL,
  1997. "failed to read pinctrl-mapping at %d", i);
  1998. return rc;
  1999. }
  2000. snprintf(pctrl_active, sizeof(pctrl_active),
  2001. "%s%s", name, "_active");
  2002. CAM_DBG(CAM_UTIL, "pctrl_active at index: %d name: %s",
  2003. i, pctrl_active);
  2004. snprintf(pctrl_suspend, sizeof(pctrl_suspend),
  2005. "%s%s", name, "_suspend");
  2006. CAM_DBG(CAM_UTIL, "pctrl_suspend at index: %d name: %s",
  2007. i, pctrl_suspend);
  2008. device_pctrl->pctrl_state[idx].gpio_state_active =
  2009. pinctrl_lookup_state(device_pctrl->pinctrl,
  2010. pctrl_active);
  2011. if (IS_ERR_OR_NULL(
  2012. device_pctrl->pctrl_state[idx].gpio_state_active)) {
  2013. CAM_ERR(CAM_UTIL,
  2014. "Failed to get the active state pinctrl handle");
  2015. device_pctrl->pctrl_state[idx].gpio_state_active =
  2016. NULL;
  2017. return -EINVAL;
  2018. }
  2019. device_pctrl->pctrl_state[idx].gpio_state_suspend =
  2020. pinctrl_lookup_state(device_pctrl->pinctrl,
  2021. pctrl_suspend);
  2022. if (IS_ERR_OR_NULL(
  2023. device_pctrl->pctrl_state[idx].gpio_state_suspend)) {
  2024. CAM_ERR(CAM_UTIL,
  2025. "Failed to get the active state pinctrl handle");
  2026. device_pctrl->pctrl_state[idx].gpio_state_suspend = NULL;
  2027. return -EINVAL;
  2028. }
  2029. }
  2030. return 0;
  2031. }
  2032. static void cam_soc_util_release_pinctrl(struct cam_hw_soc_info *soc_info)
  2033. {
  2034. if (soc_info->pinctrl_info.pinctrl)
  2035. devm_pinctrl_put(soc_info->pinctrl_info.pinctrl);
  2036. }
  2037. static void cam_soc_util_regulator_disable_default(
  2038. struct cam_hw_soc_info *soc_info)
  2039. {
  2040. int j = 0;
  2041. uint32_t num_rgltr = soc_info->num_rgltr;
  2042. for (j = num_rgltr-1; j >= 0; j--) {
  2043. if (soc_info->rgltr_ctrl_support == true) {
  2044. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2045. soc_info->rgltr_name[j],
  2046. soc_info->rgltr_min_volt[j],
  2047. soc_info->rgltr_max_volt[j],
  2048. soc_info->rgltr_op_mode[j],
  2049. soc_info->rgltr_delay[j]);
  2050. } else {
  2051. if (soc_info->rgltr[j])
  2052. regulator_disable(soc_info->rgltr[j]);
  2053. }
  2054. }
  2055. }
  2056. static int cam_soc_util_regulator_enable_default(
  2057. struct cam_hw_soc_info *soc_info)
  2058. {
  2059. int j = 0, rc = 0;
  2060. uint32_t num_rgltr = soc_info->num_rgltr;
  2061. for (j = 0; j < num_rgltr; j++) {
  2062. if (soc_info->rgltr_ctrl_support == true) {
  2063. rc = cam_soc_util_regulator_enable(soc_info->rgltr[j],
  2064. soc_info->rgltr_name[j],
  2065. soc_info->rgltr_min_volt[j],
  2066. soc_info->rgltr_max_volt[j],
  2067. soc_info->rgltr_op_mode[j],
  2068. soc_info->rgltr_delay[j]);
  2069. } else {
  2070. if (soc_info->rgltr[j])
  2071. rc = regulator_enable(soc_info->rgltr[j]);
  2072. }
  2073. if (rc) {
  2074. CAM_ERR(CAM_UTIL, "%s enable failed",
  2075. soc_info->rgltr_name[j]);
  2076. goto disable_rgltr;
  2077. }
  2078. }
  2079. return rc;
  2080. disable_rgltr:
  2081. for (j--; j >= 0; j--) {
  2082. if (soc_info->rgltr_ctrl_support == true) {
  2083. cam_soc_util_regulator_disable(soc_info->rgltr[j],
  2084. soc_info->rgltr_name[j],
  2085. soc_info->rgltr_min_volt[j],
  2086. soc_info->rgltr_max_volt[j],
  2087. soc_info->rgltr_op_mode[j],
  2088. soc_info->rgltr_delay[j]);
  2089. } else {
  2090. if (soc_info->rgltr[j])
  2091. regulator_disable(soc_info->rgltr[j]);
  2092. }
  2093. }
  2094. return rc;
  2095. }
  2096. static bool cam_soc_util_is_presil_address_space(unsigned long mem_block_start)
  2097. {
  2098. if(mem_block_start >= CAM_SS_START_PRESIL && mem_block_start < CAM_SS_START)
  2099. return true;
  2100. return false;
  2101. }
  2102. #ifndef CONFIG_CAM_PRESIL
  2103. void __iomem * cam_soc_util_get_mem_base(
  2104. unsigned long mem_block_start,
  2105. unsigned long mem_block_size,
  2106. const char *mem_block_name,
  2107. uint32_t reserve_mem)
  2108. {
  2109. void __iomem * mem_base;
  2110. if (reserve_mem) {
  2111. if (!request_mem_region(mem_block_start,
  2112. mem_block_size,
  2113. mem_block_name)) {
  2114. CAM_ERR(CAM_UTIL,
  2115. "Error Mem region request Failed:%s",
  2116. mem_block_name);
  2117. return NULL;
  2118. }
  2119. }
  2120. mem_base = ioremap(mem_block_start, mem_block_size);
  2121. if (!mem_base) {
  2122. CAM_ERR(CAM_UTIL, "get mem base failed");
  2123. }
  2124. return mem_base;
  2125. }
  2126. int cam_soc_util_request_irq(struct device *dev,
  2127. unsigned int irq_line_start,
  2128. irq_handler_t handler,
  2129. unsigned long irqflags,
  2130. const char *irq_name,
  2131. void *irq_data,
  2132. unsigned long mem_block_start)
  2133. {
  2134. int rc;
  2135. rc = devm_request_irq(dev,
  2136. irq_line_start,
  2137. handler,
  2138. IRQF_TRIGGER_RISING,
  2139. irq_name,
  2140. irq_data);
  2141. if (rc) {
  2142. CAM_ERR(CAM_UTIL, "irq request fail rc %d", rc);
  2143. return -EBUSY;
  2144. }
  2145. disable_irq(irq_line_start);
  2146. return rc;
  2147. }
  2148. #else
  2149. void __iomem * cam_soc_util_get_mem_base(
  2150. unsigned long mem_block_start,
  2151. unsigned long mem_block_size,
  2152. const char *mem_block_name,
  2153. uint32_t reserve_mem)
  2154. {
  2155. void __iomem * mem_base;
  2156. if(cam_soc_util_is_presil_address_space(mem_block_start))
  2157. mem_base = (void __iomem *)mem_block_start;
  2158. else {
  2159. if (reserve_mem) {
  2160. if (!request_mem_region(mem_block_start,
  2161. mem_block_size,
  2162. mem_block_name)) {
  2163. CAM_ERR(CAM_UTIL,
  2164. "Error Mem region request Failed:%s",
  2165. mem_block_name);
  2166. return NULL;
  2167. }
  2168. }
  2169. mem_base = ioremap(mem_block_start, mem_block_size);
  2170. }
  2171. if (!mem_base) {
  2172. CAM_ERR(CAM_UTIL, "get mem base failed");
  2173. }
  2174. return mem_base;
  2175. }
  2176. int cam_soc_util_request_irq(struct device *dev,
  2177. unsigned int irq_line_start,
  2178. irq_handler_t handler,
  2179. unsigned long irqflags,
  2180. const char *irq_name,
  2181. void *irq_data,
  2182. unsigned long mem_block_start)
  2183. {
  2184. int rc;
  2185. if(cam_soc_util_is_presil_address_space(mem_block_start)) {
  2186. rc = devm_request_irq(dev,
  2187. irq_line_start,
  2188. handler,
  2189. irqflags,
  2190. irq_name,
  2191. irq_data);
  2192. if (rc) {
  2193. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2194. return -EBUSY;
  2195. }
  2196. disable_irq(irq_line_start);
  2197. rc = !(cam_presil_subscribe_device_irq(irq_line_start,
  2198. handler, irq_data, irq_name));
  2199. CAM_DBG(CAM_PRESIL, "Subscribe presil IRQ: rc=%d NUM=%d Name=%s handler=0x%x",
  2200. rc, irq_line_start, irq_name, handler);
  2201. if (rc) {
  2202. CAM_ERR(CAM_UTIL, "presil irq request fail");
  2203. return -EBUSY;
  2204. }
  2205. } else {
  2206. rc = devm_request_irq(dev,
  2207. irq_line_start,
  2208. handler,
  2209. irqflags,
  2210. irq_name,
  2211. irq_data);
  2212. if (rc) {
  2213. CAM_ERR(CAM_UTIL, "irq request fail");
  2214. return -EBUSY;
  2215. }
  2216. disable_irq(irq_line_start);
  2217. CAM_INFO(CAM_UTIL, "Subscribe for non-presil IRQ success");
  2218. }
  2219. CAM_INFO(CAM_UTIL, "returning IRQ for mem_block_start 0x%0x rc %d",
  2220. mem_block_start, rc);
  2221. return rc;
  2222. }
  2223. #endif
  2224. int cam_soc_util_request_platform_resource(
  2225. struct cam_hw_soc_info *soc_info,
  2226. irq_handler_t handler, void *irq_data)
  2227. {
  2228. int i = 0, rc = 0;
  2229. if (!soc_info || !soc_info->dev) {
  2230. CAM_ERR(CAM_UTIL, "Invalid parameters");
  2231. return -EINVAL;
  2232. }
  2233. for (i = 0; i < soc_info->num_mem_block; i++) {
  2234. soc_info->reg_map[i].mem_base = cam_soc_util_get_mem_base(
  2235. soc_info->mem_block[i]->start,
  2236. resource_size(soc_info->mem_block[i]),
  2237. soc_info->mem_block_name[i],
  2238. soc_info->reserve_mem);
  2239. if (!soc_info->reg_map[i].mem_base) {
  2240. CAM_ERR(CAM_UTIL, "i= %d base NULL", i);
  2241. rc = -ENOMEM;
  2242. goto unmap_base;
  2243. }
  2244. soc_info->reg_map[i].mem_cam_base =
  2245. soc_info->mem_block_cam_base[i];
  2246. soc_info->reg_map[i].size =
  2247. resource_size(soc_info->mem_block[i]);
  2248. soc_info->num_reg_map++;
  2249. }
  2250. for (i = 0; i < soc_info->num_rgltr; i++) {
  2251. if (soc_info->rgltr_name[i] == NULL) {
  2252. CAM_ERR(CAM_UTIL, "can't find regulator name");
  2253. goto put_regulator;
  2254. }
  2255. rc = cam_soc_util_get_regulator(soc_info->dev,
  2256. &soc_info->rgltr[i],
  2257. soc_info->rgltr_name[i]);
  2258. if (rc)
  2259. goto put_regulator;
  2260. }
  2261. if (soc_info->irq_line) {
  2262. rc = cam_soc_util_request_irq(soc_info->dev,
  2263. soc_info->irq_line->start,
  2264. handler, IRQF_TRIGGER_RISING,
  2265. soc_info->irq_name, irq_data,
  2266. soc_info->mem_block[0]->start);
  2267. if (rc) {
  2268. CAM_ERR(CAM_UTIL, "irq request fail");
  2269. rc = -EBUSY;
  2270. goto put_regulator;
  2271. }
  2272. soc_info->irq_data = irq_data;
  2273. }
  2274. /* Get Clock */
  2275. for (i = 0; i < soc_info->num_clk; i++) {
  2276. soc_info->clk[i] = clk_get(soc_info->dev,
  2277. soc_info->clk_name[i]);
  2278. if (!soc_info->clk[i]) {
  2279. CAM_ERR(CAM_UTIL, "get failed for %s",
  2280. soc_info->clk_name[i]);
  2281. rc = -ENOENT;
  2282. goto put_clk;
  2283. }
  2284. /* Create a wrapper entry if this is a shared clock */
  2285. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i)) {
  2286. uint32_t min_level = soc_info->lowest_clk_level;
  2287. CAM_DBG(CAM_UTIL,
  2288. "Dev %s, clk %s, id %d register wrapper entry for shared clk",
  2289. soc_info->dev_name, soc_info->clk_name[i],
  2290. soc_info->clk_id[i]);
  2291. rc = cam_soc_util_clk_wrapper_register_entry(
  2292. soc_info->clk_id[i], soc_info->clk[i],
  2293. (i == soc_info->src_clk_idx) ? true : false,
  2294. soc_info, soc_info->clk_rate[min_level][i],
  2295. soc_info->clk_name[i]);
  2296. if (rc) {
  2297. CAM_ERR(CAM_UTIL,
  2298. "Failed in registering shared clk Dev %s id %d",
  2299. soc_info->dev_name,
  2300. soc_info->clk_id[i]);
  2301. clk_put(soc_info->clk[i]);
  2302. soc_info->clk[i] = NULL;
  2303. goto put_clk;
  2304. }
  2305. } else if (i == soc_info->src_clk_idx) {
  2306. rc = cam_soc_util_register_mmrm_client(
  2307. soc_info->clk_id[i], soc_info->clk[i],
  2308. soc_info->is_nrt_dev,
  2309. soc_info, soc_info->clk_name[i],
  2310. &soc_info->mmrm_handle);
  2311. if (rc) {
  2312. CAM_ERR(CAM_UTIL,
  2313. "Failed in register mmrm client Dev %s clk id %d",
  2314. soc_info->dev_name,
  2315. soc_info->clk_id[i]);
  2316. clk_put(soc_info->clk[i]);
  2317. soc_info->clk[i] = NULL;
  2318. goto put_clk;
  2319. }
  2320. }
  2321. }
  2322. rc = cam_soc_util_request_pinctrl(soc_info);
  2323. if (rc) {
  2324. CAM_ERR(CAM_UTIL, "Failed in requesting Pinctrl, rc: %d", rc);
  2325. goto put_clk;
  2326. }
  2327. rc = cam_soc_util_request_gpio_table(soc_info, true);
  2328. if (rc) {
  2329. CAM_ERR(CAM_UTIL, "Failed in request gpio table, rc=%d", rc);
  2330. goto put_clk;
  2331. }
  2332. if (soc_info->clk_control_enable)
  2333. cam_soc_util_create_clk_lvl_debugfs(soc_info);
  2334. return rc;
  2335. put_clk:
  2336. if (soc_info->mmrm_handle) {
  2337. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2338. soc_info->mmrm_handle = NULL;
  2339. }
  2340. if (i == -1)
  2341. i = soc_info->num_clk;
  2342. for (i = i - 1; i >= 0; i--) {
  2343. if (soc_info->clk[i]) {
  2344. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2345. cam_soc_util_clk_wrapper_unregister_entry(
  2346. soc_info->clk_id[i], soc_info);
  2347. clk_put(soc_info->clk[i]);
  2348. soc_info->clk[i] = NULL;
  2349. }
  2350. }
  2351. if (soc_info->irq_line) {
  2352. disable_irq(soc_info->irq_line->start);
  2353. devm_free_irq(soc_info->dev,
  2354. soc_info->irq_line->start, irq_data);
  2355. }
  2356. put_regulator:
  2357. if (i == -1)
  2358. i = soc_info->num_rgltr;
  2359. for (i = i - 1; i >= 0; i--) {
  2360. if (soc_info->rgltr[i]) {
  2361. regulator_disable(soc_info->rgltr[i]);
  2362. regulator_put(soc_info->rgltr[i]);
  2363. soc_info->rgltr[i] = NULL;
  2364. }
  2365. }
  2366. unmap_base:
  2367. if (i == -1)
  2368. i = soc_info->num_reg_map;
  2369. for (i = i - 1; i >= 0; i--) {
  2370. if (soc_info->reserve_mem)
  2371. release_mem_region(soc_info->mem_block[i]->start,
  2372. resource_size(soc_info->mem_block[i]));
  2373. iounmap(soc_info->reg_map[i].mem_base);
  2374. soc_info->reg_map[i].mem_base = NULL;
  2375. soc_info->reg_map[i].size = 0;
  2376. }
  2377. return rc;
  2378. }
  2379. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info)
  2380. {
  2381. int i;
  2382. bool b_ret = false;
  2383. if (!soc_info || !soc_info->dev) {
  2384. CAM_ERR(CAM_UTIL, "Invalid parameter");
  2385. return -EINVAL;
  2386. }
  2387. if (soc_info->mmrm_handle) {
  2388. cam_soc_util_unregister_mmrm_client(soc_info->mmrm_handle);
  2389. soc_info->mmrm_handle = NULL;
  2390. }
  2391. for (i = soc_info->num_clk - 1; i >= 0; i--) {
  2392. if (CAM_IS_BIT_SET(soc_info->shared_clk_mask, i))
  2393. cam_soc_util_clk_wrapper_unregister_entry(
  2394. soc_info->clk_id[i], soc_info);
  2395. clk_put(soc_info->clk[i]);
  2396. soc_info->clk[i] = NULL;
  2397. }
  2398. for (i = soc_info->num_rgltr - 1; i >= 0; i--) {
  2399. if (soc_info->rgltr[i]) {
  2400. regulator_put(soc_info->rgltr[i]);
  2401. soc_info->rgltr[i] = NULL;
  2402. }
  2403. }
  2404. for (i = soc_info->num_reg_map - 1; i >= 0; i--) {
  2405. iounmap(soc_info->reg_map[i].mem_base);
  2406. soc_info->reg_map[i].mem_base = NULL;
  2407. soc_info->reg_map[i].size = 0;
  2408. }
  2409. if (soc_info->irq_line) {
  2410. if (cam_presil_mode_enabled()) {
  2411. if (cam_soc_util_is_presil_address_space(soc_info->mem_block[0]->start)) {
  2412. b_ret = cam_presil_unsubscribe_device_irq(
  2413. soc_info->irq_line->start);
  2414. CAM_DBG(CAM_PRESIL, "UnSubscribe IRQ: Ret=%d NUM=%d Name=%s",
  2415. b_ret, soc_info->irq_line->start, soc_info->irq_name);
  2416. }
  2417. }
  2418. disable_irq(soc_info->irq_line->start);
  2419. devm_free_irq(soc_info->dev,
  2420. soc_info->irq_line->start, soc_info->irq_data);
  2421. }
  2422. cam_soc_util_release_pinctrl(soc_info);
  2423. /* release for gpio */
  2424. cam_soc_util_request_gpio_table(soc_info, false);
  2425. if (soc_info->clk_control_enable)
  2426. cam_soc_util_remove_clk_lvl_debugfs(soc_info);
  2427. return 0;
  2428. }
  2429. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  2430. bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq)
  2431. {
  2432. int rc = 0;
  2433. if (!soc_info)
  2434. return -EINVAL;
  2435. rc = cam_soc_util_regulator_enable_default(soc_info);
  2436. if (rc) {
  2437. CAM_ERR(CAM_UTIL, "Regulators enable failed");
  2438. return rc;
  2439. }
  2440. if (enable_clocks) {
  2441. rc = cam_soc_util_clk_enable_default(soc_info, clk_level);
  2442. if (rc)
  2443. goto disable_regulator;
  2444. }
  2445. if (enable_irq) {
  2446. rc = cam_soc_util_irq_enable(soc_info);
  2447. if (rc)
  2448. goto disable_clk;
  2449. }
  2450. return rc;
  2451. disable_clk:
  2452. if (enable_clocks)
  2453. cam_soc_util_clk_disable_default(soc_info);
  2454. disable_regulator:
  2455. cam_soc_util_regulator_disable_default(soc_info);
  2456. return rc;
  2457. }
  2458. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  2459. bool disable_clocks, bool disable_irq)
  2460. {
  2461. int rc = 0;
  2462. if (!soc_info)
  2463. return -EINVAL;
  2464. if (disable_irq)
  2465. rc |= cam_soc_util_irq_disable(soc_info);
  2466. if (disable_clocks)
  2467. cam_soc_util_clk_disable_default(soc_info);
  2468. cam_soc_util_regulator_disable_default(soc_info);
  2469. return rc;
  2470. }
  2471. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  2472. uint32_t base_index, uint32_t offset, int size)
  2473. {
  2474. void __iomem *base_addr = NULL;
  2475. CAM_DBG(CAM_UTIL, "base_idx %u size=%d", base_index, size);
  2476. if (!soc_info || base_index >= soc_info->num_reg_map ||
  2477. size <= 0 || (offset + size) >=
  2478. CAM_SOC_GET_REG_MAP_SIZE(soc_info, base_index))
  2479. return -EINVAL;
  2480. base_addr = CAM_SOC_GET_REG_MAP_START(soc_info, base_index);
  2481. /*
  2482. * All error checking already done above,
  2483. * hence ignoring the return value below.
  2484. */
  2485. cam_io_dump(base_addr, offset, size);
  2486. return 0;
  2487. }
  2488. static int cam_soc_util_dump_cont_reg_range(
  2489. struct cam_hw_soc_info *soc_info,
  2490. struct cam_reg_range_read_desc *reg_read, uint32_t base_idx,
  2491. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  2492. {
  2493. int i = 0, rc = 0;
  2494. uint32_t write_idx = 0;
  2495. if (!soc_info || !dump_out_buf || !reg_read || !cmd_buf_end) {
  2496. CAM_ERR(CAM_UTIL,
  2497. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK cmd_buf_end: %pK",
  2498. soc_info, dump_out_buf, reg_read, cmd_buf_end);
  2499. rc = -EINVAL;
  2500. goto end;
  2501. }
  2502. if ((reg_read->num_values) && ((reg_read->num_values > U32_MAX / 2) ||
  2503. (sizeof(uint32_t) > ((U32_MAX -
  2504. sizeof(struct cam_reg_dump_out_buffer) -
  2505. dump_out_buf->bytes_written) /
  2506. (reg_read->num_values * 2))))) {
  2507. CAM_ERR(CAM_UTIL,
  2508. "Integer Overflow bytes_written: [%u] num_values: [%u]",
  2509. dump_out_buf->bytes_written, reg_read->num_values);
  2510. rc = -EOVERFLOW;
  2511. goto end;
  2512. }
  2513. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  2514. (uintptr_t)(sizeof(struct cam_reg_dump_out_buffer)
  2515. - sizeof(uint32_t) + dump_out_buf->bytes_written +
  2516. (reg_read->num_values * 2 * sizeof(uint32_t)))) {
  2517. CAM_ERR(CAM_UTIL,
  2518. "Insufficient space in out buffer num_values: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  2519. reg_read->num_values, cmd_buf_end,
  2520. (uintptr_t)dump_out_buf);
  2521. rc = -EINVAL;
  2522. goto end;
  2523. }
  2524. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  2525. for (i = 0; i < reg_read->num_values; i++) {
  2526. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  2527. (uint32_t)soc_info->reg_map[base_idx].size) {
  2528. CAM_ERR(CAM_UTIL,
  2529. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2530. (reg_read->offset + (i * sizeof(uint32_t))),
  2531. (uint32_t)soc_info->reg_map[base_idx].size);
  2532. rc = -EINVAL;
  2533. goto end;
  2534. }
  2535. dump_out_buf->dump_data[write_idx++] = reg_read->offset +
  2536. (i * sizeof(uint32_t));
  2537. dump_out_buf->dump_data[write_idx++] =
  2538. cam_soc_util_r(soc_info, base_idx,
  2539. (reg_read->offset + (i * sizeof(uint32_t))));
  2540. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2541. }
  2542. end:
  2543. return rc;
  2544. }
  2545. static int cam_soc_util_dump_dmi_reg_range(
  2546. struct cam_hw_soc_info *soc_info,
  2547. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  2548. struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
  2549. {
  2550. int i = 0, rc = 0;
  2551. uint32_t write_idx = 0;
  2552. if (!soc_info || !dump_out_buf || !dmi_read || !cmd_buf_end) {
  2553. CAM_ERR(CAM_UTIL,
  2554. "Invalid input args soc_info: %pK, dump_out_buffer: %pK",
  2555. soc_info, dump_out_buf);
  2556. rc = -EINVAL;
  2557. goto end;
  2558. }
  2559. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  2560. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  2561. CAM_ERR(CAM_UTIL,
  2562. "Invalid number of requested writes, pre: %d post: %d",
  2563. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  2564. rc = -EINVAL;
  2565. goto end;
  2566. }
  2567. if ((dmi_read->num_pre_writes + dmi_read->dmi_data_read.num_values)
  2568. && ((dmi_read->num_pre_writes > U32_MAX / 2) ||
  2569. (dmi_read->dmi_data_read.num_values > U32_MAX / 2) ||
  2570. ((dmi_read->num_pre_writes * 2) > U32_MAX -
  2571. (dmi_read->dmi_data_read.num_values * 2)) ||
  2572. (sizeof(uint32_t) > ((U32_MAX -
  2573. sizeof(struct cam_reg_dump_out_buffer) -
  2574. dump_out_buf->bytes_written) / ((dmi_read->num_pre_writes +
  2575. dmi_read->dmi_data_read.num_values) * 2))))) {
  2576. CAM_ERR(CAM_UTIL,
  2577. "Integer Overflow bytes_written: [%u] num_pre_writes: [%u] num_values: [%u]",
  2578. dump_out_buf->bytes_written, dmi_read->num_pre_writes,
  2579. dmi_read->dmi_data_read.num_values);
  2580. rc = -EOVERFLOW;
  2581. goto end;
  2582. }
  2583. if ((cmd_buf_end - (uintptr_t)dump_out_buf) <=
  2584. (uintptr_t)(
  2585. sizeof(struct cam_reg_dump_out_buffer) - sizeof(uint32_t) +
  2586. (dump_out_buf->bytes_written +
  2587. (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  2588. (dmi_read->dmi_data_read.num_values * 2 *
  2589. sizeof(uint32_t))))) {
  2590. CAM_ERR(CAM_UTIL,
  2591. "Insufficient space in out buffer num_read_val: [%d] num_write_val: [%d] cmd_buf_end: %pK dump_out_buf: %pK",
  2592. dmi_read->dmi_data_read.num_values,
  2593. dmi_read->num_pre_writes, cmd_buf_end,
  2594. (uintptr_t)dump_out_buf);
  2595. rc = -EINVAL;
  2596. goto end;
  2597. }
  2598. write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
  2599. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  2600. if (dmi_read->pre_read_config[i].offset >
  2601. (uint32_t)soc_info->reg_map[base_idx].size) {
  2602. CAM_ERR(CAM_UTIL,
  2603. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2604. dmi_read->pre_read_config[i].offset,
  2605. (uint32_t)soc_info->reg_map[base_idx].size);
  2606. rc = -EINVAL;
  2607. goto end;
  2608. }
  2609. cam_soc_util_w_mb(soc_info, base_idx,
  2610. dmi_read->pre_read_config[i].offset,
  2611. dmi_read->pre_read_config[i].value);
  2612. dump_out_buf->dump_data[write_idx++] =
  2613. dmi_read->pre_read_config[i].offset;
  2614. dump_out_buf->dump_data[write_idx++] =
  2615. dmi_read->pre_read_config[i].value;
  2616. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2617. }
  2618. if (dmi_read->dmi_data_read.offset >
  2619. (uint32_t)soc_info->reg_map[base_idx].size) {
  2620. CAM_ERR(CAM_UTIL,
  2621. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2622. dmi_read->dmi_data_read.offset,
  2623. (uint32_t)soc_info->reg_map[base_idx].size);
  2624. rc = -EINVAL;
  2625. goto end;
  2626. }
  2627. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  2628. dump_out_buf->dump_data[write_idx++] =
  2629. dmi_read->dmi_data_read.offset;
  2630. dump_out_buf->dump_data[write_idx++] =
  2631. cam_soc_util_r_mb(soc_info, base_idx,
  2632. dmi_read->dmi_data_read.offset);
  2633. dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
  2634. }
  2635. for (i = 0; i < dmi_read->num_post_writes; i++) {
  2636. if (dmi_read->post_read_config[i].offset >
  2637. (uint32_t)soc_info->reg_map[base_idx].size) {
  2638. CAM_ERR(CAM_UTIL,
  2639. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2640. dmi_read->post_read_config[i].offset,
  2641. (uint32_t)soc_info->reg_map[base_idx].size);
  2642. rc = -EINVAL;
  2643. goto end;
  2644. }
  2645. cam_soc_util_w_mb(soc_info, base_idx,
  2646. dmi_read->post_read_config[i].offset,
  2647. dmi_read->post_read_config[i].value);
  2648. }
  2649. end:
  2650. return rc;
  2651. }
  2652. static int cam_soc_util_dump_dmi_reg_range_user_buf(
  2653. struct cam_hw_soc_info *soc_info,
  2654. struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
  2655. struct cam_hw_soc_dump_args *dump_args)
  2656. {
  2657. int i;
  2658. int rc;
  2659. size_t buf_len = 0;
  2660. uint8_t *dst;
  2661. size_t remain_len;
  2662. uint32_t min_len;
  2663. uint32_t *waddr, *start;
  2664. uintptr_t cpu_addr;
  2665. struct cam_hw_soc_dump_header *hdr;
  2666. if (!soc_info || !dump_args || !dmi_read) {
  2667. CAM_ERR(CAM_UTIL,
  2668. "Invalid input args soc_info: %pK, dump_args: %pK",
  2669. soc_info, dump_args);
  2670. rc = -EINVAL;
  2671. goto end;
  2672. }
  2673. if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX ||
  2674. dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) {
  2675. CAM_ERR(CAM_UTIL,
  2676. "Invalid number of requested writes, pre: %d post: %d",
  2677. dmi_read->num_pre_writes, dmi_read->num_post_writes);
  2678. rc = -EINVAL;
  2679. goto end;
  2680. }
  2681. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  2682. if (rc) {
  2683. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  2684. dump_args->buf_handle, rc);
  2685. goto end;
  2686. }
  2687. if (buf_len <= dump_args->offset) {
  2688. CAM_WARN(CAM_UTIL, "Dump offset overshoot offset %zu len %zu",
  2689. dump_args->offset, buf_len);
  2690. rc = -ENOSPC;
  2691. goto end;
  2692. }
  2693. remain_len = buf_len - dump_args->offset;
  2694. min_len = (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) +
  2695. (dmi_read->dmi_data_read.num_values * 2 * sizeof(uint32_t)) +
  2696. sizeof(uint32_t);
  2697. if (remain_len < min_len) {
  2698. CAM_WARN(CAM_UTIL,
  2699. "Dump Buffer exhaust read %d write %d remain %zu min %u",
  2700. dmi_read->dmi_data_read.num_values,
  2701. dmi_read->num_pre_writes, remain_len,
  2702. min_len);
  2703. rc = -ENOSPC;
  2704. goto end;
  2705. }
  2706. dst = (uint8_t *)cpu_addr + dump_args->offset;
  2707. hdr = (struct cam_hw_soc_dump_header *)dst;
  2708. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  2709. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN,
  2710. "DMI_DUMP:");
  2711. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  2712. start = waddr;
  2713. hdr->word_size = sizeof(uint32_t);
  2714. *waddr = soc_info->index;
  2715. waddr++;
  2716. for (i = 0; i < dmi_read->num_pre_writes; i++) {
  2717. if (dmi_read->pre_read_config[i].offset >
  2718. (uint32_t)soc_info->reg_map[base_idx].size) {
  2719. CAM_ERR(CAM_UTIL,
  2720. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2721. dmi_read->pre_read_config[i].offset,
  2722. (uint32_t)soc_info->reg_map[base_idx].size);
  2723. rc = -EINVAL;
  2724. goto end;
  2725. }
  2726. cam_soc_util_w_mb(soc_info, base_idx,
  2727. dmi_read->pre_read_config[i].offset,
  2728. dmi_read->pre_read_config[i].value);
  2729. *waddr++ = dmi_read->pre_read_config[i].offset;
  2730. *waddr++ = dmi_read->pre_read_config[i].value;
  2731. }
  2732. if (dmi_read->dmi_data_read.offset >
  2733. (uint32_t)soc_info->reg_map[base_idx].size) {
  2734. CAM_ERR(CAM_UTIL,
  2735. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2736. dmi_read->dmi_data_read.offset,
  2737. (uint32_t)soc_info->reg_map[base_idx].size);
  2738. rc = -EINVAL;
  2739. goto end;
  2740. }
  2741. for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
  2742. *waddr++ = dmi_read->dmi_data_read.offset;
  2743. *waddr++ = cam_soc_util_r_mb(soc_info, base_idx,
  2744. dmi_read->dmi_data_read.offset);
  2745. }
  2746. for (i = 0; i < dmi_read->num_post_writes; i++) {
  2747. if (dmi_read->post_read_config[i].offset >
  2748. (uint32_t)soc_info->reg_map[base_idx].size) {
  2749. CAM_ERR(CAM_UTIL,
  2750. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2751. dmi_read->post_read_config[i].offset,
  2752. (uint32_t)soc_info->reg_map[base_idx].size);
  2753. rc = -EINVAL;
  2754. goto end;
  2755. }
  2756. cam_soc_util_w_mb(soc_info, base_idx,
  2757. dmi_read->post_read_config[i].offset,
  2758. dmi_read->post_read_config[i].value);
  2759. }
  2760. hdr->size = (waddr - start) * hdr->word_size;
  2761. dump_args->offset += hdr->size +
  2762. sizeof(struct cam_hw_soc_dump_header);
  2763. end:
  2764. return rc;
  2765. }
  2766. static int cam_soc_util_dump_cont_reg_range_user_buf(
  2767. struct cam_hw_soc_info *soc_info,
  2768. struct cam_reg_range_read_desc *reg_read,
  2769. uint32_t base_idx,
  2770. struct cam_hw_soc_dump_args *dump_args)
  2771. {
  2772. int i;
  2773. int rc = 0;
  2774. size_t buf_len;
  2775. uint8_t *dst;
  2776. size_t remain_len;
  2777. uint32_t min_len;
  2778. uint32_t *waddr, *start;
  2779. uintptr_t cpu_addr;
  2780. struct cam_hw_soc_dump_header *hdr;
  2781. if (!soc_info || !dump_args || !reg_read) {
  2782. CAM_ERR(CAM_UTIL,
  2783. "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK",
  2784. soc_info, dump_args, reg_read);
  2785. rc = -EINVAL;
  2786. goto end;
  2787. }
  2788. rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len);
  2789. if (rc) {
  2790. CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d",
  2791. dump_args->buf_handle, rc);
  2792. goto end;
  2793. }
  2794. if (buf_len <= dump_args->offset) {
  2795. CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu",
  2796. dump_args->offset, buf_len);
  2797. rc = -ENOSPC;
  2798. goto end;
  2799. }
  2800. remain_len = buf_len - dump_args->offset;
  2801. min_len = (reg_read->num_values * 2 * sizeof(uint32_t)) +
  2802. sizeof(struct cam_hw_soc_dump_header) + sizeof(uint32_t);
  2803. if (remain_len < min_len) {
  2804. CAM_WARN(CAM_UTIL,
  2805. "Dump Buffer exhaust read_values %d remain %zu min %u",
  2806. reg_read->num_values,
  2807. remain_len,
  2808. min_len);
  2809. rc = -ENOSPC;
  2810. goto end;
  2811. }
  2812. dst = (uint8_t *)cpu_addr + dump_args->offset;
  2813. hdr = (struct cam_hw_soc_dump_header *)dst;
  2814. memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header));
  2815. scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, "%s_REG:",
  2816. soc_info->dev_name);
  2817. waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header));
  2818. start = waddr;
  2819. hdr->word_size = sizeof(uint32_t);
  2820. *waddr = soc_info->index;
  2821. waddr++;
  2822. for (i = 0; i < reg_read->num_values; i++) {
  2823. if ((reg_read->offset + (i * sizeof(uint32_t))) >
  2824. (uint32_t)soc_info->reg_map[base_idx].size) {
  2825. CAM_ERR(CAM_UTIL,
  2826. "Reg offset out of range, offset: 0x%X reg_map size: 0x%X",
  2827. (reg_read->offset + (i * sizeof(uint32_t))),
  2828. (uint32_t)soc_info->reg_map[base_idx].size);
  2829. rc = -EINVAL;
  2830. goto end;
  2831. }
  2832. waddr[0] = reg_read->offset + (i * sizeof(uint32_t));
  2833. waddr[1] = cam_soc_util_r(soc_info, base_idx,
  2834. (reg_read->offset + (i * sizeof(uint32_t))));
  2835. waddr += 2;
  2836. }
  2837. hdr->size = (waddr - start) * hdr->word_size;
  2838. dump_args->offset += hdr->size +
  2839. sizeof(struct cam_hw_soc_dump_header);
  2840. end:
  2841. return rc;
  2842. }
  2843. static int cam_soc_util_user_reg_dump(
  2844. struct cam_reg_dump_desc *reg_dump_desc,
  2845. struct cam_hw_soc_dump_args *dump_args,
  2846. struct cam_hw_soc_info *soc_info,
  2847. uint32_t reg_base_idx)
  2848. {
  2849. int rc = 0;
  2850. int i;
  2851. struct cam_reg_read_info *reg_read_info = NULL;
  2852. if (!dump_args || !reg_dump_desc || !soc_info) {
  2853. CAM_ERR(CAM_UTIL,
  2854. "Invalid input parameters %pK %pK %pK",
  2855. dump_args, reg_dump_desc, soc_info);
  2856. return -EINVAL;
  2857. }
  2858. for (i = 0; i < reg_dump_desc->num_read_range; i++) {
  2859. reg_read_info = &reg_dump_desc->read_range[i];
  2860. if (reg_read_info->type ==
  2861. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  2862. rc = cam_soc_util_dump_cont_reg_range_user_buf(
  2863. soc_info,
  2864. &reg_read_info->reg_read,
  2865. reg_base_idx,
  2866. dump_args);
  2867. } else if (reg_read_info->type ==
  2868. CAM_REG_DUMP_READ_TYPE_DMI) {
  2869. rc = cam_soc_util_dump_dmi_reg_range_user_buf(
  2870. soc_info,
  2871. &reg_read_info->dmi_read,
  2872. reg_base_idx,
  2873. dump_args);
  2874. } else {
  2875. CAM_ERR(CAM_UTIL,
  2876. "Invalid Reg dump read type: %d",
  2877. reg_read_info->type);
  2878. rc = -EINVAL;
  2879. goto end;
  2880. }
  2881. if (rc) {
  2882. CAM_ERR(CAM_UTIL,
  2883. "Reg range read failed rc: %d reg_base_idx: %d",
  2884. rc, reg_base_idx);
  2885. goto end;
  2886. }
  2887. }
  2888. end:
  2889. return rc;
  2890. }
  2891. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  2892. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  2893. cam_soc_util_regspace_data_cb reg_data_cb,
  2894. struct cam_hw_soc_dump_args *soc_dump_args,
  2895. bool user_triggered_dump)
  2896. {
  2897. int rc = 0, i, j;
  2898. uintptr_t cpu_addr = 0;
  2899. uintptr_t cmd_buf_start = 0;
  2900. uintptr_t cmd_in_data_end = 0;
  2901. uintptr_t cmd_buf_end = 0;
  2902. uint32_t reg_base_type = 0;
  2903. size_t buf_size = 0, remain_len = 0;
  2904. struct cam_reg_dump_input_info *reg_input_info = NULL;
  2905. struct cam_reg_dump_desc *reg_dump_desc = NULL;
  2906. struct cam_reg_dump_out_buffer *dump_out_buf = NULL;
  2907. struct cam_reg_read_info *reg_read_info = NULL;
  2908. struct cam_hw_soc_info *soc_info;
  2909. uint32_t reg_base_idx = 0;
  2910. if (!ctx || !cmd_desc || !reg_data_cb) {
  2911. CAM_ERR(CAM_UTIL, "Invalid args to reg dump [%pK] [%pK]",
  2912. cmd_desc, reg_data_cb);
  2913. return -EINVAL;
  2914. }
  2915. if (!cmd_desc->length || !cmd_desc->size) {
  2916. CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d",
  2917. cmd_desc->length, cmd_desc->size);
  2918. return -EINVAL;
  2919. }
  2920. rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, &cpu_addr, &buf_size);
  2921. if (rc || !cpu_addr || (buf_size == 0)) {
  2922. CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK",
  2923. rc, (void *)cpu_addr);
  2924. goto end;
  2925. }
  2926. CAM_DBG(CAM_UTIL, "Get cpu buf success req_id: %llu buf_size: %zu",
  2927. req_id, buf_size);
  2928. if ((buf_size < sizeof(uint32_t)) ||
  2929. ((size_t)cmd_desc->offset > (buf_size - sizeof(uint32_t)))) {
  2930. CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu",
  2931. (size_t)cmd_desc->offset);
  2932. rc = -EINVAL;
  2933. goto end;
  2934. }
  2935. remain_len = buf_size - (size_t)cmd_desc->offset;
  2936. if ((remain_len < (size_t)cmd_desc->size) || (cmd_desc->size <
  2937. cmd_desc->length)) {
  2938. CAM_ERR(CAM_UTIL,
  2939. "Invalid params for cmd buf len: %zu size: %zu remain_len: %zu",
  2940. (size_t)cmd_desc->length, (size_t)cmd_desc->length,
  2941. remain_len);
  2942. rc = -EINVAL;
  2943. goto end;
  2944. }
  2945. cmd_buf_start = cpu_addr + (uintptr_t)cmd_desc->offset;
  2946. cmd_in_data_end = cmd_buf_start + (uintptr_t)cmd_desc->length;
  2947. cmd_buf_end = cmd_buf_start + (uintptr_t)cmd_desc->size;
  2948. if ((cmd_buf_end <= cmd_buf_start) ||
  2949. (cmd_in_data_end <= cmd_buf_start)) {
  2950. CAM_ERR(CAM_UTIL,
  2951. "Invalid length or size for cmd buf: [%zu] [%zu]",
  2952. (size_t)cmd_desc->length, (size_t)cmd_desc->size);
  2953. rc = -EINVAL;
  2954. goto end;
  2955. }
  2956. CAM_DBG(CAM_UTIL,
  2957. "Buffer params start [%pK] input_end [%pK] buf_end [%pK]",
  2958. cmd_buf_start, cmd_in_data_end, cmd_buf_end);
  2959. reg_input_info = (struct cam_reg_dump_input_info *) cmd_buf_start;
  2960. if ((reg_input_info->num_dump_sets > 1) && (sizeof(uint32_t) >
  2961. ((U32_MAX - sizeof(struct cam_reg_dump_input_info)) /
  2962. (reg_input_info->num_dump_sets - 1)))) {
  2963. CAM_ERR(CAM_UTIL,
  2964. "Integer Overflow req_id: [%llu] num_dump_sets: [%u]",
  2965. req_id, reg_input_info->num_dump_sets);
  2966. rc = -EOVERFLOW;
  2967. goto end;
  2968. }
  2969. if ((!reg_input_info->num_dump_sets) ||
  2970. ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  2971. (sizeof(struct cam_reg_dump_input_info) +
  2972. ((reg_input_info->num_dump_sets - 1) * sizeof(uint32_t))))) {
  2973. CAM_ERR(CAM_UTIL,
  2974. "Invalid number of dump sets, req_id: [%llu] num_dump_sets: [%u]",
  2975. req_id, reg_input_info->num_dump_sets);
  2976. rc = -EINVAL;
  2977. goto end;
  2978. }
  2979. CAM_DBG(CAM_UTIL,
  2980. "reg_input_info req_id: %llu ctx %pK num_dump_sets: %d",
  2981. req_id, ctx, reg_input_info->num_dump_sets);
  2982. for (i = 0; i < reg_input_info->num_dump_sets; i++) {
  2983. if ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t)
  2984. reg_input_info->dump_set_offsets[i]) {
  2985. CAM_ERR(CAM_UTIL,
  2986. "Invalid dump set offset: [%pK], cmd_buf_start: [%pK] cmd_in_data_end: [%pK]",
  2987. (uintptr_t)reg_input_info->dump_set_offsets[i],
  2988. cmd_buf_start, cmd_in_data_end);
  2989. rc = -EINVAL;
  2990. goto end;
  2991. }
  2992. reg_dump_desc = (struct cam_reg_dump_desc *)
  2993. (cmd_buf_start +
  2994. (uintptr_t)reg_input_info->dump_set_offsets[i]);
  2995. if ((reg_dump_desc->num_read_range > 1) &&
  2996. (sizeof(struct cam_reg_read_info) > ((U32_MAX -
  2997. sizeof(struct cam_reg_dump_desc)) /
  2998. (reg_dump_desc->num_read_range - 1)))) {
  2999. CAM_ERR(CAM_UTIL,
  3000. "Integer Overflow req_id: [%llu] num_read_range: [%u]",
  3001. req_id, reg_dump_desc->num_read_range);
  3002. rc = -EOVERFLOW;
  3003. goto end;
  3004. }
  3005. if ((!reg_dump_desc->num_read_range) ||
  3006. ((cmd_in_data_end - (uintptr_t)reg_dump_desc) <=
  3007. (uintptr_t)(sizeof(struct cam_reg_dump_desc) +
  3008. ((reg_dump_desc->num_read_range - 1) *
  3009. sizeof(struct cam_reg_read_info))))) {
  3010. CAM_ERR(CAM_UTIL,
  3011. "Invalid number of read ranges, req_id: [%llu] num_read_range: [%d]",
  3012. req_id, reg_dump_desc->num_read_range);
  3013. rc = -EINVAL;
  3014. goto end;
  3015. }
  3016. if ((cmd_buf_end - cmd_buf_start) <= (uintptr_t)
  3017. (reg_dump_desc->dump_buffer_offset +
  3018. sizeof(struct cam_reg_dump_out_buffer))) {
  3019. CAM_ERR(CAM_UTIL,
  3020. "Invalid out buffer offset: [%pK], cmd_buf_start: [%pK] cmd_buf_end: [%pK]",
  3021. (uintptr_t)reg_dump_desc->dump_buffer_offset,
  3022. cmd_buf_start, cmd_buf_end);
  3023. rc = -EINVAL;
  3024. goto end;
  3025. }
  3026. reg_base_type = reg_dump_desc->reg_base_type;
  3027. if (reg_base_type == 0 || reg_base_type >
  3028. CAM_REG_DUMP_BASE_TYPE_SFE_RIGHT) {
  3029. CAM_ERR(CAM_UTIL,
  3030. "Invalid Reg dump base type: %d",
  3031. reg_base_type);
  3032. rc = -EINVAL;
  3033. goto end;
  3034. }
  3035. rc = reg_data_cb(reg_base_type, ctx, &soc_info, &reg_base_idx);
  3036. if (rc || !soc_info) {
  3037. CAM_ERR(CAM_UTIL,
  3038. "Reg space data callback failed rc: %d soc_info: [%pK]",
  3039. rc, soc_info);
  3040. rc = -EINVAL;
  3041. goto end;
  3042. }
  3043. if (reg_base_idx > soc_info->num_reg_map) {
  3044. CAM_ERR(CAM_UTIL,
  3045. "Invalid reg base idx: %d num reg map: %d",
  3046. reg_base_idx, soc_info->num_reg_map);
  3047. rc = -EINVAL;
  3048. goto end;
  3049. }
  3050. CAM_DBG(CAM_UTIL,
  3051. "Reg data callback success req_id: %llu base_type: %d base_idx: %d num_read_range: %d",
  3052. req_id, reg_base_type, reg_base_idx,
  3053. reg_dump_desc->num_read_range);
  3054. /* If the dump request is triggered by user space
  3055. * buffer will be different from the buffer which is received
  3056. * in init packet. In this case, dump the data to the
  3057. * user provided buffer and exit.
  3058. */
  3059. if (user_triggered_dump) {
  3060. rc = cam_soc_util_user_reg_dump(reg_dump_desc,
  3061. soc_dump_args, soc_info, reg_base_idx);
  3062. CAM_INFO(CAM_UTIL,
  3063. "%s reg_base_idx %d dumped offset %u",
  3064. soc_info->dev_name, reg_base_idx,
  3065. soc_dump_args->offset);
  3066. goto end;
  3067. }
  3068. /* Below code is executed when data is dumped to the
  3069. * out buffer received in init packet
  3070. */
  3071. dump_out_buf = (struct cam_reg_dump_out_buffer *)
  3072. (cmd_buf_start +
  3073. (uintptr_t)reg_dump_desc->dump_buffer_offset);
  3074. dump_out_buf->req_id = req_id;
  3075. dump_out_buf->bytes_written = 0;
  3076. for (j = 0; j < reg_dump_desc->num_read_range; j++) {
  3077. CAM_DBG(CAM_UTIL,
  3078. "Number of bytes written to cmd buffer: %u req_id: %llu",
  3079. dump_out_buf->bytes_written, req_id);
  3080. reg_read_info = &reg_dump_desc->read_range[j];
  3081. if (reg_read_info->type ==
  3082. CAM_REG_DUMP_READ_TYPE_CONT_RANGE) {
  3083. rc = cam_soc_util_dump_cont_reg_range(soc_info,
  3084. &reg_read_info->reg_read, reg_base_idx,
  3085. dump_out_buf, cmd_buf_end);
  3086. } else if (reg_read_info->type ==
  3087. CAM_REG_DUMP_READ_TYPE_DMI) {
  3088. rc = cam_soc_util_dump_dmi_reg_range(soc_info,
  3089. &reg_read_info->dmi_read, reg_base_idx,
  3090. dump_out_buf, cmd_buf_end);
  3091. } else {
  3092. CAM_ERR(CAM_UTIL,
  3093. "Invalid Reg dump read type: %d",
  3094. reg_read_info->type);
  3095. rc = -EINVAL;
  3096. goto end;
  3097. }
  3098. if (rc) {
  3099. CAM_ERR(CAM_UTIL,
  3100. "Reg range read failed rc: %d reg_base_idx: %d dump_out_buf: %pK",
  3101. rc, reg_base_idx, dump_out_buf);
  3102. goto end;
  3103. }
  3104. }
  3105. }
  3106. end:
  3107. return rc;
  3108. }
  3109. /**
  3110. * cam_soc_util_print_clk_freq()
  3111. *
  3112. * @brief: This function gets the clk rates for each clk from clk
  3113. * driver and prints in log
  3114. *
  3115. * @soc_info: Device soc struct to be populated
  3116. *
  3117. * @return: success or failure
  3118. */
  3119. int cam_soc_util_print_clk_freq(struct cam_hw_soc_info *soc_info)
  3120. {
  3121. int i;
  3122. unsigned long clk_rate = 0;
  3123. if (!soc_info) {
  3124. CAM_ERR(CAM_UTIL, "Invalid soc info");
  3125. return -EINVAL;
  3126. }
  3127. if ((soc_info->num_clk == 0) ||
  3128. (soc_info->num_clk >= CAM_SOC_MAX_CLK)) {
  3129. CAM_ERR(CAM_UTIL, "[%s] Invalid number of clock %d",
  3130. soc_info->dev_name, soc_info->num_clk);
  3131. return -EINVAL;
  3132. }
  3133. for (i = 0; i < soc_info->num_clk; i++) {
  3134. clk_rate = clk_get_rate(soc_info->clk[i]);
  3135. CAM_INFO(CAM_UTIL,
  3136. "[%s] idx = %d clk name = %s clk_rate=%lld",
  3137. soc_info->dev_name, i, soc_info->clk_name[i],
  3138. clk_rate);
  3139. }
  3140. return 0;
  3141. }