dsi_drm.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  12. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  13. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  14. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  15. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  16. #define DEFAULT_PANEL_PREFILL_LINES 25
  17. static struct dsi_display_mode_priv_info default_priv_info = {
  18. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  19. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  20. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  21. .dsc_enabled = false,
  22. };
  23. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  24. struct dsi_display_mode *dsi_mode)
  25. {
  26. memset(dsi_mode, 0, sizeof(*dsi_mode));
  27. dsi_mode->timing.h_active = drm_mode->hdisplay;
  28. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  29. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  30. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  31. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  32. drm_mode->hdisplay;
  33. dsi_mode->timing.h_skew = drm_mode->hskew;
  34. dsi_mode->timing.v_active = drm_mode->vdisplay;
  35. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  36. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  37. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  38. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  39. drm_mode->vdisplay;
  40. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  41. dsi_mode->pixel_clk_khz = drm_mode->clock;
  42. dsi_mode->priv_info =
  43. (struct dsi_display_mode_priv_info *)drm_mode->private;
  44. if (dsi_mode->priv_info) {
  45. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  46. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  47. }
  48. if (msm_is_mode_seamless(drm_mode))
  49. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  50. if (msm_is_mode_dynamic_fps(drm_mode))
  51. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  52. if (msm_needs_vblank_pre_modeset(drm_mode))
  53. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  54. if (msm_is_mode_seamless_dms(drm_mode))
  55. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  56. if (msm_is_mode_seamless_vrr(drm_mode))
  57. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  58. if (msm_is_mode_seamless_poms(drm_mode))
  59. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  60. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  61. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  62. dsi_mode->timing.h_sync_polarity =
  63. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  64. dsi_mode->timing.v_sync_polarity =
  65. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  66. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  67. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  68. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  69. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  70. }
  71. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  72. struct drm_display_mode *drm_mode)
  73. {
  74. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  75. memset(drm_mode, 0, sizeof(*drm_mode));
  76. drm_mode->hdisplay = dsi_mode->timing.h_active;
  77. drm_mode->hsync_start = drm_mode->hdisplay +
  78. dsi_mode->timing.h_front_porch;
  79. drm_mode->hsync_end = drm_mode->hsync_start +
  80. dsi_mode->timing.h_sync_width;
  81. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  82. drm_mode->hskew = dsi_mode->timing.h_skew;
  83. drm_mode->vdisplay = dsi_mode->timing.v_active;
  84. drm_mode->vsync_start = drm_mode->vdisplay +
  85. dsi_mode->timing.v_front_porch;
  86. drm_mode->vsync_end = drm_mode->vsync_start +
  87. dsi_mode->timing.v_sync_width;
  88. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  89. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  90. drm_mode->clock = dsi_mode->pixel_clk_khz;
  91. drm_mode->private = (int *)dsi_mode->priv_info;
  92. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  93. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  94. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  95. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  96. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  97. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  98. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  99. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  100. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  101. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  102. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  103. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  104. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  105. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  106. if (dsi_mode->timing.h_sync_polarity)
  107. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  108. if (dsi_mode->timing.v_sync_polarity)
  109. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  110. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  111. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  112. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  113. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  114. /* set mode name */
  115. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  116. drm_mode->hdisplay, drm_mode->vdisplay,
  117. drm_mode->vrefresh, drm_mode->clock,
  118. video_mode ? "vid" : "cmd");
  119. }
  120. static int dsi_bridge_attach(struct drm_bridge *bridge)
  121. {
  122. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  123. if (!bridge) {
  124. DSI_ERR("Invalid params\n");
  125. return -EINVAL;
  126. }
  127. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  128. return 0;
  129. }
  130. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  131. {
  132. int rc = 0;
  133. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  134. if (!bridge) {
  135. DSI_ERR("Invalid params\n");
  136. return;
  137. }
  138. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  139. DSI_ERR("Incorrect bridge details\n");
  140. return;
  141. }
  142. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  143. /* By this point mode should have been validated through mode_fixup */
  144. rc = dsi_display_set_mode(c_bridge->display,
  145. &(c_bridge->dsi_mode), 0x0);
  146. if (rc) {
  147. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  148. c_bridge->id, rc);
  149. return;
  150. }
  151. if (c_bridge->dsi_mode.dsi_mode_flags &
  152. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  153. DSI_MODE_FLAG_DYN_CLK)) {
  154. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  155. return;
  156. }
  157. SDE_ATRACE_BEGIN("dsi_display_prepare");
  158. rc = dsi_display_prepare(c_bridge->display);
  159. if (rc) {
  160. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  161. c_bridge->id, rc);
  162. SDE_ATRACE_END("dsi_display_prepare");
  163. return;
  164. }
  165. SDE_ATRACE_END("dsi_display_prepare");
  166. SDE_ATRACE_BEGIN("dsi_display_enable");
  167. rc = dsi_display_enable(c_bridge->display);
  168. if (rc) {
  169. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  170. c_bridge->id, rc);
  171. (void)dsi_display_unprepare(c_bridge->display);
  172. }
  173. SDE_ATRACE_END("dsi_display_enable");
  174. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  175. if (rc)
  176. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  177. rc);
  178. }
  179. static void dsi_bridge_enable(struct drm_bridge *bridge)
  180. {
  181. int rc = 0;
  182. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  183. struct dsi_display *display;
  184. if (!bridge) {
  185. DSI_ERR("Invalid params\n");
  186. return;
  187. }
  188. if (c_bridge->dsi_mode.dsi_mode_flags &
  189. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  190. DSI_MODE_FLAG_DYN_CLK)) {
  191. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  192. return;
  193. }
  194. display = c_bridge->display;
  195. rc = dsi_display_post_enable(display);
  196. if (rc)
  197. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  198. c_bridge->id, rc);
  199. if (display && display->drm_conn) {
  200. sde_connector_helper_bridge_enable(display->drm_conn);
  201. if (c_bridge->dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)
  202. sde_connector_schedule_status_work(display->drm_conn,
  203. true);
  204. }
  205. }
  206. static void dsi_bridge_disable(struct drm_bridge *bridge)
  207. {
  208. int rc = 0;
  209. struct dsi_display *display;
  210. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  211. if (!bridge) {
  212. DSI_ERR("Invalid params\n");
  213. return;
  214. }
  215. display = c_bridge->display;
  216. if (display && display->drm_conn) {
  217. if (bridge->encoder->crtc->state->adjusted_mode.private_flags &
  218. MSM_MODE_FLAG_SEAMLESS_POMS) {
  219. display->poms_pending = true;
  220. /* Disable ESD thread, during panel mode switch */
  221. sde_connector_schedule_status_work(display->drm_conn,
  222. false);
  223. } else {
  224. display->poms_pending = false;
  225. sde_connector_helper_bridge_disable(display->drm_conn);
  226. }
  227. }
  228. rc = dsi_display_pre_disable(c_bridge->display);
  229. if (rc) {
  230. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  231. c_bridge->id, rc);
  232. }
  233. }
  234. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  235. {
  236. int rc = 0;
  237. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  238. if (!bridge) {
  239. DSI_ERR("Invalid params\n");
  240. return;
  241. }
  242. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  243. SDE_ATRACE_BEGIN("dsi_display_disable");
  244. rc = dsi_display_disable(c_bridge->display);
  245. if (rc) {
  246. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  247. c_bridge->id, rc);
  248. SDE_ATRACE_END("dsi_display_disable");
  249. return;
  250. }
  251. SDE_ATRACE_END("dsi_display_disable");
  252. rc = dsi_display_unprepare(c_bridge->display);
  253. if (rc) {
  254. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  255. c_bridge->id, rc);
  256. SDE_ATRACE_END("dsi_bridge_post_disable");
  257. return;
  258. }
  259. SDE_ATRACE_END("dsi_bridge_post_disable");
  260. }
  261. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  262. const struct drm_display_mode *mode,
  263. const struct drm_display_mode *adjusted_mode)
  264. {
  265. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  266. if (!bridge || !mode || !adjusted_mode) {
  267. DSI_ERR("Invalid params\n");
  268. return;
  269. }
  270. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  271. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  272. /* restore bit_clk_rate also for dynamic clk use cases */
  273. c_bridge->dsi_mode.timing.clk_rate_hz =
  274. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  275. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  276. }
  277. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  278. const struct drm_display_mode *mode,
  279. struct drm_display_mode *adjusted_mode)
  280. {
  281. int rc = 0;
  282. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  283. struct dsi_display *display;
  284. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  285. struct drm_crtc_state *crtc_state;
  286. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  287. if (!bridge || !mode || !adjusted_mode) {
  288. DSI_ERR("Invalid params\n");
  289. return false;
  290. }
  291. display = c_bridge->display;
  292. if (!display) {
  293. DSI_ERR("Invalid params\n");
  294. return false;
  295. }
  296. /*
  297. * if no timing defined in panel, it must be external mode
  298. * and we'll use empty priv info to populate the mode
  299. */
  300. if (display->panel && !display->panel->num_timing_nodes) {
  301. *adjusted_mode = *mode;
  302. adjusted_mode->private = (int *)&default_priv_info;
  303. adjusted_mode->private_flags = 0;
  304. return true;
  305. }
  306. convert_to_dsi_mode(mode, &dsi_mode);
  307. /*
  308. * retrieve dsi mode from dsi driver's cache since not safe to take
  309. * the drm mode config mutex in all paths
  310. */
  311. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  312. if (rc)
  313. return rc;
  314. /* propagate the private info to the adjusted_mode derived dsi mode */
  315. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  316. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  317. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  318. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  319. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  320. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  321. if (rc) {
  322. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  323. return false;
  324. }
  325. if (bridge->encoder && bridge->encoder->crtc &&
  326. crtc_state->crtc) {
  327. const struct drm_display_mode *cur_mode =
  328. &crtc_state->crtc->state->mode;
  329. convert_to_dsi_mode(cur_mode, &cur_dsi_mode);
  330. cur_dsi_mode.timing.dsc_enabled =
  331. dsi_mode.priv_info->dsc_enabled;
  332. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  333. rc = dsi_display_validate_mode_change(c_bridge->display,
  334. &cur_dsi_mode, &dsi_mode);
  335. if (rc) {
  336. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  337. c_bridge->display->name, rc);
  338. return false;
  339. }
  340. /* No panel mode switch when drm pipeline is changing */
  341. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  342. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  343. (crtc_state->enable ==
  344. crtc_state->crtc->state->enable))
  345. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  346. /* No DMS/VRR when drm pipeline is changing */
  347. if (!drm_mode_equal(cur_mode, adjusted_mode) &&
  348. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  349. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  350. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  351. (!crtc_state->active_changed ||
  352. display->is_cont_splash_enabled))
  353. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  354. }
  355. /* Reject seamless transition when active changed */
  356. if (crtc_state->active_changed &&
  357. ((dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) ||
  358. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS) ||
  359. (dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK))) {
  360. DSI_ERR("seamless upon active changed 0x%x %d\n",
  361. dsi_mode.dsi_mode_flags, crtc_state->active_changed);
  362. return false;
  363. }
  364. /* convert back to drm mode, propagating the private info & flags */
  365. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  366. return true;
  367. }
  368. u64 dsi_drm_find_bit_clk_rate(void *display,
  369. const struct drm_display_mode *drm_mode)
  370. {
  371. int i = 0, count = 0;
  372. struct dsi_display *dsi_display = display;
  373. struct dsi_display_mode *dsi_mode;
  374. u64 bit_clk_rate = 0;
  375. if (!dsi_display || !drm_mode)
  376. return 0;
  377. dsi_display_get_mode_count(dsi_display, &count);
  378. for (i = 0; i < count; i++) {
  379. dsi_mode = &dsi_display->modes[i];
  380. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  381. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  382. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  383. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  384. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  385. break;
  386. }
  387. }
  388. return bit_clk_rate;
  389. }
  390. int dsi_conn_get_mode_info(struct drm_connector *connector,
  391. const struct drm_display_mode *drm_mode,
  392. struct msm_mode_info *mode_info,
  393. void *display, const struct msm_resource_caps_info *avail_res)
  394. {
  395. struct dsi_display_mode dsi_mode;
  396. struct dsi_mode_info *timing;
  397. int chroma_format;
  398. int src_bpp, tar_bpp;
  399. if (!drm_mode || !mode_info)
  400. return -EINVAL;
  401. convert_to_dsi_mode(drm_mode, &dsi_mode);
  402. if (!dsi_mode.priv_info)
  403. return -EINVAL;
  404. memset(mode_info, 0, sizeof(*mode_info));
  405. timing = &dsi_mode.timing;
  406. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  407. mode_info->vtotal = DSI_V_TOTAL(timing);
  408. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  409. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  410. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  411. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  412. mode_info->mdp_transfer_time_us =
  413. dsi_mode.priv_info->mdp_transfer_time_us;
  414. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  415. sizeof(struct msm_display_topology));
  416. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  417. if (dsi_mode.priv_info->dsc_enabled) {
  418. chroma_format = dsi_mode.priv_info->dsc.chroma_format;
  419. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  420. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  421. sizeof(dsi_mode.priv_info->dsc));
  422. tar_bpp = dsi_mode.priv_info->dsc.config.bits_per_pixel >> 4;
  423. src_bpp = msm_get_src_bpc(chroma_format,
  424. dsi_mode.priv_info->dsc.config.bits_per_component);
  425. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  426. tar_bpp);
  427. } else if (dsi_mode.priv_info->vdc_enabled) {
  428. chroma_format = dsi_mode.priv_info->vdc.chroma_format;
  429. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_VDC;
  430. memcpy(&mode_info->comp_info.vdc_info, &dsi_mode.priv_info->vdc,
  431. sizeof(dsi_mode.priv_info->vdc));
  432. tar_bpp = dsi_mode.priv_info->vdc.bits_per_pixel >> 4;
  433. src_bpp = msm_get_src_bpc(chroma_format,
  434. dsi_mode.priv_info->vdc.bits_per_component);
  435. mode_info->comp_info.comp_ratio = mult_frac(1, src_bpp,
  436. tar_bpp);
  437. }
  438. if (dsi_mode.priv_info->roi_caps.enabled) {
  439. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  440. sizeof(dsi_mode.priv_info->roi_caps));
  441. }
  442. return 0;
  443. }
  444. static const struct drm_bridge_funcs dsi_bridge_ops = {
  445. .attach = dsi_bridge_attach,
  446. .mode_fixup = dsi_bridge_mode_fixup,
  447. .pre_enable = dsi_bridge_pre_enable,
  448. .enable = dsi_bridge_enable,
  449. .disable = dsi_bridge_disable,
  450. .post_disable = dsi_bridge_post_disable,
  451. .mode_set = dsi_bridge_mode_set,
  452. };
  453. int dsi_conn_set_info_blob(struct drm_connector *connector,
  454. void *info, void *display, struct msm_mode_info *mode_info)
  455. {
  456. struct dsi_display *dsi_display = display;
  457. struct dsi_panel *panel;
  458. enum dsi_pixel_format fmt;
  459. u32 bpp;
  460. if (!info || !dsi_display)
  461. return -EINVAL;
  462. dsi_display->drm_conn = connector;
  463. sde_kms_info_add_keystr(info,
  464. "display type", dsi_display->display_type);
  465. switch (dsi_display->type) {
  466. case DSI_DISPLAY_SINGLE:
  467. sde_kms_info_add_keystr(info, "display config",
  468. "single display");
  469. break;
  470. case DSI_DISPLAY_EXT_BRIDGE:
  471. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  472. break;
  473. case DSI_DISPLAY_SPLIT:
  474. sde_kms_info_add_keystr(info, "display config",
  475. "split display");
  476. break;
  477. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  478. sde_kms_info_add_keystr(info, "display config",
  479. "split ext bridge");
  480. break;
  481. default:
  482. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  483. break;
  484. }
  485. if (!dsi_display->panel) {
  486. DSI_DEBUG("invalid panel data\n");
  487. goto end;
  488. }
  489. panel = dsi_display->panel;
  490. sde_kms_info_add_keystr(info, "panel name", panel->name);
  491. switch (panel->panel_mode) {
  492. case DSI_OP_VIDEO_MODE:
  493. sde_kms_info_add_keystr(info, "panel mode", "video");
  494. sde_kms_info_add_keystr(info, "qsync support",
  495. panel->qsync_min_fps ? "true" : "false");
  496. break;
  497. case DSI_OP_CMD_MODE:
  498. sde_kms_info_add_keystr(info, "panel mode", "command");
  499. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  500. mode_info->mdp_transfer_time_us);
  501. sde_kms_info_add_keystr(info, "qsync support",
  502. panel->qsync_min_fps ? "true" : "false");
  503. break;
  504. default:
  505. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  506. break;
  507. }
  508. sde_kms_info_add_keystr(info, "dfps support",
  509. panel->dfps_caps.dfps_support ? "true" : "false");
  510. if (panel->dfps_caps.dfps_support) {
  511. sde_kms_info_add_keyint(info, "min_fps",
  512. panel->dfps_caps.min_refresh_rate);
  513. sde_kms_info_add_keyint(info, "max_fps",
  514. panel->dfps_caps.max_refresh_rate);
  515. }
  516. sde_kms_info_add_keystr(info, "dyn bitclk support",
  517. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  518. switch (panel->phy_props.rotation) {
  519. case DSI_PANEL_ROTATE_NONE:
  520. sde_kms_info_add_keystr(info, "panel orientation", "none");
  521. break;
  522. case DSI_PANEL_ROTATE_H_FLIP:
  523. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  524. break;
  525. case DSI_PANEL_ROTATE_V_FLIP:
  526. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  527. break;
  528. case DSI_PANEL_ROTATE_HV_FLIP:
  529. sde_kms_info_add_keystr(info, "panel orientation",
  530. "horz & vert flip");
  531. break;
  532. default:
  533. DSI_DEBUG("invalid panel rotation:%d\n",
  534. panel->phy_props.rotation);
  535. break;
  536. }
  537. switch (panel->bl_config.type) {
  538. case DSI_BACKLIGHT_PWM:
  539. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  540. break;
  541. case DSI_BACKLIGHT_WLED:
  542. sde_kms_info_add_keystr(info, "backlight type", "wled");
  543. break;
  544. case DSI_BACKLIGHT_DCS:
  545. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  546. break;
  547. default:
  548. DSI_DEBUG("invalid panel backlight type:%d\n",
  549. panel->bl_config.type);
  550. break;
  551. }
  552. if (mode_info && mode_info->roi_caps.enabled) {
  553. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  554. mode_info->roi_caps.num_roi);
  555. sde_kms_info_add_keyint(info, "partial_update_xstart",
  556. mode_info->roi_caps.align.xstart_pix_align);
  557. sde_kms_info_add_keyint(info, "partial_update_walign",
  558. mode_info->roi_caps.align.width_pix_align);
  559. sde_kms_info_add_keyint(info, "partial_update_wmin",
  560. mode_info->roi_caps.align.min_width);
  561. sde_kms_info_add_keyint(info, "partial_update_ystart",
  562. mode_info->roi_caps.align.ystart_pix_align);
  563. sde_kms_info_add_keyint(info, "partial_update_halign",
  564. mode_info->roi_caps.align.height_pix_align);
  565. sde_kms_info_add_keyint(info, "partial_update_hmin",
  566. mode_info->roi_caps.align.min_height);
  567. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  568. mode_info->roi_caps.merge_rois);
  569. }
  570. fmt = dsi_display->config.common_config.dst_format;
  571. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  572. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  573. end:
  574. return 0;
  575. }
  576. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  577. bool force,
  578. void *display)
  579. {
  580. enum drm_connector_status status = connector_status_unknown;
  581. struct msm_display_info info;
  582. int rc;
  583. if (!conn || !display)
  584. return status;
  585. /* get display dsi_info */
  586. memset(&info, 0x0, sizeof(info));
  587. rc = dsi_display_get_info(conn, &info, display);
  588. if (rc) {
  589. DSI_ERR("failed to get display info, rc=%d\n", rc);
  590. return connector_status_disconnected;
  591. }
  592. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  593. status = (info.is_connected ? connector_status_connected :
  594. connector_status_disconnected);
  595. else
  596. status = connector_status_connected;
  597. conn->display_info.width_mm = info.width_mm;
  598. conn->display_info.height_mm = info.height_mm;
  599. return status;
  600. }
  601. void dsi_connector_put_modes(struct drm_connector *connector,
  602. void *display)
  603. {
  604. struct drm_display_mode *drm_mode;
  605. struct dsi_display_mode dsi_mode;
  606. struct dsi_display *dsi_display;
  607. if (!connector || !display)
  608. return;
  609. list_for_each_entry(drm_mode, &connector->modes, head) {
  610. convert_to_dsi_mode(drm_mode, &dsi_mode);
  611. dsi_display_put_mode(display, &dsi_mode);
  612. }
  613. /* free the display structure modes also */
  614. dsi_display = display;
  615. kfree(dsi_display->modes);
  616. dsi_display->modes = NULL;
  617. }
  618. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  619. {
  620. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  621. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  622. u32 dtd_size = 18;
  623. u32 header_size = sizeof(standard_header);
  624. if (!name)
  625. return -EINVAL;
  626. /* Fill standard header */
  627. memcpy(dtd, standard_header, header_size);
  628. dtd_size -= header_size;
  629. dtd_size = min_t(u32, dtd_size, strlen(name));
  630. memcpy(dtd + header_size, name, dtd_size);
  631. return 0;
  632. }
  633. static void dsi_drm_update_dtd(struct edid *edid,
  634. struct dsi_display_mode *modes, u32 modes_count)
  635. {
  636. u32 i;
  637. u32 count = min_t(u32, modes_count, 3);
  638. for (i = 0; i < count; i++) {
  639. struct detailed_timing *dtd = &edid->detailed_timings[i];
  640. struct dsi_display_mode *mode = &modes[i];
  641. struct dsi_mode_info *timing = &mode->timing;
  642. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  643. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  644. timing->h_back_porch;
  645. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  646. timing->v_back_porch;
  647. u32 h_img = 0, v_img = 0;
  648. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  649. pd->hactive_lo = timing->h_active & 0xFF;
  650. pd->hblank_lo = h_blank & 0xFF;
  651. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  652. ((timing->h_active >> 8) & 0xF) << 4;
  653. pd->vactive_lo = timing->v_active & 0xFF;
  654. pd->vblank_lo = v_blank & 0xFF;
  655. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  656. ((timing->v_active >> 8) & 0xF) << 4;
  657. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  658. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  659. pd->vsync_offset_pulse_width_lo =
  660. ((timing->v_front_porch & 0xF) << 4) |
  661. (timing->v_sync_width & 0xF);
  662. pd->hsync_vsync_offset_pulse_width_hi =
  663. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  664. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  665. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  666. (((timing->v_sync_width >> 4) & 0x3) << 0);
  667. pd->width_mm_lo = h_img & 0xFF;
  668. pd->height_mm_lo = v_img & 0xFF;
  669. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  670. ((v_img >> 8) & 0xF);
  671. pd->hborder = 0;
  672. pd->vborder = 0;
  673. pd->misc = 0;
  674. }
  675. }
  676. static void dsi_drm_update_checksum(struct edid *edid)
  677. {
  678. u8 *data = (u8 *)edid;
  679. u32 i, sum = 0;
  680. for (i = 0; i < EDID_LENGTH - 1; i++)
  681. sum += data[i];
  682. edid->checksum = 0x100 - (sum & 0xFF);
  683. }
  684. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  685. const struct msm_resource_caps_info *avail_res)
  686. {
  687. int rc, i;
  688. u32 count = 0, edid_size;
  689. struct dsi_display_mode *modes = NULL;
  690. struct drm_display_mode drm_mode;
  691. struct dsi_display *display = data;
  692. struct edid edid;
  693. u8 width_mm = connector->display_info.width_mm;
  694. u8 height_mm = connector->display_info.height_mm;
  695. const u8 edid_buf[EDID_LENGTH] = {
  696. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  697. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  698. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  699. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  700. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  701. 0x01, 0x01, 0x01, 0x01,
  702. };
  703. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  704. memcpy(&edid, edid_buf, edid_size);
  705. rc = dsi_display_get_mode_count(display, &count);
  706. if (rc) {
  707. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  708. goto end;
  709. }
  710. rc = dsi_display_get_modes(display, &modes);
  711. if (rc) {
  712. DSI_ERR("failed to get modes, rc=%d\n", rc);
  713. count = 0;
  714. goto end;
  715. }
  716. for (i = 0; i < count; i++) {
  717. struct drm_display_mode *m;
  718. memset(&drm_mode, 0x0, sizeof(drm_mode));
  719. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  720. m = drm_mode_duplicate(connector->dev, &drm_mode);
  721. if (!m) {
  722. DSI_ERR("failed to add mode %ux%u\n",
  723. drm_mode.hdisplay,
  724. drm_mode.vdisplay);
  725. count = -ENOMEM;
  726. goto end;
  727. }
  728. m->width_mm = connector->display_info.width_mm;
  729. m->height_mm = connector->display_info.height_mm;
  730. /* set the first mode in list as preferred */
  731. if (i == 0)
  732. m->type |= DRM_MODE_TYPE_PREFERRED;
  733. drm_mode_probed_add(connector, m);
  734. }
  735. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  736. if (rc) {
  737. count = 0;
  738. goto end;
  739. }
  740. edid.width_cm = (connector->display_info.width_mm) / 10;
  741. edid.height_cm = (connector->display_info.height_mm) / 10;
  742. dsi_drm_update_dtd(&edid, modes, count);
  743. dsi_drm_update_checksum(&edid);
  744. rc = drm_connector_update_edid_property(connector, &edid);
  745. if (rc)
  746. count = 0;
  747. /*
  748. * DRM EDID structure maintains panel physical dimensions in
  749. * centimeters, we will be losing the precision anything below cm.
  750. * Changing DRM framework will effect other clients at this
  751. * moment, overriding the values back to millimeter.
  752. */
  753. connector->display_info.width_mm = width_mm;
  754. connector->display_info.height_mm = height_mm;
  755. end:
  756. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  757. return count;
  758. }
  759. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  760. struct drm_display_mode *mode,
  761. void *display, const struct msm_resource_caps_info *avail_res)
  762. {
  763. struct dsi_display_mode dsi_mode;
  764. int rc;
  765. if (!connector || !mode) {
  766. DSI_ERR("Invalid params\n");
  767. return MODE_ERROR;
  768. }
  769. convert_to_dsi_mode(mode, &dsi_mode);
  770. rc = dsi_display_validate_mode(display, &dsi_mode,
  771. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  772. if (rc) {
  773. DSI_ERR("mode not supported, rc=%d\n", rc);
  774. return MODE_BAD;
  775. }
  776. return MODE_OK;
  777. }
  778. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  779. void *display,
  780. struct msm_display_kickoff_params *params)
  781. {
  782. if (!connector || !display || !params) {
  783. DSI_ERR("Invalid params\n");
  784. return -EINVAL;
  785. }
  786. return dsi_display_pre_kickoff(connector, display, params);
  787. }
  788. int dsi_conn_prepare_commit(void *display,
  789. struct msm_display_conn_params *params)
  790. {
  791. if (!display || !params) {
  792. pr_err("Invalid params\n");
  793. return -EINVAL;
  794. }
  795. return dsi_display_pre_commit(display, params);
  796. }
  797. void dsi_conn_enable_event(struct drm_connector *connector,
  798. uint32_t event_idx, bool enable, void *display)
  799. {
  800. struct dsi_event_cb_info event_info;
  801. memset(&event_info, 0, sizeof(event_info));
  802. event_info.event_cb = sde_connector_trigger_event;
  803. event_info.event_usr_ptr = connector;
  804. dsi_display_enable_event(connector, display,
  805. event_idx, &event_info, enable);
  806. }
  807. int dsi_conn_post_kickoff(struct drm_connector *connector,
  808. struct msm_display_conn_params *params)
  809. {
  810. struct drm_encoder *encoder;
  811. struct dsi_bridge *c_bridge;
  812. struct dsi_display_mode adj_mode;
  813. struct dsi_display *display;
  814. struct dsi_display_ctrl *m_ctrl, *ctrl;
  815. int i, rc = 0;
  816. bool enable;
  817. if (!connector || !connector->state) {
  818. DSI_ERR("invalid connector or connector state\n");
  819. return -EINVAL;
  820. }
  821. encoder = connector->state->best_encoder;
  822. if (!encoder) {
  823. DSI_DEBUG("best encoder is not available\n");
  824. return 0;
  825. }
  826. c_bridge = to_dsi_bridge(encoder->bridge);
  827. adj_mode = c_bridge->dsi_mode;
  828. display = c_bridge->display;
  829. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  830. m_ctrl = &display->ctrl[display->clk_master_idx];
  831. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  832. if (rc) {
  833. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  834. display->name, rc);
  835. return -EINVAL;
  836. }
  837. /* Update the rest of the controllers */
  838. display_for_each_ctrl(i, display) {
  839. ctrl = &display->ctrl[i];
  840. if (!ctrl->ctrl || (ctrl == m_ctrl))
  841. continue;
  842. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  843. if (rc) {
  844. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  845. display->name, rc);
  846. return -EINVAL;
  847. }
  848. }
  849. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  850. }
  851. /* ensure dynamic clk switch flag is reset */
  852. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  853. if (params->qsync_update) {
  854. enable = (params->qsync_mode > 0) ? true : false;
  855. display_for_each_ctrl(i, display)
  856. dsi_ctrl_setup_avr(display->ctrl[i].ctrl, enable);
  857. }
  858. return 0;
  859. }
  860. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  861. struct drm_device *dev,
  862. struct drm_encoder *encoder)
  863. {
  864. int rc = 0;
  865. struct dsi_bridge *bridge;
  866. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  867. if (!bridge) {
  868. rc = -ENOMEM;
  869. goto error;
  870. }
  871. bridge->display = display;
  872. bridge->base.funcs = &dsi_bridge_ops;
  873. bridge->base.encoder = encoder;
  874. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  875. if (rc) {
  876. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  877. goto error_free_bridge;
  878. }
  879. encoder->bridge = &bridge->base;
  880. return bridge;
  881. error_free_bridge:
  882. kfree(bridge);
  883. error:
  884. return ERR_PTR(rc);
  885. }
  886. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  887. {
  888. if (bridge && bridge->base.encoder)
  889. bridge->base.encoder->bridge = NULL;
  890. kfree(bridge);
  891. }