f853241025
UMAC HW reset feature will be using the last interrupt context in each DP interrupt combination i.e., on a system with more than 8 MSIs for DP, UMAC HW reset will be assigned a dedicated interrupt context. Add the necessary support for the same. CRs-Fixed: 3163900 Change-Id: I26abd01e4261661ed95e1aa3cb2a774e78b50d9f
92 rader
2.8 KiB
C
92 rader
2.8 KiB
C
/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <dp_types.h>
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#include <wlan_cfg.h>
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/**
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* dp_get_umac_reset_intr_ctx() - Get the interrupt context to be used by
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* UMAC reset feature
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* @soc: DP soc object
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* @intr_ctx: Interrupt context variable to be populated by this API
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*
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* Return: QDF_STATUS of operation
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*/
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static QDF_STATUS dp_get_umac_reset_intr_ctx(struct dp_soc *soc, int *intr_ctx)
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{
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int umac_reset_mask, i;
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/**
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* Go over all the contexts and check which interrupt context has
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* the UMAC reset mask set.
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*/
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for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
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umac_reset_mask = wlan_cfg_get_umac_reset_intr_mask(
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soc->wlan_cfg_ctx, i);
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if (umac_reset_mask) {
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*intr_ctx = i;
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return QDF_STATUS_SUCCESS;
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}
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}
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*intr_ctx = -1;
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return QDF_STATUS_E_FAILURE;
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}
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QDF_STATUS dp_soc_umac_reset_init(struct dp_soc *soc)
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{
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struct dp_soc_umac_reset_ctx *umac_reset_ctx;
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size_t alloc_size;
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QDF_STATUS status;
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if (!soc) {
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dp_umac_reset_err("DP SOC is null");
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return QDF_STATUS_E_NULL_VALUE;
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}
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umac_reset_ctx = &soc->umac_reset_ctx;
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qdf_mem_zero(umac_reset_ctx, sizeof(*umac_reset_ctx));
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umac_reset_ctx->current_state = UMAC_RESET_STATE_WAIT_FOR_PRE_RESET;
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status = dp_get_umac_reset_intr_ctx(soc, &umac_reset_ctx->intr_offset);
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if (QDF_IS_STATUS_ERROR(status)) {
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dp_umac_reset_err("No interrupt assignment");
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return status;
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}
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alloc_size = sizeof(struct umac_reset_shmem) +
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DP_UMAC_RESET_SHMEM_ALIGN - 1;
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umac_reset_ctx->shmem_vaddr_unaligned =
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qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
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alloc_size,
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&umac_reset_ctx->shmem_paddr_unaligned);
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if (!umac_reset_ctx->shmem_vaddr_unaligned) {
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dp_umac_reset_err("shmem allocation failed");
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return QDF_STATUS_E_NOMEM;
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}
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umac_reset_ctx->shmem_vaddr_aligned = (void *)(uintptr_t)qdf_roundup(
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(uint64_t)(uintptr_t)umac_reset_ctx->shmem_vaddr_unaligned,
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DP_UMAC_RESET_SHMEM_ALIGN);
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umac_reset_ctx->shmem_paddr_aligned = qdf_roundup(
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(uint64_t)umac_reset_ctx->shmem_paddr_unaligned,
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DP_UMAC_RESET_SHMEM_ALIGN);
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return QDF_STATUS_SUCCESS;
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}
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