sde_rm.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s] " fmt, __func__
  6. #include "sde_kms.h"
  7. #include "sde_hw_lm.h"
  8. #include "sde_hw_ctl.h"
  9. #include "sde_hw_cdm.h"
  10. #include "sde_hw_dspp.h"
  11. #include "sde_hw_ds.h"
  12. #include "sde_hw_pingpong.h"
  13. #include "sde_hw_intf.h"
  14. #include "sde_hw_wb.h"
  15. #include "sde_encoder.h"
  16. #include "sde_connector.h"
  17. #include "sde_hw_dsc.h"
  18. #include "sde_hw_vdc.h"
  19. #include "sde_crtc.h"
  20. #include "sde_hw_qdss.h"
  21. #define RESERVED_BY_OTHER(h, r) \
  22. (((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
  23. ((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
  24. #define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
  25. #define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
  26. #define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
  27. #define RM_RQ_DS(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DS))
  28. #define RM_RQ_CWB(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_CWB))
  29. #define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
  30. (t).num_comp_enc == (r).num_enc && \
  31. (t).num_intf == (r).num_intf && \
  32. (t).comp_type == (r).comp_type)
  33. /* ~one vsync poll time for rsvp_nxt to cleared by modeset from commit thread */
  34. #define RM_NXT_CLEAR_POLL_TIMEOUT_US 16600
  35. /**
  36. * toplogy information to be used when ctl path version does not
  37. * support driving more than one interface per ctl_path
  38. */
  39. static const struct sde_rm_topology_def g_top_table[SDE_RM_TOPOLOGY_MAX] = {
  40. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  41. MSM_DISPLAY_COMPRESSION_NONE },
  42. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  43. MSM_DISPLAY_COMPRESSION_NONE },
  44. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  45. MSM_DISPLAY_COMPRESSION_DSC },
  46. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true,
  47. MSM_DISPLAY_COMPRESSION_NONE },
  48. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 2, true,
  49. MSM_DISPLAY_COMPRESSION_DSC },
  50. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  51. MSM_DISPLAY_COMPRESSION_NONE },
  52. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  53. MSM_DISPLAY_COMPRESSION_DSC },
  54. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  55. MSM_DISPLAY_COMPRESSION_DSC },
  56. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true,
  57. MSM_DISPLAY_COMPRESSION_NONE },
  58. };
  59. /**
  60. * topology information to be used when the ctl path version
  61. * is SDE_CTL_CFG_VERSION_1_0_0
  62. */
  63. static const struct sde_rm_topology_def g_top_table_v1[SDE_RM_TOPOLOGY_MAX] = {
  64. { SDE_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false,
  65. MSM_DISPLAY_COMPRESSION_NONE },
  66. { SDE_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false,
  67. MSM_DISPLAY_COMPRESSION_NONE },
  68. { SDE_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false,
  69. MSM_DISPLAY_COMPRESSION_DSC },
  70. { SDE_RM_TOPOLOGY_SINGLEPIPE_VDC, 1, 1, 1, 1, false,
  71. MSM_DISPLAY_COMPRESSION_VDC },
  72. { SDE_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 1, true,
  73. MSM_DISPLAY_COMPRESSION_NONE },
  74. { SDE_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 1, true,
  75. MSM_DISPLAY_COMPRESSION_DSC },
  76. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false,
  77. MSM_DISPLAY_COMPRESSION_NONE },
  78. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false,
  79. MSM_DISPLAY_COMPRESSION_DSC },
  80. { SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC, 2, 1, 1, 1, false,
  81. MSM_DISPLAY_COMPRESSION_VDC },
  82. { SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false,
  83. MSM_DISPLAY_COMPRESSION_DSC },
  84. { SDE_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true,
  85. MSM_DISPLAY_COMPRESSION_NONE },
  86. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE, 4, 0, 2, 1, false,
  87. MSM_DISPLAY_COMPRESSION_NONE },
  88. { SDE_RM_TOPOLOGY_QUADPIPE_3DMERGE_DSC, 4, 3, 2, 1, false,
  89. MSM_DISPLAY_COMPRESSION_DSC },
  90. { SDE_RM_TOPOLOGY_QUADPIPE_DSCMERGE, 4, 4, 2, 1, false,
  91. MSM_DISPLAY_COMPRESSION_DSC },
  92. { SDE_RM_TOPOLOGY_QUADPIPE_DSC4HSMERGE, 4, 4, 1, 1, false,
  93. MSM_DISPLAY_COMPRESSION_DSC },
  94. };
  95. /**
  96. * struct sde_rm_requirements - Reservation requirements parameter bundle
  97. * @top_ctrl: topology control preference from kernel client
  98. * @top: selected topology for the display
  99. * @hw_res: Hardware resources required as reported by the encoders
  100. */
  101. struct sde_rm_requirements {
  102. uint64_t top_ctrl;
  103. const struct sde_rm_topology_def *topology;
  104. struct sde_encoder_hw_resources hw_res;
  105. };
  106. /**
  107. * struct sde_rm_rsvp - Use Case Reservation tagging structure
  108. * Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
  109. * By using as a tag, rather than lists of pointers to HW blocks used
  110. * we can avoid some list management since we don't know how many blocks
  111. * of each type a given use case may require.
  112. * @list: List head for list of all reservations
  113. * @seq: Global RSVP sequence number for debugging, especially for
  114. * differentiating differenct allocations for same encoder.
  115. * @enc_id: Reservations are tracked by Encoder DRM object ID.
  116. * CRTCs may be connected to multiple Encoders.
  117. * An encoder or connector id identifies the display path.
  118. * @topology DRM<->HW topology use case
  119. */
  120. struct sde_rm_rsvp {
  121. struct list_head list;
  122. uint32_t seq;
  123. uint32_t enc_id;
  124. enum sde_rm_topology_name topology;
  125. };
  126. /**
  127. * struct sde_rm_hw_blk - hardware block tracking list member
  128. * @list: List head for list of all hardware blocks tracking items
  129. * @rsvp: Pointer to use case reservation if reserved by a client
  130. * @rsvp_nxt: Temporary pointer used during reservation to the incoming
  131. * request. Will be swapped into rsvp if proposal is accepted
  132. * @type: Type of hardware block this structure tracks
  133. * @id: Hardware ID number, within it's own space, ie. LM_X
  134. * @catalog: Pointer to the hardware catalog entry for this block
  135. * @hw: Pointer to the hardware register access object for this block
  136. */
  137. struct sde_rm_hw_blk {
  138. struct list_head list;
  139. struct sde_rm_rsvp *rsvp;
  140. struct sde_rm_rsvp *rsvp_nxt;
  141. enum sde_hw_blk_type type;
  142. uint32_t id;
  143. struct sde_hw_blk *hw;
  144. };
  145. /**
  146. * sde_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
  147. */
  148. enum sde_rm_dbg_rsvp_stage {
  149. SDE_RM_STAGE_BEGIN,
  150. SDE_RM_STAGE_AFTER_CLEAR,
  151. SDE_RM_STAGE_AFTER_RSVPNEXT,
  152. SDE_RM_STAGE_FINAL
  153. };
  154. static void _sde_rm_inc_resource_info_lm(struct sde_rm *rm,
  155. struct msm_resource_caps_info *avail_res,
  156. struct sde_rm_hw_blk *blk)
  157. {
  158. struct sde_rm_hw_blk *blk2;
  159. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  160. avail_res->num_lm++;
  161. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  162. /* Check for 3d muxes by comparing paired lms */
  163. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  164. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  165. /*
  166. * If lm2 is free, or
  167. * lm1 & lm2 reserved by same enc, check mask
  168. */
  169. if ((!blk2->rsvp || (blk->rsvp &&
  170. blk2->rsvp->enc_id == blk->rsvp->enc_id
  171. && lm_cfg->id > lm_cfg2->id)) &&
  172. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  173. avail_res->num_3dmux++;
  174. }
  175. }
  176. static void _sde_rm_dec_resource_info_lm(struct sde_rm *rm,
  177. struct msm_resource_caps_info *avail_res,
  178. struct sde_rm_hw_blk *blk)
  179. {
  180. struct sde_rm_hw_blk *blk2;
  181. const struct sde_lm_cfg *lm_cfg, *lm_cfg2;
  182. avail_res->num_lm--;
  183. lm_cfg = to_sde_hw_mixer(blk->hw)->cap;
  184. /* Check for 3d muxes by comparing paired lms */
  185. list_for_each_entry(blk2, &rm->hw_blks[SDE_HW_BLK_LM], list) {
  186. lm_cfg2 = to_sde_hw_mixer(blk2->hw)->cap;
  187. /* If lm2 is free and lm1 is now being reserved */
  188. if (!blk2->rsvp &&
  189. test_bit(lm_cfg->id, &lm_cfg2->lm_pair_mask))
  190. avail_res->num_3dmux--;
  191. }
  192. }
  193. static void _sde_rm_inc_resource_info(struct sde_rm *rm,
  194. struct msm_resource_caps_info *avail_res,
  195. struct sde_rm_hw_blk *blk)
  196. {
  197. enum sde_hw_blk_type type = blk->type;
  198. if (type == SDE_HW_BLK_LM)
  199. _sde_rm_inc_resource_info_lm(rm, avail_res, blk);
  200. else if (type == SDE_HW_BLK_CTL)
  201. avail_res->num_ctl++;
  202. else if (type == SDE_HW_BLK_DSC)
  203. avail_res->num_dsc++;
  204. else if (type == SDE_HW_BLK_VDC)
  205. avail_res->num_vdc++;
  206. }
  207. static void _sde_rm_dec_resource_info(struct sde_rm *rm,
  208. struct msm_resource_caps_info *avail_res,
  209. struct sde_rm_hw_blk *blk)
  210. {
  211. enum sde_hw_blk_type type = blk->type;
  212. if (type == SDE_HW_BLK_LM)
  213. _sde_rm_dec_resource_info_lm(rm, avail_res, blk);
  214. else if (type == SDE_HW_BLK_CTL)
  215. avail_res->num_ctl--;
  216. else if (type == SDE_HW_BLK_DSC)
  217. avail_res->num_dsc--;
  218. else if (type == SDE_HW_BLK_VDC)
  219. avail_res->num_vdc--;
  220. }
  221. void sde_rm_get_resource_info(struct sde_rm *rm,
  222. struct drm_encoder *drm_enc,
  223. struct msm_resource_caps_info *avail_res)
  224. {
  225. struct sde_rm_hw_blk *blk;
  226. enum sde_hw_blk_type type;
  227. struct sde_rm_rsvp rsvp;
  228. memcpy(avail_res, &rm->avail_res,
  229. sizeof(rm->avail_res));
  230. if (!drm_enc)
  231. return;
  232. rsvp.enc_id = drm_enc->base.id;
  233. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  234. list_for_each_entry(blk, &rm->hw_blks[type], list)
  235. if (blk->rsvp && blk->rsvp->enc_id == rsvp.enc_id)
  236. _sde_rm_inc_resource_info(rm, avail_res, blk);
  237. }
  238. static void _sde_rm_print_rsvps(
  239. struct sde_rm *rm,
  240. enum sde_rm_dbg_rsvp_stage stage)
  241. {
  242. struct sde_rm_rsvp *rsvp;
  243. struct sde_rm_hw_blk *blk;
  244. enum sde_hw_blk_type type;
  245. SDE_DEBUG("%d\n", stage);
  246. list_for_each_entry(rsvp, &rm->rsvps, list) {
  247. SDE_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
  248. rsvp->enc_id, rsvp->topology);
  249. SDE_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
  250. }
  251. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  252. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  253. if (!blk->rsvp && !blk->rsvp_nxt)
  254. continue;
  255. SDE_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
  256. (blk->rsvp) ? blk->rsvp->seq : 0,
  257. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  258. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  259. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  260. blk->type, blk->id);
  261. SDE_EVT32(stage,
  262. (blk->rsvp) ? blk->rsvp->seq : 0,
  263. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  264. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  265. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  266. blk->type, blk->id);
  267. }
  268. }
  269. }
  270. static void _sde_rm_print_rsvps_by_type(
  271. struct sde_rm *rm,
  272. enum sde_hw_blk_type type)
  273. {
  274. struct sde_rm_hw_blk *blk;
  275. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  276. if (!blk->rsvp && !blk->rsvp_nxt)
  277. continue;
  278. SDE_ERROR("rsvp[s%ue%u->s%ue%u] %d %d\n",
  279. (blk->rsvp) ? blk->rsvp->seq : 0,
  280. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  281. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  282. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  283. blk->type, blk->id);
  284. SDE_EVT32((blk->rsvp) ? blk->rsvp->seq : 0,
  285. (blk->rsvp) ? blk->rsvp->enc_id : 0,
  286. (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
  287. (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
  288. blk->type, blk->id);
  289. }
  290. }
  291. struct sde_hw_mdp *sde_rm_get_mdp(struct sde_rm *rm)
  292. {
  293. return rm->hw_mdp;
  294. }
  295. void sde_rm_init_hw_iter(
  296. struct sde_rm_hw_iter *iter,
  297. uint32_t enc_id,
  298. enum sde_hw_blk_type type)
  299. {
  300. memset(iter, 0, sizeof(*iter));
  301. iter->enc_id = enc_id;
  302. iter->type = type;
  303. }
  304. enum sde_rm_topology_name sde_rm_get_topology_name(struct sde_rm *rm,
  305. struct msm_display_topology topology)
  306. {
  307. int i;
  308. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  309. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  310. topology))
  311. return rm->topology_tbl[i].top_name;
  312. return SDE_RM_TOPOLOGY_NONE;
  313. }
  314. static bool _sde_rm_get_hw_locked(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  315. {
  316. struct list_head *blk_list;
  317. if (!rm || !i || i->type >= SDE_HW_BLK_MAX) {
  318. SDE_ERROR("invalid rm\n");
  319. return false;
  320. }
  321. i->hw = NULL;
  322. blk_list = &rm->hw_blks[i->type];
  323. if (i->blk && (&i->blk->list == blk_list)) {
  324. SDE_DEBUG("attempt resume iteration past last\n");
  325. return false;
  326. }
  327. i->blk = list_prepare_entry(i->blk, blk_list, list);
  328. list_for_each_entry_continue(i->blk, blk_list, list) {
  329. struct sde_rm_rsvp *rsvp = i->blk->rsvp;
  330. if (i->blk->type != i->type) {
  331. SDE_ERROR("found incorrect block type %d on %d list\n",
  332. i->blk->type, i->type);
  333. return false;
  334. }
  335. if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
  336. i->hw = i->blk->hw;
  337. SDE_DEBUG("found type %d id %d for enc %d\n",
  338. i->type, i->blk->id, i->enc_id);
  339. return true;
  340. }
  341. }
  342. SDE_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
  343. return false;
  344. }
  345. static bool _sde_rm_request_hw_blk_locked(struct sde_rm *rm,
  346. struct sde_rm_hw_request *hw_blk_info)
  347. {
  348. struct list_head *blk_list;
  349. struct sde_rm_hw_blk *blk = NULL;
  350. if (!rm || !hw_blk_info || hw_blk_info->type >= SDE_HW_BLK_MAX) {
  351. SDE_ERROR("invalid rm\n");
  352. return false;
  353. }
  354. hw_blk_info->hw = NULL;
  355. blk_list = &rm->hw_blks[hw_blk_info->type];
  356. blk = list_prepare_entry(blk, blk_list, list);
  357. list_for_each_entry_continue(blk, blk_list, list) {
  358. if (blk->type != hw_blk_info->type) {
  359. SDE_ERROR("found incorrect block type %d on %d list\n",
  360. blk->type, hw_blk_info->type);
  361. return false;
  362. }
  363. if (blk->hw->id == hw_blk_info->id) {
  364. hw_blk_info->hw = blk->hw;
  365. SDE_DEBUG("found type %d id %d\n",
  366. blk->type, blk->id);
  367. return true;
  368. }
  369. }
  370. SDE_DEBUG("no match, type %d id %d\n", hw_blk_info->type,
  371. hw_blk_info->id);
  372. return false;
  373. }
  374. bool sde_rm_get_hw(struct sde_rm *rm, struct sde_rm_hw_iter *i)
  375. {
  376. bool ret;
  377. mutex_lock(&rm->rm_lock);
  378. ret = _sde_rm_get_hw_locked(rm, i);
  379. mutex_unlock(&rm->rm_lock);
  380. return ret;
  381. }
  382. bool sde_rm_request_hw_blk(struct sde_rm *rm, struct sde_rm_hw_request *hw)
  383. {
  384. bool ret;
  385. mutex_lock(&rm->rm_lock);
  386. ret = _sde_rm_request_hw_blk_locked(rm, hw);
  387. mutex_unlock(&rm->rm_lock);
  388. return ret;
  389. }
  390. static void _sde_rm_hw_destroy(enum sde_hw_blk_type type, void *hw)
  391. {
  392. switch (type) {
  393. case SDE_HW_BLK_LM:
  394. sde_hw_lm_destroy(hw);
  395. break;
  396. case SDE_HW_BLK_DSPP:
  397. sde_hw_dspp_destroy(hw);
  398. break;
  399. case SDE_HW_BLK_DS:
  400. sde_hw_ds_destroy(hw);
  401. break;
  402. case SDE_HW_BLK_CTL:
  403. sde_hw_ctl_destroy(hw);
  404. break;
  405. case SDE_HW_BLK_CDM:
  406. sde_hw_cdm_destroy(hw);
  407. break;
  408. case SDE_HW_BLK_PINGPONG:
  409. sde_hw_pingpong_destroy(hw);
  410. break;
  411. case SDE_HW_BLK_INTF:
  412. sde_hw_intf_destroy(hw);
  413. break;
  414. case SDE_HW_BLK_WB:
  415. sde_hw_wb_destroy(hw);
  416. break;
  417. case SDE_HW_BLK_DSC:
  418. sde_hw_dsc_destroy(hw);
  419. break;
  420. case SDE_HW_BLK_VDC:
  421. sde_hw_vdc_destroy(hw);
  422. break;
  423. case SDE_HW_BLK_QDSS:
  424. sde_hw_qdss_destroy(hw);
  425. break;
  426. case SDE_HW_BLK_SSPP:
  427. /* SSPPs are not managed by the resource manager */
  428. case SDE_HW_BLK_TOP:
  429. /* Top is a singleton, not managed in hw_blks list */
  430. case SDE_HW_BLK_MAX:
  431. default:
  432. SDE_ERROR("unsupported block type %d\n", type);
  433. break;
  434. }
  435. }
  436. int sde_rm_destroy(struct sde_rm *rm)
  437. {
  438. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  439. struct sde_rm_hw_blk *hw_cur, *hw_nxt;
  440. enum sde_hw_blk_type type;
  441. if (!rm) {
  442. SDE_ERROR("invalid rm\n");
  443. return -EINVAL;
  444. }
  445. list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
  446. list_del(&rsvp_cur->list);
  447. kfree(rsvp_cur);
  448. }
  449. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  450. list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
  451. list) {
  452. list_del(&hw_cur->list);
  453. _sde_rm_hw_destroy(hw_cur->type, hw_cur->hw);
  454. kfree(hw_cur);
  455. }
  456. }
  457. sde_hw_mdp_destroy(rm->hw_mdp);
  458. rm->hw_mdp = NULL;
  459. mutex_destroy(&rm->rm_lock);
  460. return 0;
  461. }
  462. static int _sde_rm_hw_blk_create(
  463. struct sde_rm *rm,
  464. struct sde_mdss_cfg *cat,
  465. void __iomem *mmio,
  466. enum sde_hw_blk_type type,
  467. uint32_t id,
  468. void *hw_catalog_info)
  469. {
  470. struct sde_rm_hw_blk *blk;
  471. struct sde_hw_mdp *hw_mdp;
  472. void *hw;
  473. hw_mdp = rm->hw_mdp;
  474. switch (type) {
  475. case SDE_HW_BLK_LM:
  476. hw = sde_hw_lm_init(id, mmio, cat);
  477. break;
  478. case SDE_HW_BLK_DSPP:
  479. hw = sde_hw_dspp_init(id, mmio, cat);
  480. break;
  481. case SDE_HW_BLK_DS:
  482. hw = sde_hw_ds_init(id, mmio, cat);
  483. break;
  484. case SDE_HW_BLK_CTL:
  485. hw = sde_hw_ctl_init(id, mmio, cat);
  486. break;
  487. case SDE_HW_BLK_CDM:
  488. hw = sde_hw_cdm_init(id, mmio, cat, hw_mdp);
  489. break;
  490. case SDE_HW_BLK_PINGPONG:
  491. hw = sde_hw_pingpong_init(id, mmio, cat);
  492. break;
  493. case SDE_HW_BLK_INTF:
  494. hw = sde_hw_intf_init(id, mmio, cat);
  495. break;
  496. case SDE_HW_BLK_WB:
  497. hw = sde_hw_wb_init(id, mmio, cat, hw_mdp);
  498. break;
  499. case SDE_HW_BLK_DSC:
  500. hw = sde_hw_dsc_init(id, mmio, cat);
  501. break;
  502. case SDE_HW_BLK_VDC:
  503. hw = sde_hw_vdc_init(id, mmio, cat);
  504. break;
  505. case SDE_HW_BLK_QDSS:
  506. hw = sde_hw_qdss_init(id, mmio, cat);
  507. break;
  508. case SDE_HW_BLK_SSPP:
  509. /* SSPPs are not managed by the resource manager */
  510. case SDE_HW_BLK_TOP:
  511. /* Top is a singleton, not managed in hw_blks list */
  512. case SDE_HW_BLK_MAX:
  513. default:
  514. SDE_ERROR("unsupported block type %d\n", type);
  515. return -EINVAL;
  516. }
  517. if (IS_ERR_OR_NULL(hw)) {
  518. SDE_ERROR("failed hw object creation: type %d, err %ld\n",
  519. type, PTR_ERR(hw));
  520. return -EFAULT;
  521. }
  522. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  523. if (!blk) {
  524. _sde_rm_hw_destroy(type, hw);
  525. return -ENOMEM;
  526. }
  527. blk->type = type;
  528. blk->id = id;
  529. blk->hw = hw;
  530. list_add_tail(&blk->list, &rm->hw_blks[type]);
  531. _sde_rm_inc_resource_info(rm, &rm->avail_res, blk);
  532. return 0;
  533. }
  534. static int _sde_rm_hw_blk_create_new(struct sde_rm *rm,
  535. struct sde_mdss_cfg *cat,
  536. void __iomem *mmio)
  537. {
  538. int i, rc = 0;
  539. for (i = 0; i < cat->dspp_count; i++) {
  540. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSPP,
  541. cat->dspp[i].id, &cat->dspp[i]);
  542. if (rc) {
  543. SDE_ERROR("failed: dspp hw not available\n");
  544. goto fail;
  545. }
  546. }
  547. if (cat->mdp[0].has_dest_scaler) {
  548. for (i = 0; i < cat->ds_count; i++) {
  549. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DS,
  550. cat->ds[i].id, &cat->ds[i]);
  551. if (rc) {
  552. SDE_ERROR("failed: ds hw not available\n");
  553. goto fail;
  554. }
  555. }
  556. }
  557. for (i = 0; i < cat->pingpong_count; i++) {
  558. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_PINGPONG,
  559. cat->pingpong[i].id, &cat->pingpong[i]);
  560. if (rc) {
  561. SDE_ERROR("failed: pp hw not available\n");
  562. goto fail;
  563. }
  564. }
  565. for (i = 0; i < cat->dsc_count; i++) {
  566. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_DSC,
  567. cat->dsc[i].id, &cat->dsc[i]);
  568. if (rc) {
  569. SDE_ERROR("failed: dsc hw not available\n");
  570. goto fail;
  571. }
  572. }
  573. for (i = 0; i < cat->vdc_count; i++) {
  574. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_VDC,
  575. cat->vdc[i].id, &cat->vdc[i]);
  576. if (rc) {
  577. SDE_ERROR("failed: vdc hw not available\n");
  578. goto fail;
  579. }
  580. }
  581. for (i = 0; i < cat->intf_count; i++) {
  582. if (cat->intf[i].type == INTF_NONE) {
  583. SDE_DEBUG("skip intf %d with type none\n", i);
  584. continue;
  585. }
  586. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_INTF,
  587. cat->intf[i].id, &cat->intf[i]);
  588. if (rc) {
  589. SDE_ERROR("failed: intf hw not available\n");
  590. goto fail;
  591. }
  592. }
  593. for (i = 0; i < cat->wb_count; i++) {
  594. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_WB,
  595. cat->wb[i].id, &cat->wb[i]);
  596. if (rc) {
  597. SDE_ERROR("failed: wb hw not available\n");
  598. goto fail;
  599. }
  600. }
  601. for (i = 0; i < cat->ctl_count; i++) {
  602. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CTL,
  603. cat->ctl[i].id, &cat->ctl[i]);
  604. if (rc) {
  605. SDE_ERROR("failed: ctl hw not available\n");
  606. goto fail;
  607. }
  608. }
  609. for (i = 0; i < cat->cdm_count; i++) {
  610. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_CDM,
  611. cat->cdm[i].id, &cat->cdm[i]);
  612. if (rc) {
  613. SDE_ERROR("failed: cdm hw not available\n");
  614. goto fail;
  615. }
  616. }
  617. for (i = 0; i < cat->qdss_count; i++) {
  618. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_QDSS,
  619. cat->qdss[i].id, &cat->qdss[i]);
  620. if (rc) {
  621. SDE_ERROR("failed: qdss hw not available\n");
  622. goto fail;
  623. }
  624. }
  625. fail:
  626. return rc;
  627. }
  628. int sde_rm_init(struct sde_rm *rm,
  629. struct sde_mdss_cfg *cat,
  630. void __iomem *mmio,
  631. struct drm_device *dev)
  632. {
  633. int i, rc = 0;
  634. enum sde_hw_blk_type type;
  635. if (!rm || !cat || !mmio || !dev) {
  636. SDE_ERROR("invalid input params\n");
  637. return -EINVAL;
  638. }
  639. /* Clear, setup lists */
  640. memset(rm, 0, sizeof(*rm));
  641. mutex_init(&rm->rm_lock);
  642. INIT_LIST_HEAD(&rm->rsvps);
  643. for (type = 0; type < SDE_HW_BLK_MAX; type++)
  644. INIT_LIST_HEAD(&rm->hw_blks[type]);
  645. rm->dev = dev;
  646. if (IS_SDE_CTL_REV_100(cat->ctl_rev))
  647. rm->topology_tbl = g_top_table_v1;
  648. else
  649. rm->topology_tbl = g_top_table;
  650. /* Some of the sub-blocks require an mdptop to be created */
  651. rm->hw_mdp = sde_hw_mdptop_init(MDP_TOP, mmio, cat);
  652. if (IS_ERR_OR_NULL(rm->hw_mdp)) {
  653. rc = PTR_ERR(rm->hw_mdp);
  654. rm->hw_mdp = NULL;
  655. SDE_ERROR("failed: mdp hw not available\n");
  656. goto fail;
  657. }
  658. /* Interrogate HW catalog and create tracking items for hw blocks */
  659. for (i = 0; i < cat->mixer_count; i++) {
  660. struct sde_lm_cfg *lm = &cat->mixer[i];
  661. if (lm->pingpong == PINGPONG_MAX) {
  662. SDE_ERROR("mixer %d without pingpong\n", lm->id);
  663. goto fail;
  664. }
  665. rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
  666. cat->mixer[i].id, &cat->mixer[i]);
  667. if (rc) {
  668. SDE_ERROR("failed: lm hw not available\n");
  669. goto fail;
  670. }
  671. if (!rm->lm_max_width) {
  672. rm->lm_max_width = lm->sblk->maxwidth;
  673. } else if (rm->lm_max_width != lm->sblk->maxwidth) {
  674. /*
  675. * Don't expect to have hw where lm max widths differ.
  676. * If found, take the min.
  677. */
  678. SDE_ERROR("unsupported: lm maxwidth differs\n");
  679. if (rm->lm_max_width > lm->sblk->maxwidth)
  680. rm->lm_max_width = lm->sblk->maxwidth;
  681. }
  682. }
  683. rc = _sde_rm_hw_blk_create_new(rm, cat, mmio);
  684. if (!rc)
  685. return 0;
  686. fail:
  687. sde_rm_destroy(rm);
  688. return rc;
  689. }
  690. static bool _sde_rm_check_lm(
  691. struct sde_rm *rm,
  692. struct sde_rm_rsvp *rsvp,
  693. struct sde_rm_requirements *reqs,
  694. const struct sde_lm_cfg *lm_cfg,
  695. struct sde_rm_hw_blk *lm,
  696. struct sde_rm_hw_blk **dspp,
  697. struct sde_rm_hw_blk **ds,
  698. struct sde_rm_hw_blk **pp)
  699. {
  700. bool is_valid_dspp, is_valid_ds, ret = true;
  701. is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
  702. is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
  703. /**
  704. * RM_RQ_X: specification of which LMs to choose
  705. * is_valid_X: indicates whether LM is tied with block X
  706. * ret: true if given LM matches the user requirement,
  707. * false otherwise
  708. */
  709. if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
  710. ret = (is_valid_dspp && is_valid_ds);
  711. else if (RM_RQ_DSPP(reqs))
  712. ret = is_valid_dspp;
  713. else if (RM_RQ_DS(reqs))
  714. ret = is_valid_ds;
  715. if (!ret) {
  716. SDE_DEBUG(
  717. "fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
  718. lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
  719. lm_cfg->dspp, (bool)(RM_RQ_DS(reqs)),
  720. lm_cfg->ds);
  721. return ret;
  722. }
  723. return true;
  724. }
  725. static bool _sde_rm_reserve_dspp(
  726. struct sde_rm *rm,
  727. struct sde_rm_rsvp *rsvp,
  728. const struct sde_lm_cfg *lm_cfg,
  729. struct sde_rm_hw_blk *lm,
  730. struct sde_rm_hw_blk **dspp)
  731. {
  732. struct sde_rm_hw_iter iter;
  733. if (lm_cfg->dspp != DSPP_MAX) {
  734. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DSPP);
  735. while (_sde_rm_get_hw_locked(rm, &iter)) {
  736. if (iter.blk->id == lm_cfg->dspp) {
  737. *dspp = iter.blk;
  738. break;
  739. }
  740. }
  741. if (!*dspp) {
  742. SDE_DEBUG("lm %d failed to retrieve dspp %d\n", lm->id,
  743. lm_cfg->dspp);
  744. return false;
  745. }
  746. if (RESERVED_BY_OTHER(*dspp, rsvp)) {
  747. SDE_DEBUG("lm %d dspp %d already reserved\n",
  748. lm->id, (*dspp)->id);
  749. return false;
  750. }
  751. }
  752. return true;
  753. }
  754. static bool _sde_rm_reserve_ds(
  755. struct sde_rm *rm,
  756. struct sde_rm_rsvp *rsvp,
  757. const struct sde_lm_cfg *lm_cfg,
  758. struct sde_rm_hw_blk *lm,
  759. struct sde_rm_hw_blk **ds)
  760. {
  761. struct sde_rm_hw_iter iter;
  762. if (lm_cfg->ds != DS_MAX) {
  763. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_DS);
  764. while (_sde_rm_get_hw_locked(rm, &iter)) {
  765. if (iter.blk->id == lm_cfg->ds) {
  766. *ds = iter.blk;
  767. break;
  768. }
  769. }
  770. if (!*ds) {
  771. SDE_DEBUG("lm %d failed to retrieve ds %d\n", lm->id,
  772. lm_cfg->ds);
  773. return false;
  774. }
  775. if (RESERVED_BY_OTHER(*ds, rsvp)) {
  776. SDE_DEBUG("lm %d ds %d already reserved\n",
  777. lm->id, (*ds)->id);
  778. return false;
  779. }
  780. }
  781. return true;
  782. }
  783. static bool _sde_rm_reserve_pp(
  784. struct sde_rm *rm,
  785. struct sde_rm_rsvp *rsvp,
  786. struct sde_rm_requirements *reqs,
  787. const struct sde_lm_cfg *lm_cfg,
  788. const struct sde_pingpong_cfg *pp_cfg,
  789. struct sde_rm_hw_blk *lm,
  790. struct sde_rm_hw_blk **dspp,
  791. struct sde_rm_hw_blk **ds,
  792. struct sde_rm_hw_blk **pp)
  793. {
  794. struct sde_rm_hw_iter iter;
  795. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_PINGPONG);
  796. while (_sde_rm_get_hw_locked(rm, &iter)) {
  797. if (iter.blk->id == lm_cfg->pingpong) {
  798. *pp = iter.blk;
  799. break;
  800. }
  801. }
  802. if (!*pp) {
  803. SDE_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
  804. return false;
  805. }
  806. if (RESERVED_BY_OTHER(*pp, rsvp)) {
  807. SDE_DEBUG("lm %d pp %d already reserved\n", lm->id,
  808. (*pp)->id);
  809. *dspp = NULL;
  810. *ds = NULL;
  811. return false;
  812. }
  813. pp_cfg = to_sde_hw_pingpong((*pp)->hw)->caps;
  814. if ((reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) &&
  815. !(test_bit(SDE_PINGPONG_SPLIT, &pp_cfg->features))) {
  816. SDE_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
  817. *dspp = NULL;
  818. *ds = NULL;
  819. return false;
  820. }
  821. return true;
  822. }
  823. /**
  824. * _sde_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
  825. * proposed use case requirements, incl. hardwired dependent blocks like
  826. * pingpong, and dspp.
  827. * @rm: sde resource manager handle
  828. * @rsvp: reservation currently being created
  829. * @reqs: proposed use case requirements
  830. * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  831. * blocks connected to the lm (pp, dspp) are available and appropriate
  832. * @dspp: output parameter, dspp block attached to the layer mixer.
  833. * NULL if dspp was not available, or not matching requirements.
  834. * @pp: output parameter, pingpong block attached to the layer mixer.
  835. * NULL if dspp was not available, or not matching requirements.
  836. * @primary_lm: if non-null, this function check if lm is compatible primary_lm
  837. * as well as satisfying all other requirements
  838. * @Return: true if lm matches all requirements, false otherwise
  839. */
  840. static bool _sde_rm_check_lm_and_get_connected_blks(
  841. struct sde_rm *rm,
  842. struct sde_rm_rsvp *rsvp,
  843. struct sde_rm_requirements *reqs,
  844. struct sde_rm_hw_blk *lm,
  845. struct sde_rm_hw_blk **dspp,
  846. struct sde_rm_hw_blk **ds,
  847. struct sde_rm_hw_blk **pp,
  848. struct sde_rm_hw_blk *primary_lm)
  849. {
  850. const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap;
  851. const struct sde_pingpong_cfg *pp_cfg;
  852. bool ret, is_conn_primary, is_conn_secondary;
  853. u32 lm_primary_pref, lm_secondary_pref, cwb_pref;
  854. *dspp = NULL;
  855. *ds = NULL;
  856. *pp = NULL;
  857. lm_primary_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
  858. lm_secondary_pref = lm_cfg->features & BIT(SDE_DISP_SECONDARY_PREF);
  859. cwb_pref = lm_cfg->features & BIT(SDE_DISP_CWB_PREF);
  860. is_conn_primary = (reqs->hw_res.display_type ==
  861. SDE_CONNECTOR_PRIMARY) ? true : false;
  862. is_conn_secondary = (reqs->hw_res.display_type ==
  863. SDE_CONNECTOR_SECONDARY) ? true : false;
  864. SDE_DEBUG("check lm %d: dspp %d ds %d pp %d features %d disp type %d\n",
  865. lm_cfg->id, lm_cfg->dspp, lm_cfg->ds, lm_cfg->pingpong,
  866. lm_cfg->features, (int)reqs->hw_res.display_type);
  867. /* Check if this layer mixer is a peer of the proposed primary LM */
  868. if (primary_lm) {
  869. const struct sde_lm_cfg *prim_lm_cfg =
  870. to_sde_hw_mixer(primary_lm->hw)->cap;
  871. if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
  872. SDE_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
  873. prim_lm_cfg->id);
  874. return false;
  875. }
  876. }
  877. /* bypass rest of the checks if LM for primary display is found */
  878. if (!lm_primary_pref && !lm_secondary_pref) {
  879. /* Check lm for valid requirements */
  880. ret = _sde_rm_check_lm(rm, rsvp, reqs, lm_cfg, lm,
  881. dspp, ds, pp);
  882. if (!ret)
  883. return ret;
  884. /**
  885. * If CWB is enabled and LM is not CWB supported
  886. * then return false.
  887. */
  888. if (RM_RQ_CWB(reqs) && !cwb_pref) {
  889. SDE_DEBUG("fail: cwb supported lm not allocated\n");
  890. return false;
  891. }
  892. } else if ((!is_conn_primary && lm_primary_pref) ||
  893. (!is_conn_secondary && lm_secondary_pref)) {
  894. SDE_DEBUG(
  895. "display preference is not met. display_type: %d lm_features: %x\n",
  896. (int)reqs->hw_res.display_type, lm_cfg->features);
  897. return false;
  898. }
  899. /* Already reserved? */
  900. if (RESERVED_BY_OTHER(lm, rsvp)) {
  901. SDE_DEBUG("lm %d already reserved\n", lm_cfg->id);
  902. return false;
  903. }
  904. /* Reserve dspp */
  905. ret = _sde_rm_reserve_dspp(rm, rsvp, lm_cfg, lm, dspp);
  906. if (!ret)
  907. return ret;
  908. /* Reserve ds */
  909. ret = _sde_rm_reserve_ds(rm, rsvp, lm_cfg, lm, ds);
  910. if (!ret)
  911. return ret;
  912. /* Reserve pp */
  913. ret = _sde_rm_reserve_pp(rm, rsvp, reqs, lm_cfg, pp_cfg, lm,
  914. dspp, ds, pp);
  915. if (!ret)
  916. return ret;
  917. return true;
  918. }
  919. static int _sde_rm_reserve_lms(
  920. struct sde_rm *rm,
  921. struct sde_rm_rsvp *rsvp,
  922. struct sde_rm_requirements *reqs,
  923. u8 *_lm_ids)
  924. {
  925. struct sde_rm_hw_blk *lm[MAX_BLOCKS];
  926. struct sde_rm_hw_blk *dspp[MAX_BLOCKS];
  927. struct sde_rm_hw_blk *ds[MAX_BLOCKS];
  928. struct sde_rm_hw_blk *pp[MAX_BLOCKS];
  929. struct sde_rm_hw_iter iter_i, iter_j;
  930. u32 lm_mask = 0;
  931. int lm_count = 0;
  932. int i, rc = 0;
  933. if (!reqs->topology->num_lm) {
  934. SDE_DEBUG("invalid number of lm: %d\n", reqs->topology->num_lm);
  935. return 0;
  936. }
  937. /* Find a primary mixer */
  938. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_LM);
  939. while (lm_count != reqs->topology->num_lm &&
  940. _sde_rm_get_hw_locked(rm, &iter_i)) {
  941. if (lm_mask & (1 << iter_i.blk->id))
  942. continue;
  943. lm[lm_count] = iter_i.blk;
  944. dspp[lm_count] = NULL;
  945. ds[lm_count] = NULL;
  946. pp[lm_count] = NULL;
  947. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  948. iter_i.blk->id,
  949. lm_count,
  950. _lm_ids ? _lm_ids[lm_count] : -1);
  951. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  952. continue;
  953. if (!_sde_rm_check_lm_and_get_connected_blks(
  954. rm, rsvp, reqs, lm[lm_count],
  955. &dspp[lm_count], &ds[lm_count],
  956. &pp[lm_count], NULL))
  957. continue;
  958. lm_mask |= (1 << iter_i.blk->id);
  959. ++lm_count;
  960. /* Return if peer is not needed */
  961. if (lm_count == reqs->topology->num_lm)
  962. break;
  963. /* Valid primary mixer found, find matching peers */
  964. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_LM);
  965. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  966. if (lm_mask & (1 << iter_j.blk->id))
  967. continue;
  968. lm[lm_count] = iter_j.blk;
  969. dspp[lm_count] = NULL;
  970. ds[lm_count] = NULL;
  971. pp[lm_count] = NULL;
  972. if (!_sde_rm_check_lm_and_get_connected_blks(
  973. rm, rsvp, reqs, iter_j.blk,
  974. &dspp[lm_count], &ds[lm_count],
  975. &pp[lm_count], iter_i.blk))
  976. continue;
  977. SDE_DEBUG("blk id = %d, _lm_ids[%d] = %d\n",
  978. iter_j.blk->id,
  979. lm_count,
  980. _lm_ids ? _lm_ids[lm_count] : -1);
  981. if (_lm_ids && (lm[lm_count])->id != _lm_ids[lm_count])
  982. continue;
  983. lm_mask |= (1 << iter_j.blk->id);
  984. ++lm_count;
  985. break;
  986. }
  987. /* Rollback primary LM if peer is not found */
  988. if (!iter_j.hw) {
  989. lm_mask &= ~(1 << iter_i.blk->id);
  990. --lm_count;
  991. }
  992. }
  993. if (lm_count != reqs->topology->num_lm) {
  994. SDE_DEBUG("unable to find appropriate mixers\n");
  995. return -ENAVAIL;
  996. }
  997. for (i = 0; i < lm_count; i++) {
  998. lm[i]->rsvp_nxt = rsvp;
  999. pp[i]->rsvp_nxt = rsvp;
  1000. if (dspp[i])
  1001. dspp[i]->rsvp_nxt = rsvp;
  1002. if (ds[i])
  1003. ds[i]->rsvp_nxt = rsvp;
  1004. SDE_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id,
  1005. dspp[i] ? dspp[i]->id : 0,
  1006. ds[i] ? ds[i]->id : 0);
  1007. }
  1008. if (reqs->topology->top_name == SDE_RM_TOPOLOGY_PPSPLIT) {
  1009. /* reserve a free PINGPONG_SLAVE block */
  1010. rc = -ENAVAIL;
  1011. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_PINGPONG);
  1012. while (_sde_rm_get_hw_locked(rm, &iter_i)) {
  1013. const struct sde_hw_pingpong *pp =
  1014. to_sde_hw_pingpong(iter_i.blk->hw);
  1015. const struct sde_pingpong_cfg *pp_cfg = pp->caps;
  1016. if (!(test_bit(SDE_PINGPONG_SLAVE, &pp_cfg->features)))
  1017. continue;
  1018. if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
  1019. continue;
  1020. iter_i.blk->rsvp_nxt = rsvp;
  1021. rc = 0;
  1022. break;
  1023. }
  1024. }
  1025. return rc;
  1026. }
  1027. static int _sde_rm_reserve_ctls(
  1028. struct sde_rm *rm,
  1029. struct sde_rm_rsvp *rsvp,
  1030. struct sde_rm_requirements *reqs,
  1031. const struct sde_rm_topology_def *top,
  1032. u8 *_ctl_ids)
  1033. {
  1034. struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
  1035. struct sde_rm_hw_iter iter;
  1036. int i = 0;
  1037. if (!top->num_ctl) {
  1038. SDE_DEBUG("invalid number of ctl: %d\n", top->num_ctl);
  1039. return 0;
  1040. }
  1041. memset(&ctls, 0, sizeof(ctls));
  1042. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CTL);
  1043. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1044. const struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
  1045. unsigned long features = ctl->caps->features;
  1046. bool has_split_display, has_ppsplit, primary_pref;
  1047. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1048. continue;
  1049. has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & features;
  1050. has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & features;
  1051. primary_pref = BIT(SDE_CTL_PRIMARY_PREF) & features;
  1052. SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
  1053. /*
  1054. * bypass rest feature checks on finding CTL preferred
  1055. * for primary displays.
  1056. */
  1057. if (!primary_pref && !_ctl_ids) {
  1058. if (top->needs_split_display != has_split_display)
  1059. continue;
  1060. if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT &&
  1061. !has_ppsplit)
  1062. continue;
  1063. } else if (!(reqs->hw_res.display_type ==
  1064. SDE_CONNECTOR_PRIMARY && primary_pref) && !_ctl_ids) {
  1065. SDE_DEBUG(
  1066. "display pref not met. display_type: %d primary_pref: %d\n",
  1067. reqs->hw_res.display_type, primary_pref);
  1068. continue;
  1069. }
  1070. ctls[i] = iter.blk;
  1071. SDE_DEBUG("blk id = %d, _ctl_ids[%d] = %d\n",
  1072. iter.blk->id, i,
  1073. _ctl_ids ? _ctl_ids[i] : -1);
  1074. if (_ctl_ids && (ctls[i]->id != _ctl_ids[i]))
  1075. continue;
  1076. SDE_DEBUG("ctl %d match\n", iter.blk->id);
  1077. if (++i == top->num_ctl)
  1078. break;
  1079. }
  1080. if (i != top->num_ctl)
  1081. return -ENAVAIL;
  1082. for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
  1083. ctls[i]->rsvp_nxt = rsvp;
  1084. SDE_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
  1085. }
  1086. return 0;
  1087. }
  1088. static bool _sde_rm_check_dsc(struct sde_rm *rm,
  1089. struct sde_rm_rsvp *rsvp,
  1090. struct sde_rm_hw_blk *dsc,
  1091. struct sde_rm_hw_blk *paired_dsc)
  1092. {
  1093. const struct sde_dsc_cfg *dsc_cfg = to_sde_hw_dsc(dsc->hw)->caps;
  1094. /* Already reserved? */
  1095. if (RESERVED_BY_OTHER(dsc, rsvp)) {
  1096. SDE_DEBUG("dsc %d already reserved\n", dsc_cfg->id);
  1097. return false;
  1098. }
  1099. /* Check if this dsc is a peer of the proposed paired DSC */
  1100. if (paired_dsc) {
  1101. const struct sde_dsc_cfg *paired_dsc_cfg =
  1102. to_sde_hw_dsc(paired_dsc->hw)->caps;
  1103. if (!test_bit(dsc_cfg->id, paired_dsc_cfg->dsc_pair_mask)) {
  1104. SDE_DEBUG("dsc %d not peer of dsc %d\n", dsc_cfg->id,
  1105. paired_dsc_cfg->id);
  1106. return false;
  1107. }
  1108. }
  1109. return true;
  1110. }
  1111. static bool _sde_rm_check_vdc(struct sde_rm *rm,
  1112. struct sde_rm_rsvp *rsvp,
  1113. struct sde_rm_hw_blk *vdc)
  1114. {
  1115. const struct sde_vdc_cfg *vdc_cfg = to_sde_hw_vdc(vdc->hw)->caps;
  1116. /* Already reserved? */
  1117. if (RESERVED_BY_OTHER(vdc, rsvp)) {
  1118. SDE_DEBUG("vdc %d already reserved\n", vdc_cfg->id);
  1119. return false;
  1120. }
  1121. return true;
  1122. }
  1123. static int _sde_rm_reserve_dsc(
  1124. struct sde_rm *rm,
  1125. struct sde_rm_rsvp *rsvp,
  1126. struct sde_rm_requirements *reqs,
  1127. u8 *_dsc_ids)
  1128. {
  1129. struct sde_rm_hw_iter iter_i, iter_j;
  1130. struct sde_rm_hw_blk *dsc[MAX_BLOCKS];
  1131. u32 reserve_mask = 0;
  1132. int alloc_count = 0;
  1133. int num_dsc_enc;
  1134. struct msm_display_dsc_info *dsc_info;
  1135. int i;
  1136. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_DSC) {
  1137. SDE_DEBUG("compression blk dsc not required\n");
  1138. return 0;
  1139. }
  1140. num_dsc_enc = reqs->topology->num_comp_enc;
  1141. dsc_info = &reqs->hw_res.comp_info->dsc_info;
  1142. if ((!num_dsc_enc) || !dsc_info) {
  1143. SDE_DEBUG("invalid topoplogy params: %d, %d\n",
  1144. num_dsc_enc, !(dsc_info == NULL));
  1145. return 0;
  1146. }
  1147. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_DSC);
  1148. /* Find a first DSC */
  1149. while (alloc_count != num_dsc_enc &&
  1150. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1151. const struct sde_hw_dsc *hw_dsc = to_sde_hw_dsc(
  1152. iter_i.blk->hw);
  1153. unsigned long features = hw_dsc->caps->features;
  1154. bool has_422_420_support =
  1155. BIT(SDE_DSC_NATIVE_422_EN) & features;
  1156. if (reserve_mask & (1 << iter_i.blk->id))
  1157. continue;
  1158. if (_dsc_ids && (iter_i.blk->id != _dsc_ids[alloc_count]))
  1159. continue;
  1160. /* if this hw block does not support required feature */
  1161. if (!_dsc_ids && (dsc_info->config.native_422 ||
  1162. dsc_info->config.native_420) && !has_422_420_support)
  1163. continue;
  1164. if (!_sde_rm_check_dsc(rm, rsvp, iter_i.blk, NULL))
  1165. continue;
  1166. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1167. iter_i.blk->id,
  1168. alloc_count,
  1169. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1170. reserve_mask |= (1 << iter_i.blk->id);
  1171. dsc[alloc_count++] = iter_i.blk;
  1172. /* Return if peer is not needed */
  1173. if (alloc_count == num_dsc_enc)
  1174. break;
  1175. /* Valid first dsc found, find matching peers */
  1176. sde_rm_init_hw_iter(&iter_j, 0, SDE_HW_BLK_DSC);
  1177. while (_sde_rm_get_hw_locked(rm, &iter_j)) {
  1178. if (reserve_mask & (1 << iter_j.blk->id))
  1179. continue;
  1180. if (_dsc_ids && (iter_j.blk->id !=
  1181. _dsc_ids[alloc_count]))
  1182. continue;
  1183. if (!_sde_rm_check_dsc(rm, rsvp,
  1184. iter_j.blk, iter_i.blk))
  1185. continue;
  1186. SDE_DEBUG("blk id = %d, _dsc_ids[%d] = %d\n",
  1187. iter_j.blk->id,
  1188. alloc_count,
  1189. _dsc_ids ? _dsc_ids[alloc_count] : -1);
  1190. reserve_mask |= (1 << iter_j.blk->id);
  1191. dsc[alloc_count++] = iter_j.blk;
  1192. break;
  1193. }
  1194. /* Rollback primary DSC if peer is not found */
  1195. if (!iter_j.hw) {
  1196. reserve_mask &= ~(1 << iter_i.blk->id);
  1197. --alloc_count;
  1198. }
  1199. }
  1200. if (alloc_count != num_dsc_enc) {
  1201. SDE_ERROR("couldn't reserve %d dsc blocks for enc id %d\n",
  1202. num_dsc_enc, rsvp->enc_id);
  1203. return -EINVAL;
  1204. }
  1205. for (i = 0; i < alloc_count; i++) {
  1206. if (!dsc[i])
  1207. break;
  1208. dsc[i]->rsvp_nxt = rsvp;
  1209. SDE_EVT32(dsc[i]->type, rsvp->enc_id, dsc[i]->id);
  1210. }
  1211. return 0;
  1212. }
  1213. static int _sde_rm_reserve_vdc(
  1214. struct sde_rm *rm,
  1215. struct sde_rm_rsvp *rsvp,
  1216. struct sde_rm_requirements *reqs,
  1217. const struct sde_rm_topology_def *top,
  1218. u8 *_vdc_ids)
  1219. {
  1220. struct sde_rm_hw_iter iter_i;
  1221. struct sde_rm_hw_blk *vdc[MAX_BLOCKS];
  1222. int alloc_count = 0;
  1223. int num_vdc_enc = top->num_comp_enc;
  1224. int i;
  1225. if (!top->num_comp_enc)
  1226. return 0;
  1227. if (reqs->hw_res.comp_info->comp_type != MSM_DISPLAY_COMPRESSION_VDC)
  1228. return 0;
  1229. sde_rm_init_hw_iter(&iter_i, 0, SDE_HW_BLK_VDC);
  1230. /* Find a VDC */
  1231. while (alloc_count != num_vdc_enc &&
  1232. _sde_rm_get_hw_locked(rm, &iter_i)) {
  1233. memset(&vdc, 0, sizeof(vdc));
  1234. alloc_count = 0;
  1235. if (_vdc_ids && (iter_i.blk->id != _vdc_ids[alloc_count]))
  1236. continue;
  1237. if (!_sde_rm_check_vdc(rm, rsvp, iter_i.blk))
  1238. continue;
  1239. SDE_DEBUG("blk id = %d, _vdc_ids[%d] = %d\n",
  1240. iter_i.blk->id,
  1241. alloc_count,
  1242. _vdc_ids ? _vdc_ids[alloc_count] : -1);
  1243. vdc[alloc_count++] = iter_i.blk;
  1244. }
  1245. if (alloc_count != num_vdc_enc) {
  1246. SDE_ERROR("couldn't reserve %d vdc blocks for enc id %d\n",
  1247. num_vdc_enc, rsvp->enc_id);
  1248. return -EINVAL;
  1249. }
  1250. for (i = 0; i < ARRAY_SIZE(vdc); i++) {
  1251. if (!vdc[i])
  1252. break;
  1253. vdc[i]->rsvp_nxt = rsvp;
  1254. SDE_EVT32(vdc[i]->type, rsvp->enc_id, vdc[i]->id);
  1255. }
  1256. return 0;
  1257. }
  1258. static int _sde_rm_reserve_qdss(
  1259. struct sde_rm *rm,
  1260. struct sde_rm_rsvp *rsvp,
  1261. const struct sde_rm_topology_def *top,
  1262. u8 *_qdss_ids)
  1263. {
  1264. struct sde_rm_hw_iter iter;
  1265. struct msm_drm_private *priv = rm->dev->dev_private;
  1266. struct sde_kms *sde_kms;
  1267. if (!priv->kms) {
  1268. SDE_ERROR("invalid kms\n");
  1269. return -EINVAL;
  1270. }
  1271. sde_kms = to_sde_kms(priv->kms);
  1272. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_QDSS);
  1273. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1274. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1275. continue;
  1276. SDE_DEBUG("blk id = %d\n", iter.blk->id);
  1277. iter.blk->rsvp_nxt = rsvp;
  1278. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1279. return 0;
  1280. }
  1281. if (!iter.hw && sde_kms->catalog->qdss_count) {
  1282. SDE_DEBUG("couldn't reserve qdss for type %d id %d\n",
  1283. SDE_HW_BLK_QDSS, iter.blk->id);
  1284. return -ENAVAIL;
  1285. }
  1286. return 0;
  1287. }
  1288. static int _sde_rm_reserve_cdm(
  1289. struct sde_rm *rm,
  1290. struct sde_rm_rsvp *rsvp,
  1291. uint32_t id,
  1292. enum sde_hw_blk_type type)
  1293. {
  1294. struct sde_rm_hw_iter iter;
  1295. sde_rm_init_hw_iter(&iter, 0, SDE_HW_BLK_CDM);
  1296. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1297. const struct sde_hw_cdm *cdm = to_sde_hw_cdm(iter.blk->hw);
  1298. const struct sde_cdm_cfg *caps = cdm->caps;
  1299. bool match = false;
  1300. if (RESERVED_BY_OTHER(iter.blk, rsvp))
  1301. continue;
  1302. if (type == SDE_HW_BLK_INTF && id != INTF_MAX)
  1303. match = test_bit(id, &caps->intf_connect);
  1304. else if (type == SDE_HW_BLK_WB && id != WB_MAX)
  1305. match = test_bit(id, &caps->wb_connect);
  1306. SDE_DEBUG("type %d id %d, cdm intfs %lu wbs %lu match %d\n",
  1307. type, id, caps->intf_connect, caps->wb_connect,
  1308. match);
  1309. if (!match)
  1310. continue;
  1311. iter.blk->rsvp_nxt = rsvp;
  1312. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1313. break;
  1314. }
  1315. if (!iter.hw) {
  1316. SDE_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
  1317. return -ENAVAIL;
  1318. }
  1319. return 0;
  1320. }
  1321. static int _sde_rm_reserve_intf_or_wb(
  1322. struct sde_rm *rm,
  1323. struct sde_rm_rsvp *rsvp,
  1324. uint32_t id,
  1325. enum sde_hw_blk_type type,
  1326. bool needs_cdm)
  1327. {
  1328. struct sde_rm_hw_iter iter;
  1329. int ret = 0;
  1330. /* Find the block entry in the rm, and note the reservation */
  1331. sde_rm_init_hw_iter(&iter, 0, type);
  1332. while (_sde_rm_get_hw_locked(rm, &iter)) {
  1333. if (iter.blk->id != id)
  1334. continue;
  1335. if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
  1336. SDE_ERROR("type %d id %d already reserved\n", type, id);
  1337. return -ENAVAIL;
  1338. }
  1339. iter.blk->rsvp_nxt = rsvp;
  1340. SDE_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
  1341. break;
  1342. }
  1343. /* Shouldn't happen since wbs / intfs are fixed at probe */
  1344. if (!iter.hw) {
  1345. SDE_ERROR("couldn't find type %d id %d\n", type, id);
  1346. return -EINVAL;
  1347. }
  1348. /* Expected only one intf or wb will request cdm */
  1349. if (needs_cdm)
  1350. ret = _sde_rm_reserve_cdm(rm, rsvp, id, type);
  1351. return ret;
  1352. }
  1353. static int _sde_rm_reserve_intf_related_hw(
  1354. struct sde_rm *rm,
  1355. struct sde_rm_rsvp *rsvp,
  1356. struct sde_encoder_hw_resources *hw_res)
  1357. {
  1358. int i, ret = 0;
  1359. u32 id;
  1360. for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
  1361. if (hw_res->intfs[i] == INTF_MODE_NONE)
  1362. continue;
  1363. id = i + INTF_0;
  1364. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1365. SDE_HW_BLK_INTF, hw_res->needs_cdm);
  1366. if (ret)
  1367. return ret;
  1368. }
  1369. for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
  1370. if (hw_res->wbs[i] == INTF_MODE_NONE)
  1371. continue;
  1372. id = i + WB_0;
  1373. ret = _sde_rm_reserve_intf_or_wb(rm, rsvp, id,
  1374. SDE_HW_BLK_WB, hw_res->needs_cdm);
  1375. if (ret)
  1376. return ret;
  1377. }
  1378. return ret;
  1379. }
  1380. static bool _sde_rm_is_display_in_cont_splash(struct sde_kms *sde_kms,
  1381. struct drm_encoder *enc)
  1382. {
  1383. int i;
  1384. struct sde_splash_display *splash_dpy;
  1385. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1386. splash_dpy = &sde_kms->splash_data.splash_display[i];
  1387. if (splash_dpy->encoder == enc)
  1388. return splash_dpy->cont_splash_enabled;
  1389. }
  1390. return false;
  1391. }
  1392. static int _sde_rm_make_lm_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1393. struct sde_rm_requirements *reqs,
  1394. struct sde_splash_display *splash_display)
  1395. {
  1396. int ret, i;
  1397. u8 *hw_ids = NULL;
  1398. /* Check if splash data provided lm_ids */
  1399. if (splash_display) {
  1400. hw_ids = splash_display->lm_ids;
  1401. for (i = 0; i < splash_display->lm_cnt; i++)
  1402. SDE_DEBUG("splash_display->lm_ids[%d] = %d\n",
  1403. i, splash_display->lm_ids[i]);
  1404. if (splash_display->lm_cnt != reqs->topology->num_lm)
  1405. SDE_DEBUG("Configured splash LMs != needed LM cnt\n");
  1406. }
  1407. /*
  1408. * Assign LMs and blocks whose usage is tied to them:
  1409. * DSPP & Pingpong.
  1410. */
  1411. ret = _sde_rm_reserve_lms(rm, rsvp, reqs, hw_ids);
  1412. return ret;
  1413. }
  1414. static int _sde_rm_make_ctl_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1415. struct sde_rm_requirements *reqs,
  1416. struct sde_splash_display *splash_display)
  1417. {
  1418. int ret, i;
  1419. u8 *hw_ids = NULL;
  1420. struct sde_rm_topology_def topology;
  1421. /* Check if splash data provided ctl_ids */
  1422. if (splash_display) {
  1423. hw_ids = splash_display->ctl_ids;
  1424. for (i = 0; i < splash_display->ctl_cnt; i++)
  1425. SDE_DEBUG("splash_display->ctl_ids[%d] = %d\n",
  1426. i, splash_display->ctl_ids[i]);
  1427. }
  1428. /*
  1429. * Do assignment preferring to give away low-resource CTLs first:
  1430. * - Check mixers without Split Display
  1431. * - Only then allow to grab from CTLs with split display capability
  1432. */
  1433. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, reqs->topology, hw_ids);
  1434. if (ret && !reqs->topology->needs_split_display &&
  1435. reqs->topology->num_ctl > SINGLE_CTL) {
  1436. memcpy(&topology, reqs->topology, sizeof(topology));
  1437. topology.needs_split_display = true;
  1438. ret = _sde_rm_reserve_ctls(rm, rsvp, reqs, &topology, hw_ids);
  1439. }
  1440. return ret;
  1441. }
  1442. static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1443. struct sde_rm_requirements *reqs,
  1444. struct sde_splash_display *splash_display)
  1445. {
  1446. int i;
  1447. u8 *hw_ids = NULL;
  1448. /* Check if splash data provided dsc_ids */
  1449. if (splash_display) {
  1450. hw_ids = splash_display->dsc_ids;
  1451. if (splash_display->dsc_cnt)
  1452. reqs->hw_res.comp_info->comp_type =
  1453. MSM_DISPLAY_COMPRESSION_DSC;
  1454. for (i = 0; i < splash_display->dsc_cnt; i++)
  1455. SDE_DEBUG("splash_data.dsc_ids[%d] = %d\n",
  1456. i, splash_display->dsc_ids[i]);
  1457. }
  1458. return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
  1459. }
  1460. static int _sde_rm_make_vdc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
  1461. struct sde_rm_requirements *reqs,
  1462. struct sde_splash_display *splash_display)
  1463. {
  1464. int ret, i;
  1465. u8 *hw_ids = NULL;
  1466. /* Check if splash data provided vdc_ids */
  1467. if (splash_display) {
  1468. hw_ids = splash_display->vdc_ids;
  1469. for (i = 0; i < splash_display->vdc_cnt; i++)
  1470. SDE_DEBUG("splash_data.vdc_ids[%d] = %d\n",
  1471. i, splash_display->vdc_ids[i]);
  1472. }
  1473. ret = _sde_rm_reserve_vdc(rm, rsvp, reqs, reqs->topology, hw_ids);
  1474. return ret;
  1475. }
  1476. static int _sde_rm_make_next_rsvp(struct sde_rm *rm, struct drm_encoder *enc,
  1477. struct drm_crtc_state *crtc_state,
  1478. struct drm_connector_state *conn_state,
  1479. struct sde_rm_rsvp *rsvp,
  1480. struct sde_rm_requirements *reqs)
  1481. {
  1482. struct msm_drm_private *priv;
  1483. struct sde_kms *sde_kms;
  1484. struct sde_splash_display *splash_display = NULL;
  1485. struct sde_splash_data *splash_data;
  1486. int i, ret;
  1487. priv = enc->dev->dev_private;
  1488. sde_kms = to_sde_kms(priv->kms);
  1489. splash_data = &sde_kms->splash_data;
  1490. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1491. for (i = 0; i < ARRAY_SIZE(splash_data->splash_display); i++) {
  1492. if (enc == splash_data->splash_display[i].encoder)
  1493. splash_display =
  1494. &splash_data->splash_display[i];
  1495. }
  1496. if (!splash_display) {
  1497. SDE_ERROR("rm is in cont_splash but data not found\n");
  1498. return -EINVAL;
  1499. }
  1500. }
  1501. /* Create reservation info, tag reserved blocks with it as we go */
  1502. rsvp->seq = ++rm->rsvp_next_seq;
  1503. rsvp->enc_id = enc->base.id;
  1504. rsvp->topology = reqs->topology->top_name;
  1505. list_add_tail(&rsvp->list, &rm->rsvps);
  1506. ret = _sde_rm_make_lm_rsvp(rm, rsvp, reqs, splash_display);
  1507. if (ret) {
  1508. SDE_ERROR("unable to find appropriate mixers\n");
  1509. _sde_rm_print_rsvps_by_type(rm, SDE_HW_BLK_LM);
  1510. return ret;
  1511. }
  1512. ret = _sde_rm_make_ctl_rsvp(rm, rsvp, reqs, splash_display);
  1513. if (ret) {
  1514. SDE_ERROR("unable to find appropriate CTL\n");
  1515. return ret;
  1516. }
  1517. /* Assign INTFs, WBs, and blks whose usage is tied to them: CTL & CDM */
  1518. ret = _sde_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
  1519. if (ret)
  1520. return ret;
  1521. ret = _sde_rm_make_dsc_rsvp(rm, rsvp, reqs, splash_display);
  1522. if (ret)
  1523. return ret;
  1524. ret = _sde_rm_make_vdc_rsvp(rm, rsvp, reqs, splash_display);
  1525. if (ret)
  1526. return ret;
  1527. ret = _sde_rm_reserve_qdss(rm, rsvp, reqs->topology, NULL);
  1528. if (ret)
  1529. return ret;
  1530. return ret;
  1531. }
  1532. /**
  1533. * _sde_rm_get_hw_blk_for_cont_splash - retrieve the LM blocks on given CTL
  1534. * and populate the connected HW blk ids in sde_splash_display
  1535. * @rm: Pointer to resource manager structure
  1536. * @ctl: Pointer to CTL hardware block
  1537. * @splash_display: Pointer to struct sde_splash_display
  1538. * return: number of active LM blocks for this CTL block
  1539. */
  1540. static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
  1541. struct sde_hw_ctl *ctl,
  1542. struct sde_splash_display *splash_display)
  1543. {
  1544. u32 lm_reg;
  1545. struct sde_rm_hw_iter iter_lm, iter_dsc;
  1546. if (!rm || !ctl || !splash_display) {
  1547. SDE_ERROR("invalid input parameters\n");
  1548. return 0;
  1549. }
  1550. sde_rm_init_hw_iter(&iter_lm, 0, SDE_HW_BLK_LM);
  1551. sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
  1552. while (_sde_rm_get_hw_locked(rm, &iter_lm)) {
  1553. if (splash_display->lm_cnt >= MAX_DATA_PATH_PER_DSIPLAY)
  1554. break;
  1555. lm_reg = ctl->ops.read_ctl_layers(ctl, iter_lm.blk->id);
  1556. if (!lm_reg)
  1557. continue;
  1558. splash_display->lm_ids[splash_display->lm_cnt++] =
  1559. iter_lm.blk->id;
  1560. SDE_DEBUG("lm_cnt=%d lm_reg[%d]=0x%x\n", splash_display->lm_cnt,
  1561. iter_lm.blk->id - LM_0, lm_reg);
  1562. if (ctl->ops.get_staged_sspp &&
  1563. ctl->ops.get_staged_sspp(ctl, iter_lm.blk->id,
  1564. &splash_display->pipes[
  1565. splash_display->pipe_cnt], 1)) {
  1566. splash_display->pipe_cnt++;
  1567. } else {
  1568. SDE_ERROR("no pipe detected on LM-%d\n",
  1569. iter_lm.blk->id - LM_0);
  1570. return 0;
  1571. }
  1572. }
  1573. while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
  1574. if (ctl->ops.read_active_status &&
  1575. !(ctl->ops.read_active_status(ctl,
  1576. SDE_HW_BLK_DSC,
  1577. iter_dsc.blk->id)))
  1578. continue;
  1579. splash_display->dsc_ids[splash_display->dsc_cnt++] =
  1580. iter_dsc.blk->id;
  1581. SDE_DEBUG("CTL[%d] path, using dsc[%d]\n",
  1582. ctl->idx,
  1583. iter_dsc.blk->id - DSC_0);
  1584. }
  1585. return splash_display->lm_cnt;
  1586. }
  1587. int sde_rm_cont_splash_res_init(struct msm_drm_private *priv,
  1588. struct sde_rm *rm,
  1589. struct sde_splash_data *splash_data,
  1590. struct sde_mdss_cfg *cat)
  1591. {
  1592. struct sde_rm_hw_iter iter_c;
  1593. int index = 0, ctl_top_cnt;
  1594. struct sde_kms *sde_kms = NULL;
  1595. struct sde_hw_mdp *hw_mdp;
  1596. struct sde_splash_display *splash_display;
  1597. u8 intf_sel;
  1598. if (!priv || !rm || !cat || !splash_data) {
  1599. SDE_ERROR("invalid input parameters\n");
  1600. return -EINVAL;
  1601. }
  1602. SDE_DEBUG("mixer_count=%d, ctl_count=%d, dsc_count=%d\n",
  1603. cat->mixer_count,
  1604. cat->ctl_count,
  1605. cat->dsc_count);
  1606. ctl_top_cnt = cat->ctl_count;
  1607. if (!priv->kms) {
  1608. SDE_ERROR("invalid kms\n");
  1609. return -EINVAL;
  1610. }
  1611. sde_kms = to_sde_kms(priv->kms);
  1612. hw_mdp = sde_rm_get_mdp(rm);
  1613. sde_rm_init_hw_iter(&iter_c, 0, SDE_HW_BLK_CTL);
  1614. while (_sde_rm_get_hw_locked(rm, &iter_c)
  1615. && (index < splash_data->num_splash_displays)) {
  1616. struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter_c.blk->hw);
  1617. if (!ctl->ops.get_ctl_intf) {
  1618. SDE_ERROR("get_ctl_intf not initialized\n");
  1619. return -EINVAL;
  1620. }
  1621. intf_sel = ctl->ops.get_ctl_intf(ctl);
  1622. if (intf_sel) {
  1623. splash_display = &splash_data->splash_display[index];
  1624. SDE_DEBUG("finding resources for display=%d ctl=%d\n",
  1625. index, iter_c.blk->id - CTL_0);
  1626. _sde_rm_get_hw_blk_for_cont_splash(rm,
  1627. ctl, splash_display);
  1628. splash_display->cont_splash_enabled = true;
  1629. splash_display->ctl_ids[splash_display->ctl_cnt++] =
  1630. iter_c.blk->id;
  1631. }
  1632. index++;
  1633. }
  1634. return 0;
  1635. }
  1636. static int _sde_rm_populate_requirements(
  1637. struct sde_rm *rm,
  1638. struct drm_encoder *enc,
  1639. struct drm_crtc_state *crtc_state,
  1640. struct drm_connector_state *conn_state,
  1641. struct sde_rm_requirements *reqs)
  1642. {
  1643. const struct drm_display_mode *mode = &crtc_state->mode;
  1644. int i, num_lm;
  1645. reqs->top_ctrl = sde_connector_get_property(conn_state,
  1646. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1647. sde_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
  1648. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++) {
  1649. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i],
  1650. reqs->hw_res.topology)) {
  1651. reqs->topology = &rm->topology_tbl[i];
  1652. break;
  1653. }
  1654. }
  1655. if (!reqs->topology) {
  1656. SDE_ERROR("invalid topology for the display\n");
  1657. return -EINVAL;
  1658. }
  1659. /*
  1660. * select dspp HW block for all dsi displays and ds for only
  1661. * primary dsi display.
  1662. */
  1663. if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI) {
  1664. if (!RM_RQ_DSPP(reqs))
  1665. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
  1666. if (!RM_RQ_DS(reqs) && rm->hw_mdp->caps->has_dest_scaler &&
  1667. sde_encoder_is_primary_display(enc))
  1668. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DS);
  1669. }
  1670. /**
  1671. * Set the requirement for LM which has CWB support if CWB is
  1672. * found enabled.
  1673. */
  1674. if (!RM_RQ_CWB(reqs) && sde_encoder_in_clone_mode(enc)) {
  1675. reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);
  1676. /*
  1677. * topology selection based on conn mode is not valid for CWB
  1678. * as WB conn populates modes based on max_mixer_width check
  1679. * but primary can be using dual LMs. This topology override for
  1680. * CWB is to check number of datapath active in primary and
  1681. * allocate same number of LM/PP blocks reserved for CWB
  1682. */
  1683. reqs->topology =
  1684. &rm->topology_tbl[SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE];
  1685. num_lm = sde_crtc_get_num_datapath(crtc_state->crtc,
  1686. conn_state->connector);
  1687. if (num_lm == 1)
  1688. reqs->topology =
  1689. &rm->topology_tbl[SDE_RM_TOPOLOGY_SINGLEPIPE];
  1690. else if (num_lm == 0)
  1691. SDE_ERROR("Primary layer mixer is not set\n");
  1692. SDE_EVT32(num_lm, reqs->topology->num_lm,
  1693. reqs->topology->top_name, reqs->topology->num_ctl);
  1694. }
  1695. SDE_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
  1696. reqs->hw_res.display_num_of_h_tiles);
  1697. SDE_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
  1698. reqs->topology->num_lm, reqs->topology->num_ctl,
  1699. reqs->topology->top_name,
  1700. reqs->topology->needs_split_display);
  1701. SDE_EVT32(mode->hdisplay, rm->lm_max_width, reqs->topology->num_lm,
  1702. reqs->top_ctrl, reqs->topology->top_name,
  1703. reqs->topology->num_ctl);
  1704. return 0;
  1705. }
  1706. static struct sde_rm_rsvp *_sde_rm_get_rsvp(
  1707. struct sde_rm *rm,
  1708. struct drm_encoder *enc)
  1709. {
  1710. struct sde_rm_rsvp *i;
  1711. if (!rm || !enc) {
  1712. SDE_ERROR("invalid params\n");
  1713. return NULL;
  1714. }
  1715. if (list_empty(&rm->rsvps))
  1716. return NULL;
  1717. list_for_each_entry(i, &rm->rsvps, list)
  1718. if (i->enc_id == enc->base.id)
  1719. return i;
  1720. return NULL;
  1721. }
  1722. static struct sde_rm_rsvp *_sde_rm_get_rsvp_nxt(
  1723. struct sde_rm *rm,
  1724. struct drm_encoder *enc)
  1725. {
  1726. struct sde_rm_rsvp *i;
  1727. if (list_empty(&rm->rsvps))
  1728. return NULL;
  1729. list_for_each_entry(i, &rm->rsvps, list)
  1730. if (i->enc_id == enc->base.id)
  1731. break;
  1732. list_for_each_entry_continue(i, &rm->rsvps, list)
  1733. if (i->enc_id == enc->base.id)
  1734. return i;
  1735. return NULL;
  1736. }
  1737. static struct drm_connector *_sde_rm_get_connector(
  1738. struct drm_encoder *enc)
  1739. {
  1740. struct drm_connector *conn = NULL, *conn_search;
  1741. struct sde_connector *c_conn = NULL;
  1742. struct drm_connector_list_iter conn_iter;
  1743. drm_connector_list_iter_begin(enc->dev, &conn_iter);
  1744. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1745. c_conn = to_sde_connector(conn_search);
  1746. if (c_conn->encoder == enc) {
  1747. conn = conn_search;
  1748. break;
  1749. }
  1750. }
  1751. drm_connector_list_iter_end(&conn_iter);
  1752. return conn;
  1753. }
  1754. int sde_rm_update_topology(struct sde_rm *rm,
  1755. struct drm_connector_state *conn_state,
  1756. struct msm_display_topology *topology)
  1757. {
  1758. int i, ret = 0;
  1759. struct msm_display_topology top;
  1760. enum sde_rm_topology_name top_name = SDE_RM_TOPOLOGY_NONE;
  1761. if (!conn_state)
  1762. return -EINVAL;
  1763. if (topology) {
  1764. top = *topology;
  1765. for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
  1766. if (RM_IS_TOPOLOGY_MATCH(rm->topology_tbl[i], top)) {
  1767. top_name = rm->topology_tbl[i].top_name;
  1768. break;
  1769. }
  1770. }
  1771. ret = msm_property_set_property(
  1772. sde_connector_get_propinfo(conn_state->connector),
  1773. sde_connector_get_property_state(conn_state),
  1774. CONNECTOR_PROP_TOPOLOGY_NAME, top_name);
  1775. return ret;
  1776. }
  1777. bool sde_rm_topology_is_quad_pipe(struct sde_rm *rm,
  1778. struct drm_crtc_state *state)
  1779. {
  1780. int i;
  1781. struct sde_crtc_state *cstate;
  1782. uint64_t topology = SDE_RM_TOPOLOGY_NONE;
  1783. if ((!rm) || (!state)) {
  1784. pr_err("invalid arguments: rm:%d state:%d\n",
  1785. rm == NULL, state == NULL);
  1786. return false;
  1787. }
  1788. cstate = to_sde_crtc_state(state);
  1789. for (i = 0; i < cstate->num_connectors; i++) {
  1790. struct drm_connector *conn = cstate->connectors[i];
  1791. topology = sde_connector_get_topology_name(conn);
  1792. if (TOPOLOGY_QUADPIPE_MERGE_MODE(topology))
  1793. return true;
  1794. }
  1795. return false;
  1796. }
  1797. bool sde_rm_topology_is_dual_pipe(struct sde_rm *rm,
  1798. struct drm_crtc_state *state)
  1799. {
  1800. int i;
  1801. struct sde_crtc_state *cstate;
  1802. uint64_t topology = SDE_RM_TOPOLOGY_NONE;
  1803. if ((!rm) || (!state)) {
  1804. pr_err("invalid arguments: rm:%d state:%d\n",
  1805. rm == NULL, state == NULL);
  1806. return false;
  1807. }
  1808. cstate = to_sde_crtc_state(state);
  1809. for (i = 0; i < cstate->num_connectors; i++) {
  1810. struct drm_connector *conn = cstate->connectors[i];
  1811. topology = sde_connector_get_topology_name(conn);
  1812. if (TOPOLOGY_DUALPIPE_MERGE_MODE(topology))
  1813. return true;
  1814. }
  1815. return false;
  1816. }
  1817. bool sde_rm_topology_is_3dmux_dsc(struct sde_rm *rm,
  1818. struct drm_crtc_state *state)
  1819. {
  1820. int i;
  1821. struct sde_crtc_state *cstate;
  1822. uint64_t topology = SDE_RM_TOPOLOGY_NONE;
  1823. const struct sde_rm_topology_def *def;
  1824. int num_lm, num_enc;
  1825. if ((!rm) || (!state)) {
  1826. pr_err("invalid arguments: rm:%d state:%d\n",
  1827. rm == NULL, state == NULL);
  1828. return false;
  1829. }
  1830. cstate = to_sde_crtc_state(state);
  1831. for (i = 0; i < cstate->num_connectors; i++) {
  1832. struct drm_connector *conn = cstate->connectors[i];
  1833. topology = sde_connector_get_topology_name(conn);
  1834. def = sde_rm_topology_get_topology_def(rm, topology);
  1835. num_lm = def->num_lm;
  1836. num_enc = def->num_comp_enc;
  1837. if (num_lm > num_enc && num_enc)
  1838. return true;
  1839. }
  1840. return false;
  1841. }
  1842. /**
  1843. * _sde_rm_release_rsvp - release resources and release a reservation
  1844. * @rm: KMS handle
  1845. * @rsvp: RSVP pointer to release and release resources for
  1846. */
  1847. static void _sde_rm_release_rsvp(
  1848. struct sde_rm *rm,
  1849. struct sde_rm_rsvp *rsvp,
  1850. struct drm_connector *conn)
  1851. {
  1852. struct sde_rm_rsvp *rsvp_c, *rsvp_n;
  1853. struct sde_rm_hw_blk *blk;
  1854. enum sde_hw_blk_type type;
  1855. if (!rsvp)
  1856. return;
  1857. SDE_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
  1858. list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
  1859. if (rsvp == rsvp_c) {
  1860. list_del(&rsvp_c->list);
  1861. break;
  1862. }
  1863. }
  1864. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  1865. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1866. if (blk->rsvp == rsvp) {
  1867. blk->rsvp = NULL;
  1868. SDE_DEBUG("rel rsvp %d enc %d %d %d\n",
  1869. rsvp->seq, rsvp->enc_id,
  1870. blk->type, blk->id);
  1871. _sde_rm_inc_resource_info(rm,
  1872. &rm->avail_res, blk);
  1873. }
  1874. if (blk->rsvp_nxt == rsvp) {
  1875. blk->rsvp_nxt = NULL;
  1876. SDE_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
  1877. rsvp->seq, rsvp->enc_id,
  1878. blk->type, blk->id);
  1879. }
  1880. }
  1881. }
  1882. kfree(rsvp);
  1883. }
  1884. void sde_rm_release(struct sde_rm *rm, struct drm_encoder *enc, bool nxt)
  1885. {
  1886. struct sde_rm_rsvp *rsvp;
  1887. struct drm_connector *conn = NULL;
  1888. struct msm_drm_private *priv;
  1889. struct sde_kms *sde_kms;
  1890. uint64_t top_ctrl = 0;
  1891. if (!rm || !enc) {
  1892. SDE_ERROR("invalid params\n");
  1893. return;
  1894. }
  1895. priv = enc->dev->dev_private;
  1896. if (!priv->kms) {
  1897. SDE_ERROR("invalid kms\n");
  1898. return;
  1899. }
  1900. sde_kms = to_sde_kms(priv->kms);
  1901. mutex_lock(&rm->rm_lock);
  1902. if (nxt)
  1903. rsvp = _sde_rm_get_rsvp_nxt(rm, enc);
  1904. else
  1905. rsvp = _sde_rm_get_rsvp(rm, enc);
  1906. if (!rsvp) {
  1907. SDE_DEBUG("failed to find rsvp for enc %d, nxt %d",
  1908. enc->base.id, nxt);
  1909. goto end;
  1910. }
  1911. if (_sde_rm_is_display_in_cont_splash(sde_kms, enc)) {
  1912. _sde_rm_release_rsvp(rm, rsvp, conn);
  1913. goto end;
  1914. }
  1915. conn = _sde_rm_get_connector(enc);
  1916. if (!conn) {
  1917. SDE_EVT32(enc->base.id, 0x0, 0xffffffff);
  1918. _sde_rm_release_rsvp(rm, rsvp, conn);
  1919. SDE_DEBUG("failed to get conn for enc %d nxt %d rsvp[s%de%d]\n",
  1920. enc->base.id, nxt, rsvp->seq, rsvp->enc_id);
  1921. goto end;
  1922. }
  1923. top_ctrl = sde_connector_get_property(conn->state,
  1924. CONNECTOR_PROP_TOPOLOGY_CONTROL);
  1925. SDE_EVT32(enc->base.id, conn->base.id, rsvp->seq, top_ctrl, nxt);
  1926. if (top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK)) {
  1927. SDE_DEBUG("rsvp[s%de%d] not releasing locked resources\n",
  1928. rsvp->seq, rsvp->enc_id);
  1929. } else {
  1930. SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
  1931. rsvp->enc_id);
  1932. _sde_rm_release_rsvp(rm, rsvp, conn);
  1933. }
  1934. end:
  1935. mutex_unlock(&rm->rm_lock);
  1936. }
  1937. static int _sde_rm_commit_rsvp(
  1938. struct sde_rm *rm,
  1939. struct sde_rm_rsvp *rsvp,
  1940. struct drm_connector_state *conn_state)
  1941. {
  1942. struct sde_rm_hw_blk *blk;
  1943. enum sde_hw_blk_type type;
  1944. int ret = 0;
  1945. /* Swap next rsvp to be the active */
  1946. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  1947. list_for_each_entry(blk, &rm->hw_blks[type], list) {
  1948. if (blk->rsvp_nxt && conn_state->best_encoder->base.id
  1949. == blk->rsvp_nxt->enc_id) {
  1950. blk->rsvp = blk->rsvp_nxt;
  1951. blk->rsvp_nxt = NULL;
  1952. _sde_rm_dec_resource_info(rm,
  1953. &rm->avail_res, blk);
  1954. }
  1955. }
  1956. }
  1957. if (!ret) {
  1958. SDE_DEBUG("rsrv enc %d topology %d\n", rsvp->enc_id,
  1959. rsvp->topology);
  1960. SDE_EVT32(rsvp->enc_id, rsvp->topology);
  1961. }
  1962. return ret;
  1963. }
  1964. /* call this only after rm_mutex held */
  1965. struct sde_rm_rsvp *_sde_rm_poll_get_rsvp_nxt_locked(struct sde_rm *rm,
  1966. struct drm_encoder *enc)
  1967. {
  1968. int i;
  1969. u32 loop_count = 20;
  1970. struct sde_rm_rsvp *rsvp_nxt = NULL;
  1971. u32 sleep = RM_NXT_CLEAR_POLL_TIMEOUT_US / loop_count;
  1972. for (i = 0; i < loop_count; i++) {
  1973. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  1974. if (!rsvp_nxt)
  1975. return rsvp_nxt;
  1976. mutex_unlock(&rm->rm_lock);
  1977. SDE_DEBUG("iteration i:%d sleep range:%uus to %uus\n",
  1978. i, sleep, sleep * 2);
  1979. usleep_range(sleep, sleep * 2);
  1980. mutex_lock(&rm->rm_lock);
  1981. }
  1982. return rsvp_nxt;
  1983. }
  1984. int sde_rm_reserve(
  1985. struct sde_rm *rm,
  1986. struct drm_encoder *enc,
  1987. struct drm_crtc_state *crtc_state,
  1988. struct drm_connector_state *conn_state,
  1989. bool test_only)
  1990. {
  1991. struct sde_rm_rsvp *rsvp_cur, *rsvp_nxt;
  1992. struct sde_rm_requirements reqs = {0,};
  1993. struct msm_drm_private *priv;
  1994. struct sde_kms *sde_kms;
  1995. struct msm_compression_info *comp_info;
  1996. int ret;
  1997. if (!rm || !enc || !crtc_state || !conn_state) {
  1998. SDE_ERROR("invalid arguments\n");
  1999. return -EINVAL;
  2000. }
  2001. if (!enc->dev || !enc->dev->dev_private) {
  2002. SDE_ERROR("drm device invalid\n");
  2003. return -EINVAL;
  2004. }
  2005. priv = enc->dev->dev_private;
  2006. if (!priv->kms) {
  2007. SDE_ERROR("invalid kms\n");
  2008. return -EINVAL;
  2009. }
  2010. sde_kms = to_sde_kms(priv->kms);
  2011. /* Check if this is just a page-flip */
  2012. if (!_sde_rm_is_display_in_cont_splash(sde_kms, enc) &&
  2013. !drm_atomic_crtc_needs_modeset(crtc_state))
  2014. return 0;
  2015. comp_info = kzalloc(sizeof(*comp_info), GFP_KERNEL);
  2016. if (!comp_info)
  2017. return -ENOMEM;
  2018. SDE_DEBUG("reserving hw for conn %d enc %d crtc %d test_only %d\n",
  2019. conn_state->connector->base.id, enc->base.id,
  2020. crtc_state->crtc->base.id, test_only);
  2021. SDE_EVT32(enc->base.id, conn_state->connector->base.id);
  2022. mutex_lock(&rm->rm_lock);
  2023. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_BEGIN);
  2024. rsvp_cur = _sde_rm_get_rsvp(rm, enc);
  2025. rsvp_nxt = _sde_rm_get_rsvp_nxt(rm, enc);
  2026. /*
  2027. * RM currently relies on rsvp_nxt assigned to the hw blocks to
  2028. * commit rsvps. This rsvp_nxt can be cleared by a back to back
  2029. * check_only commit with modeset when its predecessor atomic
  2030. * commit is delayed / not committed the reservation yet.
  2031. * Poll for rsvp_nxt clear, allow the check_only commit if rsvp_nxt
  2032. * gets cleared and bailout if it does not get cleared before timeout.
  2033. */
  2034. if (test_only && rsvp_cur && rsvp_nxt) {
  2035. rsvp_nxt = _sde_rm_poll_get_rsvp_nxt_locked(rm, enc);
  2036. if (rsvp_nxt) {
  2037. SDE_ERROR("poll timeout cur %d nxt %d enc %d\n",
  2038. rsvp_cur->seq, rsvp_nxt->seq, enc->base.id);
  2039. ret = -EINVAL;
  2040. goto end;
  2041. }
  2042. }
  2043. if (!test_only && rsvp_nxt)
  2044. goto commit_rsvp;
  2045. reqs.hw_res.comp_info = comp_info;
  2046. ret = _sde_rm_populate_requirements(rm, enc, crtc_state,
  2047. conn_state, &reqs);
  2048. if (ret) {
  2049. SDE_ERROR("failed to populate hw requirements\n");
  2050. goto end;
  2051. }
  2052. /*
  2053. * We only support one active reservation per-hw-block. But to implement
  2054. * transactional semantics for test-only, and for allowing failure while
  2055. * modifying your existing reservation, over the course of this
  2056. * function we can have two reservations:
  2057. * Current: Existing reservation
  2058. * Next: Proposed reservation. The proposed reservation may fail, or may
  2059. * be discarded if in test-only mode.
  2060. * If reservation is successful, and we're not in test-only, then we
  2061. * replace the current with the next.
  2062. */
  2063. rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
  2064. if (!rsvp_nxt) {
  2065. ret = -ENOMEM;
  2066. goto end;
  2067. }
  2068. /*
  2069. * User can request that we clear out any reservation during the
  2070. * atomic_check phase by using this CLEAR bit
  2071. */
  2072. if (rsvp_cur && test_only && RM_RQ_CLEAR(&reqs)) {
  2073. SDE_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
  2074. rsvp_cur->seq, rsvp_cur->enc_id);
  2075. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2076. rsvp_cur = NULL;
  2077. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
  2078. }
  2079. /* Check the proposed reservation, store it in hw's "next" field */
  2080. ret = _sde_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
  2081. rsvp_nxt, &reqs);
  2082. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_RSVPNEXT);
  2083. if (ret) {
  2084. SDE_ERROR("failed to reserve hw resources: %d, test_only %d\n",
  2085. ret, test_only);
  2086. _sde_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
  2087. goto end;
  2088. } else if (test_only && !RM_RQ_LOCK(&reqs)) {
  2089. /*
  2090. * Normally, if test_only, test the reservation and then undo
  2091. * However, if the user requests LOCK, then keep the reservation
  2092. * made during the atomic_check phase.
  2093. */
  2094. SDE_DEBUG("test_only: rsvp[s%de%d]\n",
  2095. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2096. goto end;
  2097. } else {
  2098. if (test_only && RM_RQ_LOCK(&reqs))
  2099. SDE_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
  2100. rsvp_nxt->seq, rsvp_nxt->enc_id);
  2101. }
  2102. commit_rsvp:
  2103. _sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
  2104. ret = _sde_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
  2105. end:
  2106. kfree(comp_info);
  2107. _sde_rm_print_rsvps(rm, SDE_RM_STAGE_FINAL);
  2108. mutex_unlock(&rm->rm_lock);
  2109. return ret;
  2110. }
  2111. int sde_rm_ext_blk_create_reserve(struct sde_rm *rm,
  2112. struct sde_hw_blk *hw, struct drm_encoder *enc)
  2113. {
  2114. struct sde_rm_hw_blk *blk;
  2115. struct sde_rm_rsvp *rsvp;
  2116. int ret = 0;
  2117. if (!rm || !hw || !enc) {
  2118. SDE_ERROR("invalid parameters\n");
  2119. return -EINVAL;
  2120. }
  2121. if (hw->type >= SDE_HW_BLK_MAX) {
  2122. SDE_ERROR("invalid HW type\n");
  2123. return -EINVAL;
  2124. }
  2125. mutex_lock(&rm->rm_lock);
  2126. rsvp = _sde_rm_get_rsvp(rm, enc);
  2127. if (!rsvp) {
  2128. rsvp = kzalloc(sizeof(*rsvp), GFP_KERNEL);
  2129. if (!rsvp) {
  2130. ret = -ENOMEM;
  2131. goto end;
  2132. }
  2133. rsvp->seq = ++rm->rsvp_next_seq;
  2134. rsvp->enc_id = enc->base.id;
  2135. list_add_tail(&rsvp->list, &rm->rsvps);
  2136. SDE_DEBUG("create rsvp %d for enc %d\n",
  2137. rsvp->seq, rsvp->enc_id);
  2138. }
  2139. blk = kzalloc(sizeof(*blk), GFP_KERNEL);
  2140. if (!blk) {
  2141. ret = -ENOMEM;
  2142. goto end;
  2143. }
  2144. blk->type = hw->type;
  2145. blk->id = hw->id;
  2146. blk->hw = hw;
  2147. blk->rsvp = rsvp;
  2148. list_add_tail(&blk->list, &rm->hw_blks[hw->type]);
  2149. SDE_DEBUG("create blk %d %d for rsvp %d enc %d\n", blk->type, blk->id,
  2150. rsvp->seq, rsvp->enc_id);
  2151. end:
  2152. mutex_unlock(&rm->rm_lock);
  2153. return ret;
  2154. }
  2155. int sde_rm_ext_blk_destroy(struct sde_rm *rm,
  2156. struct drm_encoder *enc)
  2157. {
  2158. struct sde_rm_hw_blk *blk = NULL, *p;
  2159. struct sde_rm_rsvp *rsvp;
  2160. enum sde_hw_blk_type type;
  2161. int ret = 0;
  2162. if (!rm || !enc) {
  2163. SDE_ERROR("invalid parameters\n");
  2164. return -EINVAL;
  2165. }
  2166. mutex_lock(&rm->rm_lock);
  2167. rsvp = _sde_rm_get_rsvp(rm, enc);
  2168. if (!rsvp) {
  2169. ret = -ENOENT;
  2170. SDE_ERROR("failed to find rsvp for enc %d\n", enc->base.id);
  2171. goto end;
  2172. }
  2173. for (type = 0; type < SDE_HW_BLK_MAX; type++) {
  2174. list_for_each_entry_safe(blk, p, &rm->hw_blks[type], list) {
  2175. if (blk->rsvp == rsvp) {
  2176. list_del(&blk->list);
  2177. SDE_DEBUG("del blk %d %d from rsvp %d enc %d\n",
  2178. blk->type, blk->id,
  2179. rsvp->seq, rsvp->enc_id);
  2180. kfree(blk);
  2181. }
  2182. }
  2183. }
  2184. SDE_DEBUG("del rsvp %d\n", rsvp->seq);
  2185. list_del(&rsvp->list);
  2186. kfree(rsvp);
  2187. end:
  2188. mutex_unlock(&rm->rm_lock);
  2189. return ret;
  2190. }