dp_main.c 157 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include "dp_ipa.h"
  52. #define DP_INTR_POLL_TIMER_MS 10
  53. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  54. #define DP_MCS_LENGTH (6*MAX_MCS)
  55. #define DP_NSS_LENGTH (6*SS_COUNT)
  56. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  57. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  58. #define DP_MAX_MCS_STRING_LEN 30
  59. #define DP_CURR_FW_STATS_AVAIL 19
  60. #define DP_HTT_DBG_EXT_STATS_MAX 256
  61. #ifdef IPA_OFFLOAD
  62. /* Exclude IPA rings from the interrupt context */
  63. #define TX_RING_MASK_VAL 0xb
  64. #define RX_RING_MASK_VAL 0x7
  65. #else
  66. #define TX_RING_MASK_VAL 0xF
  67. #define RX_RING_MASK_VAL 0xF
  68. #endif
  69. bool rx_hash = 1;
  70. qdf_declare_param(rx_hash, bool);
  71. #define STR_MAXLEN 64
  72. /**
  73. * default_dscp_tid_map - Default DSCP-TID mapping
  74. *
  75. * DSCP TID AC
  76. * 000000 0 WME_AC_BE
  77. * 001000 1 WME_AC_BK
  78. * 010000 1 WME_AC_BK
  79. * 011000 0 WME_AC_BE
  80. * 100000 5 WME_AC_VI
  81. * 101000 5 WME_AC_VI
  82. * 110000 6 WME_AC_VO
  83. * 111000 6 WME_AC_VO
  84. */
  85. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  86. 0, 0, 0, 0, 0, 0, 0, 0,
  87. 1, 1, 1, 1, 1, 1, 1, 1,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 0, 0, 0, 0, 0, 0, 0, 0,
  90. 5, 5, 5, 5, 5, 5, 5, 5,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 6, 6, 6, 6, 6, 6, 6, 6,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. };
  95. /*
  96. * struct dp_rate_debug
  97. *
  98. * @mcs_type: print string for a given mcs
  99. * @valid: valid mcs rate?
  100. */
  101. struct dp_rate_debug {
  102. char mcs_type[DP_MAX_MCS_STRING_LEN];
  103. uint8_t valid;
  104. };
  105. #define MCS_VALID 1
  106. #define MCS_INVALID 0
  107. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  108. {
  109. {"CCK 11 Mbps Long ", MCS_VALID},
  110. {"CCK 5.5 Mbps Long ", MCS_VALID},
  111. {"CCK 2 Mbps Long ", MCS_VALID},
  112. {"CCK 1 Mbps Long ", MCS_VALID},
  113. {"CCK 11 Mbps Short ", MCS_VALID},
  114. {"CCK 5.5 Mbps Short", MCS_VALID},
  115. {"CCK 2 Mbps Short ", MCS_VALID},
  116. {"INVALID ", MCS_INVALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_VALID},
  122. },
  123. {
  124. {"OFDM 48 Mbps", MCS_VALID},
  125. {"OFDM 24 Mbps", MCS_VALID},
  126. {"OFDM 12 Mbps", MCS_VALID},
  127. {"OFDM 6 Mbps ", MCS_VALID},
  128. {"OFDM 54 Mbps", MCS_VALID},
  129. {"OFDM 36 Mbps", MCS_VALID},
  130. {"OFDM 18 Mbps", MCS_VALID},
  131. {"OFDM 9 Mbps ", MCS_VALID},
  132. {"INVALID ", MCS_INVALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_VALID},
  137. },
  138. {
  139. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  140. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  142. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  143. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  144. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  145. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  146. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  147. {"INVALID ", MCS_INVALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_VALID},
  152. },
  153. {
  154. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  155. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  157. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  158. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  159. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  160. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  161. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  162. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  163. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  164. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  166. {"INVALID ", MCS_VALID},
  167. },
  168. {
  169. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  170. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  172. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  173. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  174. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  175. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  176. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  177. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  178. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  179. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  181. {"INVALID ", MCS_VALID},
  182. }
  183. };
  184. /**
  185. * @brief Cpu ring map types
  186. */
  187. enum dp_cpu_ring_map_types {
  188. DP_DEFAULT_MAP,
  189. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  190. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  191. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  192. DP_CPU_RING_MAP_MAX
  193. };
  194. /**
  195. * @brief Cpu to tx ring map
  196. */
  197. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  198. {0x0, 0x1, 0x2, 0x0},
  199. {0x1, 0x2, 0x1, 0x2},
  200. {0x0, 0x2, 0x0, 0x2},
  201. {0x2, 0x2, 0x2, 0x2}
  202. };
  203. /**
  204. * @brief Select the type of statistics
  205. */
  206. enum dp_stats_type {
  207. STATS_FW = 0,
  208. STATS_HOST = 1,
  209. STATS_TYPE_MAX = 2,
  210. };
  211. /**
  212. * @brief General Firmware statistics options
  213. *
  214. */
  215. enum dp_fw_stats {
  216. TXRX_FW_STATS_INVALID = -1,
  217. };
  218. /**
  219. * dp_stats_mapping_table - Firmware and Host statistics
  220. * currently supported
  221. */
  222. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  223. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  224. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  234. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  235. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  242. /* Last ENUM for HTT FW STATS */
  243. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  244. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  245. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  251. };
  252. /**
  253. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  254. * @ring_num: ring num of the ring being queried
  255. * @grp_mask: the grp_mask array for the ring type in question.
  256. *
  257. * The grp_mask array is indexed by group number and the bit fields correspond
  258. * to ring numbers. We are finding which interrupt group a ring belongs to.
  259. *
  260. * Return: the index in the grp_mask array with the ring number.
  261. * -QDF_STATUS_E_NOENT if no entry is found
  262. */
  263. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  264. {
  265. int ext_group_num;
  266. int mask = 1 << ring_num;
  267. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  268. ext_group_num++) {
  269. if (mask & grp_mask[ext_group_num])
  270. return ext_group_num;
  271. }
  272. return -QDF_STATUS_E_NOENT;
  273. }
  274. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  275. enum hal_ring_type ring_type,
  276. int ring_num)
  277. {
  278. int *grp_mask;
  279. switch (ring_type) {
  280. case WBM2SW_RELEASE:
  281. /* dp_tx_comp_handler - soc->tx_comp_ring */
  282. if (ring_num < 3)
  283. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  284. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  285. else if (ring_num == 3) {
  286. /* sw treats this as a separate ring type */
  287. grp_mask = &soc->wlan_cfg_ctx->
  288. int_rx_wbm_rel_ring_mask[0];
  289. ring_num = 0;
  290. } else {
  291. qdf_assert(0);
  292. return -QDF_STATUS_E_NOENT;
  293. }
  294. break;
  295. case REO_EXCEPTION:
  296. /* dp_rx_err_process - &soc->reo_exception_ring */
  297. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  298. break;
  299. case REO_DST:
  300. /* dp_rx_process - soc->reo_dest_ring */
  301. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  302. break;
  303. case REO_STATUS:
  304. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  305. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  306. break;
  307. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  308. case RXDMA_MONITOR_STATUS:
  309. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  310. case RXDMA_MONITOR_DST:
  311. /* dp_mon_process */
  312. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  313. break;
  314. case RXDMA_DST:
  315. /* dp_rxdma_err_process */
  316. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  317. break;
  318. case RXDMA_BUF:
  319. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  320. break;
  321. case RXDMA_MONITOR_BUF:
  322. /* TODO: support low_thresh interrupt */
  323. return -QDF_STATUS_E_NOENT;
  324. break;
  325. case TCL_DATA:
  326. case TCL_CMD:
  327. case REO_CMD:
  328. case SW2WBM_RELEASE:
  329. case WBM_IDLE_LINK:
  330. /* normally empty SW_TO_HW rings */
  331. return -QDF_STATUS_E_NOENT;
  332. break;
  333. case TCL_STATUS:
  334. case REO_REINJECT:
  335. /* misc unused rings */
  336. return -QDF_STATUS_E_NOENT;
  337. break;
  338. case CE_SRC:
  339. case CE_DST:
  340. case CE_DST_STATUS:
  341. /* CE_rings - currently handled by hif */
  342. default:
  343. return -QDF_STATUS_E_NOENT;
  344. break;
  345. }
  346. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  347. }
  348. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  349. *ring_params, int ring_type, int ring_num)
  350. {
  351. int msi_group_number;
  352. int msi_data_count;
  353. int ret;
  354. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  355. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  356. &msi_data_count, &msi_data_start,
  357. &msi_irq_start);
  358. if (ret)
  359. return;
  360. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  361. ring_num);
  362. if (msi_group_number < 0) {
  363. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  364. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  365. ring_type, ring_num);
  366. ring_params->msi_addr = 0;
  367. ring_params->msi_data = 0;
  368. return;
  369. }
  370. if (msi_group_number > msi_data_count) {
  371. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  372. FL("2 msi_groups will share an msi; msi_group_num %d"),
  373. msi_group_number);
  374. QDF_ASSERT(0);
  375. }
  376. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  377. ring_params->msi_addr = addr_low;
  378. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  379. ring_params->msi_data = (msi_group_number % msi_data_count)
  380. + msi_data_start;
  381. ring_params->flags |= HAL_SRNG_MSI_INTR;
  382. }
  383. /**
  384. * dp_print_ast_stats() - Dump AST table contents
  385. * @soc: Datapath soc handle
  386. *
  387. * return void
  388. */
  389. #ifdef FEATURE_WDS
  390. static void dp_print_ast_stats(struct dp_soc *soc)
  391. {
  392. uint8_t i;
  393. uint8_t num_entries = 0;
  394. struct dp_vdev *vdev;
  395. struct dp_pdev *pdev;
  396. struct dp_peer *peer;
  397. struct dp_ast_entry *ase, *tmp_ase;
  398. DP_PRINT_STATS("AST Stats:");
  399. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  400. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  401. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  402. DP_PRINT_STATS("AST Table:");
  403. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  404. pdev = soc->pdev_list[i];
  405. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  406. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  407. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  408. DP_PRINT_STATS("%6d mac_addr = %pM"
  409. " peer_mac_addr = %pM"
  410. " type = %d"
  411. " next_hop = %d"
  412. " is_active = %d"
  413. " is_bss = %d",
  414. ++num_entries,
  415. ase->mac_addr.raw,
  416. ase->peer->mac_addr.raw,
  417. ase->type,
  418. ase->next_hop,
  419. ase->is_active,
  420. ase->is_bss);
  421. }
  422. }
  423. }
  424. }
  425. }
  426. #else
  427. static void dp_print_ast_stats(struct dp_soc *soc)
  428. {
  429. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  430. return;
  431. }
  432. #endif
  433. /*
  434. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  435. */
  436. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  437. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  438. {
  439. void *hal_soc = soc->hal_soc;
  440. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  441. /* TODO: See if we should get align size from hal */
  442. uint32_t ring_base_align = 8;
  443. struct hal_srng_params ring_params;
  444. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  445. /* TODO: Currently hal layer takes care of endianness related settings.
  446. * See if these settings need to passed from DP layer
  447. */
  448. ring_params.flags = 0;
  449. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  450. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  451. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  452. srng->hal_srng = NULL;
  453. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  454. srng->num_entries = num_entries;
  455. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  456. soc->osdev, soc->osdev->dev, srng->alloc_size,
  457. &(srng->base_paddr_unaligned));
  458. if (!srng->base_vaddr_unaligned) {
  459. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  460. FL("alloc failed - ring_type: %d, ring_num %d"),
  461. ring_type, ring_num);
  462. return QDF_STATUS_E_NOMEM;
  463. }
  464. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  465. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  466. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  467. ((unsigned long)(ring_params.ring_base_vaddr) -
  468. (unsigned long)srng->base_vaddr_unaligned);
  469. ring_params.num_entries = num_entries;
  470. if (soc->intr_mode == DP_INTR_MSI) {
  471. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  472. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  473. FL("Using MSI for ring_type: %d, ring_num %d"),
  474. ring_type, ring_num);
  475. } else {
  476. ring_params.msi_data = 0;
  477. ring_params.msi_addr = 0;
  478. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  479. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  480. ring_type, ring_num);
  481. }
  482. /*
  483. * Setup interrupt timer and batch counter thresholds for
  484. * interrupt mitigation based on ring type
  485. */
  486. if (ring_type == REO_DST) {
  487. ring_params.intr_timer_thres_us =
  488. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  489. ring_params.intr_batch_cntr_thres_entries =
  490. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  491. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  492. ring_params.intr_timer_thres_us =
  493. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  494. ring_params.intr_batch_cntr_thres_entries =
  495. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  496. } else {
  497. ring_params.intr_timer_thres_us =
  498. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  499. ring_params.intr_batch_cntr_thres_entries =
  500. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  501. }
  502. /* Enable low threshold interrupts for rx buffer rings (regular and
  503. * monitor buffer rings.
  504. * TODO: See if this is required for any other ring
  505. */
  506. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  507. /* TODO: Setting low threshold to 1/8th of ring size
  508. * see if this needs to be configurable
  509. */
  510. ring_params.low_threshold = num_entries >> 3;
  511. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  512. ring_params.intr_timer_thres_us = 0x1000;
  513. }
  514. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  515. mac_id, &ring_params);
  516. return 0;
  517. }
  518. /**
  519. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  520. * Any buffers allocated and attached to ring entries are expected to be freed
  521. * before calling this function.
  522. */
  523. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  524. int ring_type, int ring_num)
  525. {
  526. if (!srng->hal_srng) {
  527. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  528. FL("Ring type: %d, num:%d not setup"),
  529. ring_type, ring_num);
  530. return;
  531. }
  532. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  533. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  534. srng->alloc_size,
  535. srng->base_vaddr_unaligned,
  536. srng->base_paddr_unaligned, 0);
  537. srng->hal_srng = NULL;
  538. }
  539. /* TODO: Need this interface from HIF */
  540. void *hif_get_hal_handle(void *hif_handle);
  541. /*
  542. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  543. * @dp_ctx: DP SOC handle
  544. * @budget: Number of frames/descriptors that can be processed in one shot
  545. *
  546. * Return: remaining budget/quota for the soc device
  547. */
  548. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  549. {
  550. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  551. struct dp_soc *soc = int_ctx->soc;
  552. int ring = 0;
  553. uint32_t work_done = 0;
  554. int budget = dp_budget;
  555. uint8_t tx_mask = int_ctx->tx_ring_mask;
  556. uint8_t rx_mask = int_ctx->rx_ring_mask;
  557. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  558. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  559. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  560. uint32_t remaining_quota = dp_budget;
  561. struct dp_pdev *pdev = NULL;
  562. /* Process Tx completion interrupts first to return back buffers */
  563. while (tx_mask) {
  564. if (tx_mask & 0x1) {
  565. work_done = dp_tx_comp_handler(soc,
  566. soc->tx_comp_ring[ring].hal_srng,
  567. remaining_quota);
  568. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  569. "tx mask 0x%x ring %d, budget %d, work_done %d",
  570. tx_mask, ring, budget, work_done);
  571. budget -= work_done;
  572. if (budget <= 0)
  573. goto budget_done;
  574. remaining_quota = budget;
  575. }
  576. tx_mask = tx_mask >> 1;
  577. ring++;
  578. }
  579. /* Process REO Exception ring interrupt */
  580. if (rx_err_mask) {
  581. work_done = dp_rx_err_process(soc,
  582. soc->reo_exception_ring.hal_srng,
  583. remaining_quota);
  584. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  585. "REO Exception Ring: work_done %d budget %d",
  586. work_done, budget);
  587. budget -= work_done;
  588. if (budget <= 0) {
  589. goto budget_done;
  590. }
  591. remaining_quota = budget;
  592. }
  593. /* Process Rx WBM release ring interrupt */
  594. if (rx_wbm_rel_mask) {
  595. work_done = dp_rx_wbm_err_process(soc,
  596. soc->rx_rel_ring.hal_srng, remaining_quota);
  597. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  598. "WBM Release Ring: work_done %d budget %d",
  599. work_done, budget);
  600. budget -= work_done;
  601. if (budget <= 0) {
  602. goto budget_done;
  603. }
  604. remaining_quota = budget;
  605. }
  606. /* Process Rx interrupts */
  607. if (rx_mask) {
  608. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  609. if (rx_mask & (1 << ring)) {
  610. work_done = dp_rx_process(int_ctx,
  611. soc->reo_dest_ring[ring].hal_srng,
  612. remaining_quota);
  613. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  614. "rx mask 0x%x ring %d, work_done %d budget %d",
  615. rx_mask, ring, work_done, budget);
  616. budget -= work_done;
  617. if (budget <= 0)
  618. goto budget_done;
  619. remaining_quota = budget;
  620. }
  621. }
  622. }
  623. if (reo_status_mask)
  624. dp_reo_status_ring_handler(soc);
  625. /* Process LMAC interrupts */
  626. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  627. pdev = soc->pdev_list[ring];
  628. if (pdev == NULL)
  629. continue;
  630. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  631. work_done = dp_mon_process(soc, ring, remaining_quota);
  632. budget -= work_done;
  633. if (budget <= 0)
  634. goto budget_done;
  635. remaining_quota = budget;
  636. }
  637. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  638. work_done = dp_rxdma_err_process(soc, ring,
  639. remaining_quota);
  640. budget -= work_done;
  641. if (budget <= 0)
  642. goto budget_done;
  643. remaining_quota = budget;
  644. }
  645. if (int_ctx->host2rxdma_ring_mask & (1 << ring)) {
  646. union dp_rx_desc_list_elem_t *desc_list = NULL;
  647. union dp_rx_desc_list_elem_t *tail = NULL;
  648. struct dp_srng *rx_refill_buf_ring =
  649. &pdev->rx_refill_buf_ring;
  650. DP_STATS_INC(pdev, replenish.low_thresh_intrs, 1);
  651. dp_rx_buffers_replenish(soc, ring,
  652. rx_refill_buf_ring,
  653. &soc->rx_desc_buf[ring], 0,
  654. &desc_list, &tail, HAL_RX_BUF_RBM_SW3_BM);
  655. }
  656. }
  657. qdf_lro_flush(int_ctx->lro_ctx);
  658. budget_done:
  659. return dp_budget - budget;
  660. }
  661. #ifdef DP_INTR_POLL_BASED
  662. /* dp_interrupt_timer()- timer poll for interrupts
  663. *
  664. * @arg: SoC Handle
  665. *
  666. * Return:
  667. *
  668. */
  669. static void dp_interrupt_timer(void *arg)
  670. {
  671. struct dp_soc *soc = (struct dp_soc *) arg;
  672. int i;
  673. if (qdf_atomic_read(&soc->cmn_init_done)) {
  674. for (i = 0;
  675. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  676. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  677. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  678. }
  679. }
  680. /*
  681. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  682. * @txrx_soc: DP SOC handle
  683. *
  684. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  685. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  686. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  687. *
  688. * Return: 0 for success. nonzero for failure.
  689. */
  690. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  691. {
  692. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  693. int i;
  694. soc->intr_mode = DP_INTR_POLL;
  695. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  696. soc->intr_ctx[i].dp_intr_id = i;
  697. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  698. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  699. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  700. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  701. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  702. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  703. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  704. soc->intr_ctx[i].host2rxdma_ring_mask = 0x1;
  705. soc->intr_ctx[i].soc = soc;
  706. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  707. }
  708. qdf_timer_init(soc->osdev, &soc->int_timer,
  709. dp_interrupt_timer, (void *)soc,
  710. QDF_TIMER_TYPE_WAKE_APPS);
  711. return QDF_STATUS_SUCCESS;
  712. }
  713. #if defined(CONFIG_MCL)
  714. extern int con_mode_monitor;
  715. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  716. /*
  717. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  718. * @txrx_soc: DP SOC handle
  719. *
  720. * Call the appropriate attach function based on the mode of operation.
  721. * This is a WAR for enabling monitor mode.
  722. *
  723. * Return: 0 for success. nonzero for failure.
  724. */
  725. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  726. {
  727. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  728. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  729. con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  730. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  731. "%s: Poll mode", __func__);
  732. return dp_soc_interrupt_attach_poll(txrx_soc);
  733. } else {
  734. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  735. "%s: Interrupt mode", __func__);
  736. return dp_soc_interrupt_attach(txrx_soc);
  737. }
  738. }
  739. #else
  740. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  741. {
  742. return dp_soc_interrupt_attach_poll(txrx_soc);
  743. }
  744. #endif
  745. #endif
  746. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  747. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  748. {
  749. int j;
  750. int num_irq = 0;
  751. int tx_mask =
  752. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  753. int rx_mask =
  754. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  755. int rx_mon_mask =
  756. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  757. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  758. soc->wlan_cfg_ctx, intr_ctx_num);
  759. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  760. soc->wlan_cfg_ctx, intr_ctx_num);
  761. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  762. soc->wlan_cfg_ctx, intr_ctx_num);
  763. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  764. soc->wlan_cfg_ctx, intr_ctx_num);
  765. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  766. soc->wlan_cfg_ctx, intr_ctx_num);
  767. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  768. if (tx_mask & (1 << j)) {
  769. irq_id_map[num_irq++] =
  770. (wbm2host_tx_completions_ring1 - j);
  771. }
  772. if (rx_mask & (1 << j)) {
  773. irq_id_map[num_irq++] =
  774. (reo2host_destination_ring1 - j);
  775. }
  776. if (rxdma2host_ring_mask & (1 << j)) {
  777. irq_id_map[num_irq++] =
  778. rxdma2host_destination_ring_mac1 -
  779. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  780. }
  781. if (host2rxdma_ring_mask & (1 << j)) {
  782. irq_id_map[num_irq++] =
  783. host2rxdma_host_buf_ring_mac1 -
  784. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  785. }
  786. if (rx_mon_mask & (1 << j)) {
  787. irq_id_map[num_irq++] =
  788. ppdu_end_interrupts_mac1 -
  789. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  790. }
  791. if (rx_wbm_rel_ring_mask & (1 << j))
  792. irq_id_map[num_irq++] = wbm2host_rx_release;
  793. if (rx_err_ring_mask & (1 << j))
  794. irq_id_map[num_irq++] = reo2host_exception;
  795. if (reo_status_ring_mask & (1 << j))
  796. irq_id_map[num_irq++] = reo2host_status;
  797. }
  798. *num_irq_r = num_irq;
  799. }
  800. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  801. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  802. int msi_vector_count, int msi_vector_start)
  803. {
  804. int tx_mask = wlan_cfg_get_tx_ring_mask(
  805. soc->wlan_cfg_ctx, intr_ctx_num);
  806. int rx_mask = wlan_cfg_get_rx_ring_mask(
  807. soc->wlan_cfg_ctx, intr_ctx_num);
  808. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  809. soc->wlan_cfg_ctx, intr_ctx_num);
  810. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  811. soc->wlan_cfg_ctx, intr_ctx_num);
  812. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  813. soc->wlan_cfg_ctx, intr_ctx_num);
  814. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  815. soc->wlan_cfg_ctx, intr_ctx_num);
  816. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  817. soc->wlan_cfg_ctx, intr_ctx_num);
  818. unsigned int vector =
  819. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  820. int num_irq = 0;
  821. soc->intr_mode = DP_INTR_MSI;
  822. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  823. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  824. irq_id_map[num_irq++] =
  825. pld_get_msi_irq(soc->osdev->dev, vector);
  826. *num_irq_r = num_irq;
  827. }
  828. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  829. int *irq_id_map, int *num_irq)
  830. {
  831. int msi_vector_count, ret;
  832. uint32_t msi_base_data, msi_vector_start;
  833. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  834. &msi_vector_count,
  835. &msi_base_data,
  836. &msi_vector_start);
  837. if (ret)
  838. return dp_soc_interrupt_map_calculate_integrated(soc,
  839. intr_ctx_num, irq_id_map, num_irq);
  840. else
  841. dp_soc_interrupt_map_calculate_msi(soc,
  842. intr_ctx_num, irq_id_map, num_irq,
  843. msi_vector_count, msi_vector_start);
  844. }
  845. /*
  846. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  847. * @txrx_soc: DP SOC handle
  848. *
  849. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  850. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  851. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  852. *
  853. * Return: 0 for success. nonzero for failure.
  854. */
  855. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  856. {
  857. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  858. int i = 0;
  859. int num_irq = 0;
  860. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  861. int ret = 0;
  862. /* Map of IRQ ids registered with one interrupt context */
  863. int irq_id_map[HIF_MAX_GRP_IRQ];
  864. int tx_mask =
  865. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  866. int rx_mask =
  867. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  868. int rx_mon_mask =
  869. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  870. int rx_err_ring_mask =
  871. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  872. int rx_wbm_rel_ring_mask =
  873. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  874. int reo_status_ring_mask =
  875. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  876. int rxdma2host_ring_mask =
  877. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  878. int host2rxdma_ring_mask =
  879. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  880. soc->intr_ctx[i].dp_intr_id = i;
  881. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  882. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  883. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  884. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  885. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  886. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  887. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  888. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  889. soc->intr_ctx[i].soc = soc;
  890. num_irq = 0;
  891. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  892. &num_irq);
  893. ret = hif_register_ext_group(soc->hif_handle,
  894. num_irq, irq_id_map, dp_service_srngs,
  895. &soc->intr_ctx[i], "dp_intr",
  896. HIF_EXEC_NAPI_TYPE, 2);
  897. if (ret) {
  898. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  899. FL("failed, ret = %d"), ret);
  900. return QDF_STATUS_E_FAILURE;
  901. }
  902. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  903. }
  904. hif_configure_ext_group_interrupts(soc->hif_handle);
  905. return QDF_STATUS_SUCCESS;
  906. }
  907. /*
  908. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  909. * @txrx_soc: DP SOC handle
  910. *
  911. * Return: void
  912. */
  913. static void dp_soc_interrupt_detach(void *txrx_soc)
  914. {
  915. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  916. int i;
  917. if (soc->intr_mode == DP_INTR_POLL) {
  918. qdf_timer_stop(&soc->int_timer);
  919. qdf_timer_free(&soc->int_timer);
  920. } else {
  921. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  922. }
  923. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  924. soc->intr_ctx[i].tx_ring_mask = 0;
  925. soc->intr_ctx[i].rx_ring_mask = 0;
  926. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  927. soc->intr_ctx[i].rx_err_ring_mask = 0;
  928. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  929. soc->intr_ctx[i].reo_status_ring_mask = 0;
  930. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  931. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  932. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  933. }
  934. }
  935. #define AVG_MAX_MPDUS_PER_TID 128
  936. #define AVG_TIDS_PER_CLIENT 2
  937. #define AVG_FLOWS_PER_TID 2
  938. #define AVG_MSDUS_PER_FLOW 128
  939. #define AVG_MSDUS_PER_MPDU 4
  940. /*
  941. * Allocate and setup link descriptor pool that will be used by HW for
  942. * various link and queue descriptors and managed by WBM
  943. */
  944. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  945. {
  946. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  947. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  948. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  949. uint32_t num_mpdus_per_link_desc =
  950. hal_num_mpdus_per_link_desc(soc->hal_soc);
  951. uint32_t num_msdus_per_link_desc =
  952. hal_num_msdus_per_link_desc(soc->hal_soc);
  953. uint32_t num_mpdu_links_per_queue_desc =
  954. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  955. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  956. uint32_t total_link_descs, total_mem_size;
  957. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  958. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  959. uint32_t num_link_desc_banks;
  960. uint32_t last_bank_size = 0;
  961. uint32_t entry_size, num_entries;
  962. int i;
  963. uint32_t desc_id = 0;
  964. /* Only Tx queue descriptors are allocated from common link descriptor
  965. * pool Rx queue descriptors are not included in this because (REO queue
  966. * extension descriptors) they are expected to be allocated contiguously
  967. * with REO queue descriptors
  968. */
  969. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  970. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  971. num_mpdu_queue_descs = num_mpdu_link_descs /
  972. num_mpdu_links_per_queue_desc;
  973. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  974. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  975. num_msdus_per_link_desc;
  976. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  977. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  978. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  979. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  980. /* Round up to power of 2 */
  981. total_link_descs = 1;
  982. while (total_link_descs < num_entries)
  983. total_link_descs <<= 1;
  984. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  985. FL("total_link_descs: %u, link_desc_size: %d"),
  986. total_link_descs, link_desc_size);
  987. total_mem_size = total_link_descs * link_desc_size;
  988. total_mem_size += link_desc_align;
  989. if (total_mem_size <= max_alloc_size) {
  990. num_link_desc_banks = 0;
  991. last_bank_size = total_mem_size;
  992. } else {
  993. num_link_desc_banks = (total_mem_size) /
  994. (max_alloc_size - link_desc_align);
  995. last_bank_size = total_mem_size %
  996. (max_alloc_size - link_desc_align);
  997. }
  998. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  999. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1000. total_mem_size, num_link_desc_banks);
  1001. for (i = 0; i < num_link_desc_banks; i++) {
  1002. soc->link_desc_banks[i].base_vaddr_unaligned =
  1003. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1004. max_alloc_size,
  1005. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1006. soc->link_desc_banks[i].size = max_alloc_size;
  1007. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1008. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1009. ((unsigned long)(
  1010. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1011. link_desc_align));
  1012. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1013. soc->link_desc_banks[i].base_paddr_unaligned) +
  1014. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1015. (unsigned long)(
  1016. soc->link_desc_banks[i].base_vaddr_unaligned));
  1017. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1018. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1019. FL("Link descriptor memory alloc failed"));
  1020. goto fail;
  1021. }
  1022. }
  1023. if (last_bank_size) {
  1024. /* Allocate last bank in case total memory required is not exact
  1025. * multiple of max_alloc_size
  1026. */
  1027. soc->link_desc_banks[i].base_vaddr_unaligned =
  1028. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1029. last_bank_size,
  1030. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1031. soc->link_desc_banks[i].size = last_bank_size;
  1032. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1033. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1034. ((unsigned long)(
  1035. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1036. link_desc_align));
  1037. soc->link_desc_banks[i].base_paddr =
  1038. (unsigned long)(
  1039. soc->link_desc_banks[i].base_paddr_unaligned) +
  1040. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1041. (unsigned long)(
  1042. soc->link_desc_banks[i].base_vaddr_unaligned));
  1043. }
  1044. /* Allocate and setup link descriptor idle list for HW internal use */
  1045. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1046. total_mem_size = entry_size * total_link_descs;
  1047. if (total_mem_size <= max_alloc_size) {
  1048. void *desc;
  1049. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1050. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1051. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1052. FL("Link desc idle ring setup failed"));
  1053. goto fail;
  1054. }
  1055. hal_srng_access_start_unlocked(soc->hal_soc,
  1056. soc->wbm_idle_link_ring.hal_srng);
  1057. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1058. soc->link_desc_banks[i].base_paddr; i++) {
  1059. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1060. ((unsigned long)(
  1061. soc->link_desc_banks[i].base_vaddr) -
  1062. (unsigned long)(
  1063. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1064. / link_desc_size;
  1065. unsigned long paddr = (unsigned long)(
  1066. soc->link_desc_banks[i].base_paddr);
  1067. while (num_entries && (desc = hal_srng_src_get_next(
  1068. soc->hal_soc,
  1069. soc->wbm_idle_link_ring.hal_srng))) {
  1070. hal_set_link_desc_addr(desc,
  1071. LINK_DESC_COOKIE(desc_id, i), paddr);
  1072. num_entries--;
  1073. desc_id++;
  1074. paddr += link_desc_size;
  1075. }
  1076. }
  1077. hal_srng_access_end_unlocked(soc->hal_soc,
  1078. soc->wbm_idle_link_ring.hal_srng);
  1079. } else {
  1080. uint32_t num_scatter_bufs;
  1081. uint32_t num_entries_per_buf;
  1082. uint32_t rem_entries;
  1083. uint8_t *scatter_buf_ptr;
  1084. uint16_t scatter_buf_num;
  1085. soc->wbm_idle_scatter_buf_size =
  1086. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1087. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1088. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1089. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1090. soc->hal_soc, total_mem_size,
  1091. soc->wbm_idle_scatter_buf_size);
  1092. for (i = 0; i < num_scatter_bufs; i++) {
  1093. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1094. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1095. soc->wbm_idle_scatter_buf_size,
  1096. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1097. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1098. QDF_TRACE(QDF_MODULE_ID_DP,
  1099. QDF_TRACE_LEVEL_ERROR,
  1100. FL("Scatter list memory alloc failed"));
  1101. goto fail;
  1102. }
  1103. }
  1104. /* Populate idle list scatter buffers with link descriptor
  1105. * pointers
  1106. */
  1107. scatter_buf_num = 0;
  1108. scatter_buf_ptr = (uint8_t *)(
  1109. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1110. rem_entries = num_entries_per_buf;
  1111. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1112. soc->link_desc_banks[i].base_paddr; i++) {
  1113. uint32_t num_link_descs =
  1114. (soc->link_desc_banks[i].size -
  1115. ((unsigned long)(
  1116. soc->link_desc_banks[i].base_vaddr) -
  1117. (unsigned long)(
  1118. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1119. / link_desc_size;
  1120. unsigned long paddr = (unsigned long)(
  1121. soc->link_desc_banks[i].base_paddr);
  1122. while (num_link_descs) {
  1123. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1124. LINK_DESC_COOKIE(desc_id, i), paddr);
  1125. num_link_descs--;
  1126. desc_id++;
  1127. paddr += link_desc_size;
  1128. rem_entries--;
  1129. if (rem_entries) {
  1130. scatter_buf_ptr += entry_size;
  1131. } else {
  1132. rem_entries = num_entries_per_buf;
  1133. scatter_buf_num++;
  1134. if (scatter_buf_num >= num_scatter_bufs)
  1135. break;
  1136. scatter_buf_ptr = (uint8_t *)(
  1137. soc->wbm_idle_scatter_buf_base_vaddr[
  1138. scatter_buf_num]);
  1139. }
  1140. }
  1141. }
  1142. /* Setup link descriptor idle list in HW */
  1143. hal_setup_link_idle_list(soc->hal_soc,
  1144. soc->wbm_idle_scatter_buf_base_paddr,
  1145. soc->wbm_idle_scatter_buf_base_vaddr,
  1146. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1147. (uint32_t)(scatter_buf_ptr -
  1148. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1149. scatter_buf_num-1])), total_link_descs);
  1150. }
  1151. return 0;
  1152. fail:
  1153. if (soc->wbm_idle_link_ring.hal_srng) {
  1154. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1155. WBM_IDLE_LINK, 0);
  1156. }
  1157. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1158. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1159. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1160. soc->wbm_idle_scatter_buf_size,
  1161. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1162. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1163. }
  1164. }
  1165. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1166. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1167. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1168. soc->link_desc_banks[i].size,
  1169. soc->link_desc_banks[i].base_vaddr_unaligned,
  1170. soc->link_desc_banks[i].base_paddr_unaligned,
  1171. 0);
  1172. }
  1173. }
  1174. return QDF_STATUS_E_FAILURE;
  1175. }
  1176. /*
  1177. * Free link descriptor pool that was setup HW
  1178. */
  1179. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1180. {
  1181. int i;
  1182. if (soc->wbm_idle_link_ring.hal_srng) {
  1183. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1184. WBM_IDLE_LINK, 0);
  1185. }
  1186. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1187. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1188. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1189. soc->wbm_idle_scatter_buf_size,
  1190. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1191. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1192. }
  1193. }
  1194. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1195. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1196. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1197. soc->link_desc_banks[i].size,
  1198. soc->link_desc_banks[i].base_vaddr_unaligned,
  1199. soc->link_desc_banks[i].base_paddr_unaligned,
  1200. 0);
  1201. }
  1202. }
  1203. }
  1204. /* TODO: Following should be configurable */
  1205. #define WBM_RELEASE_RING_SIZE 64
  1206. #define TCL_CMD_RING_SIZE 32
  1207. #define TCL_STATUS_RING_SIZE 32
  1208. #if defined(QCA_WIFI_QCA6290)
  1209. #define REO_DST_RING_SIZE 1024
  1210. #else
  1211. #define REO_DST_RING_SIZE 2048
  1212. #endif
  1213. #define REO_REINJECT_RING_SIZE 32
  1214. #define RX_RELEASE_RING_SIZE 1024
  1215. #define REO_EXCEPTION_RING_SIZE 128
  1216. #define REO_CMD_RING_SIZE 32
  1217. #define REO_STATUS_RING_SIZE 32
  1218. #define RXDMA_BUF_RING_SIZE 1024
  1219. #define RXDMA_REFILL_RING_SIZE 4096
  1220. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1221. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1222. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1223. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1224. #define RXDMA_ERR_DST_RING_SIZE 1024
  1225. /*
  1226. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1227. * @soc: Datapath SOC handle
  1228. *
  1229. * This is a timer function used to age out stale WDS nodes from
  1230. * AST table
  1231. */
  1232. #ifdef FEATURE_WDS
  1233. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1234. {
  1235. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1236. struct dp_pdev *pdev;
  1237. struct dp_vdev *vdev;
  1238. struct dp_peer *peer;
  1239. struct dp_ast_entry *ase, *temp_ase;
  1240. int i;
  1241. qdf_spin_lock_bh(&soc->ast_lock);
  1242. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1243. pdev = soc->pdev_list[i];
  1244. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1245. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1246. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1247. /*
  1248. * Do not expire static ast entries
  1249. */
  1250. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1251. continue;
  1252. if (ase->is_active) {
  1253. ase->is_active = FALSE;
  1254. continue;
  1255. }
  1256. DP_STATS_INC(soc, ast.aged_out, 1);
  1257. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1258. pdev->osif_pdev,
  1259. ase->mac_addr.raw);
  1260. dp_peer_del_ast(soc, ase);
  1261. }
  1262. }
  1263. }
  1264. }
  1265. qdf_spin_unlock_bh(&soc->ast_lock);
  1266. if (qdf_atomic_read(&soc->cmn_init_done))
  1267. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1268. }
  1269. /*
  1270. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1271. * @soc: Datapath SOC handle
  1272. *
  1273. * Return: None
  1274. */
  1275. static void dp_soc_wds_attach(struct dp_soc *soc)
  1276. {
  1277. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1278. dp_wds_aging_timer_fn, (void *)soc,
  1279. QDF_TIMER_TYPE_WAKE_APPS);
  1280. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1281. }
  1282. /*
  1283. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1284. * @txrx_soc: DP SOC handle
  1285. *
  1286. * Return: None
  1287. */
  1288. static void dp_soc_wds_detach(struct dp_soc *soc)
  1289. {
  1290. qdf_timer_stop(&soc->wds_aging_timer);
  1291. qdf_timer_free(&soc->wds_aging_timer);
  1292. }
  1293. #else
  1294. static void dp_soc_wds_attach(struct dp_soc *soc)
  1295. {
  1296. }
  1297. static void dp_soc_wds_detach(struct dp_soc *soc)
  1298. {
  1299. }
  1300. #endif
  1301. /*
  1302. * dp_soc_reset_ring_map() - Reset cpu ring map
  1303. * @soc: Datapath soc handler
  1304. *
  1305. * This api resets the default cpu ring map
  1306. */
  1307. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1308. {
  1309. uint8_t i;
  1310. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1311. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1312. if (nss_config == 1) {
  1313. /*
  1314. * Setting Tx ring map for one nss offloaded radio
  1315. */
  1316. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1317. } else if (nss_config == 2) {
  1318. /*
  1319. * Setting Tx ring for two nss offloaded radios
  1320. */
  1321. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1322. } else {
  1323. /*
  1324. * Setting Tx ring map for all nss offloaded radios
  1325. */
  1326. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1327. }
  1328. }
  1329. }
  1330. /*
  1331. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  1332. * @dp_soc - DP soc handle
  1333. * @ring_type - ring type
  1334. * @ring_num - ring_num
  1335. *
  1336. * return 0 or 1
  1337. */
  1338. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc, enum hal_ring_type ring_type, int ring_num)
  1339. {
  1340. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1341. uint8_t status = 0;
  1342. switch (ring_type) {
  1343. case WBM2SW_RELEASE:
  1344. case REO_DST:
  1345. case RXDMA_BUF:
  1346. status = ((nss_config) & (1 << ring_num));
  1347. break;
  1348. default:
  1349. break;
  1350. }
  1351. return status;
  1352. }
  1353. /*
  1354. * dp_soc_reset_intr_mask() - reset interrupt mask
  1355. * @dp_soc - DP Soc handle
  1356. *
  1357. * Return: Return void
  1358. */
  1359. static void dp_soc_reset_intr_mask(struct dp_soc *soc)
  1360. {
  1361. uint8_t j;
  1362. int *grp_mask = NULL;
  1363. int group_number, mask, num_ring;
  1364. /* number of tx ring */
  1365. num_ring = wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1366. /*
  1367. * group mask for tx completion ring.
  1368. */
  1369. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  1370. /* loop and reset the mask for only offloaded ring */
  1371. for (j = 0; j < num_ring; j++) {
  1372. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j)) {
  1373. continue;
  1374. }
  1375. /*
  1376. * Group number corresponding to tx offloaded ring.
  1377. */
  1378. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1379. if (group_number < 0) {
  1380. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1381. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1382. WBM2SW_RELEASE, j);
  1383. return;
  1384. }
  1385. /* reset the tx mask for offloaded ring */
  1386. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1387. mask &= (~(1 << j));
  1388. /*
  1389. * reset the interrupt mask for offloaded ring.
  1390. */
  1391. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1392. }
  1393. /* number of rx rings */
  1394. num_ring = wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1395. /*
  1396. * group mask for reo destination ring.
  1397. */
  1398. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  1399. /* loop and reset the mask for only offloaded ring */
  1400. for (j = 0; j < num_ring; j++) {
  1401. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j)) {
  1402. continue;
  1403. }
  1404. /*
  1405. * Group number corresponding to rx offloaded ring.
  1406. */
  1407. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1408. if (group_number < 0) {
  1409. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1410. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1411. REO_DST, j);
  1412. return;
  1413. }
  1414. /* set the interrupt mask for offloaded ring */
  1415. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  1416. mask &= (~(1 << j));
  1417. /*
  1418. * set the interrupt mask to zero for rx offloaded radio.
  1419. */
  1420. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  1421. }
  1422. /*
  1423. * group mask for Rx buffer refill ring
  1424. */
  1425. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  1426. /* loop and reset the mask for only offloaded ring */
  1427. for (j = 0; j < MAX_PDEV_CNT; j++) {
  1428. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  1429. continue;
  1430. }
  1431. /*
  1432. * Group number corresponding to rx offloaded ring.
  1433. */
  1434. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  1435. if (group_number < 0) {
  1436. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1437. FL("ring not part of any group; ring_type: %d,ring_num %d"),
  1438. REO_DST, j);
  1439. return;
  1440. }
  1441. /* set the interrupt mask for offloaded ring */
  1442. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1443. group_number);
  1444. mask &= (~(1 << j));
  1445. /*
  1446. * set the interrupt mask to zero for rx offloaded radio.
  1447. */
  1448. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  1449. group_number, mask);
  1450. }
  1451. }
  1452. #ifdef IPA_OFFLOAD
  1453. /**
  1454. * dp_reo_remap_config() - configure reo remap register value based
  1455. * nss configuration.
  1456. * based on offload_radio value below remap configuration
  1457. * get applied.
  1458. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1459. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1460. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1461. * 3 - both Radios handled by NSS (remap not required)
  1462. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1463. *
  1464. * @remap1: output parameter indicates reo remap 1 register value
  1465. * @remap2: output parameter indicates reo remap 2 register value
  1466. * Return: bool type, true if remap is configured else false.
  1467. */
  1468. static bool dp_reo_remap_config(struct dp_soc *soc,
  1469. uint32_t *remap1,
  1470. uint32_t *remap2)
  1471. {
  1472. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1473. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1474. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1475. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1476. return true;
  1477. }
  1478. #else
  1479. static bool dp_reo_remap_config(struct dp_soc *soc,
  1480. uint32_t *remap1,
  1481. uint32_t *remap2)
  1482. {
  1483. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1484. switch (offload_radio) {
  1485. case 0:
  1486. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1487. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1488. (0x3 << 18) | (0x4 << 21)) << 8;
  1489. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1490. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1491. (0x3 << 18) | (0x4 << 21)) << 8;
  1492. break;
  1493. case 1:
  1494. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1495. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1496. (0x2 << 18) | (0x3 << 21)) << 8;
  1497. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1498. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1499. (0x4 << 18) | (0x2 << 21)) << 8;
  1500. break;
  1501. case 2:
  1502. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1503. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1504. (0x1 << 18) | (0x3 << 21)) << 8;
  1505. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1506. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1507. (0x4 << 18) | (0x1 << 21)) << 8;
  1508. break;
  1509. case 3:
  1510. /* return false if both radios are offloaded to NSS */
  1511. return false;
  1512. }
  1513. return true;
  1514. }
  1515. #endif
  1516. /*
  1517. * dp_soc_cmn_setup() - Common SoC level initializion
  1518. * @soc: Datapath SOC handle
  1519. *
  1520. * This is an internal function used to setup common SOC data structures,
  1521. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1522. */
  1523. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1524. {
  1525. int i;
  1526. struct hal_reo_params reo_params;
  1527. int tx_ring_size;
  1528. int tx_comp_ring_size;
  1529. if (qdf_atomic_read(&soc->cmn_init_done))
  1530. return 0;
  1531. if (dp_peer_find_attach(soc))
  1532. goto fail0;
  1533. if (dp_hw_link_desc_pool_setup(soc))
  1534. goto fail1;
  1535. /* Setup SRNG rings */
  1536. /* Common rings */
  1537. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1538. WBM_RELEASE_RING_SIZE)) {
  1539. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1540. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1541. goto fail1;
  1542. }
  1543. soc->num_tcl_data_rings = 0;
  1544. /* Tx data rings */
  1545. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1546. soc->num_tcl_data_rings =
  1547. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1548. tx_comp_ring_size =
  1549. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1550. tx_ring_size =
  1551. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1552. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1553. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1554. TCL_DATA, i, 0, tx_ring_size)) {
  1555. QDF_TRACE(QDF_MODULE_ID_DP,
  1556. QDF_TRACE_LEVEL_ERROR,
  1557. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1558. goto fail1;
  1559. }
  1560. /*
  1561. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1562. * count
  1563. */
  1564. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1565. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1566. QDF_TRACE(QDF_MODULE_ID_DP,
  1567. QDF_TRACE_LEVEL_ERROR,
  1568. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1569. goto fail1;
  1570. }
  1571. }
  1572. } else {
  1573. /* This will be incremented during per pdev ring setup */
  1574. soc->num_tcl_data_rings = 0;
  1575. }
  1576. if (dp_tx_soc_attach(soc)) {
  1577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1578. FL("dp_tx_soc_attach failed"));
  1579. goto fail1;
  1580. }
  1581. /* TCL command and status rings */
  1582. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1583. TCL_CMD_RING_SIZE)) {
  1584. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1585. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1586. goto fail1;
  1587. }
  1588. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1589. TCL_STATUS_RING_SIZE)) {
  1590. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1591. FL("dp_srng_setup failed for tcl_status_ring"));
  1592. goto fail1;
  1593. }
  1594. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1595. * descriptors
  1596. */
  1597. /* Rx data rings */
  1598. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1599. soc->num_reo_dest_rings =
  1600. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1601. QDF_TRACE(QDF_MODULE_ID_DP,
  1602. QDF_TRACE_LEVEL_ERROR,
  1603. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1604. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1605. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1606. i, 0, REO_DST_RING_SIZE)) {
  1607. QDF_TRACE(QDF_MODULE_ID_DP,
  1608. QDF_TRACE_LEVEL_ERROR,
  1609. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1610. goto fail1;
  1611. }
  1612. }
  1613. } else {
  1614. /* This will be incremented during per pdev ring setup */
  1615. soc->num_reo_dest_rings = 0;
  1616. }
  1617. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1618. /* REO reinjection ring */
  1619. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1620. REO_REINJECT_RING_SIZE)) {
  1621. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1622. FL("dp_srng_setup failed for reo_reinject_ring"));
  1623. goto fail1;
  1624. }
  1625. /* Rx release ring */
  1626. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1627. RX_RELEASE_RING_SIZE)) {
  1628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1629. FL("dp_srng_setup failed for rx_rel_ring"));
  1630. goto fail1;
  1631. }
  1632. /* Rx exception ring */
  1633. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1634. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1636. FL("dp_srng_setup failed for reo_exception_ring"));
  1637. goto fail1;
  1638. }
  1639. /* REO command and status rings */
  1640. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1641. REO_CMD_RING_SIZE)) {
  1642. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1643. FL("dp_srng_setup failed for reo_cmd_ring"));
  1644. goto fail1;
  1645. }
  1646. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1647. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1648. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1649. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1650. REO_STATUS_RING_SIZE)) {
  1651. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1652. FL("dp_srng_setup failed for reo_status_ring"));
  1653. goto fail1;
  1654. }
  1655. qdf_spinlock_create(&soc->ast_lock);
  1656. dp_soc_wds_attach(soc);
  1657. /* Reset the cpu ring map if radio is NSS offloaded */
  1658. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1659. dp_soc_reset_cpu_ring_map(soc);
  1660. dp_soc_reset_intr_mask(soc);
  1661. }
  1662. /* Setup HW REO */
  1663. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1664. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1665. /*
  1666. * Reo ring remap is not required if both radios
  1667. * are offloaded to NSS
  1668. */
  1669. if (!dp_reo_remap_config(soc,
  1670. &reo_params.remap1,
  1671. &reo_params.remap2))
  1672. goto out;
  1673. reo_params.rx_hash_enabled = true;
  1674. }
  1675. out:
  1676. hal_reo_setup(soc->hal_soc, &reo_params);
  1677. qdf_atomic_set(&soc->cmn_init_done, 1);
  1678. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1679. return 0;
  1680. fail1:
  1681. /*
  1682. * Cleanup will be done as part of soc_detach, which will
  1683. * be called on pdev attach failure
  1684. */
  1685. fail0:
  1686. return QDF_STATUS_E_FAILURE;
  1687. }
  1688. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1689. static void dp_lro_hash_setup(struct dp_soc *soc)
  1690. {
  1691. struct cdp_lro_hash_config lro_hash;
  1692. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1693. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1695. FL("LRO disabled RX hash disabled"));
  1696. return;
  1697. }
  1698. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1699. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1700. lro_hash.lro_enable = 1;
  1701. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1702. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1703. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1704. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1705. }
  1706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW, FL("enabled"));
  1707. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1708. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1709. LRO_IPV4_SEED_ARR_SZ));
  1710. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1711. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1712. LRO_IPV6_SEED_ARR_SZ));
  1713. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  1714. "lro_hash: lro_enable: 0x%x tcp_flag 0x%x tcp_flag_mask 0x%x",
  1715. lro_hash.lro_enable, lro_hash.tcp_flag,
  1716. lro_hash.tcp_flag_mask);
  1717. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1718. QDF_TRACE_LEVEL_ERROR,
  1719. (void *)lro_hash.toeplitz_hash_ipv4,
  1720. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1721. LRO_IPV4_SEED_ARR_SZ));
  1722. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1723. QDF_TRACE_LEVEL_ERROR,
  1724. (void *)lro_hash.toeplitz_hash_ipv6,
  1725. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1726. LRO_IPV6_SEED_ARR_SZ));
  1727. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1728. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1729. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1730. (soc->osif_soc, &lro_hash);
  1731. }
  1732. /*
  1733. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1734. * @soc: data path SoC handle
  1735. * @pdev: Physical device handle
  1736. *
  1737. * Return: 0 - success, > 0 - failure
  1738. */
  1739. #ifdef QCA_HOST2FW_RXBUF_RING
  1740. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1741. struct dp_pdev *pdev)
  1742. {
  1743. int max_mac_rings =
  1744. wlan_cfg_get_num_mac_rings
  1745. (pdev->wlan_cfg_ctx);
  1746. int i;
  1747. for (i = 0; i < max_mac_rings; i++) {
  1748. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1749. "%s: pdev_id %d mac_id %d\n",
  1750. __func__, pdev->pdev_id, i);
  1751. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1752. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1753. QDF_TRACE(QDF_MODULE_ID_DP,
  1754. QDF_TRACE_LEVEL_ERROR,
  1755. FL("failed rx mac ring setup"));
  1756. return QDF_STATUS_E_FAILURE;
  1757. }
  1758. }
  1759. return QDF_STATUS_SUCCESS;
  1760. }
  1761. #else
  1762. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1763. struct dp_pdev *pdev)
  1764. {
  1765. return QDF_STATUS_SUCCESS;
  1766. }
  1767. #endif
  1768. /**
  1769. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1770. * @pdev - DP_PDEV handle
  1771. *
  1772. * Return: void
  1773. */
  1774. static inline void
  1775. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1776. {
  1777. uint8_t map_id;
  1778. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1779. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1780. sizeof(default_dscp_tid_map));
  1781. }
  1782. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1783. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1784. pdev->dscp_tid_map[map_id],
  1785. map_id);
  1786. }
  1787. }
  1788. /*
  1789. * dp_pdev_attach_wifi3() - attach txrx pdev
  1790. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1791. * @txrx_soc: Datapath SOC handle
  1792. * @htc_handle: HTC handle for host-target interface
  1793. * @qdf_osdev: QDF OS device
  1794. * @pdev_id: PDEV ID
  1795. *
  1796. * Return: DP PDEV handle on success, NULL on failure
  1797. */
  1798. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1799. struct cdp_cfg *ctrl_pdev,
  1800. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1801. {
  1802. int tx_ring_size;
  1803. int tx_comp_ring_size;
  1804. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1805. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1806. if (!pdev) {
  1807. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1808. FL("DP PDEV memory allocation failed"));
  1809. goto fail0;
  1810. }
  1811. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1812. if (!pdev->wlan_cfg_ctx) {
  1813. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1814. FL("pdev cfg_attach failed"));
  1815. qdf_mem_free(pdev);
  1816. goto fail0;
  1817. }
  1818. /*
  1819. * set nss pdev config based on soc config
  1820. */
  1821. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1822. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1823. pdev->soc = soc;
  1824. pdev->osif_pdev = ctrl_pdev;
  1825. pdev->pdev_id = pdev_id;
  1826. soc->pdev_list[pdev_id] = pdev;
  1827. soc->pdev_count++;
  1828. TAILQ_INIT(&pdev->vdev_list);
  1829. pdev->vdev_count = 0;
  1830. qdf_spinlock_create(&pdev->tx_mutex);
  1831. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1832. TAILQ_INIT(&pdev->neighbour_peers_list);
  1833. if (dp_soc_cmn_setup(soc)) {
  1834. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1835. FL("dp_soc_cmn_setup failed"));
  1836. goto fail1;
  1837. }
  1838. /* Setup per PDEV TCL rings if configured */
  1839. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1840. tx_ring_size =
  1841. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1842. tx_comp_ring_size =
  1843. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1844. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1845. pdev_id, pdev_id, tx_ring_size)) {
  1846. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1847. FL("dp_srng_setup failed for tcl_data_ring"));
  1848. goto fail1;
  1849. }
  1850. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1851. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1852. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1853. FL("dp_srng_setup failed for tx_comp_ring"));
  1854. goto fail1;
  1855. }
  1856. soc->num_tcl_data_rings++;
  1857. }
  1858. /* Tx specific init */
  1859. if (dp_tx_pdev_attach(pdev)) {
  1860. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1861. FL("dp_tx_pdev_attach failed"));
  1862. goto fail1;
  1863. }
  1864. /* Setup per PDEV REO rings if configured */
  1865. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1866. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1867. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1868. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1869. FL("dp_srng_setup failed for reo_dest_ringn"));
  1870. goto fail1;
  1871. }
  1872. soc->num_reo_dest_rings++;
  1873. }
  1874. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1875. RXDMA_REFILL_RING_SIZE)) {
  1876. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1877. FL("dp_srng_setup failed rx refill ring"));
  1878. goto fail1;
  1879. }
  1880. if (dp_rxdma_ring_setup(soc, pdev)) {
  1881. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1882. FL("RXDMA ring config failed"));
  1883. goto fail1;
  1884. }
  1885. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1886. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1887. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1888. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1889. goto fail1;
  1890. }
  1891. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  1892. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  1893. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1894. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1895. goto fail1;
  1896. }
  1897. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  1898. RXDMA_MONITOR_STATUS, 0, pdev_id,
  1899. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  1900. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1901. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  1902. goto fail1;
  1903. }
  1904. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  1905. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  1906. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1907. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  1908. goto fail1;
  1909. }
  1910. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  1911. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  1912. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1913. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  1914. goto fail1;
  1915. }
  1916. /* Setup second Rx refill buffer ring */
  1917. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2,
  1918. pdev->pdev_id, RXDMA_REFILL_RING_SIZE)) {
  1919. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1920. FL("dp_srng_setup failed second rx refill ring"));
  1921. goto fail1;
  1922. }
  1923. if (dp_ipa_ring_resource_setup(soc, pdev))
  1924. goto fail1;
  1925. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  1926. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1927. FL("dp_ipa_uc_attach failed"));
  1928. goto fail1;
  1929. }
  1930. /* Rx specific init */
  1931. if (dp_rx_pdev_attach(pdev)) {
  1932. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1933. FL("dp_rx_pdev_attach failed"));
  1934. goto fail0;
  1935. }
  1936. DP_STATS_INIT(pdev);
  1937. #ifndef CONFIG_WIN
  1938. /* MCL */
  1939. dp_local_peer_id_pool_init(pdev);
  1940. #endif
  1941. dp_dscp_tid_map_setup(pdev);
  1942. /* Rx monitor mode specific init */
  1943. if (dp_rx_pdev_mon_attach(pdev)) {
  1944. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1945. "dp_rx_pdev_attach failed\n");
  1946. goto fail1;
  1947. }
  1948. if (dp_wdi_event_attach(pdev)) {
  1949. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1950. "dp_wdi_evet_attach failed\n");
  1951. goto fail1;
  1952. }
  1953. /* set the reo destination during initialization */
  1954. pdev->reo_dest = pdev->pdev_id + 1;
  1955. return (struct cdp_pdev *)pdev;
  1956. fail1:
  1957. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  1958. fail0:
  1959. return NULL;
  1960. }
  1961. /*
  1962. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  1963. * @soc: data path SoC handle
  1964. * @pdev: Physical device handle
  1965. *
  1966. * Return: void
  1967. */
  1968. #ifdef QCA_HOST2FW_RXBUF_RING
  1969. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1970. struct dp_pdev *pdev)
  1971. {
  1972. int max_mac_rings =
  1973. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  1974. int i;
  1975. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  1976. max_mac_rings : MAX_RX_MAC_RINGS;
  1977. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  1978. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  1979. RXDMA_BUF, 1);
  1980. }
  1981. #else
  1982. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  1983. struct dp_pdev *pdev)
  1984. {
  1985. }
  1986. #endif
  1987. /*
  1988. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  1989. * @pdev: device object
  1990. *
  1991. * Return: void
  1992. */
  1993. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  1994. {
  1995. struct dp_neighbour_peer *peer = NULL;
  1996. struct dp_neighbour_peer *temp_peer = NULL;
  1997. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  1998. neighbour_peer_list_elem, temp_peer) {
  1999. /* delete this peer from the list */
  2000. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2001. peer, neighbour_peer_list_elem);
  2002. qdf_mem_free(peer);
  2003. }
  2004. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2005. }
  2006. /*
  2007. * dp_pdev_detach_wifi3() - detach txrx pdev
  2008. * @txrx_pdev: Datapath PDEV handle
  2009. * @force: Force detach
  2010. *
  2011. */
  2012. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2013. {
  2014. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2015. struct dp_soc *soc = pdev->soc;
  2016. dp_wdi_event_detach(pdev);
  2017. dp_tx_pdev_detach(pdev);
  2018. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2019. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2020. TCL_DATA, pdev->pdev_id);
  2021. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2022. WBM2SW_RELEASE, pdev->pdev_id);
  2023. }
  2024. dp_rx_pdev_detach(pdev);
  2025. dp_rx_pdev_mon_detach(pdev);
  2026. dp_neighbour_peers_detach(pdev);
  2027. qdf_spinlock_destroy(&pdev->tx_mutex);
  2028. dp_ipa_uc_detach(soc, pdev);
  2029. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring2, RXDMA_BUF, 2);
  2030. /* Cleanup per PDEV REO rings if configured */
  2031. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2032. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2033. REO_DST, pdev->pdev_id);
  2034. }
  2035. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2036. dp_rxdma_ring_cleanup(soc, pdev);
  2037. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2038. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2039. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2040. RXDMA_MONITOR_STATUS, 0);
  2041. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2042. RXDMA_MONITOR_DESC, 0);
  2043. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2044. soc->pdev_list[pdev->pdev_id] = NULL;
  2045. soc->pdev_count--;
  2046. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2047. qdf_mem_free(pdev);
  2048. }
  2049. /*
  2050. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2051. * @soc: DP SOC handle
  2052. */
  2053. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2054. {
  2055. struct reo_desc_list_node *desc;
  2056. struct dp_rx_tid *rx_tid;
  2057. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2058. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2059. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2060. rx_tid = &desc->rx_tid;
  2061. qdf_mem_unmap_nbytes_single(soc->osdev,
  2062. rx_tid->hw_qdesc_paddr,
  2063. QDF_DMA_BIDIRECTIONAL,
  2064. rx_tid->hw_qdesc_alloc_size);
  2065. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2066. qdf_mem_free(desc);
  2067. }
  2068. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2069. qdf_list_destroy(&soc->reo_desc_freelist);
  2070. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2071. }
  2072. /*
  2073. * dp_soc_detach_wifi3() - Detach txrx SOC
  2074. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2075. */
  2076. static void dp_soc_detach_wifi3(void *txrx_soc)
  2077. {
  2078. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2079. int i;
  2080. qdf_atomic_set(&soc->cmn_init_done, 0);
  2081. qdf_flush_work(&soc->htt_stats.work);
  2082. qdf_disable_work(&soc->htt_stats.work);
  2083. /* Free pending htt stats messages */
  2084. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2085. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2086. if (soc->pdev_list[i])
  2087. dp_pdev_detach_wifi3(
  2088. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2089. }
  2090. dp_peer_find_detach(soc);
  2091. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2092. * SW descriptors
  2093. */
  2094. /* Free the ring memories */
  2095. /* Common rings */
  2096. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2097. dp_tx_soc_detach(soc);
  2098. /* Tx data rings */
  2099. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2100. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2101. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2102. TCL_DATA, i);
  2103. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2104. WBM2SW_RELEASE, i);
  2105. }
  2106. }
  2107. /* TCL command and status rings */
  2108. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2109. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2110. /* Rx data rings */
  2111. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2112. soc->num_reo_dest_rings =
  2113. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2114. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2115. /* TODO: Get number of rings and ring sizes
  2116. * from wlan_cfg
  2117. */
  2118. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2119. REO_DST, i);
  2120. }
  2121. }
  2122. /* REO reinjection ring */
  2123. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2124. /* Rx release ring */
  2125. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2126. /* Rx exception ring */
  2127. /* TODO: Better to store ring_type and ring_num in
  2128. * dp_srng during setup
  2129. */
  2130. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2131. /* REO command and status rings */
  2132. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2133. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2134. dp_hw_link_desc_pool_cleanup(soc);
  2135. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2136. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2137. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2138. htt_soc_detach(soc->htt_handle);
  2139. dp_reo_cmdlist_destroy(soc);
  2140. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2141. dp_reo_desc_freelist_destroy(soc);
  2142. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2143. dp_soc_wds_detach(soc);
  2144. qdf_spinlock_destroy(&soc->ast_lock);
  2145. qdf_mem_free(soc);
  2146. }
  2147. /*
  2148. * dp_rxdma_ring_config() - configure the RX DMA rings
  2149. *
  2150. * This function is used to configure the MAC rings.
  2151. * On MCL host provides buffers in Host2FW ring
  2152. * FW refills (copies) buffers to the ring and updates
  2153. * ring_idx in register
  2154. *
  2155. * @soc: data path SoC handle
  2156. *
  2157. * Return: void
  2158. */
  2159. #ifdef QCA_HOST2FW_RXBUF_RING
  2160. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2161. {
  2162. int i;
  2163. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2164. struct dp_pdev *pdev = soc->pdev_list[i];
  2165. if (pdev) {
  2166. int mac_id = 0;
  2167. int j;
  2168. bool dbs_enable = 0;
  2169. int max_mac_rings =
  2170. wlan_cfg_get_num_mac_rings
  2171. (pdev->wlan_cfg_ctx);
  2172. htt_srng_setup(soc->htt_handle, 0,
  2173. pdev->rx_refill_buf_ring.hal_srng,
  2174. RXDMA_BUF);
  2175. if (pdev->rx_refill_buf_ring2.hal_srng)
  2176. htt_srng_setup(soc->htt_handle, 0,
  2177. pdev->rx_refill_buf_ring2.hal_srng,
  2178. RXDMA_BUF);
  2179. if (soc->cdp_soc.ol_ops->
  2180. is_hw_dbs_2x2_capable) {
  2181. dbs_enable = soc->cdp_soc.ol_ops->
  2182. is_hw_dbs_2x2_capable(soc->psoc);
  2183. }
  2184. if (dbs_enable) {
  2185. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2186. QDF_TRACE_LEVEL_ERROR,
  2187. FL("DBS enabled max_mac_rings %d\n"),
  2188. max_mac_rings);
  2189. } else {
  2190. max_mac_rings = 1;
  2191. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2192. QDF_TRACE_LEVEL_ERROR,
  2193. FL("DBS disabled, max_mac_rings %d\n"),
  2194. max_mac_rings);
  2195. }
  2196. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2197. FL("pdev_id %d max_mac_rings %d\n"),
  2198. pdev->pdev_id, max_mac_rings);
  2199. for (j = 0; j < max_mac_rings; j++) {
  2200. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2201. QDF_TRACE_LEVEL_ERROR,
  2202. FL("mac_id %d\n"), mac_id);
  2203. htt_srng_setup(soc->htt_handle, mac_id,
  2204. pdev->rx_mac_buf_ring[j]
  2205. .hal_srng,
  2206. RXDMA_BUF);
  2207. mac_id++;
  2208. }
  2209. /* Configure monitor mode rings */
  2210. htt_srng_setup(soc->htt_handle, i,
  2211. pdev->rxdma_mon_buf_ring.hal_srng,
  2212. RXDMA_MONITOR_BUF);
  2213. htt_srng_setup(soc->htt_handle, i,
  2214. pdev->rxdma_mon_dst_ring.hal_srng,
  2215. RXDMA_MONITOR_DST);
  2216. htt_srng_setup(soc->htt_handle, i,
  2217. pdev->rxdma_mon_status_ring.hal_srng,
  2218. RXDMA_MONITOR_STATUS);
  2219. htt_srng_setup(soc->htt_handle, i,
  2220. pdev->rxdma_mon_desc_ring.hal_srng,
  2221. RXDMA_MONITOR_DESC);
  2222. htt_srng_setup(soc->htt_handle, i,
  2223. pdev->rxdma_err_dst_ring.hal_srng,
  2224. RXDMA_DST);
  2225. }
  2226. }
  2227. }
  2228. #else
  2229. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2230. {
  2231. int i;
  2232. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2233. struct dp_pdev *pdev = soc->pdev_list[i];
  2234. if (pdev) {
  2235. htt_srng_setup(soc->htt_handle, i,
  2236. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2237. htt_srng_setup(soc->htt_handle, i,
  2238. pdev->rxdma_mon_buf_ring.hal_srng,
  2239. RXDMA_MONITOR_BUF);
  2240. htt_srng_setup(soc->htt_handle, i,
  2241. pdev->rxdma_mon_dst_ring.hal_srng,
  2242. RXDMA_MONITOR_DST);
  2243. htt_srng_setup(soc->htt_handle, i,
  2244. pdev->rxdma_mon_status_ring.hal_srng,
  2245. RXDMA_MONITOR_STATUS);
  2246. htt_srng_setup(soc->htt_handle, i,
  2247. pdev->rxdma_mon_desc_ring.hal_srng,
  2248. RXDMA_MONITOR_DESC);
  2249. htt_srng_setup(soc->htt_handle, i,
  2250. pdev->rxdma_err_dst_ring.hal_srng,
  2251. RXDMA_DST);
  2252. }
  2253. }
  2254. }
  2255. #endif
  2256. /*
  2257. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2258. * @txrx_soc: Datapath SOC handle
  2259. */
  2260. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2261. {
  2262. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2263. htt_soc_attach_target(soc->htt_handle);
  2264. dp_rxdma_ring_config(soc);
  2265. DP_STATS_INIT(soc);
  2266. /* initialize work queue for stats processing */
  2267. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2268. return 0;
  2269. }
  2270. /*
  2271. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2272. * @txrx_soc: Datapath SOC handle
  2273. */
  2274. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2275. {
  2276. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2277. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2278. }
  2279. /*
  2280. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2281. * @txrx_soc: Datapath SOC handle
  2282. * @nss_cfg: nss config
  2283. */
  2284. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2285. {
  2286. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2287. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2288. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2289. FL("nss-wifi<0> nss config is enabled"));
  2290. }
  2291. /*
  2292. * dp_vdev_attach_wifi3() - attach txrx vdev
  2293. * @txrx_pdev: Datapath PDEV handle
  2294. * @vdev_mac_addr: MAC address of the virtual interface
  2295. * @vdev_id: VDEV Id
  2296. * @wlan_op_mode: VDEV operating mode
  2297. *
  2298. * Return: DP VDEV handle on success, NULL on failure
  2299. */
  2300. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2301. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2302. {
  2303. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2304. struct dp_soc *soc = pdev->soc;
  2305. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2306. int tx_ring_size;
  2307. if (!vdev) {
  2308. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2309. FL("DP VDEV memory allocation failed"));
  2310. goto fail0;
  2311. }
  2312. vdev->pdev = pdev;
  2313. vdev->vdev_id = vdev_id;
  2314. vdev->opmode = op_mode;
  2315. vdev->osdev = soc->osdev;
  2316. vdev->osif_rx = NULL;
  2317. vdev->osif_rsim_rx_decap = NULL;
  2318. vdev->osif_get_key = NULL;
  2319. vdev->osif_rx_mon = NULL;
  2320. vdev->osif_tx_free_ext = NULL;
  2321. vdev->osif_vdev = NULL;
  2322. vdev->delete.pending = 0;
  2323. vdev->safemode = 0;
  2324. vdev->drop_unenc = 1;
  2325. #ifdef notyet
  2326. vdev->filters_num = 0;
  2327. #endif
  2328. qdf_mem_copy(
  2329. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2330. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2331. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2332. vdev->dscp_tid_map_id = 0;
  2333. vdev->mcast_enhancement_en = 0;
  2334. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2335. /* TODO: Initialize default HTT meta data that will be used in
  2336. * TCL descriptors for packets transmitted from this VDEV
  2337. */
  2338. TAILQ_INIT(&vdev->peer_list);
  2339. /* add this vdev into the pdev's list */
  2340. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2341. pdev->vdev_count++;
  2342. dp_tx_vdev_attach(vdev);
  2343. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2344. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2345. goto fail1;
  2346. if ((soc->intr_mode == DP_INTR_POLL) &&
  2347. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2348. if (pdev->vdev_count == 1)
  2349. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2350. }
  2351. dp_lro_hash_setup(soc);
  2352. /* LRO */
  2353. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2354. wlan_op_mode_sta == vdev->opmode)
  2355. vdev->lro_enable = true;
  2356. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2357. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2358. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2359. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2360. DP_STATS_INIT(vdev);
  2361. return (struct cdp_vdev *)vdev;
  2362. fail1:
  2363. dp_tx_vdev_detach(vdev);
  2364. qdf_mem_free(vdev);
  2365. fail0:
  2366. return NULL;
  2367. }
  2368. /**
  2369. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2370. * @vdev: Datapath VDEV handle
  2371. * @osif_vdev: OSIF vdev handle
  2372. * @txrx_ops: Tx and Rx operations
  2373. *
  2374. * Return: DP VDEV handle on success, NULL on failure
  2375. */
  2376. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2377. void *osif_vdev,
  2378. struct ol_txrx_ops *txrx_ops)
  2379. {
  2380. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2381. vdev->osif_vdev = osif_vdev;
  2382. vdev->osif_rx = txrx_ops->rx.rx;
  2383. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2384. vdev->osif_get_key = txrx_ops->get_key;
  2385. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2386. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2387. #ifdef notyet
  2388. #if ATH_SUPPORT_WAPI
  2389. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2390. #endif
  2391. #endif
  2392. #ifdef UMAC_SUPPORT_PROXY_ARP
  2393. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2394. #endif
  2395. vdev->me_convert = txrx_ops->me_convert;
  2396. /* TODO: Enable the following once Tx code is integrated */
  2397. txrx_ops->tx.tx = dp_tx_send;
  2398. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_LOW,
  2399. "DP Vdev Register success");
  2400. }
  2401. /*
  2402. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2403. * @txrx_vdev: Datapath VDEV handle
  2404. * @callback: Callback OL_IF on completion of detach
  2405. * @cb_context: Callback context
  2406. *
  2407. */
  2408. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2409. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2410. {
  2411. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2412. struct dp_pdev *pdev = vdev->pdev;
  2413. struct dp_soc *soc = pdev->soc;
  2414. /* preconditions */
  2415. qdf_assert(vdev);
  2416. /* remove the vdev from its parent pdev's list */
  2417. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2418. /*
  2419. * Use peer_ref_mutex while accessing peer_list, in case
  2420. * a peer is in the process of being removed from the list.
  2421. */
  2422. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2423. /* check that the vdev has no peers allocated */
  2424. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2425. /* debug print - will be removed later */
  2426. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2427. FL("not deleting vdev object %pK (%pM)"
  2428. "until deletion finishes for all its peers"),
  2429. vdev, vdev->mac_addr.raw);
  2430. /* indicate that the vdev needs to be deleted */
  2431. vdev->delete.pending = 1;
  2432. vdev->delete.callback = callback;
  2433. vdev->delete.context = cb_context;
  2434. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2435. return;
  2436. }
  2437. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2438. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2439. vdev->vdev_id);
  2440. dp_tx_vdev_detach(vdev);
  2441. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2442. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2443. qdf_mem_free(vdev);
  2444. if (callback)
  2445. callback(cb_context);
  2446. }
  2447. /*
  2448. * dp_peer_create_wifi3() - attach txrx peer
  2449. * @txrx_vdev: Datapath VDEV handle
  2450. * @peer_mac_addr: Peer MAC address
  2451. *
  2452. * Return: DP peeer handle on success, NULL on failure
  2453. */
  2454. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2455. uint8_t *peer_mac_addr)
  2456. {
  2457. struct dp_peer *peer;
  2458. int i;
  2459. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2460. struct dp_pdev *pdev;
  2461. struct dp_soc *soc;
  2462. /* preconditions */
  2463. qdf_assert(vdev);
  2464. qdf_assert(peer_mac_addr);
  2465. pdev = vdev->pdev;
  2466. soc = pdev->soc;
  2467. #ifdef notyet
  2468. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2469. soc->mempool_ol_ath_peer);
  2470. #else
  2471. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2472. #endif
  2473. if (!peer)
  2474. return NULL; /* failure */
  2475. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2476. TAILQ_INIT(&peer->ast_entry_list);
  2477. /* store provided params */
  2478. peer->vdev = vdev;
  2479. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2480. qdf_spinlock_create(&peer->peer_info_lock);
  2481. qdf_mem_copy(
  2482. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2483. /* TODO: See of rx_opt_proc is really required */
  2484. peer->rx_opt_proc = soc->rx_opt_proc;
  2485. /* initialize the peer_id */
  2486. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2487. peer->peer_ids[i] = HTT_INVALID_PEER;
  2488. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2489. qdf_atomic_init(&peer->ref_cnt);
  2490. /* keep one reference for attach */
  2491. qdf_atomic_inc(&peer->ref_cnt);
  2492. /* add this peer into the vdev's list */
  2493. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2494. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2495. /* TODO: See if hash based search is required */
  2496. dp_peer_find_hash_add(soc, peer);
  2497. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2498. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2499. vdev, peer, peer->mac_addr.raw,
  2500. qdf_atomic_read(&peer->ref_cnt));
  2501. /*
  2502. * For every peer MAp message search and set if bss_peer
  2503. */
  2504. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2505. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2506. "vdev bss_peer!!!!");
  2507. peer->bss_peer = 1;
  2508. vdev->vap_bss_peer = peer;
  2509. }
  2510. #ifndef CONFIG_WIN
  2511. dp_local_peer_id_alloc(pdev, peer);
  2512. #endif
  2513. DP_STATS_INIT(peer);
  2514. return (void *)peer;
  2515. }
  2516. /*
  2517. * dp_peer_setup_wifi3() - initialize the peer
  2518. * @vdev_hdl: virtual device object
  2519. * @peer: Peer object
  2520. *
  2521. * Return: void
  2522. */
  2523. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2524. {
  2525. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2526. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2527. struct dp_pdev *pdev;
  2528. struct dp_soc *soc;
  2529. bool hash_based = 0;
  2530. enum cdp_host_reo_dest_ring reo_dest;
  2531. /* preconditions */
  2532. qdf_assert(vdev);
  2533. qdf_assert(peer);
  2534. pdev = vdev->pdev;
  2535. soc = pdev->soc;
  2536. dp_peer_rx_init(pdev, peer);
  2537. peer->last_assoc_rcvd = 0;
  2538. peer->last_disassoc_rcvd = 0;
  2539. peer->last_deauth_rcvd = 0;
  2540. /*
  2541. * hash based steering is disabled for Radios which are offloaded
  2542. * to NSS
  2543. */
  2544. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2545. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2546. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2547. FL("hash based steering for pdev: %d is %d\n"),
  2548. pdev->pdev_id, hash_based);
  2549. /*
  2550. * Below line of code will ensure the proper reo_dest ring is choosen
  2551. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  2552. */
  2553. reo_dest = pdev->reo_dest;
  2554. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2555. /* TODO: Check the destination ring number to be passed to FW */
  2556. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2557. pdev->osif_pdev, peer->mac_addr.raw,
  2558. peer->vdev->vdev_id, hash_based, reo_dest);
  2559. }
  2560. return;
  2561. }
  2562. /*
  2563. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2564. * @vdev_handle: virtual device object
  2565. * @htt_pkt_type: type of pkt
  2566. *
  2567. * Return: void
  2568. */
  2569. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2570. enum htt_cmn_pkt_type val)
  2571. {
  2572. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2573. vdev->tx_encap_type = val;
  2574. }
  2575. /*
  2576. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2577. * @vdev_handle: virtual device object
  2578. * @htt_pkt_type: type of pkt
  2579. *
  2580. * Return: void
  2581. */
  2582. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2583. enum htt_cmn_pkt_type val)
  2584. {
  2585. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2586. vdev->rx_decap_type = val;
  2587. }
  2588. /*
  2589. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2590. * @pdev_handle: physical device object
  2591. * @val: reo destination ring index (1 - 4)
  2592. *
  2593. * Return: void
  2594. */
  2595. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2596. enum cdp_host_reo_dest_ring val)
  2597. {
  2598. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2599. if (pdev)
  2600. pdev->reo_dest = val;
  2601. }
  2602. /*
  2603. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2604. * @pdev_handle: physical device object
  2605. *
  2606. * Return: reo destination ring index
  2607. */
  2608. static enum cdp_host_reo_dest_ring
  2609. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2610. {
  2611. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2612. if (pdev)
  2613. return pdev->reo_dest;
  2614. else
  2615. return cdp_host_reo_dest_ring_unknown;
  2616. }
  2617. #ifdef QCA_SUPPORT_SON
  2618. static void dp_son_peer_authorize(struct dp_peer *peer)
  2619. {
  2620. struct dp_soc *soc;
  2621. soc = peer->vdev->pdev->soc;
  2622. peer->peer_bs_inact_flag = 0;
  2623. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2624. return;
  2625. }
  2626. #else
  2627. static void dp_son_peer_authorize(struct dp_peer *peer)
  2628. {
  2629. return;
  2630. }
  2631. #endif
  2632. /*
  2633. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2634. * @pdev_handle: device object
  2635. * @val: value to be set
  2636. *
  2637. * Return: void
  2638. */
  2639. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2640. uint32_t val)
  2641. {
  2642. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2643. /* Enable/Disable smart mesh filtering. This flag will be checked
  2644. * during rx processing to check if packets are from NAC clients.
  2645. */
  2646. pdev->filter_neighbour_peers = val;
  2647. return 0;
  2648. }
  2649. /*
  2650. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2651. * address for smart mesh filtering
  2652. * @pdev_handle: device object
  2653. * @cmd: Add/Del command
  2654. * @macaddr: nac client mac address
  2655. *
  2656. * Return: void
  2657. */
  2658. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2659. uint32_t cmd, uint8_t *macaddr)
  2660. {
  2661. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2662. struct dp_neighbour_peer *peer = NULL;
  2663. if (!macaddr)
  2664. goto fail0;
  2665. /* Store address of NAC (neighbour peer) which will be checked
  2666. * against TA of received packets.
  2667. */
  2668. if (cmd == DP_NAC_PARAM_ADD) {
  2669. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2670. sizeof(*peer));
  2671. if (!peer) {
  2672. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2673. FL("DP neighbour peer node memory allocation failed"));
  2674. goto fail0;
  2675. }
  2676. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2677. macaddr, DP_MAC_ADDR_LEN);
  2678. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2679. /* add this neighbour peer into the list */
  2680. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2681. neighbour_peer_list_elem);
  2682. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2683. return 1;
  2684. } else if (cmd == DP_NAC_PARAM_DEL) {
  2685. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2686. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2687. neighbour_peer_list_elem) {
  2688. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2689. macaddr, DP_MAC_ADDR_LEN)) {
  2690. /* delete this peer from the list */
  2691. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2692. peer, neighbour_peer_list_elem);
  2693. qdf_mem_free(peer);
  2694. break;
  2695. }
  2696. }
  2697. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2698. return 1;
  2699. }
  2700. fail0:
  2701. return 0;
  2702. }
  2703. /*
  2704. * dp_get_sec_type() - Get the security type
  2705. * @peer: Datapath peer handle
  2706. * @sec_idx: Security id (mcast, ucast)
  2707. *
  2708. * return sec_type: Security type
  2709. */
  2710. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2711. {
  2712. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2713. return dpeer->security[sec_idx].sec_type;
  2714. }
  2715. /*
  2716. * dp_peer_authorize() - authorize txrx peer
  2717. * @peer_handle: Datapath peer handle
  2718. * @authorize
  2719. *
  2720. */
  2721. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2722. {
  2723. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2724. struct dp_soc *soc;
  2725. if (peer != NULL) {
  2726. soc = peer->vdev->pdev->soc;
  2727. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2728. dp_son_peer_authorize(peer);
  2729. peer->authorize = authorize ? 1 : 0;
  2730. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2731. }
  2732. }
  2733. /*
  2734. * dp_peer_unref_delete() - unref and delete peer
  2735. * @peer_handle: Datapath peer handle
  2736. *
  2737. */
  2738. void dp_peer_unref_delete(void *peer_handle)
  2739. {
  2740. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2741. struct dp_vdev *vdev = peer->vdev;
  2742. struct dp_pdev *pdev = vdev->pdev;
  2743. struct dp_soc *soc = pdev->soc;
  2744. struct dp_peer *tmppeer;
  2745. int found = 0;
  2746. uint16_t peer_id;
  2747. /*
  2748. * Hold the lock all the way from checking if the peer ref count
  2749. * is zero until the peer references are removed from the hash
  2750. * table and vdev list (if the peer ref count is zero).
  2751. * This protects against a new HL tx operation starting to use the
  2752. * peer object just after this function concludes it's done being used.
  2753. * Furthermore, the lock needs to be held while checking whether the
  2754. * vdev's list of peers is empty, to make sure that list is not modified
  2755. * concurrently with the empty check.
  2756. */
  2757. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2758. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2759. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2760. peer, qdf_atomic_read(&peer->ref_cnt));
  2761. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2762. peer_id = peer->peer_ids[0];
  2763. /*
  2764. * Make sure that the reference to the peer in
  2765. * peer object map is removed
  2766. */
  2767. if (peer_id != HTT_INVALID_PEER)
  2768. soc->peer_id_to_obj_map[peer_id] = NULL;
  2769. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2770. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2771. /* remove the reference to the peer from the hash table */
  2772. dp_peer_find_hash_remove(soc, peer);
  2773. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2774. if (tmppeer == peer) {
  2775. found = 1;
  2776. break;
  2777. }
  2778. }
  2779. if (found) {
  2780. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2781. peer_list_elem);
  2782. } else {
  2783. /*Ignoring the remove operation as peer not found*/
  2784. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2785. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2786. peer, vdev, &peer->vdev->peer_list);
  2787. }
  2788. /* cleanup the peer data */
  2789. dp_peer_cleanup(vdev, peer);
  2790. /* check whether the parent vdev has no peers left */
  2791. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2792. /*
  2793. * Now that there are no references to the peer, we can
  2794. * release the peer reference lock.
  2795. */
  2796. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2797. /*
  2798. * Check if the parent vdev was waiting for its peers
  2799. * to be deleted, in order for it to be deleted too.
  2800. */
  2801. if (vdev->delete.pending) {
  2802. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2803. vdev->delete.callback;
  2804. void *vdev_delete_context =
  2805. vdev->delete.context;
  2806. QDF_TRACE(QDF_MODULE_ID_DP,
  2807. QDF_TRACE_LEVEL_INFO_HIGH,
  2808. FL("deleting vdev object %pK (%pM)"
  2809. " - its last peer is done"),
  2810. vdev, vdev->mac_addr.raw);
  2811. /* all peers are gone, go ahead and delete it */
  2812. qdf_mem_free(vdev);
  2813. if (vdev_delete_cb)
  2814. vdev_delete_cb(vdev_delete_context);
  2815. }
  2816. } else {
  2817. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2818. }
  2819. #ifdef notyet
  2820. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2821. #else
  2822. qdf_mem_free(peer);
  2823. #endif
  2824. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2825. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2826. vdev->vdev_id, peer->mac_addr.raw);
  2827. }
  2828. } else {
  2829. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2830. }
  2831. }
  2832. /*
  2833. * dp_peer_detach_wifi3() – Detach txrx peer
  2834. * @peer_handle: Datapath peer handle
  2835. * @bitmap: bitmap indicating special handling of request.
  2836. *
  2837. */
  2838. static void dp_peer_delete_wifi3(void *peer_handle, uint32_t bitmap)
  2839. {
  2840. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2841. /* redirect the peer's rx delivery function to point to a
  2842. * discard func
  2843. */
  2844. peer->rx_opt_proc = dp_rx_discard;
  2845. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2846. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2847. #ifndef CONFIG_WIN
  2848. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2849. #endif
  2850. qdf_spinlock_destroy(&peer->peer_info_lock);
  2851. /*
  2852. * Remove the reference added during peer_attach.
  2853. * The peer will still be left allocated until the
  2854. * PEER_UNMAP message arrives to remove the other
  2855. * reference, added by the PEER_MAP message.
  2856. */
  2857. dp_peer_unref_delete(peer_handle);
  2858. }
  2859. /*
  2860. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2861. * @peer_handle: Datapath peer handle
  2862. *
  2863. */
  2864. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2865. {
  2866. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2867. return vdev->mac_addr.raw;
  2868. }
  2869. /*
  2870. * dp_vdev_set_wds() - Enable per packet stats
  2871. * @vdev_handle: DP VDEV handle
  2872. * @val: value
  2873. *
  2874. * Return: none
  2875. */
  2876. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2877. {
  2878. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2879. vdev->wds_enabled = val;
  2880. return 0;
  2881. }
  2882. /*
  2883. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  2884. * @peer_handle: Datapath peer handle
  2885. *
  2886. */
  2887. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  2888. uint8_t vdev_id)
  2889. {
  2890. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  2891. struct dp_vdev *vdev = NULL;
  2892. if (qdf_unlikely(!pdev))
  2893. return NULL;
  2894. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  2895. if (vdev->vdev_id == vdev_id)
  2896. break;
  2897. }
  2898. return (struct cdp_vdev *)vdev;
  2899. }
  2900. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  2901. {
  2902. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2903. return vdev->opmode;
  2904. }
  2905. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  2906. {
  2907. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2908. struct dp_pdev *pdev = vdev->pdev;
  2909. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  2910. }
  2911. /**
  2912. * dp_reset_monitor_mode() - Disable monitor mode
  2913. * @pdev_handle: Datapath PDEV handle
  2914. *
  2915. * Return: 0 on success, not 0 on failure
  2916. */
  2917. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  2918. {
  2919. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2920. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2921. struct dp_soc *soc;
  2922. uint8_t pdev_id;
  2923. pdev_id = pdev->pdev_id;
  2924. soc = pdev->soc;
  2925. pdev->monitor_vdev = NULL;
  2926. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  2927. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2928. pdev->rxdma_mon_buf_ring.hal_srng,
  2929. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2930. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2931. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  2932. RX_BUFFER_SIZE, &htt_tlv_filter);
  2933. return 0;
  2934. }
  2935. /**
  2936. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  2937. * @vdev_handle: Datapath VDEV handle
  2938. * @smart_monitor: Flag to denote if its smart monitor mode
  2939. *
  2940. * Return: 0 on success, not 0 on failure
  2941. */
  2942. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  2943. uint8_t smart_monitor)
  2944. {
  2945. /* Many monitor VAPs can exists in a system but only one can be up at
  2946. * anytime
  2947. */
  2948. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2949. struct dp_pdev *pdev;
  2950. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  2951. struct dp_soc *soc;
  2952. uint8_t pdev_id;
  2953. qdf_assert(vdev);
  2954. pdev = vdev->pdev;
  2955. pdev_id = pdev->pdev_id;
  2956. soc = pdev->soc;
  2957. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  2958. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  2959. pdev, pdev_id, soc, vdev);
  2960. /*Check if current pdev's monitor_vdev exists */
  2961. if (pdev->monitor_vdev) {
  2962. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2963. "vdev=%pK\n", vdev);
  2964. qdf_assert(vdev);
  2965. }
  2966. pdev->monitor_vdev = vdev;
  2967. /* If smart monitor mode, do not configure monitor ring */
  2968. if (smart_monitor)
  2969. return QDF_STATUS_SUCCESS;
  2970. htt_tlv_filter.mpdu_start = 1;
  2971. htt_tlv_filter.msdu_start = 1;
  2972. htt_tlv_filter.packet = 1;
  2973. htt_tlv_filter.msdu_end = 1;
  2974. htt_tlv_filter.mpdu_end = 1;
  2975. htt_tlv_filter.packet_header = 1;
  2976. htt_tlv_filter.attention = 1;
  2977. htt_tlv_filter.ppdu_start = 0;
  2978. htt_tlv_filter.ppdu_end = 0;
  2979. htt_tlv_filter.ppdu_end_user_stats = 0;
  2980. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  2981. htt_tlv_filter.ppdu_end_status_done = 0;
  2982. htt_tlv_filter.header_per_msdu = 1;
  2983. htt_tlv_filter.enable_fp = 1;
  2984. htt_tlv_filter.enable_md = 0;
  2985. htt_tlv_filter.enable_mo = 1;
  2986. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  2987. pdev->rxdma_mon_buf_ring.hal_srng,
  2988. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  2989. htt_tlv_filter.mpdu_start = 1;
  2990. htt_tlv_filter.msdu_start = 1;
  2991. htt_tlv_filter.packet = 0;
  2992. htt_tlv_filter.msdu_end = 1;
  2993. htt_tlv_filter.mpdu_end = 1;
  2994. htt_tlv_filter.packet_header = 1;
  2995. htt_tlv_filter.attention = 1;
  2996. htt_tlv_filter.ppdu_start = 1;
  2997. htt_tlv_filter.ppdu_end = 1;
  2998. htt_tlv_filter.ppdu_end_user_stats = 1;
  2999. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3000. htt_tlv_filter.ppdu_end_status_done = 1;
  3001. htt_tlv_filter.header_per_msdu = 0;
  3002. htt_tlv_filter.enable_fp = 1;
  3003. htt_tlv_filter.enable_md = 0;
  3004. htt_tlv_filter.enable_mo = 1;
  3005. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3006. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3007. RX_BUFFER_SIZE, &htt_tlv_filter);
  3008. return QDF_STATUS_SUCCESS;
  3009. }
  3010. #ifdef MESH_MODE_SUPPORT
  3011. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3012. {
  3013. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3014. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3015. FL("val %d"), val);
  3016. vdev->mesh_vdev = val;
  3017. }
  3018. /*
  3019. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3020. * @vdev_hdl: virtual device object
  3021. * @val: value to be set
  3022. *
  3023. * Return: void
  3024. */
  3025. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3026. {
  3027. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3028. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3029. FL("val %d"), val);
  3030. vdev->mesh_rx_filter = val;
  3031. }
  3032. #endif
  3033. /*
  3034. * dp_aggregate_pdev_ctrl_frames_stats()- function to agreegate peer stats
  3035. * Current scope is bar recieved count
  3036. *
  3037. * @pdev_handle: DP_PDEV handle
  3038. *
  3039. * Return: void
  3040. */
  3041. #define STATS_PROC_TIMEOUT (HZ/10)
  3042. static void
  3043. dp_aggregate_pdev_ctrl_frames_stats(struct dp_pdev *pdev)
  3044. {
  3045. struct dp_vdev *vdev;
  3046. struct dp_peer *peer;
  3047. uint32_t waitcnt;
  3048. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3049. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3050. if (!peer) {
  3051. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3052. FL("DP Invalid Peer refernce"));
  3053. return;
  3054. }
  3055. waitcnt = 0;
  3056. dp_peer_rxtid_stats(peer, dp_rx_bar_stats_cb, pdev);
  3057. while (!(qdf_atomic_read(&(pdev->stats.cmd_complete)))
  3058. && waitcnt < 10) {
  3059. schedule_timeout_interruptible(
  3060. STATS_PROC_TIMEOUT);
  3061. waitcnt++;
  3062. }
  3063. qdf_atomic_set(&(pdev->stats.cmd_complete), 0);
  3064. }
  3065. }
  3066. }
  3067. /**
  3068. * dp_rx_bar_stats_cb(): BAR received stats callback
  3069. * @soc: SOC handle
  3070. * @cb_ctxt: Call back context
  3071. * @reo_status: Reo status
  3072. *
  3073. * return: void
  3074. */
  3075. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3076. union hal_reo_status *reo_status)
  3077. {
  3078. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3079. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3080. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3081. DP_TRACE_STATS(FATAL, "REO stats failure %d \n",
  3082. queue_status->header.status);
  3083. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3084. return;
  3085. }
  3086. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3087. qdf_atomic_set(&(pdev->stats.cmd_complete), 1);
  3088. }
  3089. /**
  3090. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3091. * @vdev: DP VDEV handle
  3092. *
  3093. * return: void
  3094. */
  3095. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3096. {
  3097. struct dp_peer *peer = NULL;
  3098. struct dp_soc *soc = vdev->pdev->soc;
  3099. int i;
  3100. uint8_t pream_type;
  3101. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3102. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3103. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3104. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3105. for (i = 0; i < MAX_MCS; i++) {
  3106. DP_STATS_AGGR(vdev, peer,
  3107. tx.pkt_type[pream_type].mcs_count[i]);
  3108. DP_STATS_AGGR(vdev, peer,
  3109. rx.pkt_type[pream_type].mcs_count[i]);
  3110. }
  3111. }
  3112. for (i = 0; i < MAX_BW; i++) {
  3113. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3114. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3115. }
  3116. for (i = 0; i < SS_COUNT; i++)
  3117. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3118. for (i = 0; i < WME_AC_MAX; i++) {
  3119. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3120. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3121. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3122. }
  3123. for (i = 0; i < MAX_GI; i++) {
  3124. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3125. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3126. }
  3127. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3128. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3129. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3130. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3131. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3132. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3133. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3134. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3135. DP_STATS_AGGR(vdev, peer, tx.retries);
  3136. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3137. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3138. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3139. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3140. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3141. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3142. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3143. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3144. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3145. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3146. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3147. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3148. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3149. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3150. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3151. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3152. peer->stats.rx.multicast.num;
  3153. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3154. peer->stats.rx.multicast.bytes;
  3155. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3156. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3157. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3158. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3159. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3160. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3161. vdev->stats.tx.last_ack_rssi =
  3162. peer->stats.tx.last_ack_rssi;
  3163. }
  3164. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3165. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3166. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3167. }
  3168. /**
  3169. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3170. * @pdev: DP PDEV handle
  3171. *
  3172. * return: void
  3173. */
  3174. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3175. {
  3176. struct dp_vdev *vdev = NULL;
  3177. uint8_t i;
  3178. uint8_t pream_type;
  3179. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3180. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3181. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3182. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3183. dp_aggregate_vdev_stats(vdev);
  3184. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3185. for (i = 0; i < MAX_MCS; i++) {
  3186. DP_STATS_AGGR(pdev, vdev,
  3187. tx.pkt_type[pream_type].mcs_count[i]);
  3188. DP_STATS_AGGR(pdev, vdev,
  3189. rx.pkt_type[pream_type].mcs_count[i]);
  3190. }
  3191. }
  3192. for (i = 0; i < MAX_BW; i++) {
  3193. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3194. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3195. }
  3196. for (i = 0; i < SS_COUNT; i++)
  3197. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3198. for (i = 0; i < WME_AC_MAX; i++) {
  3199. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3200. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3201. DP_STATS_AGGR(pdev, vdev,
  3202. tx.excess_retries_ac[i]);
  3203. }
  3204. for (i = 0; i < MAX_GI; i++) {
  3205. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3206. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3207. }
  3208. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3209. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3210. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3211. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3212. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3213. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3214. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3215. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3216. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3217. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3218. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3219. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3220. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3221. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3222. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3223. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3224. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3225. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3226. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3227. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3228. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3229. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3230. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3231. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3232. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3233. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3234. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3235. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3236. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3237. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3238. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3239. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3240. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3241. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3242. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3243. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3244. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3245. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3246. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3247. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3248. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3249. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3250. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3251. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3252. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3253. DP_STATS_AGGR(pdev, vdev,
  3254. tx_i.mcast_en.dropped_map_error);
  3255. DP_STATS_AGGR(pdev, vdev,
  3256. tx_i.mcast_en.dropped_self_mac);
  3257. DP_STATS_AGGR(pdev, vdev,
  3258. tx_i.mcast_en.dropped_send_fail);
  3259. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3260. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3261. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3262. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3263. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3264. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3265. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3266. pdev->stats.tx_i.dropped.dma_error +
  3267. pdev->stats.tx_i.dropped.ring_full +
  3268. pdev->stats.tx_i.dropped.enqueue_fail +
  3269. pdev->stats.tx_i.dropped.desc_na +
  3270. pdev->stats.tx_i.dropped.res_full;
  3271. pdev->stats.tx.last_ack_rssi =
  3272. vdev->stats.tx.last_ack_rssi;
  3273. pdev->stats.tx_i.tso.num_seg =
  3274. vdev->stats.tx_i.tso.num_seg;
  3275. }
  3276. }
  3277. /**
  3278. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3279. * @pdev: DP_PDEV Handle
  3280. *
  3281. * Return:void
  3282. */
  3283. static inline void
  3284. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3285. {
  3286. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3287. DP_PRINT_STATS("Received From Stack:");
  3288. DP_PRINT_STATS(" Packets = %d",
  3289. pdev->stats.tx_i.rcvd.num);
  3290. DP_PRINT_STATS(" Bytes = %d",
  3291. pdev->stats.tx_i.rcvd.bytes);
  3292. DP_PRINT_STATS("Processed:");
  3293. DP_PRINT_STATS(" Packets = %d",
  3294. pdev->stats.tx_i.processed.num);
  3295. DP_PRINT_STATS(" Bytes = %d",
  3296. pdev->stats.tx_i.processed.bytes);
  3297. DP_PRINT_STATS("Completions:");
  3298. DP_PRINT_STATS(" Packets = %d",
  3299. pdev->stats.tx.comp_pkt.num);
  3300. DP_PRINT_STATS(" Bytes = %d",
  3301. pdev->stats.tx.comp_pkt.bytes);
  3302. DP_PRINT_STATS("Dropped:");
  3303. DP_PRINT_STATS(" Total = %d",
  3304. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3305. DP_PRINT_STATS(" Dma_map_error = %d",
  3306. pdev->stats.tx_i.dropped.dma_error);
  3307. DP_PRINT_STATS(" Ring Full = %d",
  3308. pdev->stats.tx_i.dropped.ring_full);
  3309. DP_PRINT_STATS(" Descriptor Not available = %d",
  3310. pdev->stats.tx_i.dropped.desc_na);
  3311. DP_PRINT_STATS(" HW enqueue failed= %d",
  3312. pdev->stats.tx_i.dropped.enqueue_fail);
  3313. DP_PRINT_STATS(" Resources Full = %d",
  3314. pdev->stats.tx_i.dropped.res_full);
  3315. DP_PRINT_STATS(" FW removed = %d",
  3316. pdev->stats.tx.dropped.fw_rem);
  3317. DP_PRINT_STATS(" FW removed transmitted = %d",
  3318. pdev->stats.tx.dropped.fw_rem_tx);
  3319. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3320. pdev->stats.tx.dropped.fw_rem_notx);
  3321. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3322. pdev->stats.tx.dropped.age_out);
  3323. DP_PRINT_STATS("Scatter Gather:");
  3324. DP_PRINT_STATS(" Packets = %d",
  3325. pdev->stats.tx_i.sg.sg_pkt.num);
  3326. DP_PRINT_STATS(" Bytes = %d",
  3327. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3328. DP_PRINT_STATS(" Dropped By Host = %d",
  3329. pdev->stats.tx_i.sg.dropped_host);
  3330. DP_PRINT_STATS(" Dropped By Target = %d",
  3331. pdev->stats.tx_i.sg.dropped_target);
  3332. DP_PRINT_STATS("TSO:");
  3333. DP_PRINT_STATS(" Number of Segments = %d",
  3334. pdev->stats.tx_i.tso.num_seg);
  3335. DP_PRINT_STATS(" Packets = %d",
  3336. pdev->stats.tx_i.tso.tso_pkt.num);
  3337. DP_PRINT_STATS(" Bytes = %d",
  3338. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3339. DP_PRINT_STATS(" Dropped By Host = %d",
  3340. pdev->stats.tx_i.tso.dropped_host);
  3341. DP_PRINT_STATS("Mcast Enhancement:");
  3342. DP_PRINT_STATS(" Packets = %d",
  3343. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3344. DP_PRINT_STATS(" Bytes = %d",
  3345. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3346. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3347. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3348. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3349. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3350. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3351. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3352. DP_PRINT_STATS(" Unicast sent = %d",
  3353. pdev->stats.tx_i.mcast_en.ucast);
  3354. DP_PRINT_STATS("Raw:");
  3355. DP_PRINT_STATS(" Packets = %d",
  3356. pdev->stats.tx_i.raw.raw_pkt.num);
  3357. DP_PRINT_STATS(" Bytes = %d",
  3358. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3359. DP_PRINT_STATS(" DMA map error = %d",
  3360. pdev->stats.tx_i.raw.dma_map_error);
  3361. DP_PRINT_STATS("Reinjected:");
  3362. DP_PRINT_STATS(" Packets = %d",
  3363. pdev->stats.tx_i.reinject_pkts.num);
  3364. DP_PRINT_STATS("Bytes = %d\n",
  3365. pdev->stats.tx_i.reinject_pkts.bytes);
  3366. DP_PRINT_STATS("Inspected:");
  3367. DP_PRINT_STATS(" Packets = %d",
  3368. pdev->stats.tx_i.inspect_pkts.num);
  3369. DP_PRINT_STATS(" Bytes = %d",
  3370. pdev->stats.tx_i.inspect_pkts.bytes);
  3371. }
  3372. /**
  3373. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3374. * @pdev: DP_PDEV Handle
  3375. *
  3376. * Return: void
  3377. */
  3378. static inline void
  3379. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3380. {
  3381. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3382. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3383. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3384. pdev->stats.rx.rcvd_reo[0].num,
  3385. pdev->stats.rx.rcvd_reo[1].num,
  3386. pdev->stats.rx.rcvd_reo[2].num,
  3387. pdev->stats.rx.rcvd_reo[3].num);
  3388. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3389. pdev->stats.rx.rcvd_reo[0].bytes,
  3390. pdev->stats.rx.rcvd_reo[1].bytes,
  3391. pdev->stats.rx.rcvd_reo[2].bytes,
  3392. pdev->stats.rx.rcvd_reo[3].bytes);
  3393. DP_PRINT_STATS("Replenished:");
  3394. DP_PRINT_STATS(" Packets = %d",
  3395. pdev->stats.replenish.pkts.num);
  3396. DP_PRINT_STATS(" Bytes = %d",
  3397. pdev->stats.replenish.pkts.bytes);
  3398. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3399. pdev->stats.buf_freelist);
  3400. DP_PRINT_STATS(" Low threshold intr = %d",
  3401. pdev->stats.replenish.low_thresh_intrs);
  3402. DP_PRINT_STATS("Dropped:");
  3403. DP_PRINT_STATS(" msdu_not_done = %d",
  3404. pdev->stats.dropped.msdu_not_done);
  3405. DP_PRINT_STATS("Sent To Stack:");
  3406. DP_PRINT_STATS(" Packets = %d",
  3407. pdev->stats.rx.to_stack.num);
  3408. DP_PRINT_STATS(" Bytes = %d",
  3409. pdev->stats.rx.to_stack.bytes);
  3410. DP_PRINT_STATS("Multicast/Broadcast:");
  3411. DP_PRINT_STATS(" Packets = %d",
  3412. pdev->stats.rx.multicast.num);
  3413. DP_PRINT_STATS(" Bytes = %d",
  3414. pdev->stats.rx.multicast.bytes);
  3415. DP_PRINT_STATS("Errors:");
  3416. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3417. pdev->stats.replenish.rxdma_err);
  3418. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3419. pdev->stats.err.desc_alloc_fail);
  3420. /* Get bar_recv_cnt */
  3421. dp_aggregate_pdev_ctrl_frames_stats(pdev);
  3422. DP_PRINT_STATS("BAR Received Count: = %d",
  3423. pdev->stats.rx.bar_recv_cnt);
  3424. }
  3425. /**
  3426. * dp_print_soc_tx_stats(): Print SOC level stats
  3427. * @soc DP_SOC Handle
  3428. *
  3429. * Return: void
  3430. */
  3431. static inline void
  3432. dp_print_soc_tx_stats(struct dp_soc *soc)
  3433. {
  3434. DP_PRINT_STATS("SOC Tx Stats:\n");
  3435. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3436. soc->stats.tx.desc_in_use);
  3437. DP_PRINT_STATS("Invalid peer:");
  3438. DP_PRINT_STATS(" Packets = %d",
  3439. soc->stats.tx.tx_invalid_peer.num);
  3440. DP_PRINT_STATS(" Bytes = %d",
  3441. soc->stats.tx.tx_invalid_peer.bytes);
  3442. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3443. soc->stats.tx.tcl_ring_full[0],
  3444. soc->stats.tx.tcl_ring_full[1],
  3445. soc->stats.tx.tcl_ring_full[2]);
  3446. }
  3447. /**
  3448. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3449. * @soc: DP_SOC Handle
  3450. *
  3451. * Return:void
  3452. */
  3453. static inline void
  3454. dp_print_soc_rx_stats(struct dp_soc *soc)
  3455. {
  3456. uint32_t i;
  3457. char reo_error[DP_REO_ERR_LENGTH];
  3458. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3459. uint8_t index = 0;
  3460. DP_PRINT_STATS("SOC Rx Stats:\n");
  3461. DP_PRINT_STATS("Errors:\n");
  3462. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3463. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3464. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3465. DP_PRINT_STATS("Invalid RBM = %d",
  3466. soc->stats.rx.err.invalid_rbm);
  3467. DP_PRINT_STATS("Invalid Vdev = %d",
  3468. soc->stats.rx.err.invalid_vdev);
  3469. DP_PRINT_STATS("Invalid Pdev = %d",
  3470. soc->stats.rx.err.invalid_pdev);
  3471. DP_PRINT_STATS("Invalid Peer = %d",
  3472. soc->stats.rx.err.rx_invalid_peer.num);
  3473. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3474. soc->stats.rx.err.hal_ring_access_fail);
  3475. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3476. index += qdf_snprint(&rxdma_error[index],
  3477. DP_RXDMA_ERR_LENGTH - index,
  3478. " %d", soc->stats.rx.err.rxdma_error[i]);
  3479. }
  3480. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3481. rxdma_error);
  3482. index = 0;
  3483. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3484. index += qdf_snprint(&reo_error[index],
  3485. DP_REO_ERR_LENGTH - index,
  3486. " %d", soc->stats.rx.err.reo_error[i]);
  3487. }
  3488. DP_PRINT_STATS("REO Error(0-14):%s",
  3489. reo_error);
  3490. }
  3491. /**
  3492. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3493. * @soc: DP_SOC handle
  3494. * @srng: DP_SRNG handle
  3495. * @ring_name: SRNG name
  3496. *
  3497. * Return: void
  3498. */
  3499. static inline void
  3500. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3501. char *ring_name)
  3502. {
  3503. uint32_t tailp;
  3504. uint32_t headp;
  3505. if (srng->hal_srng != NULL) {
  3506. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3507. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3508. ring_name, headp, tailp);
  3509. }
  3510. }
  3511. /**
  3512. * dp_print_ring_stats(): Print tail and head pointer
  3513. * @pdev: DP_PDEV handle
  3514. *
  3515. * Return:void
  3516. */
  3517. static inline void
  3518. dp_print_ring_stats(struct dp_pdev *pdev)
  3519. {
  3520. uint32_t i;
  3521. char ring_name[STR_MAXLEN + 1];
  3522. dp_print_ring_stat_from_hal(pdev->soc,
  3523. &pdev->soc->reo_exception_ring,
  3524. "Reo Exception Ring");
  3525. dp_print_ring_stat_from_hal(pdev->soc,
  3526. &pdev->soc->reo_reinject_ring,
  3527. "Reo Inject Ring");
  3528. dp_print_ring_stat_from_hal(pdev->soc,
  3529. &pdev->soc->reo_cmd_ring,
  3530. "Reo Command Ring");
  3531. dp_print_ring_stat_from_hal(pdev->soc,
  3532. &pdev->soc->reo_status_ring,
  3533. "Reo Status Ring");
  3534. dp_print_ring_stat_from_hal(pdev->soc,
  3535. &pdev->soc->rx_rel_ring,
  3536. "Rx Release ring");
  3537. dp_print_ring_stat_from_hal(pdev->soc,
  3538. &pdev->soc->tcl_cmd_ring,
  3539. "Tcl command Ring");
  3540. dp_print_ring_stat_from_hal(pdev->soc,
  3541. &pdev->soc->tcl_status_ring,
  3542. "Tcl Status Ring");
  3543. dp_print_ring_stat_from_hal(pdev->soc,
  3544. &pdev->soc->wbm_desc_rel_ring,
  3545. "Wbm Desc Rel Ring");
  3546. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3547. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3548. dp_print_ring_stat_from_hal(pdev->soc,
  3549. &pdev->soc->reo_dest_ring[i],
  3550. ring_name);
  3551. }
  3552. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3553. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3554. dp_print_ring_stat_from_hal(pdev->soc,
  3555. &pdev->soc->tcl_data_ring[i],
  3556. ring_name);
  3557. }
  3558. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3559. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3560. dp_print_ring_stat_from_hal(pdev->soc,
  3561. &pdev->soc->tx_comp_ring[i],
  3562. ring_name);
  3563. }
  3564. dp_print_ring_stat_from_hal(pdev->soc,
  3565. &pdev->rx_refill_buf_ring,
  3566. "Rx Refill Buf Ring");
  3567. dp_print_ring_stat_from_hal(pdev->soc,
  3568. &pdev->rx_refill_buf_ring2,
  3569. "Second Rx Refill Buf Ring");
  3570. dp_print_ring_stat_from_hal(pdev->soc,
  3571. &pdev->rxdma_mon_buf_ring,
  3572. "Rxdma Mon Buf Ring");
  3573. dp_print_ring_stat_from_hal(pdev->soc,
  3574. &pdev->rxdma_mon_dst_ring,
  3575. "Rxdma Mon Dst Ring");
  3576. dp_print_ring_stat_from_hal(pdev->soc,
  3577. &pdev->rxdma_mon_status_ring,
  3578. "Rxdma Mon Status Ring");
  3579. dp_print_ring_stat_from_hal(pdev->soc,
  3580. &pdev->rxdma_mon_desc_ring,
  3581. "Rxdma mon desc Ring");
  3582. dp_print_ring_stat_from_hal(pdev->soc,
  3583. &pdev->rxdma_err_dst_ring,
  3584. "Rxdma err dst ring");
  3585. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3586. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3587. dp_print_ring_stat_from_hal(pdev->soc,
  3588. &pdev->rx_mac_buf_ring[i],
  3589. ring_name);
  3590. }
  3591. }
  3592. /**
  3593. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3594. * @vdev: DP_VDEV handle
  3595. *
  3596. * Return:void
  3597. */
  3598. static inline void
  3599. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3600. {
  3601. struct dp_peer *peer = NULL;
  3602. DP_STATS_CLR(vdev->pdev);
  3603. DP_STATS_CLR(vdev->pdev->soc);
  3604. DP_STATS_CLR(vdev);
  3605. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3606. if (!peer)
  3607. return;
  3608. DP_STATS_CLR(peer);
  3609. }
  3610. }
  3611. /**
  3612. * dp_print_rx_rates(): Print Rx rate stats
  3613. * @vdev: DP_VDEV handle
  3614. *
  3615. * Return:void
  3616. */
  3617. static inline void
  3618. dp_print_rx_rates(struct dp_vdev *vdev)
  3619. {
  3620. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3621. uint8_t i, mcs, pkt_type;
  3622. uint8_t index = 0;
  3623. char nss[DP_NSS_LENGTH];
  3624. DP_PRINT_STATS("Rx Rate Info:\n");
  3625. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3626. index = 0;
  3627. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3628. if (!dp_rate_string[pkt_type][mcs].valid)
  3629. continue;
  3630. DP_PRINT_STATS(" %s = %d",
  3631. dp_rate_string[pkt_type][mcs].mcs_type,
  3632. pdev->stats.rx.pkt_type[pkt_type].
  3633. mcs_count[mcs]);
  3634. }
  3635. DP_PRINT_STATS("\n");
  3636. }
  3637. index = 0;
  3638. for (i = 0; i < SS_COUNT; i++) {
  3639. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3640. " %d", pdev->stats.rx.nss[i]);
  3641. }
  3642. DP_PRINT_STATS("NSS(0-7) = %s",
  3643. nss);
  3644. DP_PRINT_STATS("SGI ="
  3645. " 0.8us %d,"
  3646. " 0.4us %d,"
  3647. " 1.6us %d,"
  3648. " 3.2us %d,",
  3649. pdev->stats.rx.sgi_count[0],
  3650. pdev->stats.rx.sgi_count[1],
  3651. pdev->stats.rx.sgi_count[2],
  3652. pdev->stats.rx.sgi_count[3]);
  3653. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3654. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3655. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3656. DP_PRINT_STATS("Reception Type ="
  3657. " SU: %d,"
  3658. " MU_MIMO:%d,"
  3659. " MU_OFDMA:%d,"
  3660. " MU_OFDMA_MIMO:%d\n",
  3661. pdev->stats.rx.reception_type[0],
  3662. pdev->stats.rx.reception_type[1],
  3663. pdev->stats.rx.reception_type[2],
  3664. pdev->stats.rx.reception_type[3]);
  3665. DP_PRINT_STATS("Aggregation:\n");
  3666. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3667. pdev->stats.rx.ampdu_cnt);
  3668. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3669. pdev->stats.rx.non_ampdu_cnt);
  3670. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3671. pdev->stats.rx.amsdu_cnt);
  3672. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3673. pdev->stats.rx.non_amsdu_cnt);
  3674. }
  3675. /**
  3676. * dp_print_tx_rates(): Print tx rates
  3677. * @vdev: DP_VDEV handle
  3678. *
  3679. * Return:void
  3680. */
  3681. static inline void
  3682. dp_print_tx_rates(struct dp_vdev *vdev)
  3683. {
  3684. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3685. uint8_t mcs, pkt_type;
  3686. uint32_t index;
  3687. DP_PRINT_STATS("Tx Rate Info:\n");
  3688. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3689. index = 0;
  3690. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3691. if (!dp_rate_string[pkt_type][mcs].valid)
  3692. continue;
  3693. DP_PRINT_STATS(" %s = %d",
  3694. dp_rate_string[pkt_type][mcs].mcs_type,
  3695. pdev->stats.tx.pkt_type[pkt_type].
  3696. mcs_count[mcs]);
  3697. }
  3698. DP_PRINT_STATS("\n");
  3699. }
  3700. DP_PRINT_STATS("SGI ="
  3701. " 0.8us %d"
  3702. " 0.4us %d"
  3703. " 1.6us %d"
  3704. " 3.2us %d",
  3705. pdev->stats.tx.sgi_count[0],
  3706. pdev->stats.tx.sgi_count[1],
  3707. pdev->stats.tx.sgi_count[2],
  3708. pdev->stats.tx.sgi_count[3]);
  3709. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3710. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3711. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3712. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3713. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3714. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3715. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3716. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3717. DP_PRINT_STATS("Aggregation:\n");
  3718. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3719. pdev->stats.tx.amsdu_cnt);
  3720. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3721. pdev->stats.tx.non_amsdu_cnt);
  3722. }
  3723. /**
  3724. * dp_print_peer_stats():print peer stats
  3725. * @peer: DP_PEER handle
  3726. *
  3727. * return void
  3728. */
  3729. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3730. {
  3731. uint8_t i, mcs, pkt_type;
  3732. uint32_t index;
  3733. char nss[DP_NSS_LENGTH];
  3734. DP_PRINT_STATS("Node Tx Stats:\n");
  3735. DP_PRINT_STATS("Total Packet Completions = %d",
  3736. peer->stats.tx.comp_pkt.num);
  3737. DP_PRINT_STATS("Total Bytes Completions = %d",
  3738. peer->stats.tx.comp_pkt.bytes);
  3739. DP_PRINT_STATS("Success Packets = %d",
  3740. peer->stats.tx.tx_success.num);
  3741. DP_PRINT_STATS("Success Bytes = %d",
  3742. peer->stats.tx.tx_success.bytes);
  3743. DP_PRINT_STATS("Packets Failed = %d",
  3744. peer->stats.tx.tx_failed);
  3745. DP_PRINT_STATS("Packets In OFDMA = %d",
  3746. peer->stats.tx.ofdma);
  3747. DP_PRINT_STATS("Packets In STBC = %d",
  3748. peer->stats.tx.stbc);
  3749. DP_PRINT_STATS("Packets In LDPC = %d",
  3750. peer->stats.tx.ldpc);
  3751. DP_PRINT_STATS("Packet Retries = %d",
  3752. peer->stats.tx.retries);
  3753. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3754. peer->stats.tx.amsdu_cnt);
  3755. DP_PRINT_STATS("Last Packet RSSI = %d",
  3756. peer->stats.tx.last_ack_rssi);
  3757. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3758. peer->stats.tx.dropped.fw_rem);
  3759. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3760. peer->stats.tx.dropped.fw_rem_tx);
  3761. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3762. peer->stats.tx.dropped.fw_rem_notx);
  3763. DP_PRINT_STATS("Dropped : Age Out = %d",
  3764. peer->stats.tx.dropped.age_out);
  3765. DP_PRINT_STATS("Rate Info:");
  3766. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3767. index = 0;
  3768. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3769. if (!dp_rate_string[pkt_type][mcs].valid)
  3770. continue;
  3771. DP_PRINT_STATS(" %s = %d",
  3772. dp_rate_string[pkt_type][mcs].mcs_type,
  3773. peer->stats.tx.pkt_type[pkt_type].
  3774. mcs_count[mcs]);
  3775. }
  3776. DP_PRINT_STATS("\n");
  3777. }
  3778. DP_PRINT_STATS("SGI = "
  3779. " 0.8us %d"
  3780. " 0.4us %d"
  3781. " 1.6us %d"
  3782. " 3.2us %d",
  3783. peer->stats.tx.sgi_count[0],
  3784. peer->stats.tx.sgi_count[1],
  3785. peer->stats.tx.sgi_count[2],
  3786. peer->stats.tx.sgi_count[3]);
  3787. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3788. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3789. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3790. DP_PRINT_STATS("Aggregation:");
  3791. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3792. peer->stats.tx.amsdu_cnt);
  3793. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3794. peer->stats.tx.non_amsdu_cnt);
  3795. DP_PRINT_STATS("Node Rx Stats:");
  3796. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3797. peer->stats.rx.to_stack.num);
  3798. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3799. peer->stats.rx.to_stack.bytes);
  3800. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3801. DP_PRINT_STATS("Packets Received = %d",
  3802. peer->stats.rx.rcvd_reo[i].num);
  3803. DP_PRINT_STATS("Bytes Received = %d",
  3804. peer->stats.rx.rcvd_reo[i].bytes);
  3805. }
  3806. DP_PRINT_STATS("Multicast Packets Received = %d",
  3807. peer->stats.rx.multicast.num);
  3808. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3809. peer->stats.rx.multicast.bytes);
  3810. DP_PRINT_STATS("WDS Packets Received = %d",
  3811. peer->stats.rx.wds.num);
  3812. DP_PRINT_STATS("WDS Bytes Received = %d",
  3813. peer->stats.rx.wds.bytes);
  3814. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3815. peer->stats.rx.intra_bss.pkts.num);
  3816. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3817. peer->stats.rx.intra_bss.pkts.bytes);
  3818. DP_PRINT_STATS("Raw Packets Received = %d",
  3819. peer->stats.rx.raw.num);
  3820. DP_PRINT_STATS("Raw Bytes Received = %d",
  3821. peer->stats.rx.raw.bytes);
  3822. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3823. peer->stats.rx.err.mic_err);
  3824. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3825. peer->stats.rx.err.decrypt_err);
  3826. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3827. peer->stats.rx.non_ampdu_cnt);
  3828. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3829. peer->stats.rx.ampdu_cnt);
  3830. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3831. peer->stats.rx.non_amsdu_cnt);
  3832. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3833. peer->stats.rx.amsdu_cnt);
  3834. DP_PRINT_STATS("SGI ="
  3835. " 0.8us %d"
  3836. " 0.4us %d"
  3837. " 1.6us %d"
  3838. " 3.2us %d",
  3839. peer->stats.rx.sgi_count[0],
  3840. peer->stats.rx.sgi_count[1],
  3841. peer->stats.rx.sgi_count[2],
  3842. peer->stats.rx.sgi_count[3]);
  3843. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3844. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3845. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3846. DP_PRINT_STATS("Reception Type ="
  3847. " SU %d,"
  3848. " MU_MIMO %d,"
  3849. " MU_OFDMA %d,"
  3850. " MU_OFDMA_MIMO %d",
  3851. peer->stats.rx.reception_type[0],
  3852. peer->stats.rx.reception_type[1],
  3853. peer->stats.rx.reception_type[2],
  3854. peer->stats.rx.reception_type[3]);
  3855. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3856. index = 0;
  3857. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3858. if (!dp_rate_string[pkt_type][mcs].valid)
  3859. continue;
  3860. DP_PRINT_STATS(" %s = %d",
  3861. dp_rate_string[pkt_type][mcs].mcs_type,
  3862. peer->stats.rx.pkt_type[pkt_type].
  3863. mcs_count[mcs]);
  3864. }
  3865. DP_PRINT_STATS("\n");
  3866. }
  3867. index = 0;
  3868. for (i = 0; i < SS_COUNT; i++) {
  3869. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3870. " %d", peer->stats.rx.nss[i]);
  3871. }
  3872. DP_PRINT_STATS("NSS(0-7) = %s",
  3873. nss);
  3874. DP_PRINT_STATS("Aggregation:");
  3875. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3876. peer->stats.rx.ampdu_cnt);
  3877. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3878. peer->stats.rx.non_ampdu_cnt);
  3879. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3880. peer->stats.rx.amsdu_cnt);
  3881. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3882. peer->stats.rx.non_amsdu_cnt);
  3883. }
  3884. /**
  3885. * dp_print_host_stats()- Function to print the stats aggregated at host
  3886. * @vdev_handle: DP_VDEV handle
  3887. * @type: host stats type
  3888. *
  3889. * Available Stat types
  3890. * TXRX_CLEAR_STATS : Clear the stats
  3891. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3892. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3893. * TXRX_TX_HOST_STATS: Print Tx Stats
  3894. * TXRX_RX_HOST_STATS: Print Rx Stats
  3895. * TXRX_AST_STATS: Print AST Stats
  3896. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  3897. *
  3898. * Return: 0 on success, print error message in case of failure
  3899. */
  3900. static int
  3901. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3902. {
  3903. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3904. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3905. dp_aggregate_pdev_stats(pdev);
  3906. switch (type) {
  3907. case TXRX_CLEAR_STATS:
  3908. dp_txrx_host_stats_clr(vdev);
  3909. break;
  3910. case TXRX_RX_RATE_STATS:
  3911. dp_print_rx_rates(vdev);
  3912. break;
  3913. case TXRX_TX_RATE_STATS:
  3914. dp_print_tx_rates(vdev);
  3915. break;
  3916. case TXRX_TX_HOST_STATS:
  3917. dp_print_pdev_tx_stats(pdev);
  3918. dp_print_soc_tx_stats(pdev->soc);
  3919. break;
  3920. case TXRX_RX_HOST_STATS:
  3921. dp_print_pdev_rx_stats(pdev);
  3922. dp_print_soc_rx_stats(pdev->soc);
  3923. break;
  3924. case TXRX_AST_STATS:
  3925. dp_print_ast_stats(pdev->soc);
  3926. break;
  3927. case TXRX_SRNG_PTR_STATS:
  3928. dp_print_ring_stats(pdev);
  3929. break;
  3930. default:
  3931. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3932. break;
  3933. }
  3934. return 0;
  3935. }
  3936. /*
  3937. * dp_get_host_peer_stats()- function to print peer stats
  3938. * @pdev_handle: DP_PDEV handle
  3939. * @mac_addr: mac address of the peer
  3940. *
  3941. * Return: void
  3942. */
  3943. static void
  3944. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3945. {
  3946. struct dp_peer *peer;
  3947. uint8_t local_id;
  3948. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3949. &local_id);
  3950. if (!peer) {
  3951. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3952. "%s: Invalid peer\n", __func__);
  3953. return;
  3954. }
  3955. dp_print_peer_stats(peer);
  3956. dp_peer_rxtid_stats(peer, dp_rx_tid_stats_cb, NULL);
  3957. return;
  3958. }
  3959. /*
  3960. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  3961. * @pdev: DP_PDEV handle
  3962. *
  3963. * Return: void
  3964. */
  3965. static void
  3966. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  3967. {
  3968. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  3969. htt_tlv_filter.mpdu_start = 0;
  3970. htt_tlv_filter.msdu_start = 0;
  3971. htt_tlv_filter.packet = 0;
  3972. htt_tlv_filter.msdu_end = 0;
  3973. htt_tlv_filter.mpdu_end = 0;
  3974. htt_tlv_filter.packet_header = 1;
  3975. htt_tlv_filter.attention = 1;
  3976. htt_tlv_filter.ppdu_start = 1;
  3977. htt_tlv_filter.ppdu_end = 1;
  3978. htt_tlv_filter.ppdu_end_user_stats = 1;
  3979. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3980. htt_tlv_filter.ppdu_end_status_done = 1;
  3981. htt_tlv_filter.enable_fp = 1;
  3982. htt_tlv_filter.enable_md = 0;
  3983. htt_tlv_filter.enable_mo = 0;
  3984. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  3985. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3986. RX_BUFFER_SIZE, &htt_tlv_filter);
  3987. }
  3988. /*
  3989. * dp_config_tx_capture()- API to enable/disable tx capture
  3990. * @pdev_handle: DP_PDEV handle
  3991. * @val: user provided value
  3992. *
  3993. * Return: void
  3994. */
  3995. static void
  3996. dp_config_tx_capture(struct cdp_pdev *pdev_handle, int val)
  3997. {
  3998. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3999. if (val) {
  4000. pdev->tx_sniffer_enable = 1;
  4001. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4002. } else {
  4003. pdev->tx_sniffer_enable = 0;
  4004. if (!pdev->enhanced_stats_en)
  4005. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4006. }
  4007. }
  4008. /*
  4009. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4010. * @pdev_handle: DP_PDEV handle
  4011. *
  4012. * Return: void
  4013. */
  4014. static void
  4015. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4016. {
  4017. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4018. pdev->enhanced_stats_en = 1;
  4019. dp_ppdu_ring_cfg(pdev);
  4020. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4021. }
  4022. /*
  4023. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4024. * @pdev_handle: DP_PDEV handle
  4025. *
  4026. * Return: void
  4027. */
  4028. static void
  4029. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4030. {
  4031. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4032. pdev->enhanced_stats_en = 0;
  4033. if (!pdev->tx_sniffer_enable)
  4034. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4035. }
  4036. /*
  4037. * dp_get_fw_peer_stats()- function to print peer stats
  4038. * @pdev_handle: DP_PDEV handle
  4039. * @mac_addr: mac address of the peer
  4040. * @cap: Type of htt stats requested
  4041. *
  4042. * Currently Supporting only MAC ID based requests Only
  4043. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4044. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4045. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4046. *
  4047. * Return: void
  4048. */
  4049. static void
  4050. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4051. uint32_t cap)
  4052. {
  4053. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4054. uint32_t config_param0 = 0;
  4055. uint32_t config_param1 = 0;
  4056. uint32_t config_param2 = 0;
  4057. uint32_t config_param3 = 0;
  4058. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4059. config_param0 |= (1 << (cap + 1));
  4060. config_param1 = 0x8f;
  4061. config_param2 |= (mac_addr[0] & 0x000000ff);
  4062. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4063. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4064. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4065. config_param3 |= (mac_addr[4] & 0x000000ff);
  4066. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4067. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4068. config_param0, config_param1, config_param2,
  4069. config_param3);
  4070. }
  4071. /*
  4072. * dp_set_pdev_param: function to set parameters in pdev
  4073. * @pdev_handle: DP pdev handle
  4074. * @param: parameter type to be set
  4075. * @val: value of parameter to be set
  4076. *
  4077. * return: void
  4078. */
  4079. static void dp_set_pdev_param(struct cdp_pdev *pdev_handle,
  4080. enum cdp_pdev_param_type param, uint8_t val)
  4081. {
  4082. switch (param) {
  4083. case CDP_CONFIG_TX_CAPTURE:
  4084. dp_config_tx_capture(pdev_handle, val);
  4085. break;
  4086. default:
  4087. break;
  4088. }
  4089. }
  4090. /*
  4091. * dp_set_vdev_param: function to set parameters in vdev
  4092. * @param: parameter type to be set
  4093. * @val: value of parameter to be set
  4094. *
  4095. * return: void
  4096. */
  4097. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4098. enum cdp_vdev_param_type param, uint32_t val)
  4099. {
  4100. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4101. switch (param) {
  4102. case CDP_ENABLE_WDS:
  4103. vdev->wds_enabled = val;
  4104. break;
  4105. case CDP_ENABLE_NAWDS:
  4106. vdev->nawds_enabled = val;
  4107. break;
  4108. case CDP_ENABLE_MCAST_EN:
  4109. vdev->mcast_enhancement_en = val;
  4110. break;
  4111. case CDP_ENABLE_PROXYSTA:
  4112. vdev->proxysta_vdev = val;
  4113. break;
  4114. case CDP_UPDATE_TDLS_FLAGS:
  4115. vdev->tdls_link_connected = val;
  4116. break;
  4117. case CDP_CFG_WDS_AGING_TIMER:
  4118. if (val == 0)
  4119. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4120. else if (val != vdev->wds_aging_timer_val)
  4121. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4122. vdev->wds_aging_timer_val = val;
  4123. break;
  4124. case CDP_ENABLE_AP_BRIDGE:
  4125. if (wlan_op_mode_sta != vdev->opmode)
  4126. vdev->ap_bridge_enabled = val;
  4127. else
  4128. vdev->ap_bridge_enabled = false;
  4129. break;
  4130. default:
  4131. break;
  4132. }
  4133. dp_tx_vdev_update_search_flags(vdev);
  4134. }
  4135. /**
  4136. * dp_peer_set_nawds: set nawds bit in peer
  4137. * @peer_handle: pointer to peer
  4138. * @value: enable/disable nawds
  4139. *
  4140. * return: void
  4141. */
  4142. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4143. {
  4144. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4145. peer->nawds_enabled = value;
  4146. }
  4147. /*
  4148. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4149. * @vdev_handle: DP_VDEV handle
  4150. * @map_id:ID of map that needs to be updated
  4151. *
  4152. * Return: void
  4153. */
  4154. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4155. uint8_t map_id)
  4156. {
  4157. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4158. vdev->dscp_tid_map_id = map_id;
  4159. return;
  4160. }
  4161. /**
  4162. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4163. * @pdev: DP_PDEV handle
  4164. * @map_id: ID of map that needs to be updated
  4165. * @tos: index value in map
  4166. * @tid: tid value passed by the user
  4167. *
  4168. * Return: void
  4169. */
  4170. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4171. uint8_t map_id, uint8_t tos, uint8_t tid)
  4172. {
  4173. uint8_t dscp;
  4174. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4175. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4176. pdev->dscp_tid_map[map_id][dscp] = tid;
  4177. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4178. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4179. map_id, dscp);
  4180. return;
  4181. }
  4182. /**
  4183. * dp_fw_stats_process(): Process TxRX FW stats request
  4184. * @vdev_handle: DP VDEV handle
  4185. * @val: value passed by user
  4186. *
  4187. * return: int
  4188. */
  4189. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4190. {
  4191. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4192. struct dp_pdev *pdev = NULL;
  4193. if (!vdev) {
  4194. DP_TRACE(NONE, "VDEV not found");
  4195. return 1;
  4196. }
  4197. pdev = vdev->pdev;
  4198. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4199. }
  4200. /*
  4201. * dp_txrx_stats() - function to map to firmware and host stats
  4202. * @vdev: virtual handle
  4203. * @stats: type of statistics requested
  4204. *
  4205. * Return: integer
  4206. */
  4207. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4208. {
  4209. int host_stats;
  4210. int fw_stats;
  4211. if (stats >= CDP_TXRX_MAX_STATS)
  4212. return 0;
  4213. /*
  4214. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4215. * has to be updated if new FW HTT stats added
  4216. */
  4217. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4218. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4219. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4220. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4221. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4222. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4223. stats, fw_stats, host_stats);
  4224. if (fw_stats != TXRX_FW_STATS_INVALID)
  4225. return dp_fw_stats_process(vdev, fw_stats);
  4226. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4227. (host_stats <= TXRX_HOST_STATS_MAX))
  4228. return dp_print_host_stats(vdev, host_stats);
  4229. else
  4230. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4231. "Wrong Input for TxRx Stats");
  4232. return 0;
  4233. }
  4234. /*
  4235. * dp_print_napi_stats(): NAPI stats
  4236. * @soc - soc handle
  4237. */
  4238. static void dp_print_napi_stats(struct dp_soc *soc)
  4239. {
  4240. hif_print_napi_stats(soc->hif_handle);
  4241. }
  4242. /*
  4243. * dp_print_per_ring_stats(): Packet count per ring
  4244. * @soc - soc handle
  4245. */
  4246. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4247. {
  4248. uint8_t core, ring;
  4249. uint64_t total_packets;
  4250. DP_TRACE(FATAL, "Reo packets per ring:");
  4251. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4252. total_packets = 0;
  4253. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4254. for (core = 0; core < NR_CPUS; core++) {
  4255. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4256. core, soc->stats.rx.ring_packets[core][ring]);
  4257. total_packets += soc->stats.rx.ring_packets[core][ring];
  4258. }
  4259. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4260. ring, total_packets);
  4261. }
  4262. }
  4263. /*
  4264. * dp_txrx_path_stats() - Function to display dump stats
  4265. * @soc - soc handle
  4266. *
  4267. * return: none
  4268. */
  4269. static void dp_txrx_path_stats(struct dp_soc *soc)
  4270. {
  4271. uint8_t error_code;
  4272. uint8_t loop_pdev;
  4273. struct dp_pdev *pdev;
  4274. uint8_t i;
  4275. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4276. pdev = soc->pdev_list[loop_pdev];
  4277. dp_aggregate_pdev_stats(pdev);
  4278. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4279. "Tx path Statistics:");
  4280. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4281. pdev->stats.tx_i.rcvd.num,
  4282. pdev->stats.tx_i.rcvd.bytes);
  4283. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4284. pdev->stats.tx_i.processed.num,
  4285. pdev->stats.tx_i.processed.bytes);
  4286. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4287. pdev->stats.tx.tx_success.num,
  4288. pdev->stats.tx.tx_success.bytes);
  4289. DP_TRACE(FATAL, "Dropped in host:");
  4290. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4291. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4292. DP_TRACE(FATAL, "Descriptor not available: %u",
  4293. pdev->stats.tx_i.dropped.desc_na);
  4294. DP_TRACE(FATAL, "Ring full: %u",
  4295. pdev->stats.tx_i.dropped.ring_full);
  4296. DP_TRACE(FATAL, "Enqueue fail: %u",
  4297. pdev->stats.tx_i.dropped.enqueue_fail);
  4298. DP_TRACE(FATAL, "DMA Error: %u",
  4299. pdev->stats.tx_i.dropped.dma_error);
  4300. DP_TRACE(FATAL, "Dropped in hardware:");
  4301. DP_TRACE(FATAL, "total packets dropped: %u",
  4302. pdev->stats.tx.tx_failed);
  4303. DP_TRACE(FATAL, "mpdu age out: %u",
  4304. pdev->stats.tx.dropped.age_out);
  4305. DP_TRACE(FATAL, "firmware removed: %u",
  4306. pdev->stats.tx.dropped.fw_rem);
  4307. DP_TRACE(FATAL, "firmware removed tx: %u",
  4308. pdev->stats.tx.dropped.fw_rem_tx);
  4309. DP_TRACE(FATAL, "firmware removed notx %u",
  4310. pdev->stats.tx.dropped.fw_rem_notx);
  4311. DP_TRACE(FATAL, "peer_invalid: %u",
  4312. pdev->soc->stats.tx.tx_invalid_peer.num);
  4313. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4314. DP_TRACE(FATAL, "Single Packet: %u",
  4315. pdev->stats.tx_comp_histogram.pkts_1);
  4316. DP_TRACE(FATAL, "2-20 Packets: %u",
  4317. pdev->stats.tx_comp_histogram.pkts_2_20);
  4318. DP_TRACE(FATAL, "21-40 Packets: %u",
  4319. pdev->stats.tx_comp_histogram.pkts_21_40);
  4320. DP_TRACE(FATAL, "41-60 Packets: %u",
  4321. pdev->stats.tx_comp_histogram.pkts_41_60);
  4322. DP_TRACE(FATAL, "61-80 Packets: %u",
  4323. pdev->stats.tx_comp_histogram.pkts_61_80);
  4324. DP_TRACE(FATAL, "81-100 Packets: %u",
  4325. pdev->stats.tx_comp_histogram.pkts_81_100);
  4326. DP_TRACE(FATAL, "101-200 Packets: %u",
  4327. pdev->stats.tx_comp_histogram.pkts_101_200);
  4328. DP_TRACE(FATAL, " 201+ Packets: %u",
  4329. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4330. DP_TRACE(FATAL, "Rx path statistics");
  4331. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4332. pdev->stats.rx.to_stack.num,
  4333. pdev->stats.rx.to_stack.bytes);
  4334. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4335. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4336. i, pdev->stats.rx.rcvd_reo[i].num,
  4337. pdev->stats.rx.rcvd_reo[i].bytes);
  4338. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4339. pdev->stats.rx.intra_bss.pkts.num,
  4340. pdev->stats.rx.intra_bss.pkts.bytes);
  4341. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4342. pdev->stats.rx.intra_bss.fail.num,
  4343. pdev->stats.rx.intra_bss.fail.bytes);
  4344. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4345. pdev->stats.rx.raw.num,
  4346. pdev->stats.rx.raw.bytes);
  4347. DP_TRACE(FATAL, "dropped: error %u msdus",
  4348. pdev->stats.rx.err.mic_err);
  4349. DP_TRACE(FATAL, "peer invalid %u",
  4350. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4351. DP_TRACE(FATAL, "Reo Statistics");
  4352. DP_TRACE(FATAL, "rbm error: %u msdus",
  4353. pdev->soc->stats.rx.err.invalid_rbm);
  4354. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4355. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4356. DP_TRACE(FATAL, "Reo errors");
  4357. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4358. error_code++) {
  4359. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4360. error_code,
  4361. pdev->soc->stats.rx.err.reo_error[error_code]);
  4362. }
  4363. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4364. error_code++) {
  4365. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4366. error_code,
  4367. pdev->soc->stats.rx.err
  4368. .rxdma_error[error_code]);
  4369. }
  4370. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4371. DP_TRACE(FATAL, "Single Packet: %u",
  4372. pdev->stats.rx_ind_histogram.pkts_1);
  4373. DP_TRACE(FATAL, "2-20 Packets: %u",
  4374. pdev->stats.rx_ind_histogram.pkts_2_20);
  4375. DP_TRACE(FATAL, "21-40 Packets: %u",
  4376. pdev->stats.rx_ind_histogram.pkts_21_40);
  4377. DP_TRACE(FATAL, "41-60 Packets: %u",
  4378. pdev->stats.rx_ind_histogram.pkts_41_60);
  4379. DP_TRACE(FATAL, "61-80 Packets: %u",
  4380. pdev->stats.rx_ind_histogram.pkts_61_80);
  4381. DP_TRACE(FATAL, "81-100 Packets: %u",
  4382. pdev->stats.rx_ind_histogram.pkts_81_100);
  4383. DP_TRACE(FATAL, "101-200 Packets: %u",
  4384. pdev->stats.rx_ind_histogram.pkts_101_200);
  4385. DP_TRACE(FATAL, " 201+ Packets: %u",
  4386. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4387. DP_TRACE_STATS(ERROR, "%s: tso_enable: %u lro_enable: %u rx_hash: %u napi_enable: %u",
  4388. __func__,
  4389. pdev->soc->wlan_cfg_ctx->tso_enabled,
  4390. pdev->soc->wlan_cfg_ctx->lro_enabled,
  4391. pdev->soc->wlan_cfg_ctx->rx_hash,
  4392. pdev->soc->wlan_cfg_ctx->napi_enabled);
  4393. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4394. DP_TRACE_STATS(ERROR, "%s: Tx flow stop queue: %u tx flow start queue offset: %u",
  4395. __func__,
  4396. pdev->soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold,
  4397. pdev->soc->wlan_cfg_ctx->tx_flow_start_queue_offset);
  4398. #endif
  4399. }
  4400. }
  4401. /*
  4402. * dp_txrx_dump_stats() - Dump statistics
  4403. * @value - Statistics option
  4404. */
  4405. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4406. {
  4407. struct dp_soc *soc =
  4408. (struct dp_soc *)psoc;
  4409. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4410. if (!soc) {
  4411. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4412. "%s: soc is NULL", __func__);
  4413. return QDF_STATUS_E_INVAL;
  4414. }
  4415. switch (value) {
  4416. case CDP_TXRX_PATH_STATS:
  4417. dp_txrx_path_stats(soc);
  4418. break;
  4419. case CDP_RX_RING_STATS:
  4420. dp_print_per_ring_stats(soc);
  4421. break;
  4422. case CDP_TXRX_TSO_STATS:
  4423. /* TODO: NOT IMPLEMENTED */
  4424. break;
  4425. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4426. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4427. break;
  4428. case CDP_DP_NAPI_STATS:
  4429. dp_print_napi_stats(soc);
  4430. break;
  4431. case CDP_TXRX_DESC_STATS:
  4432. /* TODO: NOT IMPLEMENTED */
  4433. break;
  4434. default:
  4435. status = QDF_STATUS_E_INVAL;
  4436. break;
  4437. }
  4438. return status;
  4439. }
  4440. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4441. /**
  4442. * dp_update_flow_control_parameters() - API to store datapath
  4443. * config parameters
  4444. * @soc: soc handle
  4445. * @cfg: ini parameter handle
  4446. *
  4447. * Return: void
  4448. */
  4449. static inline
  4450. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4451. struct cdp_config_params *params)
  4452. {
  4453. soc->wlan_cfg_ctx->tx_flow_stop_queue_threshold =
  4454. params->tx_flow_stop_queue_threshold;
  4455. soc->wlan_cfg_ctx->tx_flow_start_queue_offset =
  4456. params->tx_flow_start_queue_offset;
  4457. }
  4458. #else
  4459. static inline
  4460. void dp_update_flow_control_parameters(struct dp_soc *soc,
  4461. struct cdp_config_params *params)
  4462. {
  4463. }
  4464. #endif
  4465. /**
  4466. * dp_update_config_parameters() - API to store datapath
  4467. * config parameters
  4468. * @soc: soc handle
  4469. * @cfg: ini parameter handle
  4470. *
  4471. * Return: status
  4472. */
  4473. static
  4474. QDF_STATUS dp_update_config_parameters(struct cdp_soc *psoc,
  4475. struct cdp_config_params *params)
  4476. {
  4477. struct dp_soc *soc = (struct dp_soc *)psoc;
  4478. if (!(soc)) {
  4479. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4480. "%s: Invalid handle", __func__);
  4481. return QDF_STATUS_E_INVAL;
  4482. }
  4483. soc->wlan_cfg_ctx->tso_enabled = params->tso_enable;
  4484. soc->wlan_cfg_ctx->lro_enabled = params->lro_enable;
  4485. soc->wlan_cfg_ctx->rx_hash = params->flow_steering_enable;
  4486. soc->wlan_cfg_ctx->tcp_udp_checksumoffload =
  4487. params->tcp_udp_checksumoffload;
  4488. soc->wlan_cfg_ctx->napi_enabled = params->napi_enable;
  4489. dp_update_flow_control_parameters(soc, params);
  4490. return QDF_STATUS_SUCCESS;
  4491. }
  4492. static struct cdp_wds_ops dp_ops_wds = {
  4493. .vdev_set_wds = dp_vdev_set_wds,
  4494. };
  4495. /*
  4496. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4497. * @soc - datapath soc handle
  4498. * @peer - datapath peer handle
  4499. *
  4500. * Delete the AST entries belonging to a peer
  4501. */
  4502. #ifdef FEATURE_WDS
  4503. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4504. struct dp_peer *peer)
  4505. {
  4506. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4507. qdf_spin_lock_bh(&soc->ast_lock);
  4508. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4509. if (ast_entry->next_hop) {
  4510. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4511. peer->vdev->pdev->osif_pdev,
  4512. ast_entry->mac_addr.raw);
  4513. }
  4514. dp_peer_del_ast(soc, ast_entry);
  4515. }
  4516. qdf_spin_unlock_bh(&soc->ast_lock);
  4517. }
  4518. #else
  4519. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4520. struct dp_peer *peer)
  4521. {
  4522. }
  4523. #endif
  4524. /*
  4525. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4526. * @vdev_handle - datapath vdev handle
  4527. * @callback - callback function
  4528. * @ctxt: callback context
  4529. *
  4530. */
  4531. static void
  4532. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4533. ol_txrx_data_tx_cb callback, void *ctxt)
  4534. {
  4535. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4536. vdev->tx_non_std_data_callback.func = callback;
  4537. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4538. }
  4539. #ifdef CONFIG_WIN
  4540. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4541. {
  4542. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4543. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4544. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4545. dp_peer_delete_ast_entries(soc, peer);
  4546. }
  4547. #endif
  4548. static struct cdp_cmn_ops dp_ops_cmn = {
  4549. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4550. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4551. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4552. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4553. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4554. .txrx_peer_create = dp_peer_create_wifi3,
  4555. .txrx_peer_setup = dp_peer_setup_wifi3,
  4556. #ifdef CONFIG_WIN
  4557. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4558. #else
  4559. .txrx_peer_teardown = NULL,
  4560. #endif
  4561. .txrx_peer_delete = dp_peer_delete_wifi3,
  4562. .txrx_vdev_register = dp_vdev_register_wifi3,
  4563. .txrx_soc_detach = dp_soc_detach_wifi3,
  4564. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4565. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4566. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4567. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4568. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4569. .delba_process = dp_delba_process_wifi3,
  4570. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4571. .flush_cache_rx_queue = NULL,
  4572. /* TODO: get API's for dscp-tid need to be added*/
  4573. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4574. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4575. .txrx_stats = dp_txrx_stats,
  4576. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4577. .display_stats = dp_txrx_dump_stats,
  4578. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4579. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4580. #ifdef DP_INTR_POLL_BASED
  4581. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4582. #else
  4583. .txrx_intr_attach = dp_soc_interrupt_attach,
  4584. #endif
  4585. .txrx_intr_detach = dp_soc_interrupt_detach,
  4586. .set_pn_check = dp_set_pn_check_wifi3,
  4587. .update_config_parameters = dp_update_config_parameters,
  4588. /* TODO: Add other functions */
  4589. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4590. };
  4591. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4592. .txrx_peer_authorize = dp_peer_authorize,
  4593. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4594. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4595. #ifdef MESH_MODE_SUPPORT
  4596. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4597. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4598. #endif
  4599. .txrx_set_vdev_param = dp_set_vdev_param,
  4600. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4601. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4602. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4603. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4604. .txrx_update_filter_neighbour_peers =
  4605. dp_update_filter_neighbour_peers,
  4606. .txrx_get_sec_type = dp_get_sec_type,
  4607. /* TODO: Add other functions */
  4608. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4609. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4610. .txrx_set_pdev_param = dp_set_pdev_param,
  4611. };
  4612. static struct cdp_me_ops dp_ops_me = {
  4613. #ifdef ATH_SUPPORT_IQUE
  4614. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4615. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4616. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4617. #endif
  4618. };
  4619. static struct cdp_mon_ops dp_ops_mon = {
  4620. .txrx_monitor_set_filter_ucast_data = NULL,
  4621. .txrx_monitor_set_filter_mcast_data = NULL,
  4622. .txrx_monitor_set_filter_non_data = NULL,
  4623. .txrx_monitor_get_filter_ucast_data = NULL,
  4624. .txrx_monitor_get_filter_mcast_data = NULL,
  4625. .txrx_monitor_get_filter_non_data = NULL,
  4626. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4627. };
  4628. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4629. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4630. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4631. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4632. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4633. /* TODO */
  4634. };
  4635. static struct cdp_raw_ops dp_ops_raw = {
  4636. /* TODO */
  4637. };
  4638. #ifdef CONFIG_WIN
  4639. static struct cdp_pflow_ops dp_ops_pflow = {
  4640. /* TODO */
  4641. };
  4642. #endif /* CONFIG_WIN */
  4643. #ifdef FEATURE_RUNTIME_PM
  4644. /**
  4645. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4646. * @opaque_pdev: DP pdev context
  4647. *
  4648. * DP is ready to runtime suspend if there are no pending TX packets.
  4649. *
  4650. * Return: QDF_STATUS
  4651. */
  4652. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4653. {
  4654. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4655. struct dp_soc *soc = pdev->soc;
  4656. /* Call DP TX flow control API to check if there is any
  4657. pending packets */
  4658. if (soc->intr_mode == DP_INTR_POLL)
  4659. qdf_timer_stop(&soc->int_timer);
  4660. return QDF_STATUS_SUCCESS;
  4661. }
  4662. /**
  4663. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4664. * @opaque_pdev: DP pdev context
  4665. *
  4666. * Resume DP for runtime PM.
  4667. *
  4668. * Return: QDF_STATUS
  4669. */
  4670. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4671. {
  4672. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4673. struct dp_soc *soc = pdev->soc;
  4674. void *hal_srng;
  4675. int i;
  4676. if (soc->intr_mode == DP_INTR_POLL)
  4677. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4678. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4679. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4680. if (hal_srng) {
  4681. /* We actually only need to acquire the lock */
  4682. hal_srng_access_start(soc->hal_soc, hal_srng);
  4683. /* Update SRC ring head pointer for HW to send
  4684. all pending packets */
  4685. hal_srng_access_end(soc->hal_soc, hal_srng);
  4686. }
  4687. }
  4688. return QDF_STATUS_SUCCESS;
  4689. }
  4690. #endif /* FEATURE_RUNTIME_PM */
  4691. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4692. {
  4693. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4694. struct dp_soc *soc = pdev->soc;
  4695. if (soc->intr_mode == DP_INTR_POLL)
  4696. qdf_timer_stop(&soc->int_timer);
  4697. return QDF_STATUS_SUCCESS;
  4698. }
  4699. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4700. {
  4701. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4702. struct dp_soc *soc = pdev->soc;
  4703. if (soc->intr_mode == DP_INTR_POLL)
  4704. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4705. return QDF_STATUS_SUCCESS;
  4706. }
  4707. #ifndef CONFIG_WIN
  4708. static struct cdp_misc_ops dp_ops_misc = {
  4709. .tx_non_std = dp_tx_non_std,
  4710. .get_opmode = dp_get_opmode,
  4711. #ifdef FEATURE_RUNTIME_PM
  4712. .runtime_suspend = dp_runtime_suspend,
  4713. .runtime_resume = dp_runtime_resume,
  4714. #endif /* FEATURE_RUNTIME_PM */
  4715. };
  4716. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4717. /* WIFI 3.0 DP implement as required. */
  4718. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4719. .register_pause_cb = dp_txrx_register_pause_cb,
  4720. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4721. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4722. };
  4723. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4724. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4725. };
  4726. #ifdef IPA_OFFLOAD
  4727. static struct cdp_ipa_ops dp_ops_ipa = {
  4728. .ipa_get_resource = dp_ipa_get_resource,
  4729. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4730. .ipa_op_response = dp_ipa_op_response,
  4731. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4732. .ipa_get_stat = dp_ipa_get_stat,
  4733. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4734. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4735. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4736. .ipa_setup = dp_ipa_setup,
  4737. .ipa_cleanup = dp_ipa_cleanup,
  4738. .ipa_setup_iface = dp_ipa_setup_iface,
  4739. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4740. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4741. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4742. .ipa_set_perf_level = dp_ipa_set_perf_level
  4743. };
  4744. #endif
  4745. static struct cdp_bus_ops dp_ops_bus = {
  4746. .bus_suspend = dp_bus_suspend,
  4747. .bus_resume = dp_bus_resume
  4748. };
  4749. static struct cdp_ocb_ops dp_ops_ocb = {
  4750. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4751. };
  4752. static struct cdp_throttle_ops dp_ops_throttle = {
  4753. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4754. };
  4755. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4756. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4757. };
  4758. static struct cdp_cfg_ops dp_ops_cfg = {
  4759. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4760. };
  4761. static struct cdp_peer_ops dp_ops_peer = {
  4762. .register_peer = dp_register_peer,
  4763. .clear_peer = dp_clear_peer,
  4764. .find_peer_by_addr = dp_find_peer_by_addr,
  4765. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4766. .local_peer_id = dp_local_peer_id,
  4767. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4768. .peer_state_update = dp_peer_state_update,
  4769. .get_vdevid = dp_get_vdevid,
  4770. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4771. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4772. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4773. .get_peer_state = dp_get_peer_state,
  4774. .last_assoc_received = dp_get_last_assoc_received,
  4775. .last_disassoc_received = dp_get_last_disassoc_received,
  4776. .last_deauth_received = dp_get_last_deauth_received,
  4777. };
  4778. #endif
  4779. static struct cdp_ops dp_txrx_ops = {
  4780. .cmn_drv_ops = &dp_ops_cmn,
  4781. .ctrl_ops = &dp_ops_ctrl,
  4782. .me_ops = &dp_ops_me,
  4783. .mon_ops = &dp_ops_mon,
  4784. .host_stats_ops = &dp_ops_host_stats,
  4785. .wds_ops = &dp_ops_wds,
  4786. .raw_ops = &dp_ops_raw,
  4787. #ifdef CONFIG_WIN
  4788. .pflow_ops = &dp_ops_pflow,
  4789. #endif /* CONFIG_WIN */
  4790. #ifndef CONFIG_WIN
  4791. .misc_ops = &dp_ops_misc,
  4792. .cfg_ops = &dp_ops_cfg,
  4793. .flowctl_ops = &dp_ops_flowctl,
  4794. .l_flowctl_ops = &dp_ops_l_flowctl,
  4795. #ifdef IPA_OFFLOAD
  4796. .ipa_ops = &dp_ops_ipa,
  4797. #endif
  4798. .bus_ops = &dp_ops_bus,
  4799. .ocb_ops = &dp_ops_ocb,
  4800. .peer_ops = &dp_ops_peer,
  4801. .throttle_ops = &dp_ops_throttle,
  4802. .mob_stats_ops = &dp_ops_mob_stats,
  4803. #endif
  4804. };
  4805. /*
  4806. * dp_soc_set_txrx_ring_map()
  4807. * @dp_soc: DP handler for soc
  4808. *
  4809. * Return: Void
  4810. */
  4811. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4812. {
  4813. uint32_t i;
  4814. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4815. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4816. }
  4817. }
  4818. /*
  4819. * dp_soc_attach_wifi3() - Attach txrx SOC
  4820. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4821. * @htc_handle: Opaque HTC handle
  4822. * @hif_handle: Opaque HIF handle
  4823. * @qdf_osdev: QDF device
  4824. *
  4825. * Return: DP SOC handle on success, NULL on failure
  4826. */
  4827. /*
  4828. * Local prototype added to temporarily address warning caused by
  4829. * -Wmissing-prototypes. A more correct solution, namely to expose
  4830. * a prototype in an appropriate header file, will come later.
  4831. */
  4832. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4833. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4834. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4835. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4836. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4837. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4838. {
  4839. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4840. if (!soc) {
  4841. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4842. FL("DP SOC memory allocation failed"));
  4843. goto fail0;
  4844. }
  4845. soc->cdp_soc.ops = &dp_txrx_ops;
  4846. soc->cdp_soc.ol_ops = ol_ops;
  4847. soc->osif_soc = osif_soc;
  4848. soc->osdev = qdf_osdev;
  4849. soc->hif_handle = hif_handle;
  4850. soc->psoc = psoc;
  4851. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4852. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4853. soc->hal_soc, qdf_osdev);
  4854. if (!soc->htt_handle) {
  4855. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4856. FL("HTT attach failed"));
  4857. goto fail1;
  4858. }
  4859. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4860. if (!soc->wlan_cfg_ctx) {
  4861. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4862. FL("wlan_cfg_soc_attach failed"));
  4863. goto fail2;
  4864. }
  4865. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4866. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4867. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4868. CDP_CFG_MAX_PEER_ID);
  4869. if (ret != -EINVAL) {
  4870. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4871. }
  4872. }
  4873. qdf_spinlock_create(&soc->peer_ref_mutex);
  4874. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4875. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4876. /* fill the tx/rx cpu ring map*/
  4877. dp_soc_set_txrx_ring_map(soc);
  4878. qdf_spinlock_create(&soc->htt_stats.lock);
  4879. /* initialize work queue for stats processing */
  4880. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4881. return (void *)soc;
  4882. fail2:
  4883. htt_soc_detach(soc->htt_handle);
  4884. fail1:
  4885. qdf_mem_free(soc);
  4886. fail0:
  4887. return NULL;
  4888. }
  4889. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4890. /*
  4891. * dp_set_pktlog_wifi3() - attach txrx vdev
  4892. * @pdev: Datapath PDEV handle
  4893. * @event: which event's notifications are being subscribed to
  4894. * @enable: WDI event subscribe or not. (True or False)
  4895. *
  4896. * Return: Success, NULL on failure
  4897. */
  4898. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4899. bool enable)
  4900. {
  4901. struct dp_soc *soc = pdev->soc;
  4902. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4903. if (enable) {
  4904. switch (event) {
  4905. case WDI_EVENT_RX_DESC:
  4906. if (pdev->monitor_vdev) {
  4907. /* Nothing needs to be done if monitor mode is
  4908. * enabled
  4909. */
  4910. return 0;
  4911. }
  4912. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4913. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4914. htt_tlv_filter.mpdu_start = 1;
  4915. htt_tlv_filter.msdu_start = 1;
  4916. htt_tlv_filter.msdu_end = 1;
  4917. htt_tlv_filter.mpdu_end = 1;
  4918. htt_tlv_filter.packet_header = 1;
  4919. htt_tlv_filter.attention = 1;
  4920. htt_tlv_filter.ppdu_start = 1;
  4921. htt_tlv_filter.ppdu_end = 1;
  4922. htt_tlv_filter.ppdu_end_user_stats = 1;
  4923. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4924. htt_tlv_filter.ppdu_end_status_done = 1;
  4925. htt_tlv_filter.enable_fp = 1;
  4926. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4927. pdev->pdev_id,
  4928. pdev->rxdma_mon_status_ring.hal_srng,
  4929. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4930. &htt_tlv_filter);
  4931. }
  4932. break;
  4933. case WDI_EVENT_LITE_RX:
  4934. if (pdev->monitor_vdev) {
  4935. /* Nothing needs to be done if monitor mode is
  4936. * enabled
  4937. */
  4938. return 0;
  4939. }
  4940. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4941. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4942. htt_tlv_filter.ppdu_start = 1;
  4943. htt_tlv_filter.ppdu_end = 1;
  4944. htt_tlv_filter.ppdu_end_user_stats = 1;
  4945. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4946. htt_tlv_filter.ppdu_end_status_done = 1;
  4947. htt_tlv_filter.enable_fp = 1;
  4948. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4949. pdev->pdev_id,
  4950. pdev->rxdma_mon_status_ring.hal_srng,
  4951. RXDMA_MONITOR_STATUS,
  4952. RX_BUFFER_SIZE_PKTLOG_LITE,
  4953. &htt_tlv_filter);
  4954. }
  4955. break;
  4956. case WDI_EVENT_LITE_T2H:
  4957. if (pdev->monitor_vdev) {
  4958. /* Nothing needs to be done if monitor mode is
  4959. * enabled
  4960. */
  4961. return 0;
  4962. }
  4963. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4964. * passing value 0xffff. Once these macros will define in htt
  4965. * header file will use proper macros
  4966. */
  4967. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4968. break;
  4969. default:
  4970. /* Nothing needs to be done for other pktlog types */
  4971. break;
  4972. }
  4973. } else {
  4974. switch (event) {
  4975. case WDI_EVENT_RX_DESC:
  4976. case WDI_EVENT_LITE_RX:
  4977. if (pdev->monitor_vdev) {
  4978. /* Nothing needs to be done if monitor mode is
  4979. * enabled
  4980. */
  4981. return 0;
  4982. }
  4983. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4984. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4985. /* htt_tlv_filter is initialized to 0 */
  4986. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4987. pdev->pdev_id,
  4988. pdev->rxdma_mon_status_ring.hal_srng,
  4989. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4990. &htt_tlv_filter);
  4991. }
  4992. break;
  4993. case WDI_EVENT_LITE_T2H:
  4994. if (pdev->monitor_vdev) {
  4995. /* Nothing needs to be done if monitor mode is
  4996. * enabled
  4997. */
  4998. return 0;
  4999. }
  5000. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  5001. * passing value 0. Once these macros will define in htt
  5002. * header file will use proper macros
  5003. */
  5004. dp_h2t_cfg_stats_msg_send(pdev, 0);
  5005. break;
  5006. default:
  5007. /* Nothing needs to be done for other pktlog types */
  5008. break;
  5009. }
  5010. }
  5011. return 0;
  5012. }
  5013. #endif