hal_rx.h 85 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_RX_H_
  20. #define _HAL_RX_H_
  21. #include <hal_api.h>
  22. #include "hal_rx_hw_defines.h"
  23. #include "hal_hw_headers.h"
  24. /*************************************
  25. * Ring desc offset/shift/masks
  26. *************************************/
  27. #define HAL_INVALID_PPDU_ID 0xFFFFFFFF
  28. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  29. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  30. #define HAL_RX_MASK(block, field) block##_##field##_MASK
  31. #define HAL_RX_TLV_L3_TYPE_INVALID 0xFFFF
  32. #define HAL_RX_GET(_ptr, block, field) \
  33. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  34. HAL_RX_MASK(block, field)) >> \
  35. HAL_RX_LSB(block, field))
  36. #define HAL_RX_GET_64(_ptr, block, field) \
  37. (((*((volatile uint64_t *)(_ptr) + \
  38. (HAL_RX_OFFSET(block, field) >> 3))) & \
  39. HAL_RX_MASK(block, field)) >> \
  40. HAL_RX_LSB(block, field))
  41. #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \
  42. (*(uint32_t *)(((uint8_t *)_ptr) + \
  43. _wrd ## _ ## _field ## _OFFSET) |= \
  44. (((_val) << _wrd ## _ ## _field ## _LSB) & \
  45. _wrd ## _ ## _field ## _MASK))
  46. /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */
  47. #ifndef RX_DATA_BUFFER_SIZE
  48. #define RX_DATA_BUFFER_SIZE 2048
  49. #endif
  50. #ifndef RX_MONITOR_BUFFER_SIZE
  51. #define RX_MONITOR_BUFFER_SIZE 2048
  52. #endif
  53. #define RXDMA_OPTIMIZATION
  54. /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes
  55. * including buffer reservation, buffer alignment and skb shared info size.
  56. */
  57. #define RX_MON_STATUS_BASE_BUF_SIZE 2048
  58. #define RX_MON_STATUS_BUF_ALIGN 128
  59. #define RX_MON_STATUS_BUF_RESERVATION 128
  60. #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \
  61. (RX_MON_STATUS_BUF_RESERVATION + \
  62. RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE))
  63. #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
  64. /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */
  65. #define HAL_RX_NON_QOS_TID 16
  66. enum {
  67. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  68. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  69. HAL_HW_RX_DECAP_FORMAT_ETH2,
  70. HAL_HW_RX_DECAP_FORMAT_8023,
  71. };
  72. /**
  73. * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons
  74. *
  75. * @reo_psh_rsn: REO push reason
  76. * @reo_err_code: REO Error code
  77. * @rxdma_psh_rsn: RXDMA push reason
  78. * @rxdma_err_code: RXDMA Error code
  79. * @reserved_1: Reserved bits
  80. * @wbm_err_src: WBM error source
  81. * @pool_id: pool ID, indicates which rxdma pool
  82. * @reserved_2: Reserved bits
  83. */
  84. struct hal_wbm_err_desc_info {
  85. uint16_t reo_psh_rsn:2,
  86. reo_err_code:5,
  87. rxdma_psh_rsn:2,
  88. rxdma_err_code:5,
  89. reserved_1:2;
  90. uint8_t wbm_err_src:3,
  91. pool_id:2,
  92. msdu_continued:1,
  93. reserved_2:2;
  94. };
  95. /**
  96. * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info
  97. * @first_buffer: First buffer of MSDU
  98. * @last_buffer: Last buffer of MSDU
  99. * @is_decap_raw: Is RAW Frame
  100. * @reserved_1: Reserved
  101. *
  102. * MSDU with continuation:
  103. * -----------------------------------------------------------
  104. * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 |
  105. * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 |
  106. * | is_decap_raw:1/0 | Same as earlier | Same as earlier|
  107. * -----------------------------------------------------------
  108. *
  109. * Single buffer MSDU:
  110. * ------------------
  111. * | first_buffer:1 |
  112. * | last_buffer :1 |
  113. * | is_decap_raw:1/0 |
  114. * ------------------
  115. */
  116. struct hal_rx_mon_dest_buf_info {
  117. uint8_t first_buffer:1,
  118. last_buffer:1,
  119. is_decap_raw:1,
  120. reserved_1:5;
  121. };
  122. /**
  123. * struct hal_rx_msdu_metadata:Structure to hold rx fast path information.
  124. *
  125. * @l3_hdr_pad: l3 header padding
  126. * @reserved: Reserved bits
  127. * @sa_sw_peer_id: sa sw peer id
  128. * @sa_idx: sa index
  129. * @da_idx: da index
  130. */
  131. struct hal_rx_msdu_metadata {
  132. uint32_t l3_hdr_pad:16,
  133. sa_sw_peer_id:16;
  134. uint32_t sa_idx:16,
  135. da_idx:16;
  136. };
  137. struct hal_proto_params {
  138. uint8_t tcp_proto;
  139. uint8_t udp_proto;
  140. uint8_t ipv6_proto;
  141. };
  142. /**
  143. * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason"
  144. *
  145. * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected
  146. * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing
  147. */
  148. enum hal_reo_error_status {
  149. HAL_REO_ERROR_DETECTED = 0,
  150. HAL_REO_ROUTING_INSTRUCTION = 1,
  151. };
  152. /**
  153. * @msdu_flags: [0] first_msdu_in_mpdu
  154. * [1] last_msdu_in_mpdu
  155. * [2] msdu_continuation - MSDU spread across buffers
  156. * [23] sa_is_valid - SA match in peer table
  157. * [24] sa_idx_timeout - Timeout while searching for SA match
  158. * [25] da_is_valid - Used to identtify intra-bss forwarding
  159. * [26] da_is_MCBC
  160. * [27] da_idx_timeout - Timeout while searching for DA match
  161. *
  162. */
  163. struct hal_rx_msdu_desc_info {
  164. uint32_t msdu_flags;
  165. uint16_t msdu_len; /* 14 bits for length */
  166. };
  167. /**
  168. * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO
  169. *
  170. * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU
  171. * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU
  172. * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation
  173. * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST
  174. * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out
  175. * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST
  176. * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address
  177. * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out
  178. * @ HAL_MSDU_F_INTRA_BSS: This is an intrabss packet
  179. */
  180. enum hal_rx_msdu_desc_flags {
  181. HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0),
  182. HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1),
  183. HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2),
  184. HAL_MSDU_F_SA_IS_VALID = (0x1 << 23),
  185. HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24),
  186. HAL_MSDU_F_DA_IS_VALID = (0x1 << 25),
  187. HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26),
  188. HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27),
  189. HAL_MSDU_F_INTRA_BSS = (0x1 << 28),
  190. };
  191. /*
  192. * @msdu_count: no. of msdus in the MPDU
  193. * @mpdu_seq: MPDU sequence number
  194. * @mpdu_flags [0] Fragment flag
  195. * [1] MPDU_retry_bit
  196. * [2] AMPDU flag
  197. * [3] raw_ampdu
  198. * @peer_meta_data: Upper bits containing peer id, vdev id
  199. * @bar_frame: indicates if received frame is a bar frame
  200. * @tid: tid value of received MPDU
  201. */
  202. struct hal_rx_mpdu_desc_info {
  203. uint16_t msdu_count;
  204. uint16_t mpdu_seq; /* 12 bits for length */
  205. uint32_t mpdu_flags;
  206. uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */
  207. uint16_t bar_frame;
  208. uint8_t tid:4,
  209. reserved:4;
  210. };
  211. /**
  212. * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO
  213. *
  214. * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation)
  215. * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU
  216. * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU
  217. * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU
  218. * @ HAL_MPDU_F_QOS_CONTROL_VALID: MPDU has a QoS control field
  219. */
  220. enum hal_rx_mpdu_desc_flags {
  221. HAL_MPDU_F_FRAGMENT = (0x1 << 20),
  222. HAL_MPDU_F_RETRY_BIT = (0x1 << 21),
  223. HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22),
  224. HAL_MPDU_F_RAW_AMPDU = (0x1 << 30),
  225. HAL_MPDU_F_QOS_CONTROL_VALID = (0x1 << 31)
  226. };
  227. /* Return Buffer manager ID */
  228. #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0
  229. #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1
  230. #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2
  231. #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3
  232. #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id)
  233. #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1)
  234. #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2)
  235. #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3)
  236. #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4)
  237. #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5)
  238. #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6)
  239. #define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id)
  240. #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8
  241. #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0
  242. #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff
  243. #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \
  244. (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \
  245. HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \
  246. HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \
  247. HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB))
  248. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0
  249. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  250. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  251. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4
  252. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  253. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  254. /*
  255. * macro to set the LSW of the nbuf data physical address
  256. * to the rxdma ring entry
  257. */
  258. #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \
  259. ((*(((unsigned int *) buff_addr_info) + \
  260. (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
  261. (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \
  262. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK)
  263. /*
  264. * macro to set the LSB of MSW of the nbuf data physical address
  265. * to the rxdma ring entry
  266. */
  267. #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \
  268. ((*(((unsigned int *) buff_addr_info) + \
  269. (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
  270. (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \
  271. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK)
  272. #ifdef DP_RX_DESC_COOKIE_INVALIDATE
  273. #define HAL_RX_COOKIE_INVALID_MASK 0x80000000
  274. /*
  275. * macro to get the invalid bit for sw cookie
  276. */
  277. #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \
  278. ((*(((unsigned int *)buff_addr_info) + \
  279. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  280. HAL_RX_COOKIE_INVALID_MASK)
  281. /*
  282. * macro to set the invalid bit for sw cookie
  283. */
  284. #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \
  285. ((*(((unsigned int *)buff_addr_info) + \
  286. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  287. HAL_RX_COOKIE_INVALID_MASK)
  288. /*
  289. * macro to reset the invalid bit for sw cookie
  290. */
  291. #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \
  292. ((*(((unsigned int *)buff_addr_info) + \
  293. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  294. ~HAL_RX_COOKIE_INVALID_MASK)
  295. #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \
  296. (HAL_RX_BUF_COOKIE_INVALID_GET(& \
  297. (((struct reo_destination_ring *) \
  298. reo_desc)->buf_or_link_desc_addr_info)))
  299. #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \
  300. (HAL_RX_BUF_COOKIE_INVALID_SET(& \
  301. (((struct reo_destination_ring *) \
  302. reo_desc)->buf_or_link_desc_addr_info)))
  303. #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000
  304. #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \
  305. ((*(((unsigned int *)buff_addr_info) + \
  306. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  307. HAL_RX_LINK_COOKIE_INVALID_MASK)
  308. #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \
  309. ((*(((unsigned int *)buff_addr_info) + \
  310. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  311. HAL_RX_LINK_COOKIE_INVALID_MASK)
  312. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \
  313. (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \
  314. (((struct reo_destination_ring *) \
  315. reo_desc)->buf_or_link_desc_addr_info)))
  316. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \
  317. (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \
  318. (((struct reo_destination_ring *) \
  319. reo_desc)->buf_or_link_desc_addr_info)))
  320. #endif
  321. /* TODO: Convert the following structure fields accesseses to offsets */
  322. #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \
  323. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  324. (((struct reo_destination_ring *) \
  325. reo_desc)->buf_or_link_desc_addr_info)))
  326. #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \
  327. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  328. (((struct reo_destination_ring *) \
  329. reo_desc)->buf_or_link_desc_addr_info)))
  330. #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \
  331. (HAL_RX_BUF_COOKIE_INVALID_RESET(& \
  332. (((struct reo_destination_ring *) \
  333. reo_desc)->buf_or_link_desc_addr_info)))
  334. #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \
  335. HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \
  336. _field, _val)
  337. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0
  338. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  339. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  340. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  341. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  342. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \
  343. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \
  344. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB))
  345. #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \
  346. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  347. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \
  348. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \
  349. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB))
  350. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0
  351. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
  352. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
  353. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0
  354. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1
  355. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
  356. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  357. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  358. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \
  359. (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \
  360. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  361. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  362. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  363. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \
  364. (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \
  365. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK)
  366. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  367. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  368. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  369. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  370. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  371. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  372. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  373. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK)
  374. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0
  375. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3
  376. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8
  377. #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \
  378. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  379. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \
  380. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \
  381. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB))
  382. static inline uint32_t
  383. hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl,
  384. rx_msdu_desc_info_t msdu_desc_info_hdl)
  385. {
  386. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  387. return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl);
  388. }
  389. /*
  390. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  391. * pre-header.
  392. */
  393. static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl,
  394. void *hw_desc_addr)
  395. {
  396. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  397. return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr);
  398. }
  399. /**
  400. * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params
  401. * @hal_soc_hdl: hal soc handle
  402. * @desc_addr: ring descriptor
  403. * @mpdu_desc_info: Buffer to fill the mpdu desc info params
  404. *
  405. * Return: None
  406. */
  407. static inline void
  408. hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr,
  409. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  410. {
  411. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  412. return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr,
  413. mpdu_desc_info);
  414. }
  415. #define HAL_RX_NUM_MSDU_DESC 6
  416. #define HAL_RX_MAX_SAVED_RING_DESC 16
  417. /* TODO: rework the structure */
  418. struct hal_rx_msdu_list {
  419. struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
  420. uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC];
  421. uint8_t rbm[HAL_RX_NUM_MSDU_DESC];
  422. /* physical address of the msdu */
  423. uint64_t paddr[HAL_RX_NUM_MSDU_DESC];
  424. };
  425. struct hal_buf_info {
  426. uint64_t paddr;
  427. uint32_t sw_cookie;
  428. uint8_t rbm;
  429. };
  430. /* This special cookie value will be used to indicate FW allocated buffers
  431. * received through RXDMA2SW ring for RXDMA WARs
  432. */
  433. #define HAL_RX_COOKIE_SPECIAL 0x1fffff
  434. /**
  435. * enum hal_reo_error_code: Indicates that type of buffer or descriptor
  436. *
  437. * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer
  438. * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link
  439. * descriptor
  440. */
  441. enum hal_rx_reo_buf_type {
  442. HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0,
  443. HAL_RX_REO_MSDU_LINK_DESC_TYPE,
  444. };
  445. /**
  446. * enum hal_reo_error_code: Error code describing the type of error detected
  447. *
  448. * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the
  449. * REO_ENTRANCE ring is set to 0
  450. * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set
  451. * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session
  452. * having been setup
  453. * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN,
  454. * Retry bit set: duplicate frame
  455. * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame
  456. * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame)
  457. * received with 2K jump in SN
  458. * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN
  459. * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received
  460. * with SN falling within the OOR window
  461. * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the
  462. * OOR window
  463. * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session
  464. * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN
  465. * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet
  466. * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  467. * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor
  468. * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  469. * of the pn_error_detected_flag been set in the REO Queue descriptor
  470. * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of
  471. * the queue descriptor(address) being blocked as SW/FW seems to be currently
  472. * in the process of making updates to this descriptor
  473. */
  474. enum hal_reo_error_code {
  475. HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0,
  476. HAL_REO_ERR_QUEUE_DESC_INVALID,
  477. HAL_REO_ERR_AMPDU_IN_NON_BA,
  478. HAL_REO_ERR_NON_BA_DUPLICATE,
  479. HAL_REO_ERR_BA_DUPLICATE,
  480. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP,
  481. HAL_REO_ERR_BAR_FRAME_2K_JUMP,
  482. HAL_REO_ERR_REGULAR_FRAME_OOR,
  483. HAL_REO_ERR_BAR_FRAME_OOR,
  484. HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION,
  485. HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN,
  486. HAL_REO_ERR_PN_CHECK_FAILED,
  487. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET,
  488. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET,
  489. HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET,
  490. HAL_REO_ERR_MAX
  491. };
  492. /**
  493. * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected
  494. *
  495. * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow
  496. * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO
  497. * overflow
  498. * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving
  499. * incomplete
  500. * MPDU from the PHY
  501. * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed
  502. * @ HAL_RXDMA_ERR_DECRYPT : Decryption error
  503. * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error
  504. * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be
  505. * encrypted but wasn’t
  506. * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error
  507. * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded
  508. * the max allowed
  509. * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error
  510. * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error
  511. * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout
  512. * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout
  513. * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout
  514. * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request
  515. * @ HAL_RXDMA_AMSDU_FRAGMENT : Rx PCU reported A-MSDU
  516. * present as well as a fragmented MPDU
  517. * @ HAL_RXDMA_MULTICAST_ECHO : RX OLE reported a multicast echo
  518. * @ HAL_RXDMA_AMSDU_ADDR_MISMATCH : RX OLE reported AMSDU address mismatch
  519. * @ HAL_RXDMA_UNAUTHORIZED_WDS : RX PCU reported unauthorized wds
  520. * @ HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS :RX PCU reported group cast AMSDU or WDS
  521. * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors
  522. */
  523. enum hal_rxdma_error_code {
  524. HAL_RXDMA_ERR_OVERFLOW = 0,
  525. HAL_RXDMA_ERR_MPDU_LENGTH,
  526. HAL_RXDMA_ERR_FCS,
  527. HAL_RXDMA_ERR_DECRYPT,
  528. HAL_RXDMA_ERR_TKIP_MIC,
  529. HAL_RXDMA_ERR_UNENCRYPTED,
  530. HAL_RXDMA_ERR_MSDU_LEN,
  531. HAL_RXDMA_ERR_MSDU_LIMIT,
  532. HAL_RXDMA_ERR_WIFI_PARSE,
  533. HAL_RXDMA_ERR_AMSDU_PARSE,
  534. HAL_RXDMA_ERR_SA_TIMEOUT,
  535. HAL_RXDMA_ERR_DA_TIMEOUT,
  536. HAL_RXDMA_ERR_FLOW_TIMEOUT,
  537. HAL_RXDMA_ERR_FLUSH_REQUEST,
  538. HAL_RXDMA_AMSDU_FRAGMENT,
  539. HAL_RXDMA_MULTICAST_ECHO,
  540. HAL_RXDMA_AMSDU_ADDR_MISMATCH,
  541. HAL_RXDMA_UNAUTHORIZED_WDS,
  542. HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS,
  543. HAL_RXDMA_ERR_WAR = 31,
  544. HAL_RXDMA_ERR_MAX
  545. };
  546. /**
  547. * HW BM action settings in WBM release ring
  548. */
  549. #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0
  550. #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1
  551. /**
  552. * enum hal_rx_wbm_error_source: Indicates which module initiated the
  553. * release of this buffer or descriptor
  554. *
  555. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  556. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  557. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  558. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  559. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  560. */
  561. enum hal_rx_wbm_error_source {
  562. HAL_RX_WBM_ERR_SRC_TQM = 0,
  563. HAL_RX_WBM_ERR_SRC_RXDMA,
  564. HAL_RX_WBM_ERR_SRC_REO,
  565. HAL_RX_WBM_ERR_SRC_FW,
  566. HAL_RX_WBM_ERR_SRC_SW,
  567. };
  568. /**
  569. * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor
  570. * released
  571. *
  572. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  573. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  574. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  575. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  576. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  577. */
  578. enum hal_rx_wbm_buf_type {
  579. HAL_RX_WBM_BUF_TYPE_REL_BUF = 0,
  580. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC,
  581. HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC,
  582. HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC,
  583. HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC,
  584. };
  585. #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
  586. //#include "hal_rx_be.h"
  587. /*
  588. * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address
  589. *
  590. * @nbuf: Network buffer
  591. * Returns: flag to indicate whether the nbuf has MC/BC address
  592. */
  593. static inline uint32_t
  594. hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl,
  595. qdf_nbuf_t nbuf)
  596. {
  597. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  598. return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf);
  599. }
  600. /**
  601. * hal_rx_priv_info_set_in_tlv(): Save the private info to
  602. * the reserved bytes of rx_tlv_hdr
  603. * @buf: start of rx_tlv_hdr
  604. * @wbm_er_info: hal_wbm_err_desc_info structure
  605. * Return: void
  606. */
  607. static inline void
  608. hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl,
  609. uint8_t *buf, uint8_t *priv_data,
  610. uint32_t len)
  611. {
  612. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  613. return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf,
  614. priv_data,
  615. len);
  616. }
  617. /*
  618. * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from
  619. * reo_entrance_ring descriptor
  620. *
  621. * @reo_ent_desc: reo_entrance_ring descriptor
  622. * Returns: value of rxdma_push_reason
  623. */
  624. static inline
  625. uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc)
  626. {
  627. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  628. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)),
  629. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK,
  630. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB);
  631. }
  632. /**
  633. * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from
  634. * reo_entrance_ring descriptor
  635. * @reo_ent_desc: reo_entrance_ring descriptor
  636. * Return: value of rxdma_error_code
  637. */
  638. static inline
  639. uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc)
  640. {
  641. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  642. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)),
  643. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK,
  644. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB);
  645. }
  646. /**
  647. * hal_rx_priv_info_get_from_tlv(): retrieve the private data from
  648. * the reserved bytes of rx_tlv_hdr.
  649. * @buf: start of rx_tlv_hdr
  650. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  651. * Return: void
  652. */
  653. static inline void
  654. hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl,
  655. uint8_t *buf, uint8_t *wbm_er_info,
  656. uint32_t len)
  657. {
  658. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  659. return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf,
  660. wbm_er_info,
  661. len);
  662. }
  663. static inline void
  664. hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size,
  665. uint16_t *rx_mon_pkt_tlv_size)
  666. {
  667. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  668. return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size,
  669. rx_mon_pkt_tlv_size);
  670. }
  671. /*
  672. * hal_rx_encryption_info_valid(): Returns encryption type.
  673. *
  674. * @hal_soc_hdl: hal soc handle
  675. * @buf: rx_tlv_hdr of the received packet
  676. *
  677. * Return: encryption type
  678. */
  679. static inline uint32_t
  680. hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  681. {
  682. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  683. return hal_soc->ops->hal_rx_encryption_info_valid(buf);
  684. }
  685. /*
  686. * hal_rx_print_pn: Prints the PN of rx packet.
  687. * @hal_soc_hdl: hal soc handle
  688. * @buf: rx_tlv_hdr of the received packet
  689. *
  690. * Return: void
  691. */
  692. static inline void
  693. hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  694. {
  695. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  696. hal_soc->ops->hal_rx_print_pn(buf);
  697. }
  698. /**
  699. * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the
  700. * l3_header padding from rx_msdu_end TLV
  701. *
  702. * @buf: pointer to the start of RX PKT TLV headers
  703. * Return: number of l3 header padding bytes
  704. */
  705. static inline uint32_t
  706. hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl,
  707. uint8_t *buf)
  708. {
  709. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  710. return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf);
  711. }
  712. /**
  713. * hal_rx_msdu_end_sa_idx_get(): API to get the
  714. * sa_idx from rx_msdu_end TLV
  715. *
  716. * @ buf: pointer to the start of RX PKT TLV headers
  717. * Return: sa_idx (SA AST index)
  718. */
  719. static inline uint16_t
  720. hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl,
  721. uint8_t *buf)
  722. {
  723. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  724. return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf);
  725. }
  726. /**
  727. * hal_rx_msdu_end_sa_is_valid_get(): API to get the
  728. * sa_is_valid bit from rx_msdu_end TLV
  729. *
  730. * @ buf: pointer to the start of RX PKT TLV headers
  731. * Return: sa_is_valid bit
  732. */
  733. static inline uint8_t
  734. hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  735. uint8_t *buf)
  736. {
  737. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  738. return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf);
  739. }
  740. /**
  741. * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length
  742. * from rx_msdu_start TLV
  743. *
  744. * @buf: pointer to the start of RX PKT TLV headers
  745. * @len: msdu length
  746. *
  747. * Return: none
  748. */
  749. static inline void
  750. hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  751. uint32_t len)
  752. {
  753. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  754. return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len);
  755. }
  756. /**
  757. * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO
  758. *
  759. * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame
  760. * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame
  761. * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame
  762. * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame
  763. * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame
  764. * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame
  765. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame
  766. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame
  767. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame
  768. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame
  769. * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported
  770. * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit
  771. */
  772. enum hal_rx_mpdu_info_sw_frame_group_id_type {
  773. HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0,
  774. HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA,
  775. HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA,
  776. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA,
  777. HAL_MPDU_SW_FRAME_GROUP_MGMT,
  778. HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8,
  779. HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12,
  780. HAL_MPDU_SW_FRAME_GROUP_CTRL = 20,
  781. HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25,
  782. HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28,
  783. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31,
  784. HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36,
  785. HAL_MPDU_SW_FRAME_GROUP_MAX = 37,
  786. };
  787. /**
  788. * hal_rx_mpdu_start_mpdu_qos_control_valid_get():
  789. * Retrieve qos control valid bit from the tlv.
  790. * @hal_soc_hdl: hal_soc handle
  791. * @buf: pointer to rx pkt TLV.
  792. *
  793. * Return: qos control value.
  794. */
  795. static inline uint32_t
  796. hal_rx_mpdu_start_mpdu_qos_control_valid_get(
  797. hal_soc_handle_t hal_soc_hdl,
  798. uint8_t *buf)
  799. {
  800. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  801. if ((!hal_soc) || (!hal_soc->ops)) {
  802. hal_err("hal handle is NULL");
  803. QDF_BUG(0);
  804. return QDF_STATUS_E_INVAL;
  805. }
  806. if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get)
  807. return hal_soc->ops->
  808. hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf);
  809. return QDF_STATUS_E_INVAL;
  810. }
  811. /**
  812. * hal_rx_is_unicast: check packet is unicast frame or not.
  813. * @hal_soc_hdl: hal_soc handle
  814. * @buf: pointer to rx pkt TLV.
  815. *
  816. * Return: true on unicast.
  817. */
  818. static inline bool
  819. hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  820. {
  821. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  822. return hal_soc->ops->hal_rx_is_unicast(buf);
  823. }
  824. /**
  825. * hal_rx_tid_get: get tid based on qos control valid.
  826. * @hal_soc_hdl: hal soc handle
  827. * @buf: pointer to rx pkt TLV.
  828. *
  829. * Return: tid
  830. */
  831. static inline uint32_t
  832. hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  833. {
  834. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  835. return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf);
  836. }
  837. /**
  838. * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id
  839. * @hal_soc_hdl: hal soc handle
  840. * @buf: pointer to rx pkt TLV.
  841. *
  842. * Return: sw peer_id
  843. */
  844. static inline uint32_t
  845. hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  846. uint8_t *buf)
  847. {
  848. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  849. return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf);
  850. }
  851. /**
  852. * hal_rx_tlv_peer_meta_data_get() - Retrieve PEER_META_DATA
  853. * @hal_soc_hdl: hal soc handle
  854. * @buf: pointer to rx pkt TLV.
  855. *
  856. * Return: peer meta data
  857. */
  858. static inline uint32_t
  859. hal_rx_tlv_peer_meta_data_get(hal_soc_handle_t hal_soc_hdl,
  860. uint8_t *buf)
  861. {
  862. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  863. return hal_soc->ops->hal_rx_tlv_peer_meta_data_get(buf);
  864. }
  865. /*
  866. * hal_rx_mpdu_get_tods(): API to get the tods info
  867. * from rx_mpdu_start
  868. *
  869. * @buf: pointer to the start of RX PKT TLV header
  870. * Return: uint32_t(to_ds)
  871. */
  872. static inline uint32_t
  873. hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  874. {
  875. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  876. return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf);
  877. }
  878. /*
  879. * hal_rx_mpdu_get_fr_ds(): API to get the from ds info
  880. * from rx_mpdu_start
  881. * @hal_soc_hdl: hal soc handle
  882. * @buf: pointer to the start of RX PKT TLV header
  883. *
  884. * Return: uint32_t(fr_ds)
  885. */
  886. static inline uint32_t
  887. hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  888. {
  889. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  890. return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf);
  891. }
  892. /*
  893. * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu
  894. * @hal_soc_hdl: hal soc handle
  895. * @buf: pointer to the start of RX PKT TLV headera
  896. * @mac_addr: pointer to mac address
  897. *
  898. * Return: success/failure
  899. */
  900. static inline
  901. QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl,
  902. uint8_t *buf, uint8_t *mac_addr)
  903. {
  904. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  905. return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr);
  906. }
  907. /*
  908. * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu
  909. * in the packet
  910. * @hal_soc_hdl: hal soc handle
  911. * @buf: pointer to the start of RX PKT TLV header
  912. * @mac_addr: pointer to mac address
  913. *
  914. * Return: success/failure
  915. */
  916. static inline
  917. QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl,
  918. uint8_t *buf, uint8_t *mac_addr)
  919. {
  920. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  921. return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr);
  922. }
  923. /*
  924. * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu
  925. * in the packet
  926. * @hal_soc_hdl: hal soc handle
  927. * @buf: pointer to the start of RX PKT TLV header
  928. * @mac_addr: pointer to mac address
  929. *
  930. * Return: success/failure
  931. */
  932. static inline
  933. QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl,
  934. uint8_t *buf, uint8_t *mac_addr)
  935. {
  936. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  937. return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr);
  938. }
  939. /*
  940. * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu
  941. * in the packet
  942. * @hal_soc_hdl: hal_soc handle
  943. * @buf: pointer to the start of RX PKT TLV header
  944. * @mac_addr: pointer to mac address
  945. * Return: success/failure
  946. */
  947. static inline
  948. QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl,
  949. uint8_t *buf, uint8_t *mac_addr)
  950. {
  951. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  952. return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr);
  953. }
  954. /**
  955. * hal_rx_msdu_end_da_idx_get: API to get da_idx
  956. * from rx_msdu_end TLV
  957. *
  958. * @ buf: pointer to the start of RX PKT TLV headers
  959. * Return: da index
  960. */
  961. static inline uint16_t
  962. hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  963. {
  964. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  965. return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf);
  966. }
  967. /**
  968. * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid
  969. * from rx_msdu_end TLV
  970. * @hal_soc_hdl: hal soc handle
  971. * @ buf: pointer to the start of RX PKT TLV headers
  972. *
  973. * Return: da_is_valid
  974. */
  975. static inline uint8_t
  976. hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  977. uint8_t *buf)
  978. {
  979. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  980. return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf);
  981. }
  982. /**
  983. * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
  984. * from rx_msdu_end TLV
  985. *
  986. * @buf: pointer to the start of RX PKT TLV headers
  987. *
  988. * Return: da_is_mcbc
  989. */
  990. static inline uint8_t
  991. hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  992. {
  993. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  994. return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf);
  995. }
  996. /**
  997. * hal_rx_msdu_end_is_tkip_mic_err: API to check if pkt has mic error
  998. * from rx_msdu_end TLV
  999. *
  1000. * @buf: pointer to the start of RX PKT TLV headers
  1001. *
  1002. * Return: tkip_mic_err
  1003. */
  1004. static inline uint8_t
  1005. hal_rx_msdu_end_is_tkip_mic_err(hal_soc_handle_t hal_soc_hdl,
  1006. uint8_t *buf)
  1007. {
  1008. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1009. if (hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err)
  1010. return hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err(buf);
  1011. else
  1012. return 0;
  1013. }
  1014. /**
  1015. * hal_rx_msdu_end_first_msdu_get: API to get first msdu status
  1016. * from rx_msdu_end TLV
  1017. * @hal_soc_hdl: hal soc handle
  1018. * @buf: pointer to the start of RX PKT TLV headers
  1019. *
  1020. * Return: first_msdu
  1021. */
  1022. static inline uint8_t
  1023. hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1024. uint8_t *buf)
  1025. {
  1026. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1027. return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf);
  1028. }
  1029. /**
  1030. * hal_rx_msdu_end_last_msdu_get: API to get last msdu status
  1031. * from rx_msdu_end TLV
  1032. * @hal_soc_hdl: hal soc handle
  1033. * @buf: pointer to the start of RX PKT TLV headers
  1034. *
  1035. * Return: last_msdu
  1036. */
  1037. static inline uint8_t
  1038. hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1039. uint8_t *buf)
  1040. {
  1041. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1042. return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf);
  1043. }
  1044. /**
  1045. * hal_rx_msdu_cce_match_get: API to get CCE match
  1046. * from rx_msdu_end TLV
  1047. * @buf: pointer to the start of RX PKT TLV headers
  1048. * Return: cce_meta_data
  1049. */
  1050. static inline bool
  1051. hal_rx_msdu_cce_match_get(hal_soc_handle_t hal_soc_hdl,
  1052. uint8_t *buf)
  1053. {
  1054. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1055. return hal_soc->ops->hal_rx_msdu_cce_match_get(buf);
  1056. }
  1057. /**
  1058. * hal_rx_msdu_cce_metadata_get: API to get CCE metadata
  1059. * from rx_msdu_end TLV
  1060. * @buf: pointer to the start of RX PKT TLV headers
  1061. * Return: cce_meta_data
  1062. */
  1063. static inline uint16_t
  1064. hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1065. uint8_t *buf)
  1066. {
  1067. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1068. return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf);
  1069. }
  1070. /*******************************************************************************
  1071. * RX REO ERROR APIS
  1072. ******************************************************************************/
  1073. /**
  1074. * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details
  1075. * @msdu_link_ptr - msdu link ptr
  1076. * @hal - pointer to hal_soc
  1077. * Return - Pointer to rx_msdu_details structure
  1078. *
  1079. */
  1080. static inline
  1081. void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr,
  1082. struct hal_soc *hal_soc)
  1083. {
  1084. return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr);
  1085. }
  1086. /**
  1087. * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
  1088. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1089. * @hal - pointer to hal_soc
  1090. * Return - Pointer to rx_msdu_desc_info structure.
  1091. *
  1092. */
  1093. static inline
  1094. void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr,
  1095. struct hal_soc *hal_soc)
  1096. {
  1097. return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr);
  1098. }
  1099. /**
  1100. * hal_rx_reo_buf_paddr_get: Gets the physical address and
  1101. * cookie from the REO destination ring element
  1102. *
  1103. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1104. * the current descriptor
  1105. * @ buf_info: structure to return the buffer information
  1106. * Return: void
  1107. */
  1108. static inline
  1109. void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl,
  1110. hal_ring_desc_t rx_desc,
  1111. struct hal_buf_info *buf_info)
  1112. {
  1113. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1114. if (hal_soc->ops->hal_rx_reo_buf_paddr_get)
  1115. return hal_soc->ops->hal_rx_reo_buf_paddr_get(
  1116. rx_desc,
  1117. buf_info);
  1118. }
  1119. /**
  1120. * hal_rx_wbm_rel_buf_paddr_get: Gets the physical address and
  1121. * cookie from the WBM release ring element
  1122. *
  1123. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1124. * the current descriptor
  1125. * @ buf_info: structure to return the buffer information
  1126. * Return: void
  1127. */
  1128. static inline
  1129. void hal_rx_wbm_rel_buf_paddr_get(hal_soc_handle_t hal_soc_hdl,
  1130. hal_ring_desc_t rx_desc,
  1131. struct hal_buf_info *buf_info)
  1132. {
  1133. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1134. if (hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get)
  1135. return hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get(rx_desc,
  1136. buf_info);
  1137. }
  1138. /**
  1139. * hal_rx_buf_cookie_rbm_get: Gets the physical address and
  1140. * cookie from the REO entrance ring element
  1141. *
  1142. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1143. * the current descriptor
  1144. * @ buf_info: structure to return the buffer information
  1145. * @ msdu_cnt: pointer to msdu count in MPDU
  1146. * Return: void
  1147. */
  1148. static inline
  1149. void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl,
  1150. uint32_t *buf_addr_info,
  1151. struct hal_buf_info *buf_info)
  1152. {
  1153. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1154. return hal_soc->ops->hal_rx_buf_cookie_rbm_get(
  1155. buf_addr_info,
  1156. buf_info);
  1157. }
  1158. /**
  1159. * hal_rx_msdu_link_desc_get(): API to get the MSDU information
  1160. * from the MSDU link descriptor
  1161. *
  1162. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  1163. * MSDU link descriptor (struct rx_msdu_link)
  1164. *
  1165. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  1166. *
  1167. * @num_msdus: Number of MSDUs in the MPDU
  1168. *
  1169. * Return: void
  1170. */
  1171. static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl,
  1172. void *msdu_link_desc,
  1173. struct hal_rx_msdu_list *msdu_list,
  1174. uint16_t *num_msdus)
  1175. {
  1176. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1177. struct rx_msdu_details *msdu_details;
  1178. struct rx_msdu_desc_info *msdu_desc_info;
  1179. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1180. int i;
  1181. struct hal_buf_info buf_info;
  1182. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  1183. dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK",
  1184. __func__, __LINE__, msdu_link, msdu_details);
  1185. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  1186. /* num_msdus received in mpdu descriptor may be incorrect
  1187. * sometimes due to HW issue. Check msdu buffer address also
  1188. */
  1189. if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET(
  1190. &msdu_details[i].buffer_addr_info_details) == 0))
  1191. break;
  1192. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  1193. &msdu_details[i].buffer_addr_info_details) == 0) {
  1194. /* set the last msdu bit in the prev msdu_desc_info */
  1195. msdu_desc_info =
  1196. hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc);
  1197. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1198. break;
  1199. }
  1200. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  1201. hal_soc);
  1202. /* set first MSDU bit or the last MSDU bit */
  1203. if (!i)
  1204. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1205. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  1206. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1207. msdu_list->msdu_info[i].msdu_flags =
  1208. hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info);
  1209. msdu_list->msdu_info[i].msdu_len =
  1210. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  1211. /* addr field in buf_info will not be valid */
  1212. hal_rx_buf_cookie_rbm_get(
  1213. hal_soc_hdl,
  1214. (uint32_t *)&msdu_details[i].buffer_addr_info_details,
  1215. &buf_info);
  1216. msdu_list->sw_cookie[i] = buf_info.sw_cookie;
  1217. msdu_list->rbm[i] = buf_info.rbm;
  1218. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  1219. &msdu_details[i].buffer_addr_info_details) |
  1220. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  1221. &msdu_details[i].buffer_addr_info_details) << 32;
  1222. dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d",
  1223. __func__, __LINE__, i, msdu_list->sw_cookie[i]);
  1224. }
  1225. *num_msdus = i;
  1226. }
  1227. /**
  1228. * hal_rx_is_pn_error() - Indicate if this error was caused by a
  1229. * PN check failure
  1230. *
  1231. * @reo_desc: opaque pointer used by HAL to get the REO destination entry
  1232. *
  1233. * Return: true: error caused by PN check, false: other error
  1234. */
  1235. static inline bool hal_rx_reo_is_pn_error(uint32_t error_code)
  1236. {
  1237. return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) ||
  1238. (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ?
  1239. true : false;
  1240. }
  1241. /**
  1242. * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in
  1243. * the sequence number
  1244. *
  1245. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1246. *
  1247. * Return: true: error caused by 2K jump, false: other error
  1248. */
  1249. static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code)
  1250. {
  1251. return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) ||
  1252. (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ?
  1253. true : false;
  1254. }
  1255. /**
  1256. * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR
  1257. *
  1258. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1259. *
  1260. * Return: true: error caused by OOR, false: other error
  1261. */
  1262. static inline bool hal_rx_reo_is_oor_error(uint32_t error_code)
  1263. {
  1264. return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ?
  1265. true : false;
  1266. }
  1267. /**
  1268. * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error
  1269. * @error_code: error code obtained from ring descriptor.
  1270. *
  1271. * Return: true, if the error code is 2k-jump or OOR
  1272. * false, for other error codes.
  1273. */
  1274. static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code)
  1275. {
  1276. return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) ||
  1277. (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ?
  1278. true : false;
  1279. }
  1280. /**
  1281. * hal_dump_wbm_rel_desc() - dump wbm release descriptor
  1282. * @hal_desc: hardware descriptor pointer
  1283. *
  1284. * This function will print wbm release descriptor
  1285. *
  1286. * Return: none
  1287. */
  1288. static inline void hal_dump_wbm_rel_desc(void *src_srng_desc)
  1289. {
  1290. uint32_t *wbm_comp = (uint32_t *)src_srng_desc;
  1291. uint32_t i;
  1292. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1293. "Current Rx wbm release descriptor is");
  1294. for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) {
  1295. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1296. "DWORD[i] = 0x%x", wbm_comp[i]);
  1297. }
  1298. }
  1299. /**
  1300. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  1301. *
  1302. * @ hal_soc_hdl : HAL version of the SOC pointer
  1303. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  1304. * @ buf_addr_info : void pointer to the buffer_addr_info
  1305. * @ bm_action : put in IDLE list or release to MSDU_LIST
  1306. *
  1307. * Return: void
  1308. */
  1309. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  1310. static inline
  1311. void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl,
  1312. void *src_srng_desc,
  1313. hal_buff_addrinfo_t buf_addr_info,
  1314. uint8_t bm_action)
  1315. {
  1316. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1317. if (hal_soc->ops->hal_rx_msdu_link_desc_set)
  1318. return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl,
  1319. src_srng_desc,
  1320. buf_addr_info,
  1321. bm_action);
  1322. }
  1323. /**
  1324. * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the
  1325. * BUFFER_ADDR_INFO, give the RX descriptor
  1326. * (Assumption -- BUFFER_ADDR_INFO is the
  1327. * first field in the descriptor structure)
  1328. */
  1329. #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \
  1330. ((hal_link_desc_t)(ring_desc))
  1331. #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1332. #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1333. /*******************************************************************************
  1334. * RX WBM ERROR APIS
  1335. ******************************************************************************/
  1336. #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1337. (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \
  1338. WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \
  1339. WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB)
  1340. /**
  1341. * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed
  1342. * the frame to this release ring
  1343. *
  1344. * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this
  1345. * frame to this queue
  1346. * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per
  1347. * received routing instructions. No error within REO was detected
  1348. */
  1349. enum hal_rx_wbm_reo_push_reason {
  1350. HAL_RX_WBM_REO_PSH_RSN_ERROR = 0,
  1351. HAL_RX_WBM_REO_PSH_RSN_ROUTE,
  1352. };
  1353. /**
  1354. * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to
  1355. * this release ring
  1356. *
  1357. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed
  1358. * this frame to this queue
  1359. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue
  1360. * per received routing instructions. No error within RXDMA was detected
  1361. */
  1362. enum hal_rx_wbm_rxdma_push_reason {
  1363. HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0,
  1364. HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE,
  1365. HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH,
  1366. };
  1367. static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start,
  1368. uint8_t dbg_level,
  1369. struct hal_soc *hal)
  1370. {
  1371. hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level);
  1372. }
  1373. /**
  1374. * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured
  1375. * human readable format.
  1376. * @ msdu_end: pointer the msdu_end TLV in pkt.
  1377. * @ dbg_level: log level.
  1378. *
  1379. * Return: void
  1380. */
  1381. static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc,
  1382. struct rx_msdu_end *msdu_end,
  1383. uint8_t dbg_level)
  1384. {
  1385. hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level);
  1386. }
  1387. /**
  1388. * hal_srng_ring_id_get: API to retrieve ring id from hal ring
  1389. * structure
  1390. * @hal_ring: pointer to hal_srng structure
  1391. *
  1392. * Return: ring_id
  1393. */
  1394. static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl)
  1395. {
  1396. return ((struct hal_srng *)hal_ring_hdl)->ring_id;
  1397. }
  1398. #define DOT11_SEQ_FRAG_MASK 0x000f
  1399. #define DOT11_FC1_MORE_FRAG_OFFSET 0x04
  1400. /**
  1401. * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number
  1402. *
  1403. * @nbuf: Network buffer
  1404. * Returns: rx fragment number
  1405. */
  1406. static inline
  1407. uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc,
  1408. uint8_t *buf)
  1409. {
  1410. return hal_soc->ops->hal_rx_get_rx_fragment_number(buf);
  1411. }
  1412. /*
  1413. * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid
  1414. * @hal_soc_hdl: hal soc handle
  1415. * @nbuf: Network buffer
  1416. *
  1417. * Return: value of sequence control valid field
  1418. */
  1419. static inline
  1420. uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl,
  1421. uint8_t *buf)
  1422. {
  1423. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1424. return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf);
  1425. }
  1426. /*
  1427. * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid
  1428. * @hal_soc_hdl: hal soc handle
  1429. * @nbuf: Network buffer
  1430. *
  1431. * Returns: value of frame control valid field
  1432. */
  1433. static inline
  1434. uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl,
  1435. uint8_t *buf)
  1436. {
  1437. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1438. return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf);
  1439. }
  1440. /**
  1441. * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid
  1442. * @hal_soc_hdl: hal soc handle
  1443. * @nbuf: Network buffer
  1444. * Returns: value of mpdu 4th address valid field
  1445. */
  1446. static inline
  1447. bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl,
  1448. uint8_t *buf)
  1449. {
  1450. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1451. return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf);
  1452. }
  1453. /*
  1454. * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info
  1455. *
  1456. * @rx_mpdu_desc_info: HAL view of rx mpdu desc info
  1457. * Returns: None
  1458. */
  1459. static inline void
  1460. hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info)
  1461. {
  1462. qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info));
  1463. }
  1464. /**
  1465. * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and
  1466. * save it to hal_wbm_err_desc_info structure passed by caller
  1467. * @wbm_desc: wbm ring descriptor
  1468. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  1469. * Return: void
  1470. */
  1471. static inline
  1472. void hal_rx_wbm_err_info_get(void *wbm_desc,
  1473. struct hal_wbm_err_desc_info *wbm_er_info,
  1474. hal_soc_handle_t hal_soc_hdl)
  1475. {
  1476. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1477. hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info);
  1478. }
  1479. /**
  1480. * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation
  1481. * bit from wbm release ring descriptor
  1482. * @wbm_desc: wbm ring descriptor
  1483. * Return: uint8_t
  1484. */
  1485. static inline
  1486. uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl,
  1487. void *wbm_desc)
  1488. {
  1489. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1490. return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc);
  1491. }
  1492. /**
  1493. * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status
  1494. *
  1495. * @ hal_soc: HAL version of the SOC pointer
  1496. * @ hw_desc_addr: Start address of Rx HW TLVs
  1497. * @ rs: Status for monitor mode
  1498. *
  1499. * Return: void
  1500. */
  1501. static inline
  1502. void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl,
  1503. void *hw_desc_addr,
  1504. struct mon_rx_status *rs)
  1505. {
  1506. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1507. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs);
  1508. }
  1509. /*
  1510. * hal_rx_get_tlv(): API to get the tlv
  1511. *
  1512. * @hal_soc: HAL version of the SOC pointer
  1513. * @rx_tlv: TLV data extracted from the rx packet
  1514. * Return: uint8_t
  1515. */
  1516. static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv)
  1517. {
  1518. return hal_soc->ops->hal_rx_get_tlv(rx_tlv);
  1519. }
  1520. /*
  1521. * hal_rx_msdu_start_nss_get(): API to get the NSS
  1522. * Interval from rx_msdu_start
  1523. *
  1524. * @hal_soc: HAL version of the SOC pointer
  1525. * @buf: pointer to the start of RX PKT TLV header
  1526. * Return: uint32_t(nss)
  1527. */
  1528. static inline
  1529. uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1530. {
  1531. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1532. return hal_soc->ops->hal_rx_msdu_start_nss_get(buf);
  1533. }
  1534. /**
  1535. * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured
  1536. * human readable format.
  1537. * @ msdu_start: pointer the msdu_start TLV in pkt.
  1538. * @ dbg_level: log level.
  1539. *
  1540. * Return: void
  1541. */
  1542. static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc,
  1543. struct rx_msdu_start *msdu_start,
  1544. uint8_t dbg_level)
  1545. {
  1546. hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level);
  1547. }
  1548. /**
  1549. * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start
  1550. * info details
  1551. *
  1552. * @ buf - Pointer to buffer containing rx pkt tlvs.
  1553. *
  1554. *
  1555. */
  1556. static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl,
  1557. uint8_t *buf)
  1558. {
  1559. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1560. return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf);
  1561. }
  1562. /*
  1563. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  1564. * Interval from rx_msdu_start
  1565. *
  1566. * @buf: pointer to the start of RX PKT TLV header
  1567. * Return: uint32_t(reception_type)
  1568. */
  1569. static inline
  1570. uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl,
  1571. uint8_t *buf)
  1572. {
  1573. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1574. return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf);
  1575. }
  1576. /**
  1577. * hal_reo_status_get_header_generic - Process reo desc info
  1578. * @d - Pointer to reo descriptior
  1579. * @b - tlv type info
  1580. * @h - Pointer to hal_reo_status_header where info to be stored
  1581. * @hal- pointer to hal_soc structure
  1582. * Return - none.
  1583. *
  1584. */
  1585. static inline
  1586. void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b,
  1587. void *h, struct hal_soc *hal_soc)
  1588. {
  1589. hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h);
  1590. }
  1591. /**
  1592. * hal_rx_desc_is_first_msdu() - Check if first msdu
  1593. *
  1594. * @hal_soc_hdl: hal_soc handle
  1595. * @hw_desc_addr: hardware descriptor address
  1596. *
  1597. * Return: 0 - success/ non-zero failure
  1598. */
  1599. static inline
  1600. uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl,
  1601. void *hw_desc_addr)
  1602. {
  1603. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1604. return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr);
  1605. }
  1606. /**
  1607. * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from
  1608. * the rx tlv fields.
  1609. * @hal_soc_hdl: HAL SoC handle
  1610. * @buf: rx tlv start address [To be validated by caller]
  1611. * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated.
  1612. *
  1613. * Return: None
  1614. */
  1615. static inline void
  1616. hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1617. uint8_t *buf,
  1618. void *mpdu_desc_info_hdl)
  1619. {
  1620. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1621. if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info)
  1622. return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf,
  1623. mpdu_desc_info_hdl);
  1624. }
  1625. static inline uint32_t
  1626. hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr)
  1627. {
  1628. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1629. return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr);
  1630. }
  1631. static inline
  1632. bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl,
  1633. uint8_t *rx_tlv_hdr)
  1634. {
  1635. uint8_t decap_format;
  1636. if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) {
  1637. decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl,
  1638. rx_tlv_hdr);
  1639. if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW)
  1640. return true;
  1641. }
  1642. return false;
  1643. }
  1644. /**
  1645. * hal_rx_msdu_fse_metadata_get: API to get FSE metadata
  1646. * from rx_msdu_end TLV
  1647. * @buf: pointer to the start of RX PKT TLV headers
  1648. *
  1649. * Return: fse metadata value from MSDU END TLV
  1650. */
  1651. static inline uint32_t
  1652. hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1653. uint8_t *buf)
  1654. {
  1655. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1656. return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf);
  1657. }
  1658. /**
  1659. * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from
  1660. * <struct buffer_addr_info> structure
  1661. * @buf_addr_info: pointer to <struct buffer_addr_info> structure
  1662. * @buf_info: structure to return the buffer information including
  1663. * paddr/cookie
  1664. *
  1665. * return: None
  1666. */
  1667. static inline
  1668. void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info,
  1669. struct hal_buf_info *buf_info)
  1670. {
  1671. buf_info->paddr =
  1672. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  1673. ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  1674. }
  1675. /**
  1676. * hal_rx_msdu_flow_idx_get: API to get flow index
  1677. * from rx_msdu_end TLV
  1678. * @buf: pointer to the start of RX PKT TLV headers
  1679. *
  1680. * Return: flow index value from MSDU END TLV
  1681. */
  1682. static inline uint32_t
  1683. hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl,
  1684. uint8_t *buf)
  1685. {
  1686. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1687. return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf);
  1688. }
  1689. /**
  1690. * hal_rx_msdu_get_reo_destination_indication: API to get reo
  1691. * destination index from rx_msdu_end TLV
  1692. * @buf: pointer to the start of RX PKT TLV headers
  1693. * @reo_destination_indication: pointer to return value of
  1694. * reo_destination_indication
  1695. *
  1696. * Return: reo_destination_indication value from MSDU END TLV
  1697. */
  1698. static inline void
  1699. hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl,
  1700. uint8_t *buf,
  1701. uint32_t *reo_destination_indication)
  1702. {
  1703. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1704. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf,
  1705. reo_destination_indication);
  1706. }
  1707. /**
  1708. * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout
  1709. * from rx_msdu_end TLV
  1710. * @buf: pointer to the start of RX PKT TLV headers
  1711. *
  1712. * Return: flow index timeout value from MSDU END TLV
  1713. */
  1714. static inline bool
  1715. hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl,
  1716. uint8_t *buf)
  1717. {
  1718. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1719. return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf);
  1720. }
  1721. /**
  1722. * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid
  1723. * from rx_msdu_end TLV
  1724. * @buf: pointer to the start of RX PKT TLV headers
  1725. *
  1726. * Return: flow index invalid value from MSDU END TLV
  1727. */
  1728. static inline bool
  1729. hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl,
  1730. uint8_t *buf)
  1731. {
  1732. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1733. return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf);
  1734. }
  1735. /**
  1736. * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id
  1737. * @hal_soc_hdl: hal_soc handle
  1738. * @rx_tlv_hdr: Rx_tlv_hdr
  1739. * @rxdma_dst_ring_desc: Rx HW descriptor
  1740. *
  1741. * Return: ppdu id
  1742. */
  1743. static inline
  1744. uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl,
  1745. void *rx_tlv_hdr,
  1746. void *rxdma_dst_ring_desc)
  1747. {
  1748. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1749. return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr,
  1750. rxdma_dst_ring_desc);
  1751. }
  1752. /**
  1753. * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id
  1754. * @hal_soc_hdl: hal_soc handle
  1755. * @buf: rx tlv address
  1756. *
  1757. * Return: sw peer id
  1758. */
  1759. static inline
  1760. uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  1761. uint8_t *buf)
  1762. {
  1763. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1764. return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf);
  1765. }
  1766. static inline
  1767. void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl,
  1768. void *link_desc_addr)
  1769. {
  1770. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1771. return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr);
  1772. }
  1773. static inline
  1774. void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl,
  1775. void *msdu_addr)
  1776. {
  1777. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1778. return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr);
  1779. }
  1780. static inline
  1781. void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1782. void *hw_addr)
  1783. {
  1784. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1785. return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr);
  1786. }
  1787. static inline
  1788. void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1789. void *hw_addr)
  1790. {
  1791. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1792. return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr);
  1793. }
  1794. static inline
  1795. uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl,
  1796. uint8_t *buf)
  1797. {
  1798. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1799. return hal_soc->ops->hal_rx_get_fc_valid(buf);
  1800. }
  1801. static inline
  1802. uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1803. {
  1804. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1805. return hal_soc->ops->hal_rx_get_to_ds_flag(buf);
  1806. }
  1807. static inline
  1808. uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl,
  1809. uint8_t *buf)
  1810. {
  1811. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1812. return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf);
  1813. }
  1814. static inline
  1815. uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl,
  1816. uint8_t *buf)
  1817. {
  1818. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1819. return hal_soc->ops->hal_rx_get_filter_category(buf);
  1820. }
  1821. static inline
  1822. uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl,
  1823. uint8_t *buf)
  1824. {
  1825. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1826. return hal_soc->ops->hal_rx_get_ppdu_id(buf);
  1827. }
  1828. /**
  1829. * hal_reo_config(): Set reo config parameters
  1830. * @soc: hal soc handle
  1831. * @reg_val: value to be set
  1832. * @reo_params: reo parameters
  1833. *
  1834. * Return: void
  1835. */
  1836. static inline
  1837. void hal_reo_config(struct hal_soc *hal_soc,
  1838. uint32_t reg_val,
  1839. struct hal_reo_params *reo_params)
  1840. {
  1841. hal_soc->ops->hal_reo_config(hal_soc,
  1842. reg_val,
  1843. reo_params);
  1844. }
  1845. /**
  1846. * hal_rx_msdu_get_flow_params: API to get flow index,
  1847. * flow index invalid and flow index timeout from rx_msdu_end TLV
  1848. * @buf: pointer to the start of RX PKT TLV headers
  1849. * @flow_invalid: pointer to return value of flow_idx_valid
  1850. * @flow_timeout: pointer to return value of flow_idx_timeout
  1851. * @flow_index: pointer to return value of flow_idx
  1852. *
  1853. * Return: none
  1854. */
  1855. static inline void
  1856. hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl,
  1857. uint8_t *buf,
  1858. bool *flow_invalid,
  1859. bool *flow_timeout,
  1860. uint32_t *flow_index)
  1861. {
  1862. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1863. hal_soc->ops->hal_rx_msdu_get_flow_params(buf,
  1864. flow_invalid,
  1865. flow_timeout,
  1866. flow_index);
  1867. }
  1868. static inline
  1869. uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl,
  1870. uint8_t *buf)
  1871. {
  1872. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1873. return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf);
  1874. }
  1875. static inline
  1876. uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl,
  1877. uint8_t *buf)
  1878. {
  1879. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1880. return hal_soc->ops->hal_rx_get_rx_sequence(buf);
  1881. }
  1882. static inline void
  1883. hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl,
  1884. void *rx_tlv,
  1885. void *ppdu_info)
  1886. {
  1887. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1888. if (hal_soc->ops->hal_rx_get_bb_info)
  1889. hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info);
  1890. }
  1891. static inline void
  1892. hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl,
  1893. void *rx_tlv,
  1894. void *ppdu_info)
  1895. {
  1896. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1897. if (hal_soc->ops->hal_rx_get_rtt_info)
  1898. hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info);
  1899. }
  1900. /**
  1901. * hal_rx_msdu_metadata_get(): API to get the
  1902. * fast path information from rx_msdu_end TLV
  1903. *
  1904. * @ hal_soc_hdl: DP soc handle
  1905. * @ buf: pointer to the start of RX PKT TLV headers
  1906. * @ msdu_metadata: Structure to hold msdu end information
  1907. * Return: none
  1908. */
  1909. static inline void
  1910. hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  1911. struct hal_rx_msdu_metadata *msdu_md)
  1912. {
  1913. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1914. return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md);
  1915. }
  1916. /**
  1917. * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum
  1918. * from rx_msdu_end TLV
  1919. * @buf: pointer to the start of RX PKT TLV headers
  1920. *
  1921. * Return: cumulative_l4_checksum
  1922. */
  1923. static inline uint16_t
  1924. hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl,
  1925. uint8_t *buf)
  1926. {
  1927. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1928. if (!hal_soc || !hal_soc->ops) {
  1929. hal_err("hal handle is NULL");
  1930. QDF_BUG(0);
  1931. return 0;
  1932. }
  1933. if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum)
  1934. return 0;
  1935. return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf);
  1936. }
  1937. /**
  1938. * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length
  1939. * from rx_msdu_end TLV
  1940. * @buf: pointer to the start of RX PKT TLV headers
  1941. *
  1942. * Return: cumulative_ip_length
  1943. */
  1944. static inline uint16_t
  1945. hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl,
  1946. uint8_t *buf)
  1947. {
  1948. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1949. if (!hal_soc || !hal_soc->ops) {
  1950. hal_err("hal handle is NULL");
  1951. QDF_BUG(0);
  1952. return 0;
  1953. }
  1954. if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length)
  1955. return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf);
  1956. return 0;
  1957. }
  1958. /**
  1959. * hal_rx_get_udp_proto: API to get UDP proto field
  1960. * from rx_msdu_start TLV
  1961. * @buf: pointer to the start of RX PKT TLV headers
  1962. *
  1963. * Return: UDP proto field value
  1964. */
  1965. static inline bool
  1966. hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1967. {
  1968. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1969. if (!hal_soc || !hal_soc->ops) {
  1970. hal_err("hal handle is NULL");
  1971. QDF_BUG(0);
  1972. return 0;
  1973. }
  1974. if (hal_soc->ops->hal_rx_get_udp_proto)
  1975. return hal_soc->ops->hal_rx_get_udp_proto(buf);
  1976. return 0;
  1977. }
  1978. /**
  1979. * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation
  1980. * from rx_msdu_end TLV
  1981. * @buf: pointer to the start of RX PKT TLV headers
  1982. *
  1983. * Return: flow_agg_continuation bit field value
  1984. */
  1985. static inline bool
  1986. hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl,
  1987. uint8_t *buf)
  1988. {
  1989. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1990. if (!hal_soc || !hal_soc->ops) {
  1991. hal_err("hal handle is NULL");
  1992. QDF_BUG(0);
  1993. return 0;
  1994. }
  1995. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation)
  1996. return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf);
  1997. return 0;
  1998. }
  1999. /**
  2000. * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from
  2001. * rx_msdu_end TLV
  2002. * @buf: pointer to the start of RX PKT TLV headers
  2003. *
  2004. * Return: flow_agg count value
  2005. */
  2006. static inline uint8_t
  2007. hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl,
  2008. uint8_t *buf)
  2009. {
  2010. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2011. if (!hal_soc || !hal_soc->ops) {
  2012. hal_err("hal handle is NULL");
  2013. QDF_BUG(0);
  2014. return 0;
  2015. }
  2016. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count)
  2017. return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf);
  2018. return 0;
  2019. }
  2020. /**
  2021. * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV
  2022. * @buf: pointer to the start of RX PKT TLV headers
  2023. *
  2024. * Return: fisa flow_agg timeout bit value
  2025. */
  2026. static inline bool
  2027. hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2028. {
  2029. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2030. if (!hal_soc || !hal_soc->ops) {
  2031. hal_err("hal handle is NULL");
  2032. QDF_BUG(0);
  2033. return 0;
  2034. }
  2035. if (hal_soc->ops->hal_rx_get_fisa_timeout)
  2036. return hal_soc->ops->hal_rx_get_fisa_timeout(buf);
  2037. return 0;
  2038. }
  2039. /**
  2040. * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv
  2041. * tag is valid
  2042. *
  2043. * @hal_soc_hdl: HAL SOC handle
  2044. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  2045. *
  2046. * Return: true if RX_MPDU_START tlv tag is valid, else false
  2047. */
  2048. static inline uint8_t
  2049. hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl,
  2050. void *rx_tlv_hdr)
  2051. {
  2052. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2053. if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid)
  2054. return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr);
  2055. return 0;
  2056. }
  2057. /**
  2058. * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc
  2059. * buffer addr info
  2060. * @link_desc_va: pointer to current msdu link Desc
  2061. * @next_addr_info: buffer to save next msdu link Desc buffer addr info
  2062. *
  2063. * return: None
  2064. */
  2065. static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info(
  2066. void *link_desc_va,
  2067. struct buffer_addr_info *next_addr_info)
  2068. {
  2069. struct rx_msdu_link *msdu_link = link_desc_va;
  2070. if (!msdu_link) {
  2071. qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info));
  2072. return;
  2073. }
  2074. *next_addr_info = msdu_link->next_msdu_link_desc_addr_info;
  2075. }
  2076. /**
  2077. * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc
  2078. * buffer addr info
  2079. * @link_desc_va: pointer to current msdu link Desc
  2080. *
  2081. * return: None
  2082. */
  2083. static inline
  2084. void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va)
  2085. {
  2086. struct rx_msdu_link *msdu_link = link_desc_va;
  2087. if (msdu_link)
  2088. qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info,
  2089. sizeof(msdu_link->next_msdu_link_desc_addr_info));
  2090. }
  2091. /**
  2092. * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid
  2093. *
  2094. * @buf_addr_info: pointer to buf_addr_info structure
  2095. *
  2096. * return: true: has valid paddr, false: not.
  2097. */
  2098. static inline
  2099. bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info)
  2100. {
  2101. return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ?
  2102. false : true;
  2103. }
  2104. /**
  2105. * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from
  2106. * rx_pkt_tlvs structure
  2107. *
  2108. * @hal_soc_hdl: HAL SOC handle
  2109. * return: msdu_end_tlv offset value
  2110. */
  2111. static inline
  2112. uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  2113. {
  2114. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2115. if (!hal_soc || !hal_soc->ops) {
  2116. hal_err("hal handle is NULL");
  2117. QDF_BUG(0);
  2118. return 0;
  2119. }
  2120. return hal_soc->ops->hal_rx_msdu_end_offset_get();
  2121. }
  2122. /**
  2123. * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from
  2124. * rx_pkt_tlvs structure
  2125. *
  2126. * @hal_soc_hdl: HAL SOC handle
  2127. * return: msdu_start_tlv offset value
  2128. */
  2129. static inline
  2130. uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  2131. {
  2132. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2133. if (!hal_soc || !hal_soc->ops) {
  2134. hal_err("hal handle is NULL");
  2135. QDF_BUG(0);
  2136. return 0;
  2137. }
  2138. return hal_soc->ops->hal_rx_msdu_start_offset_get();
  2139. }
  2140. /**
  2141. * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from
  2142. * rx_pkt_tlvs structure
  2143. *
  2144. * @hal_soc_hdl: HAL SOC handle
  2145. * return: mpdu_start_tlv offset value
  2146. */
  2147. static inline
  2148. uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  2149. {
  2150. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2151. if (!hal_soc || !hal_soc->ops) {
  2152. hal_err("hal handle is NULL");
  2153. QDF_BUG(0);
  2154. return 0;
  2155. }
  2156. return hal_soc->ops->hal_rx_mpdu_start_offset_get();
  2157. }
  2158. static inline
  2159. uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl)
  2160. {
  2161. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2162. if (!hal_soc || !hal_soc->ops) {
  2163. hal_err("hal handle is NULL");
  2164. QDF_BUG(0);
  2165. return 0;
  2166. }
  2167. return hal_soc->ops->hal_rx_pkt_tlv_offset_get();
  2168. }
  2169. /**
  2170. * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from
  2171. * rx_pkt_tlvs structure
  2172. *
  2173. * @hal_soc_hdl: HAL SOC handle
  2174. * return: mpdu_end_tlv offset value
  2175. */
  2176. static inline
  2177. uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  2178. {
  2179. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2180. if (!hal_soc || !hal_soc->ops) {
  2181. hal_err("hal handle is NULL");
  2182. QDF_BUG(0);
  2183. return 0;
  2184. }
  2185. return hal_soc->ops->hal_rx_mpdu_end_offset_get();
  2186. }
  2187. /**
  2188. * hal_rx_attn_offset_get(): Get the ATTENTION offset from
  2189. * rx_pkt_tlvs structure
  2190. *
  2191. * @hal_soc_hdl: HAL SOC handle
  2192. * return: attn_tlv offset value
  2193. */
  2194. static inline
  2195. uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl)
  2196. {
  2197. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2198. if (!hal_soc || !hal_soc->ops) {
  2199. hal_err("hal handle is NULL");
  2200. QDF_BUG(0);
  2201. return 0;
  2202. }
  2203. return hal_soc->ops->hal_rx_attn_offset_get();
  2204. }
  2205. /**
  2206. * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
  2207. * @msdu_details_ptr - Pointer to msdu_details_ptr
  2208. * @hal - pointer to hal_soc
  2209. * Return - Pointer to rx_msdu_desc_info structure.
  2210. *
  2211. */
  2212. static inline
  2213. void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr,
  2214. struct hal_soc *hal_soc)
  2215. {
  2216. return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr(
  2217. msdu_details_ptr);
  2218. }
  2219. static inline void
  2220. hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl,
  2221. uint8_t *buf, uint8_t dbg_level)
  2222. {
  2223. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2224. hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level);
  2225. }
  2226. //TODO - Change the names to not include tlv names
  2227. static inline uint16_t
  2228. hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2229. {
  2230. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2231. return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf);
  2232. }
  2233. static inline uint32_t
  2234. hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2235. {
  2236. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2237. return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf);
  2238. }
  2239. static inline uint32_t
  2240. hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2241. {
  2242. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2243. return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf);
  2244. }
  2245. static inline uint16_t
  2246. hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2247. {
  2248. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2249. return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf);
  2250. }
  2251. static inline int
  2252. hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl,
  2253. uint8_t *rx_pkt_tlv,
  2254. struct hal_offload_info *offload_info)
  2255. {
  2256. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2257. return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv,
  2258. offload_info);
  2259. }
  2260. static inline int
  2261. hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  2262. void *proto_params)
  2263. {
  2264. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2265. return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params);
  2266. }
  2267. static inline int
  2268. hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  2269. uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset)
  2270. {
  2271. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2272. return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf,
  2273. l3_hdr_offset,
  2274. l4_hdr_offset);
  2275. }
  2276. static inline uint32_t
  2277. hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2278. {
  2279. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2280. return hal_soc->ops->hal_rx_tlv_mic_err_get(buf);
  2281. }
  2282. /*
  2283. * hal_rx_tlv_get_pkt_type(): API to get the pkt type
  2284. * from rx_msdu_start
  2285. *
  2286. * @buf: pointer to the start of RX PKT TLV header
  2287. * Return: uint32_t(pkt type)
  2288. */
  2289. static inline uint32_t
  2290. hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2291. {
  2292. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2293. return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf);
  2294. }
  2295. static inline void
  2296. hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl,
  2297. uint8_t *buf, uint64_t *pn_num)
  2298. {
  2299. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2300. hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num);
  2301. }
  2302. static inline uint8_t *
  2303. hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc)
  2304. {
  2305. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2306. if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr)
  2307. return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc);
  2308. return NULL;
  2309. }
  2310. static inline uint64_t
  2311. hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc,
  2312. uint8_t *buf)
  2313. {
  2314. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2315. if (hal_soc->ops->hal_rx_get_qdesc_addr)
  2316. return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf);
  2317. return 0;
  2318. }
  2319. static inline void
  2320. hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl,
  2321. uint8_t *desc, uint32_t dst_ind)
  2322. {
  2323. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2324. if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind)
  2325. hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind);
  2326. }
  2327. static inline uint32_t
  2328. hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2329. {
  2330. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2331. if (hal_soc->ops->hal_rx_tlv_get_is_decrypted)
  2332. return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf);
  2333. return 0;
  2334. }
  2335. static inline uint8_t *
  2336. hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2337. {
  2338. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2339. return hal_soc->ops->hal_rx_pkt_hdr_get(buf);
  2340. }
  2341. static inline uint8_t
  2342. hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2343. {
  2344. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2345. if (hal_soc->ops->hal_rx_msdu_get_keyid)
  2346. return hal_soc->ops->hal_rx_msdu_get_keyid(buf);
  2347. return 0;
  2348. }
  2349. static inline uint32_t
  2350. hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2351. {
  2352. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2353. if (hal_soc->ops->hal_rx_tlv_get_freq)
  2354. return hal_soc->ops->hal_rx_tlv_get_freq(buf);
  2355. return 0;
  2356. }
  2357. static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl,
  2358. void *mpdu_desc_info, uint32_t val)
  2359. {
  2360. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2361. if (hal_soc->ops->hal_mpdu_desc_info_set)
  2362. return hal_soc->ops->hal_mpdu_desc_info_set(
  2363. hal_soc_hdl, mpdu_desc_info, val);
  2364. }
  2365. static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl,
  2366. void *msdu_desc_info,
  2367. uint32_t val, uint32_t nbuf_len)
  2368. {
  2369. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2370. if (hal_soc->ops->hal_msdu_desc_info_set)
  2371. return hal_soc->ops->hal_msdu_desc_info_set(
  2372. hal_soc_hdl, msdu_desc_info, val, nbuf_len);
  2373. }
  2374. static inline uint32_t
  2375. hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc)
  2376. {
  2377. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2378. if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get)
  2379. return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get(
  2380. hal_soc_hdl, msdu_link_desc);
  2381. return 0;
  2382. }
  2383. static inline uint32_t
  2384. hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2385. {
  2386. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2387. return hal_soc->ops->hal_rx_tlv_sgi_get(buf);
  2388. }
  2389. static inline uint32_t
  2390. hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2391. {
  2392. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2393. return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf);
  2394. }
  2395. static inline uint32_t
  2396. hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2397. {
  2398. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2399. return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf);
  2400. }
  2401. static inline uint32_t
  2402. hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2403. {
  2404. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2405. return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf);
  2406. }
  2407. static inline uint32_t
  2408. hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2409. {
  2410. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2411. return hal_soc->ops->hal_rx_tlv_bw_get(buf);
  2412. }
  2413. static inline uint32_t
  2414. hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl,
  2415. hal_ring_desc_t ring_desc)
  2416. {
  2417. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2418. return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc);
  2419. }
  2420. /**
  2421. * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager"
  2422. * from the BUFFER_ADDR_INFO structure
  2423. * given a REO destination ring descriptor.
  2424. * @ ring_desc: RX(REO/WBM release) destination ring descriptor
  2425. *
  2426. * Return: uint8_t (value of the return_buffer_manager)
  2427. */
  2428. static inline uint8_t
  2429. hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl,
  2430. hal_ring_desc_t ring_desc)
  2431. {
  2432. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2433. return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc);
  2434. }
  2435. /*
  2436. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  2437. * rxdma ring entry.
  2438. * @rxdma_entry: descriptor entry
  2439. * @paddr: physical address of nbuf data pointer.
  2440. * @cookie: SW cookie used as a index to SW rx desc.
  2441. * @manager: who owns the nbuf (host, NSS, etc...).
  2442. *
  2443. */
  2444. static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl,
  2445. void *rxdma_entry,
  2446. qdf_dma_addr_t paddr,
  2447. uint32_t cookie,
  2448. uint8_t manager)
  2449. {
  2450. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2451. return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry,
  2452. paddr,
  2453. cookie,
  2454. manager);
  2455. }
  2456. static inline uint32_t
  2457. hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2458. {
  2459. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2460. return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc);
  2461. }
  2462. static inline void
  2463. hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr,
  2464. uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err)
  2465. {
  2466. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2467. return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr,
  2468. ip_csum_err,
  2469. tcp_udp_csum_err);
  2470. }
  2471. static inline void
  2472. hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl,
  2473. uint8_t *rx_tlv_hdr,
  2474. struct hal_rx_pkt_capture_flags *flags)
  2475. {
  2476. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2477. return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr,
  2478. flags);
  2479. }
  2480. static inline uint8_t
  2481. hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2482. {
  2483. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2484. return hal_soc->ops->hal_rx_err_status_get(rx_desc);
  2485. }
  2486. static inline uint8_t
  2487. hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2488. {
  2489. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2490. return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc);
  2491. }
  2492. /**
  2493. * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor.
  2494. * @hal_soc_hdl: HAL SoC handle
  2495. * @ring_desc: REO ring descriptor
  2496. * @prev_pn: Buffer to populate the previos PN
  2497. *
  2498. * Return: None
  2499. */
  2500. static inline void
  2501. hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc,
  2502. uint64_t *prev_pn)
  2503. {
  2504. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2505. if (hal_soc->ops->hal_rx_reo_prev_pn_get)
  2506. return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn);
  2507. }
  2508. /**
  2509. * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit
  2510. * from rx mpdu info
  2511. * @buf: pointer to rx_pkt_tlvs
  2512. *
  2513. * No input validdataion, since this function is supposed to be
  2514. * called from fastpath.
  2515. *
  2516. * Return: ampdu flag
  2517. */
  2518. static inline bool
  2519. hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2520. {
  2521. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2522. return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf);
  2523. }
  2524. #ifdef REO_SHARED_QREF_TABLE_EN
  2525. /**
  2526. * hal_reo_shared_qaddr_write(): Write REo tid queue addr
  2527. * LUT shared by SW and HW at the index given by peer id
  2528. * and tid.
  2529. *
  2530. * @hal_soc: hal soc pointer
  2531. * @reo_qref_addr: pointer to index pointed to be peer_id
  2532. * and tid
  2533. * @tid: tid queue number
  2534. * @hw_qdesc_paddr: reo queue addr
  2535. */
  2536. static inline void
  2537. hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl,
  2538. uint16_t peer_id,
  2539. int tid,
  2540. qdf_dma_addr_t hw_qdesc_paddr)
  2541. {
  2542. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2543. if (hal_soc->ops->hal_reo_shared_qaddr_write)
  2544. return hal_soc->ops->hal_reo_shared_qaddr_write(hal_soc_hdl,
  2545. peer_id, tid, hw_qdesc_paddr);
  2546. }
  2547. /**
  2548. * hal_reo_shared_qaddr_init(): Initialize reo qref LUT
  2549. * @hal_soc: Hal soc pointer
  2550. * @qref_reset: reset qref LUT
  2551. *
  2552. * Write MLO and Non MLO table start addr to HW reg
  2553. *
  2554. * Return: void
  2555. */
  2556. static inline void
  2557. hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset)
  2558. {
  2559. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2560. if (hal_soc->ops->hal_reo_shared_qaddr_init)
  2561. return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl,
  2562. qref_reset);
  2563. }
  2564. /**
  2565. * hal_reo_shared_qaddr_cache_clear(): Set and unset 'clear_qdesc_array'
  2566. * bit in reo reg for shared qref feature. This is done for every MLO
  2567. * connection to clear HW reo internal storage for clearing stale entry
  2568. * of prev peer having same peer id
  2569. *
  2570. * @hal_soc: Hal soc pointer
  2571. *
  2572. * Write MLO and Non MLO table start addr to HW reg
  2573. *
  2574. * Return: void
  2575. */
  2576. static inline void hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl)
  2577. {
  2578. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2579. if (hal_soc->ops->hal_reo_shared_qaddr_cache_clear)
  2580. return hal_soc->ops->hal_reo_shared_qaddr_cache_clear(hal_soc_hdl);
  2581. }
  2582. #else
  2583. static inline void
  2584. hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl,
  2585. uint16_t peer_id,
  2586. int tid,
  2587. qdf_dma_addr_t hw_qdesc_paddr) {}
  2588. static inline void
  2589. hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) {}
  2590. static inline void
  2591. hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {}
  2592. #endif /* REO_SHARED_QREF_TABLE_EN */
  2593. static inline uint8_t
  2594. hal_reo_shared_qaddr_is_enable(hal_soc_handle_t hal_soc_hdl)
  2595. {
  2596. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2597. return hal->reo_qref.reo_qref_table_en;
  2598. }
  2599. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  2600. static inline uint8_t
  2601. hal_get_first_wow_wakeup_packet(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2602. {
  2603. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2604. return hal_soc->ops->hal_get_first_wow_wakeup_packet(buf);
  2605. }
  2606. #endif
  2607. static inline uint32_t
  2608. hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2609. {
  2610. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2611. return hal_soc->ops->hal_rx_tlv_l3_type_get ?
  2612. hal_soc->ops->hal_rx_tlv_l3_type_get(buf) :
  2613. HAL_RX_TLV_L3_TYPE_INVALID;
  2614. }
  2615. /**
  2616. * hal_get_tsf_time() - Get tsf time
  2617. * @hal_soc_hdl: HAL soc handle
  2618. * @mac_id: mac_id
  2619. * @tsf: pointer to update tsf value
  2620. * @tsf_sync_soc_time: pointer to update tsf sync time
  2621. *
  2622. * Return: None.
  2623. */
  2624. static inline void
  2625. hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
  2626. uint32_t mac_id, uint64_t *tsf,
  2627. uint64_t *tsf_sync_soc_time)
  2628. {
  2629. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2630. if (hal_soc->ops->hal_get_tsf_time)
  2631. hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id,
  2632. tsf, tsf_sync_soc_time);
  2633. }
  2634. #endif /* _HAL_RX_H */