qmi.c 109 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/soc/qcom/qmi.h>
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "main.h"
  11. #include "qmi.h"
  12. #include "genl.h"
  13. #define WLFW_SERVICE_INS_ID_V01 1
  14. #define WLFW_CLIENT_ID 0x4b4e454c
  15. #define BDF_FILE_NAME_PREFIX "bdwlan"
  16. #define ELF_BDF_FILE_NAME "bdwlan.elf"
  17. #define ELF_BDF_FILE_NAME_GF "bdwlang.elf"
  18. #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e"
  19. #define ELF_BDF_FILE_NAME_GF_PREFIX "bdwlang.e"
  20. #define BIN_BDF_FILE_NAME "bdwlan.bin"
  21. #define BIN_BDF_FILE_NAME_GF "bdwlang.bin"
  22. #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b"
  23. #define BIN_BDF_FILE_NAME_GF_PREFIX "bdwlang.b"
  24. #define REGDB_FILE_NAME "regdb.bin"
  25. #define HDS_FILE_NAME "hds.bin"
  26. #define CHIP_ID_GF_MASK 0x10
  27. #define QDSS_TRACE_CONFIG_FILE "qdss_trace_config"
  28. /*
  29. * Download QDSS config file based on build type. Add build type string to
  30. * file name. Download "qdss_trace_config_debug_v<n>.cfg" for debug build
  31. * and "qdss_trace_config_perf_v<n>.cfg" for perf build.
  32. */
  33. #ifdef CONFIG_CNSS2_DEBUG
  34. #define QDSS_FILE_BUILD_STR "debug_"
  35. #else
  36. #define QDSS_FILE_BUILD_STR "perf_"
  37. #endif
  38. #define HW_V1_NUMBER "v1"
  39. #define HW_V2_NUMBER "v2"
  40. #define CE_MSI_NAME "CE"
  41. #define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout)
  42. #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS)
  43. #define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF
  44. #define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF
  45. #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K
  46. #define IMSPRIVATE_SERVICE_MAX_MSG_LEN SZ_8K
  47. #define DMS_QMI_MAX_MSG_LEN SZ_256
  48. #define MAX_SHADOW_REG_RESERVED 2
  49. #define MAX_NUM_SHADOW_REG_V3 (QMI_WLFW_MAX_NUM_SHADOW_REG_V3_USAGE_V01 - \
  50. MAX_SHADOW_REG_RESERVED)
  51. #define QMI_WLFW_MAC_READY_TIMEOUT_MS 50
  52. #define QMI_WLFW_MAC_READY_MAX_RETRY 200
  53. // these error values are not defined in <linux/soc/qcom/qmi.h> and fw is sending as error response
  54. #define QMI_ERR_HARDWARE_RESTRICTED_V01 0x0053
  55. #define QMI_ERR_ENOMEM_V01 0x0002
  56. enum nm_modem_bit {
  57. SLEEP_CLOCK_SELECT_INTERNAL_BIT = BIT(1),
  58. HOST_CSTATE_BIT = BIT(2),
  59. };
  60. #ifdef CONFIG_CNSS2_DEBUG
  61. static bool ignore_qmi_failure;
  62. #define CNSS_QMI_ASSERT() CNSS_ASSERT(ignore_qmi_failure)
  63. void cnss_ignore_qmi_failure(bool ignore)
  64. {
  65. ignore_qmi_failure = ignore;
  66. }
  67. #else
  68. #define CNSS_QMI_ASSERT() do { } while (0)
  69. void cnss_ignore_qmi_failure(bool ignore) { }
  70. #endif
  71. static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode)
  72. {
  73. switch (mode) {
  74. case CNSS_MISSION:
  75. return "MISSION";
  76. case CNSS_FTM:
  77. return "FTM";
  78. case CNSS_EPPING:
  79. return "EPPING";
  80. case CNSS_WALTEST:
  81. return "WALTEST";
  82. case CNSS_OFF:
  83. return "OFF";
  84. case CNSS_CCPM:
  85. return "CCPM";
  86. case CNSS_QVIT:
  87. return "QVIT";
  88. case CNSS_CALIBRATION:
  89. return "CALIBRATION";
  90. default:
  91. return "UNKNOWN";
  92. }
  93. }
  94. static int qmi_send_wait(struct qmi_handle *qmi, void *req, void *rsp,
  95. struct qmi_elem_info *req_ei,
  96. struct qmi_elem_info *rsp_ei,
  97. int req_id, size_t req_len,
  98. unsigned long timeout)
  99. {
  100. struct qmi_txn txn;
  101. int ret;
  102. char *err_msg;
  103. struct qmi_response_type_v01 *resp = rsp;
  104. ret = qmi_txn_init(qmi, &txn, rsp_ei, rsp);
  105. if (ret < 0) {
  106. err_msg = "Qmi fail: fail to init txn,";
  107. goto out;
  108. }
  109. ret = qmi_send_request(qmi, NULL, &txn, req_id,
  110. req_len, req_ei, req);
  111. if (ret < 0) {
  112. qmi_txn_cancel(&txn);
  113. err_msg = "Qmi fail: fail to send req,";
  114. goto out;
  115. }
  116. ret = qmi_txn_wait(&txn, timeout);
  117. if (ret < 0) {
  118. err_msg = "Qmi fail: wait timeout,";
  119. goto out;
  120. } else if (resp->result != QMI_RESULT_SUCCESS_V01) {
  121. err_msg = "Qmi fail: request rejected,";
  122. cnss_pr_err("Qmi fail: respons with error:%d\n",
  123. resp->error);
  124. ret = -resp->result;
  125. goto out;
  126. }
  127. cnss_pr_dbg("req %x success\n", req_id);
  128. return 0;
  129. out:
  130. cnss_pr_err("%s req %x, ret %d\n", err_msg, req_id, ret);
  131. return ret;
  132. }
  133. static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv)
  134. {
  135. struct wlfw_ind_register_req_msg_v01 *req;
  136. struct wlfw_ind_register_resp_msg_v01 *resp;
  137. struct qmi_txn txn;
  138. int ret = 0;
  139. cnss_pr_dbg("Sending indication register message, state: 0x%lx\n",
  140. plat_priv->driver_state);
  141. req = kzalloc(sizeof(*req), GFP_KERNEL);
  142. if (!req)
  143. return -ENOMEM;
  144. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  145. if (!resp) {
  146. kfree(req);
  147. return -ENOMEM;
  148. }
  149. req->client_id_valid = 1;
  150. req->client_id = WLFW_CLIENT_ID;
  151. req->request_mem_enable_valid = 1;
  152. req->request_mem_enable = 1;
  153. req->fw_mem_ready_enable_valid = 1;
  154. req->fw_mem_ready_enable = 1;
  155. /* fw_ready indication is replaced by fw_init_done in HST/HSP */
  156. req->fw_init_done_enable_valid = 1;
  157. req->fw_init_done_enable = 1;
  158. req->pin_connect_result_enable_valid = 1;
  159. req->pin_connect_result_enable = 1;
  160. req->cal_done_enable_valid = 1;
  161. req->cal_done_enable = 1;
  162. req->qdss_trace_req_mem_enable_valid = 1;
  163. req->qdss_trace_req_mem_enable = 1;
  164. req->qdss_trace_save_enable_valid = 1;
  165. req->qdss_trace_save_enable = 1;
  166. req->qdss_trace_free_enable_valid = 1;
  167. req->qdss_trace_free_enable = 1;
  168. req->respond_get_info_enable_valid = 1;
  169. req->respond_get_info_enable = 1;
  170. req->wfc_call_twt_config_enable_valid = 1;
  171. req->wfc_call_twt_config_enable = 1;
  172. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  173. wlfw_ind_register_resp_msg_v01_ei, resp);
  174. if (ret < 0) {
  175. cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n",
  176. ret);
  177. goto out;
  178. }
  179. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  180. QMI_WLFW_IND_REGISTER_REQ_V01,
  181. WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN,
  182. wlfw_ind_register_req_msg_v01_ei, req);
  183. if (ret < 0) {
  184. qmi_txn_cancel(&txn);
  185. cnss_pr_err("Failed to send indication register request, err: %d\n",
  186. ret);
  187. goto out;
  188. }
  189. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  190. if (ret < 0) {
  191. cnss_pr_err("Failed to wait for response of indication register request, err: %d\n",
  192. ret);
  193. goto out;
  194. }
  195. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  196. cnss_pr_err("Indication register request failed, result: %d, err: %d\n",
  197. resp->resp.result, resp->resp.error);
  198. ret = -resp->resp.result;
  199. goto out;
  200. }
  201. if (resp->fw_status_valid) {
  202. if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) {
  203. ret = -EALREADY;
  204. goto qmi_registered;
  205. }
  206. }
  207. kfree(req);
  208. kfree(resp);
  209. return 0;
  210. out:
  211. CNSS_QMI_ASSERT();
  212. qmi_registered:
  213. kfree(req);
  214. kfree(resp);
  215. return ret;
  216. }
  217. static void cnss_wlfw_host_cap_parse_mlo(struct cnss_plat_data *plat_priv,
  218. struct wlfw_host_cap_req_msg_v01 *req)
  219. {
  220. if (plat_priv->device_id == KIWI_DEVICE_ID ||
  221. plat_priv->device_id == MANGO_DEVICE_ID ||
  222. plat_priv->device_id == PEACH_DEVICE_ID) {
  223. req->mlo_capable_valid = 1;
  224. req->mlo_capable = 1;
  225. req->mlo_chip_id_valid = 1;
  226. req->mlo_chip_id = 0;
  227. req->mlo_group_id_valid = 1;
  228. req->mlo_group_id = 0;
  229. req->max_mlo_peer_valid = 1;
  230. /* Max peer number generally won't change for the same device
  231. * but needs to be synced with host driver.
  232. */
  233. req->max_mlo_peer = 32;
  234. req->mlo_num_chips_valid = 1;
  235. req->mlo_num_chips = 1;
  236. req->mlo_chip_info_valid = 1;
  237. req->mlo_chip_info[0].chip_id = 0;
  238. req->mlo_chip_info[0].num_local_links = 2;
  239. req->mlo_chip_info[0].hw_link_id[0] = 0;
  240. req->mlo_chip_info[0].hw_link_id[1] = 1;
  241. req->mlo_chip_info[0].valid_mlo_link_id[0] = 1;
  242. req->mlo_chip_info[0].valid_mlo_link_id[1] = 1;
  243. }
  244. }
  245. static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
  246. {
  247. struct wlfw_host_cap_req_msg_v01 *req;
  248. struct wlfw_host_cap_resp_msg_v01 *resp;
  249. struct qmi_txn txn;
  250. int ret = 0;
  251. u64 iova_start = 0, iova_size = 0,
  252. iova_ipa_start = 0, iova_ipa_size = 0;
  253. u64 feature_list = 0;
  254. cnss_pr_dbg("Sending host capability message, state: 0x%lx\n",
  255. plat_priv->driver_state);
  256. req = kzalloc(sizeof(*req), GFP_KERNEL);
  257. if (!req)
  258. return -ENOMEM;
  259. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  260. if (!resp) {
  261. kfree(req);
  262. return -ENOMEM;
  263. }
  264. req->num_clients_valid = 1;
  265. req->num_clients = 1;
  266. cnss_pr_dbg("Number of clients is %d\n", req->num_clients);
  267. req->wake_msi = cnss_bus_get_wake_irq(plat_priv);
  268. if (req->wake_msi) {
  269. cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi);
  270. req->wake_msi_valid = 1;
  271. }
  272. req->bdf_support_valid = 1;
  273. req->bdf_support = 1;
  274. req->m3_support_valid = 1;
  275. req->m3_support = 1;
  276. req->m3_cache_support_valid = 1;
  277. req->m3_cache_support = 1;
  278. req->cal_done_valid = 1;
  279. req->cal_done = plat_priv->cal_done;
  280. cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);
  281. if (plat_priv->sleep_clk) {
  282. req->nm_modem_valid = 1;
  283. /* Notify firmware about the sleep clock selection,
  284. * nm_modem_bit[1] is used for this purpose.
  285. */
  286. req->nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT;
  287. }
  288. if (plat_priv->supported_link_speed) {
  289. req->pcie_link_info_valid = 1;
  290. req->pcie_link_info.pci_link_speed =
  291. plat_priv->supported_link_speed;
  292. cnss_pr_dbg("Supported link speed in Host Cap %d\n",
  293. plat_priv->supported_link_speed);
  294. }
  295. if (cnss_bus_is_smmu_s1_enabled(plat_priv) &&
  296. !cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
  297. !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
  298. &iova_ipa_size)) {
  299. req->ddr_range_valid = 1;
  300. req->ddr_range[0].start = iova_start;
  301. req->ddr_range[0].size = iova_size + iova_ipa_size;
  302. cnss_pr_dbg("Sending iova starting 0x%llx with size 0x%llx\n",
  303. req->ddr_range[0].start, req->ddr_range[0].size);
  304. }
  305. req->host_build_type_valid = 1;
  306. req->host_build_type = cnss_get_host_build_type();
  307. cnss_wlfw_host_cap_parse_mlo(plat_priv, req);
  308. ret = cnss_get_feature_list(plat_priv, &feature_list);
  309. if (!ret) {
  310. req->feature_list_valid = 1;
  311. req->feature_list = feature_list;
  312. cnss_pr_dbg("Sending feature list 0x%llx\n",
  313. req->feature_list);
  314. }
  315. if (cnss_get_platform_name(plat_priv, req->platform_name,
  316. QMI_WLFW_MAX_PLATFORM_NAME_LEN_V01))
  317. req->platform_name_valid = 1;
  318. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  319. wlfw_host_cap_resp_msg_v01_ei, resp);
  320. if (ret < 0) {
  321. cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n",
  322. ret);
  323. goto out;
  324. }
  325. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  326. QMI_WLFW_HOST_CAP_REQ_V01,
  327. WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  328. wlfw_host_cap_req_msg_v01_ei, req);
  329. if (ret < 0) {
  330. qmi_txn_cancel(&txn);
  331. cnss_pr_err("Failed to send host capability request, err: %d\n",
  332. ret);
  333. goto out;
  334. }
  335. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  336. if (ret < 0) {
  337. cnss_pr_err("Failed to wait for response of host capability request, err: %d\n",
  338. ret);
  339. goto out;
  340. }
  341. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  342. cnss_pr_err("Host capability request failed, result: %d, err: %d\n",
  343. resp->resp.result, resp->resp.error);
  344. ret = -resp->resp.result;
  345. goto out;
  346. }
  347. kfree(req);
  348. kfree(resp);
  349. return 0;
  350. out:
  351. CNSS_QMI_ASSERT();
  352. kfree(req);
  353. kfree(resp);
  354. return ret;
  355. }
  356. int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv)
  357. {
  358. struct wlfw_respond_mem_req_msg_v01 *req;
  359. struct wlfw_respond_mem_resp_msg_v01 *resp;
  360. struct qmi_txn txn;
  361. struct cnss_fw_mem *fw_mem = plat_priv->fw_mem;
  362. int ret = 0, i;
  363. cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n",
  364. plat_priv->driver_state);
  365. req = kzalloc(sizeof(*req), GFP_KERNEL);
  366. if (!req)
  367. return -ENOMEM;
  368. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  369. if (!resp) {
  370. kfree(req);
  371. return -ENOMEM;
  372. }
  373. if (plat_priv->fw_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  374. cnss_pr_err("Invalid seg len %u\n", plat_priv->fw_mem_seg_len);
  375. ret = -EINVAL;
  376. goto out;
  377. }
  378. req->mem_seg_len = plat_priv->fw_mem_seg_len;
  379. for (i = 0; i < req->mem_seg_len; i++) {
  380. if (!fw_mem[i].pa || !fw_mem[i].size) {
  381. if (fw_mem[i].type == 0) {
  382. cnss_pr_err("Invalid memory for FW type, segment = %d\n",
  383. i);
  384. ret = -EINVAL;
  385. goto out;
  386. }
  387. cnss_pr_err("Memory for FW is not available for type: %u\n",
  388. fw_mem[i].type);
  389. ret = -ENOMEM;
  390. goto out;
  391. }
  392. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  393. fw_mem[i].va, &fw_mem[i].pa,
  394. fw_mem[i].size, fw_mem[i].type);
  395. req->mem_seg[i].addr = fw_mem[i].pa;
  396. req->mem_seg[i].size = fw_mem[i].size;
  397. req->mem_seg[i].type = fw_mem[i].type;
  398. }
  399. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  400. wlfw_respond_mem_resp_msg_v01_ei, resp);
  401. if (ret < 0) {
  402. cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n",
  403. ret);
  404. goto out;
  405. }
  406. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  407. QMI_WLFW_RESPOND_MEM_REQ_V01,
  408. WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN,
  409. wlfw_respond_mem_req_msg_v01_ei, req);
  410. if (ret < 0) {
  411. qmi_txn_cancel(&txn);
  412. cnss_pr_err("Failed to send respond memory request, err: %d\n",
  413. ret);
  414. goto out;
  415. }
  416. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  417. if (ret < 0) {
  418. cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n",
  419. ret);
  420. goto out;
  421. }
  422. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  423. cnss_pr_err("Respond memory request failed, result: %d, err: %d\n",
  424. resp->resp.result, resp->resp.error);
  425. ret = -resp->resp.result;
  426. goto out;
  427. }
  428. kfree(req);
  429. kfree(resp);
  430. return 0;
  431. out:
  432. CNSS_QMI_ASSERT();
  433. kfree(req);
  434. kfree(resp);
  435. return ret;
  436. }
  437. int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv)
  438. {
  439. struct wlfw_cap_req_msg_v01 *req;
  440. struct wlfw_cap_resp_msg_v01 *resp;
  441. struct qmi_txn txn;
  442. char *fw_build_timestamp;
  443. int ret = 0, i;
  444. cnss_pr_dbg("Sending target capability message, state: 0x%lx\n",
  445. plat_priv->driver_state);
  446. req = kzalloc(sizeof(*req), GFP_KERNEL);
  447. if (!req)
  448. return -ENOMEM;
  449. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  450. if (!resp) {
  451. kfree(req);
  452. return -ENOMEM;
  453. }
  454. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  455. wlfw_cap_resp_msg_v01_ei, resp);
  456. if (ret < 0) {
  457. cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n",
  458. ret);
  459. goto out;
  460. }
  461. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  462. QMI_WLFW_CAP_REQ_V01,
  463. WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN,
  464. wlfw_cap_req_msg_v01_ei, req);
  465. if (ret < 0) {
  466. qmi_txn_cancel(&txn);
  467. cnss_pr_err("Failed to send respond target capability request, err: %d\n",
  468. ret);
  469. goto out;
  470. }
  471. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  472. if (ret < 0) {
  473. cnss_pr_err("Failed to wait for response of target capability request, err: %d\n",
  474. ret);
  475. goto out;
  476. }
  477. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  478. cnss_pr_err("Target capability request failed, result: %d, err: %d\n",
  479. resp->resp.result, resp->resp.error);
  480. ret = -resp->resp.result;
  481. goto out;
  482. }
  483. if (resp->chip_info_valid) {
  484. plat_priv->chip_info.chip_id = resp->chip_info.chip_id;
  485. plat_priv->chip_info.chip_family = resp->chip_info.chip_family;
  486. }
  487. if (resp->board_info_valid)
  488. plat_priv->board_info.board_id = resp->board_info.board_id;
  489. else
  490. plat_priv->board_info.board_id = 0xFF;
  491. if (resp->soc_info_valid)
  492. plat_priv->soc_info.soc_id = resp->soc_info.soc_id;
  493. if (resp->fw_version_info_valid) {
  494. plat_priv->fw_version_info.fw_version =
  495. resp->fw_version_info.fw_version;
  496. fw_build_timestamp = resp->fw_version_info.fw_build_timestamp;
  497. fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0';
  498. strlcpy(plat_priv->fw_version_info.fw_build_timestamp,
  499. resp->fw_version_info.fw_build_timestamp,
  500. QMI_WLFW_MAX_TIMESTAMP_LEN + 1);
  501. }
  502. if (resp->fw_build_id_valid) {
  503. resp->fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN] = '\0';
  504. strlcpy(plat_priv->fw_build_id, resp->fw_build_id,
  505. QMI_WLFW_MAX_BUILD_ID_LEN + 1);
  506. }
  507. /* FW will send aop retention volatage for qca6490 */
  508. if (resp->voltage_mv_valid) {
  509. plat_priv->cpr_info.voltage = resp->voltage_mv;
  510. cnss_pr_dbg("Voltage for CPR: %dmV\n",
  511. plat_priv->cpr_info.voltage);
  512. cnss_update_cpr_info(plat_priv);
  513. }
  514. if (resp->time_freq_hz_valid) {
  515. plat_priv->device_freq_hz = resp->time_freq_hz;
  516. cnss_pr_dbg("Device frequency is %d HZ\n",
  517. plat_priv->device_freq_hz);
  518. }
  519. if (resp->otp_version_valid)
  520. plat_priv->otp_version = resp->otp_version;
  521. if (resp->dev_mem_info_valid) {
  522. for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) {
  523. plat_priv->dev_mem_info[i].start =
  524. resp->dev_mem_info[i].start;
  525. plat_priv->dev_mem_info[i].size =
  526. resp->dev_mem_info[i].size;
  527. cnss_pr_buf("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n",
  528. i, plat_priv->dev_mem_info[i].start,
  529. plat_priv->dev_mem_info[i].size);
  530. }
  531. }
  532. if (resp->fw_caps_valid) {
  533. plat_priv->fw_pcie_gen_switch =
  534. !!(resp->fw_caps & QMI_WLFW_HOST_PCIE_GEN_SWITCH_V01);
  535. plat_priv->fw_aux_uc_support =
  536. !!(resp->fw_caps & QMI_WLFW_AUX_UC_SUPPORT_V01);
  537. cnss_pr_dbg("FW aux uc support capability: %d\n",
  538. plat_priv->fw_aux_uc_support);
  539. plat_priv->fw_caps = resp->fw_caps;
  540. }
  541. if (resp->hang_data_length_valid &&
  542. resp->hang_data_length &&
  543. resp->hang_data_length <= WLFW_MAX_HANG_EVENT_DATA_SIZE)
  544. plat_priv->hang_event_data_len = resp->hang_data_length;
  545. else
  546. plat_priv->hang_event_data_len = 0;
  547. if (resp->hang_data_addr_offset_valid)
  548. plat_priv->hang_data_addr_offset = resp->hang_data_addr_offset;
  549. else
  550. plat_priv->hang_data_addr_offset = 0;
  551. if (resp->hwid_bitmap_valid)
  552. plat_priv->hwid_bitmap = resp->hwid_bitmap;
  553. if (resp->ol_cpr_cfg_valid)
  554. cnss_aop_ol_cpr_cfg_setup(plat_priv, &resp->ol_cpr_cfg);
  555. /* Disable WLAN PDC in AOP firmware for boards which support on chip PMIC
  556. * so AOP will ignore SW_CTRL changes and do not update regulator votes.
  557. **/
  558. for (i = 0; i < plat_priv->on_chip_pmic_devices_count; i++) {
  559. if (plat_priv->board_info.board_id ==
  560. plat_priv->on_chip_pmic_board_ids[i]) {
  561. cnss_pr_dbg("Disabling WLAN PDC for board_id: %02x\n",
  562. plat_priv->board_info.board_id);
  563. ret = cnss_aop_send_msg(plat_priv,
  564. "{class: wlan_pdc, ss: rf, res: pdc, enable: 0}");
  565. if (ret < 0)
  566. cnss_pr_dbg("Failed to Send AOP Msg");
  567. break;
  568. }
  569. }
  570. cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, otp_version: 0x%x\n",
  571. plat_priv->chip_info.chip_id,
  572. plat_priv->chip_info.chip_family,
  573. plat_priv->board_info.board_id, plat_priv->soc_info.soc_id,
  574. plat_priv->otp_version);
  575. cnss_pr_dbg("fw_version: 0x%x, fw_build_timestamp: %s, fw_build_id: %s, hwid_bitmap:0x%x\n",
  576. plat_priv->fw_version_info.fw_version,
  577. plat_priv->fw_version_info.fw_build_timestamp,
  578. plat_priv->fw_build_id,
  579. plat_priv->hwid_bitmap);
  580. cnss_pr_dbg("Hang event params, Length: 0x%x, Offset Address: 0x%x\n",
  581. plat_priv->hang_event_data_len,
  582. plat_priv->hang_data_addr_offset);
  583. kfree(req);
  584. kfree(resp);
  585. return 0;
  586. out:
  587. CNSS_QMI_ASSERT();
  588. kfree(req);
  589. kfree(resp);
  590. return ret;
  591. }
  592. static char *cnss_bdf_type_to_str(enum cnss_bdf_type bdf_type)
  593. {
  594. switch (bdf_type) {
  595. case CNSS_BDF_BIN:
  596. case CNSS_BDF_ELF:
  597. return "BDF";
  598. case CNSS_BDF_REGDB:
  599. return "REGDB";
  600. case CNSS_BDF_HDS:
  601. return "HDS";
  602. default:
  603. return "UNKNOWN";
  604. }
  605. }
  606. static int cnss_get_bdf_file_name(struct cnss_plat_data *plat_priv,
  607. u32 bdf_type, char *filename,
  608. u32 filename_len)
  609. {
  610. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  611. int ret = 0;
  612. switch (bdf_type) {
  613. case CNSS_BDF_ELF:
  614. /* Board ID will be equal or less than 0xFF in GF mask case */
  615. if (plat_priv->board_info.board_id == 0xFF) {
  616. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  617. snprintf(filename_tmp, filename_len,
  618. ELF_BDF_FILE_NAME_GF);
  619. else
  620. snprintf(filename_tmp, filename_len,
  621. ELF_BDF_FILE_NAME);
  622. } else if (plat_priv->board_info.board_id < 0xFF) {
  623. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  624. snprintf(filename_tmp, filename_len,
  625. ELF_BDF_FILE_NAME_GF_PREFIX "%02x",
  626. plat_priv->board_info.board_id);
  627. else
  628. snprintf(filename_tmp, filename_len,
  629. ELF_BDF_FILE_NAME_PREFIX "%02x",
  630. plat_priv->board_info.board_id);
  631. } else {
  632. snprintf(filename_tmp, filename_len,
  633. BDF_FILE_NAME_PREFIX "%02x.e%02x",
  634. plat_priv->board_info.board_id >> 8 & 0xFF,
  635. plat_priv->board_info.board_id & 0xFF);
  636. }
  637. break;
  638. case CNSS_BDF_BIN:
  639. if (plat_priv->board_info.board_id == 0xFF) {
  640. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  641. snprintf(filename_tmp, filename_len,
  642. BIN_BDF_FILE_NAME_GF);
  643. else
  644. snprintf(filename_tmp, filename_len,
  645. BIN_BDF_FILE_NAME);
  646. } else if (plat_priv->board_info.board_id < 0xFF) {
  647. if (plat_priv->chip_info.chip_id & CHIP_ID_GF_MASK)
  648. snprintf(filename_tmp, filename_len,
  649. BIN_BDF_FILE_NAME_GF_PREFIX "%02x",
  650. plat_priv->board_info.board_id);
  651. else
  652. snprintf(filename_tmp, filename_len,
  653. BIN_BDF_FILE_NAME_PREFIX "%02x",
  654. plat_priv->board_info.board_id);
  655. } else {
  656. snprintf(filename_tmp, filename_len,
  657. BDF_FILE_NAME_PREFIX "%02x.b%02x",
  658. plat_priv->board_info.board_id >> 8 & 0xFF,
  659. plat_priv->board_info.board_id & 0xFF);
  660. }
  661. break;
  662. case CNSS_BDF_REGDB:
  663. snprintf(filename_tmp, filename_len, REGDB_FILE_NAME);
  664. break;
  665. case CNSS_BDF_HDS:
  666. snprintf(filename_tmp, filename_len, HDS_FILE_NAME);
  667. break;
  668. default:
  669. cnss_pr_err("Invalid BDF type: %d\n",
  670. plat_priv->ctrl_params.bdf_type);
  671. ret = -EINVAL;
  672. break;
  673. }
  674. if (!ret)
  675. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  676. return ret;
  677. }
  678. int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv,
  679. u32 bdf_type)
  680. {
  681. struct wlfw_bdf_download_req_msg_v01 *req;
  682. struct wlfw_bdf_download_resp_msg_v01 *resp;
  683. struct qmi_txn txn;
  684. char filename[MAX_FIRMWARE_NAME_LEN];
  685. const struct firmware *fw_entry = NULL;
  686. const u8 *temp;
  687. unsigned int remaining;
  688. int ret = 0;
  689. cnss_pr_dbg("Sending QMI_WLFW_BDF_DOWNLOAD_REQ_V01 message for bdf_type: %d (%s), state: 0x%lx\n",
  690. bdf_type, cnss_bdf_type_to_str(bdf_type), plat_priv->driver_state);
  691. req = kzalloc(sizeof(*req), GFP_KERNEL);
  692. if (!req)
  693. return -ENOMEM;
  694. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  695. if (!resp) {
  696. kfree(req);
  697. return -ENOMEM;
  698. }
  699. ret = cnss_get_bdf_file_name(plat_priv, bdf_type,
  700. filename, sizeof(filename));
  701. if (ret)
  702. goto err_req_fw;
  703. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n", filename);
  704. if (bdf_type == CNSS_BDF_REGDB)
  705. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  706. filename);
  707. else
  708. ret = firmware_request_nowarn(&fw_entry, filename,
  709. &plat_priv->plat_dev->dev);
  710. if (ret) {
  711. cnss_pr_err("Failed to load %s: %s, ret: %d\n",
  712. cnss_bdf_type_to_str(bdf_type), filename, ret);
  713. goto err_req_fw;
  714. }
  715. temp = fw_entry->data;
  716. remaining = fw_entry->size;
  717. cnss_pr_dbg("Downloading %s: %s, size: %u\n",
  718. cnss_bdf_type_to_str(bdf_type), filename, remaining);
  719. while (remaining) {
  720. req->valid = 1;
  721. req->file_id_valid = 1;
  722. req->file_id = plat_priv->board_info.board_id;
  723. req->total_size_valid = 1;
  724. req->total_size = remaining;
  725. req->seg_id_valid = 1;
  726. req->data_valid = 1;
  727. req->end_valid = 1;
  728. req->bdf_type_valid = 1;
  729. req->bdf_type = bdf_type;
  730. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  731. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  732. } else {
  733. req->data_len = remaining;
  734. req->end = 1;
  735. }
  736. memcpy(req->data, temp, req->data_len);
  737. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  738. wlfw_bdf_download_resp_msg_v01_ei, resp);
  739. if (ret < 0) {
  740. cnss_pr_err("Failed to initialize txn for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  741. cnss_bdf_type_to_str(bdf_type), ret);
  742. goto err_send;
  743. }
  744. ret = qmi_send_request
  745. (&plat_priv->qmi_wlfw, NULL, &txn,
  746. QMI_WLFW_BDF_DOWNLOAD_REQ_V01,
  747. WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  748. wlfw_bdf_download_req_msg_v01_ei, req);
  749. if (ret < 0) {
  750. qmi_txn_cancel(&txn);
  751. cnss_pr_err("Failed to send QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, error: %d\n",
  752. cnss_bdf_type_to_str(bdf_type), ret);
  753. goto err_send;
  754. }
  755. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  756. if (ret < 0) {
  757. cnss_pr_err("Timeout while waiting for FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s, err: %d\n",
  758. cnss_bdf_type_to_str(bdf_type), ret);
  759. goto err_send;
  760. }
  761. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  762. cnss_pr_err("FW response for QMI_WLFW_BDF_DOWNLOAD_REQ_V01 request for %s failed, result: %d, err: %d\n",
  763. cnss_bdf_type_to_str(bdf_type), resp->resp.result,
  764. resp->resp.error);
  765. ret = -resp->resp.result;
  766. goto err_send;
  767. }
  768. remaining -= req->data_len;
  769. temp += req->data_len;
  770. req->seg_id++;
  771. }
  772. release_firmware(fw_entry);
  773. if (resp->host_bdf_data_valid) {
  774. /* QCA6490 enable S3E regulator for IPA configuration only */
  775. if (!(resp->host_bdf_data & QMI_WLFW_HW_XPA_V01))
  776. cnss_enable_int_pow_amp_vreg(plat_priv);
  777. plat_priv->cbc_file_download =
  778. resp->host_bdf_data & QMI_WLFW_CBC_FILE_DOWNLOAD_V01;
  779. cnss_pr_info("Host BDF config: HW_XPA: %d CalDB: %d\n",
  780. resp->host_bdf_data & QMI_WLFW_HW_XPA_V01,
  781. plat_priv->cbc_file_download);
  782. }
  783. kfree(req);
  784. kfree(resp);
  785. return 0;
  786. err_send:
  787. release_firmware(fw_entry);
  788. err_req_fw:
  789. if (!(bdf_type == CNSS_BDF_REGDB ||
  790. test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state) ||
  791. ret == -EAGAIN))
  792. CNSS_QMI_ASSERT();
  793. kfree(req);
  794. kfree(resp);
  795. return ret;
  796. }
  797. int cnss_wlfw_tme_patch_dnld_send_sync(struct cnss_plat_data *plat_priv,
  798. enum wlfw_tme_lite_file_type_v01 file)
  799. {
  800. struct wlfw_tme_lite_info_req_msg_v01 *req;
  801. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  802. struct qmi_txn txn;
  803. struct cnss_fw_mem *tme_lite_mem = &plat_priv->tme_lite_mem;
  804. int ret = 0;
  805. cnss_pr_dbg("Sending TME patch information message, state: 0x%lx\n",
  806. plat_priv->driver_state);
  807. if (plat_priv->device_id != PEACH_DEVICE_ID)
  808. return 0;
  809. req = kzalloc(sizeof(*req), GFP_KERNEL);
  810. if (!req)
  811. return -ENOMEM;
  812. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  813. if (!resp) {
  814. kfree(req);
  815. return -ENOMEM;
  816. }
  817. if (!tme_lite_mem->pa || !tme_lite_mem->size) {
  818. cnss_pr_err("Memory for TME patch is not available\n");
  819. ret = -ENOMEM;
  820. goto out;
  821. }
  822. cnss_pr_dbg("TME-L patch memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  823. tme_lite_mem->va, &tme_lite_mem->pa, tme_lite_mem->size);
  824. req->tme_file = file;
  825. req->addr = plat_priv->tme_lite_mem.pa;
  826. req->size = plat_priv->tme_lite_mem.size;
  827. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  828. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  829. if (ret < 0) {
  830. cnss_pr_err("Failed to initialize txn for TME patch information request, err: %d\n",
  831. ret);
  832. goto out;
  833. }
  834. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  835. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  836. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  837. wlfw_tme_lite_info_req_msg_v01_ei, req);
  838. if (ret < 0) {
  839. qmi_txn_cancel(&txn);
  840. cnss_pr_err("Failed to send TME patch information request, err: %d\n",
  841. ret);
  842. goto out;
  843. }
  844. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  845. if (ret < 0) {
  846. cnss_pr_err("Failed to wait for response of TME patch information request, err: %d\n",
  847. ret);
  848. goto out;
  849. }
  850. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  851. cnss_pr_err("TME patch information request failed, result: %d, err: %d\n",
  852. resp->resp.result, resp->resp.error);
  853. ret = -resp->resp.result;
  854. goto out;
  855. }
  856. kfree(req);
  857. kfree(resp);
  858. return 0;
  859. out:
  860. kfree(req);
  861. kfree(resp);
  862. return ret;
  863. }
  864. int cnss_wlfw_tme_opt_file_dnld_send_sync(struct cnss_plat_data *plat_priv,
  865. enum wlfw_tme_lite_file_type_v01 file)
  866. {
  867. struct wlfw_tme_lite_info_req_msg_v01 *req;
  868. struct wlfw_tme_lite_info_resp_msg_v01 *resp;
  869. struct qmi_txn txn;
  870. struct cnss_fw_mem *tme_opt_file_mem = NULL;
  871. char *file_name = NULL;
  872. int ret = 0;
  873. if (plat_priv->device_id != PEACH_DEVICE_ID)
  874. return 0;
  875. cnss_pr_dbg("Sending TME opt file information message, state: 0x%lx\n",
  876. plat_priv->driver_state);
  877. req = kzalloc(sizeof(*req), GFP_KERNEL);
  878. if (!req)
  879. return -ENOMEM;
  880. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  881. if (!resp) {
  882. kfree(req);
  883. return -ENOMEM;
  884. }
  885. if (file == WLFW_TME_LITE_OEM_FUSE_FILE_V01) {
  886. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[0];
  887. file_name = TME_OEM_FUSE_FILE_NAME;
  888. } else if (file == WLFW_TME_LITE_RPR_FILE_V01) {
  889. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[1];
  890. file_name = TME_RPR_FILE_NAME;
  891. } else if (file == WLFW_TME_LITE_DPR_FILE_V01) {
  892. tme_opt_file_mem = &plat_priv->tme_opt_file_mem[2];
  893. file_name = TME_DPR_FILE_NAME;
  894. }
  895. if (!tme_opt_file_mem || !tme_opt_file_mem->pa ||
  896. !tme_opt_file_mem->size) {
  897. cnss_pr_err("Memory for TME opt file is not available\n");
  898. ret = -ENOMEM;
  899. goto out;
  900. }
  901. cnss_pr_dbg("TME opt file %s memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  902. file_name, tme_opt_file_mem->va, &tme_opt_file_mem->pa, tme_opt_file_mem->size);
  903. req->tme_file = file;
  904. req->addr = tme_opt_file_mem->pa;
  905. req->size = tme_opt_file_mem->size;
  906. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  907. wlfw_tme_lite_info_resp_msg_v01_ei, resp);
  908. if (ret < 0) {
  909. cnss_pr_err("Failed to initialize txn for TME opt file information request, err: %d\n",
  910. ret);
  911. goto out;
  912. }
  913. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  914. QMI_WLFW_TME_LITE_INFO_REQ_V01,
  915. WLFW_TME_LITE_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  916. wlfw_tme_lite_info_req_msg_v01_ei, req);
  917. if (ret < 0) {
  918. qmi_txn_cancel(&txn);
  919. cnss_pr_err("Failed to send TME opt file information request, err: %d\n",
  920. ret);
  921. goto out;
  922. }
  923. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  924. if (ret < 0) {
  925. cnss_pr_err("Failed to wait for response of TME opt file information request, err: %d\n",
  926. ret);
  927. goto out;
  928. }
  929. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  930. ret = -resp->resp.result;
  931. if (resp->resp.error == QMI_ERR_HARDWARE_RESTRICTED_V01) {
  932. cnss_pr_err("TME Power On failed\n");
  933. goto out;
  934. } else if (resp->resp.error == QMI_ERR_ENOMEM_V01) {
  935. cnss_pr_err("malloc SRAM failed\n");
  936. goto out;
  937. }
  938. cnss_pr_err("TME opt file information request failed, result: %d, err: %d\n",
  939. resp->resp.result, resp->resp.error);
  940. goto out;
  941. }
  942. kfree(req);
  943. kfree(resp);
  944. return 0;
  945. out:
  946. CNSS_QMI_ASSERT();
  947. kfree(req);
  948. kfree(resp);
  949. return ret;
  950. }
  951. int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv)
  952. {
  953. struct wlfw_m3_info_req_msg_v01 *req;
  954. struct wlfw_m3_info_resp_msg_v01 *resp;
  955. struct qmi_txn txn;
  956. struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem;
  957. int ret = 0;
  958. cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n",
  959. plat_priv->driver_state);
  960. req = kzalloc(sizeof(*req), GFP_KERNEL);
  961. if (!req)
  962. return -ENOMEM;
  963. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  964. if (!resp) {
  965. kfree(req);
  966. return -ENOMEM;
  967. }
  968. if (!m3_mem->pa || !m3_mem->size) {
  969. cnss_pr_err("Memory for M3 is not available\n");
  970. ret = -ENOMEM;
  971. goto out;
  972. }
  973. cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  974. m3_mem->va, &m3_mem->pa, m3_mem->size);
  975. req->addr = plat_priv->m3_mem.pa;
  976. req->size = plat_priv->m3_mem.size;
  977. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  978. wlfw_m3_info_resp_msg_v01_ei, resp);
  979. if (ret < 0) {
  980. cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n",
  981. ret);
  982. goto out;
  983. }
  984. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  985. QMI_WLFW_M3_INFO_REQ_V01,
  986. WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  987. wlfw_m3_info_req_msg_v01_ei, req);
  988. if (ret < 0) {
  989. qmi_txn_cancel(&txn);
  990. cnss_pr_err("Failed to send M3 information request, err: %d\n",
  991. ret);
  992. goto out;
  993. }
  994. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  995. if (ret < 0) {
  996. cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n",
  997. ret);
  998. goto out;
  999. }
  1000. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1001. cnss_pr_err("M3 information request failed, result: %d, err: %d\n",
  1002. resp->resp.result, resp->resp.error);
  1003. ret = -resp->resp.result;
  1004. goto out;
  1005. }
  1006. kfree(req);
  1007. kfree(resp);
  1008. return 0;
  1009. out:
  1010. CNSS_QMI_ASSERT();
  1011. kfree(req);
  1012. kfree(resp);
  1013. return ret;
  1014. }
  1015. int cnss_wlfw_aux_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1016. {
  1017. struct wlfw_aux_uc_info_req_msg_v01 *req;
  1018. struct wlfw_aux_uc_info_resp_msg_v01 *resp;
  1019. struct qmi_txn txn;
  1020. struct cnss_fw_mem *aux_mem = &plat_priv->aux_mem;
  1021. int ret = 0;
  1022. cnss_pr_dbg("Sending QMI_WLFW_AUX_UC_INFO_REQ_V01 message, state: 0x%lx\n",
  1023. plat_priv->driver_state);
  1024. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1025. if (!req)
  1026. return -ENOMEM;
  1027. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1028. if (!resp) {
  1029. kfree(req);
  1030. return -ENOMEM;
  1031. }
  1032. if (!aux_mem->pa || !aux_mem->size) {
  1033. cnss_pr_err("Memory for AUX is not available\n");
  1034. ret = -ENOMEM;
  1035. goto out;
  1036. }
  1037. cnss_pr_dbg("AUX memory, va: 0x%pK, pa: %pa, size: 0x%zx\n",
  1038. aux_mem->va, &aux_mem->pa, aux_mem->size);
  1039. req->addr = plat_priv->aux_mem.pa;
  1040. req->size = plat_priv->aux_mem.size;
  1041. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1042. wlfw_aux_uc_info_resp_msg_v01_ei, resp);
  1043. if (ret < 0) {
  1044. cnss_pr_err("Failed to initialize txn for QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1045. ret);
  1046. goto out;
  1047. }
  1048. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1049. QMI_WLFW_AUX_UC_INFO_REQ_V01,
  1050. WLFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  1051. wlfw_aux_uc_info_req_msg_v01_ei, req);
  1052. if (ret < 0) {
  1053. qmi_txn_cancel(&txn);
  1054. cnss_pr_err("Failed to send QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1055. ret);
  1056. goto out;
  1057. }
  1058. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1059. if (ret < 0) {
  1060. cnss_pr_err("Failed to wait for response of QMI_WLFW_AUX_UC_INFO_REQ_V01 request, err: %d\n",
  1061. ret);
  1062. goto out;
  1063. }
  1064. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1065. cnss_pr_err("QMI_WLFW_AUX_UC_INFO_REQ_V01 request failed, result: %d, err: %d\n",
  1066. resp->resp.result, resp->resp.error);
  1067. ret = -resp->resp.result;
  1068. goto out;
  1069. }
  1070. kfree(req);
  1071. kfree(resp);
  1072. return 0;
  1073. out:
  1074. CNSS_QMI_ASSERT();
  1075. kfree(req);
  1076. kfree(resp);
  1077. return ret;
  1078. }
  1079. int cnss_wlfw_wlan_mac_req_send_sync(struct cnss_plat_data *plat_priv,
  1080. u8 *mac, u32 mac_len)
  1081. {
  1082. struct wlfw_mac_addr_req_msg_v01 req;
  1083. struct wlfw_mac_addr_resp_msg_v01 resp = {0};
  1084. struct qmi_txn txn;
  1085. int ret;
  1086. if (!plat_priv || !mac || mac_len != QMI_WLFW_MAC_ADDR_SIZE_V01)
  1087. return -EINVAL;
  1088. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1089. wlfw_mac_addr_resp_msg_v01_ei, &resp);
  1090. if (ret < 0) {
  1091. cnss_pr_err("Failed to initialize txn for mac req, err: %d\n",
  1092. ret);
  1093. ret = -EIO;
  1094. goto out;
  1095. }
  1096. cnss_pr_dbg("Sending WLAN mac req [%pM], state: 0x%lx\n",
  1097. mac, plat_priv->driver_state);
  1098. memcpy(req.mac_addr, mac, mac_len);
  1099. req.mac_addr_valid = 1;
  1100. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1101. QMI_WLFW_MAC_ADDR_REQ_V01,
  1102. WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN,
  1103. wlfw_mac_addr_req_msg_v01_ei, &req);
  1104. if (ret < 0) {
  1105. qmi_txn_cancel(&txn);
  1106. cnss_pr_err("Failed to send mac req, err: %d\n", ret);
  1107. ret = -EIO;
  1108. goto out;
  1109. }
  1110. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1111. if (ret < 0) {
  1112. cnss_pr_err("Failed to wait for resp of mac req, err: %d\n",
  1113. ret);
  1114. ret = -EIO;
  1115. goto out;
  1116. }
  1117. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1118. cnss_pr_err("WLAN mac req failed, result: %d, err: %d\n",
  1119. resp.resp.result);
  1120. ret = -resp.resp.result;
  1121. }
  1122. out:
  1123. return ret;
  1124. }
  1125. int cnss_wlfw_qdss_data_send_sync(struct cnss_plat_data *plat_priv, char *file_name,
  1126. u32 total_size)
  1127. {
  1128. int ret = 0;
  1129. struct wlfw_qdss_trace_data_req_msg_v01 *req;
  1130. struct wlfw_qdss_trace_data_resp_msg_v01 *resp;
  1131. unsigned char *p_qdss_trace_data_temp, *p_qdss_trace_data = NULL;
  1132. unsigned int remaining;
  1133. struct qmi_txn txn;
  1134. cnss_pr_dbg("%s\n", __func__);
  1135. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1136. if (!req)
  1137. return -ENOMEM;
  1138. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1139. if (!resp) {
  1140. kfree(req);
  1141. return -ENOMEM;
  1142. }
  1143. p_qdss_trace_data = kzalloc(total_size, GFP_KERNEL);
  1144. if (!p_qdss_trace_data) {
  1145. ret = ENOMEM;
  1146. goto end;
  1147. }
  1148. remaining = total_size;
  1149. p_qdss_trace_data_temp = p_qdss_trace_data;
  1150. while (remaining && resp->end == 0) {
  1151. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1152. wlfw_qdss_trace_data_resp_msg_v01_ei, resp);
  1153. if (ret < 0) {
  1154. cnss_pr_err("Fail to init txn for QDSS trace resp %d\n",
  1155. ret);
  1156. goto fail;
  1157. }
  1158. ret = qmi_send_request
  1159. (&plat_priv->qmi_wlfw, NULL, &txn,
  1160. QMI_WLFW_QDSS_TRACE_DATA_REQ_V01,
  1161. WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN,
  1162. wlfw_qdss_trace_data_req_msg_v01_ei, req);
  1163. if (ret < 0) {
  1164. qmi_txn_cancel(&txn);
  1165. cnss_pr_err("Fail to send QDSS trace data req %d\n",
  1166. ret);
  1167. goto fail;
  1168. }
  1169. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1170. if (ret < 0) {
  1171. cnss_pr_err("QDSS trace resp wait failed with rc %d\n",
  1172. ret);
  1173. goto fail;
  1174. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1175. cnss_pr_err("QMI QDSS trace request rejected, result:%d error:%d\n",
  1176. resp->resp.result, resp->resp.error);
  1177. ret = -resp->resp.result;
  1178. goto fail;
  1179. } else {
  1180. ret = 0;
  1181. }
  1182. cnss_pr_dbg("%s: response total size %d data len %d",
  1183. __func__, resp->total_size, resp->data_len);
  1184. if ((resp->total_size_valid == 1 &&
  1185. resp->total_size == total_size) &&
  1186. (resp->seg_id_valid == 1 && resp->seg_id == req->seg_id) &&
  1187. (resp->data_valid == 1 &&
  1188. resp->data_len <= QMI_WLFW_MAX_DATA_SIZE_V01) &&
  1189. resp->data_len <= remaining) {
  1190. memcpy(p_qdss_trace_data_temp,
  1191. resp->data, resp->data_len);
  1192. } else {
  1193. cnss_pr_err("%s: Unmatched qdss trace data, Expect total_size %u, seg_id %u, Recv total_size_valid %u, total_size %u, seg_id_valid %u, seg_id %u, data_len_valid %u, data_len %u",
  1194. __func__,
  1195. total_size, req->seg_id,
  1196. resp->total_size_valid,
  1197. resp->total_size,
  1198. resp->seg_id_valid,
  1199. resp->seg_id,
  1200. resp->data_valid,
  1201. resp->data_len);
  1202. ret = -1;
  1203. goto fail;
  1204. }
  1205. remaining -= resp->data_len;
  1206. p_qdss_trace_data_temp += resp->data_len;
  1207. req->seg_id++;
  1208. }
  1209. if (remaining == 0 && (resp->end_valid && resp->end)) {
  1210. ret = cnss_genl_send_msg(p_qdss_trace_data,
  1211. CNSS_GENL_MSG_TYPE_QDSS, file_name,
  1212. total_size);
  1213. if (ret < 0) {
  1214. cnss_pr_err("Fail to save QDSS trace data: %d\n",
  1215. ret);
  1216. ret = -1;
  1217. goto fail;
  1218. }
  1219. } else {
  1220. cnss_pr_err("%s: QDSS trace file corrupted: remaining %u, end_valid %u, end %u",
  1221. __func__,
  1222. remaining, resp->end_valid, resp->end);
  1223. ret = -1;
  1224. goto fail;
  1225. }
  1226. fail:
  1227. kfree(p_qdss_trace_data);
  1228. end:
  1229. kfree(req);
  1230. kfree(resp);
  1231. return ret;
  1232. }
  1233. void cnss_get_qdss_cfg_filename(struct cnss_plat_data *plat_priv,
  1234. char *filename, u32 filename_len,
  1235. bool fallback_file)
  1236. {
  1237. char filename_tmp[MAX_FIRMWARE_NAME_LEN];
  1238. char *build_str = QDSS_FILE_BUILD_STR;
  1239. if (fallback_file)
  1240. build_str = "";
  1241. if (plat_priv->device_version.major_version == FW_V2_NUMBER)
  1242. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1243. "_%s%s.cfg", build_str, HW_V2_NUMBER);
  1244. else
  1245. snprintf(filename_tmp, filename_len, QDSS_TRACE_CONFIG_FILE
  1246. "_%s%s.cfg", build_str, HW_V1_NUMBER);
  1247. cnss_bus_add_fw_prefix_name(plat_priv, filename, filename_tmp);
  1248. }
  1249. int cnss_wlfw_qdss_dnld_send_sync(struct cnss_plat_data *plat_priv)
  1250. {
  1251. struct wlfw_qdss_trace_config_download_req_msg_v01 *req;
  1252. struct wlfw_qdss_trace_config_download_resp_msg_v01 *resp;
  1253. struct qmi_txn txn;
  1254. const struct firmware *fw_entry = NULL;
  1255. const u8 *temp;
  1256. char qdss_cfg_filename[MAX_FIRMWARE_NAME_LEN];
  1257. unsigned int remaining;
  1258. int ret = 0;
  1259. cnss_pr_dbg("Sending QDSS config download message, state: 0x%lx\n",
  1260. plat_priv->driver_state);
  1261. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1262. if (!req)
  1263. return -ENOMEM;
  1264. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1265. if (!resp) {
  1266. kfree(req);
  1267. return -ENOMEM;
  1268. }
  1269. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1270. sizeof(qdss_cfg_filename), false);
  1271. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1272. qdss_cfg_filename);
  1273. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1274. qdss_cfg_filename);
  1275. if (ret) {
  1276. cnss_pr_dbg("Unable to load %s ret %d, try default file\n",
  1277. qdss_cfg_filename, ret);
  1278. cnss_get_qdss_cfg_filename(plat_priv, qdss_cfg_filename,
  1279. sizeof(qdss_cfg_filename),
  1280. true);
  1281. cnss_pr_dbg("Invoke firmware_request_nowarn for %s\n",
  1282. qdss_cfg_filename);
  1283. ret = cnss_request_firmware_direct(plat_priv, &fw_entry,
  1284. qdss_cfg_filename);
  1285. if (ret) {
  1286. cnss_pr_err("Unable to load %s ret %d\n",
  1287. qdss_cfg_filename, ret);
  1288. goto err_req_fw;
  1289. }
  1290. }
  1291. temp = fw_entry->data;
  1292. remaining = fw_entry->size;
  1293. cnss_pr_dbg("Downloading QDSS: %s, size: %u\n",
  1294. qdss_cfg_filename, remaining);
  1295. while (remaining) {
  1296. req->total_size_valid = 1;
  1297. req->total_size = remaining;
  1298. req->seg_id_valid = 1;
  1299. req->data_valid = 1;
  1300. req->end_valid = 1;
  1301. if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1302. req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01;
  1303. } else {
  1304. req->data_len = remaining;
  1305. req->end = 1;
  1306. }
  1307. memcpy(req->data, temp, req->data_len);
  1308. ret = qmi_txn_init
  1309. (&plat_priv->qmi_wlfw, &txn,
  1310. wlfw_qdss_trace_config_download_resp_msg_v01_ei,
  1311. resp);
  1312. if (ret < 0) {
  1313. cnss_pr_err("Failed to initialize txn for QDSS download request, err: %d\n",
  1314. ret);
  1315. goto err_send;
  1316. }
  1317. ret = qmi_send_request
  1318. (&plat_priv->qmi_wlfw, NULL, &txn,
  1319. QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01,
  1320. WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN,
  1321. wlfw_qdss_trace_config_download_req_msg_v01_ei, req);
  1322. if (ret < 0) {
  1323. qmi_txn_cancel(&txn);
  1324. cnss_pr_err("Failed to send respond QDSS download request, err: %d\n",
  1325. ret);
  1326. goto err_send;
  1327. }
  1328. ret = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1329. if (ret < 0) {
  1330. cnss_pr_err("Failed to wait for response of QDSS download request, err: %d\n",
  1331. ret);
  1332. goto err_send;
  1333. }
  1334. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1335. cnss_pr_err("QDSS download request failed, result: %d, err: %d\n",
  1336. resp->resp.result, resp->resp.error);
  1337. ret = -resp->resp.result;
  1338. goto err_send;
  1339. }
  1340. remaining -= req->data_len;
  1341. temp += req->data_len;
  1342. req->seg_id++;
  1343. }
  1344. release_firmware(fw_entry);
  1345. kfree(req);
  1346. kfree(resp);
  1347. return 0;
  1348. err_send:
  1349. release_firmware(fw_entry);
  1350. err_req_fw:
  1351. kfree(req);
  1352. kfree(resp);
  1353. return ret;
  1354. }
  1355. static int wlfw_send_qdss_trace_mode_req
  1356. (struct cnss_plat_data *plat_priv,
  1357. enum wlfw_qdss_trace_mode_enum_v01 mode,
  1358. unsigned long long option)
  1359. {
  1360. int rc = 0;
  1361. int tmp = 0;
  1362. struct wlfw_qdss_trace_mode_req_msg_v01 *req;
  1363. struct wlfw_qdss_trace_mode_resp_msg_v01 *resp;
  1364. struct qmi_txn txn;
  1365. if (!plat_priv)
  1366. return -ENODEV;
  1367. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1368. if (!req)
  1369. return -ENOMEM;
  1370. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1371. if (!resp) {
  1372. kfree(req);
  1373. return -ENOMEM;
  1374. }
  1375. req->mode_valid = 1;
  1376. req->mode = mode;
  1377. req->option_valid = 1;
  1378. req->option = option;
  1379. tmp = plat_priv->hw_trc_override;
  1380. req->hw_trc_disable_override_valid = 1;
  1381. req->hw_trc_disable_override =
  1382. (tmp > QMI_PARAM_DISABLE_V01 ? QMI_PARAM_DISABLE_V01 :
  1383. (tmp < 0 ? QMI_PARAM_INVALID_V01 : tmp));
  1384. cnss_pr_dbg("%s: mode %u, option %llu, hw_trc_disable_override: %u",
  1385. __func__, mode, option, req->hw_trc_disable_override);
  1386. rc = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1387. wlfw_qdss_trace_mode_resp_msg_v01_ei, resp);
  1388. if (rc < 0) {
  1389. cnss_pr_err("Fail to init txn for QDSS Mode resp %d\n",
  1390. rc);
  1391. goto out;
  1392. }
  1393. rc = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1394. QMI_WLFW_QDSS_TRACE_MODE_REQ_V01,
  1395. WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1396. wlfw_qdss_trace_mode_req_msg_v01_ei, req);
  1397. if (rc < 0) {
  1398. qmi_txn_cancel(&txn);
  1399. cnss_pr_err("Fail to send QDSS Mode req %d\n", rc);
  1400. goto out;
  1401. }
  1402. rc = qmi_txn_wait(&txn, plat_priv->ctrl_params.qmi_timeout);
  1403. if (rc < 0) {
  1404. cnss_pr_err("QDSS Mode resp wait failed with rc %d\n",
  1405. rc);
  1406. goto out;
  1407. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1408. cnss_pr_err("QMI QDSS Mode request rejected, result:%d error:%d\n",
  1409. resp->resp.result, resp->resp.error);
  1410. rc = -resp->resp.result;
  1411. goto out;
  1412. }
  1413. kfree(resp);
  1414. kfree(req);
  1415. return rc;
  1416. out:
  1417. kfree(resp);
  1418. kfree(req);
  1419. CNSS_QMI_ASSERT();
  1420. return rc;
  1421. }
  1422. int wlfw_qdss_trace_start(struct cnss_plat_data *plat_priv)
  1423. {
  1424. return wlfw_send_qdss_trace_mode_req(plat_priv,
  1425. QMI_WLFW_QDSS_TRACE_ON_V01, 0);
  1426. }
  1427. int wlfw_qdss_trace_stop(struct cnss_plat_data *plat_priv, unsigned long long option)
  1428. {
  1429. return wlfw_send_qdss_trace_mode_req(plat_priv, QMI_WLFW_QDSS_TRACE_OFF_V01,
  1430. option);
  1431. }
  1432. int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv,
  1433. enum cnss_driver_mode mode)
  1434. {
  1435. struct wlfw_wlan_mode_req_msg_v01 *req;
  1436. struct wlfw_wlan_mode_resp_msg_v01 *resp;
  1437. struct qmi_txn txn;
  1438. int ret = 0;
  1439. if (!plat_priv)
  1440. return -ENODEV;
  1441. cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n",
  1442. cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state);
  1443. if (mode == CNSS_OFF &&
  1444. test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1445. cnss_pr_dbg("Recovery is in progress, ignore mode off request\n");
  1446. return 0;
  1447. }
  1448. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1449. if (!req)
  1450. return -ENOMEM;
  1451. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1452. if (!resp) {
  1453. kfree(req);
  1454. return -ENOMEM;
  1455. }
  1456. req->mode = (enum wlfw_driver_mode_enum_v01)mode;
  1457. req->hw_debug_valid = 1;
  1458. req->hw_debug = 0;
  1459. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1460. wlfw_wlan_mode_resp_msg_v01_ei, resp);
  1461. if (ret < 0) {
  1462. cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n",
  1463. cnss_qmi_mode_to_str(mode), mode, ret);
  1464. goto out;
  1465. }
  1466. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1467. QMI_WLFW_WLAN_MODE_REQ_V01,
  1468. WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN,
  1469. wlfw_wlan_mode_req_msg_v01_ei, req);
  1470. if (ret < 0) {
  1471. qmi_txn_cancel(&txn);
  1472. cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n",
  1473. cnss_qmi_mode_to_str(mode), mode, ret);
  1474. goto out;
  1475. }
  1476. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1477. if (ret < 0) {
  1478. cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n",
  1479. cnss_qmi_mode_to_str(mode), mode, ret);
  1480. goto out;
  1481. }
  1482. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1483. cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n",
  1484. cnss_qmi_mode_to_str(mode), mode, resp->resp.result,
  1485. resp->resp.error);
  1486. ret = -resp->resp.result;
  1487. goto out;
  1488. }
  1489. kfree(req);
  1490. kfree(resp);
  1491. return 0;
  1492. out:
  1493. if (mode == CNSS_OFF) {
  1494. cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n");
  1495. ret = 0;
  1496. } else {
  1497. CNSS_QMI_ASSERT();
  1498. }
  1499. kfree(req);
  1500. kfree(resp);
  1501. return ret;
  1502. }
  1503. int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv,
  1504. struct cnss_wlan_enable_cfg *config,
  1505. const char *host_version)
  1506. {
  1507. struct wlfw_wlan_cfg_req_msg_v01 *req;
  1508. struct wlfw_wlan_cfg_resp_msg_v01 *resp;
  1509. struct qmi_txn txn;
  1510. u32 i, ce_id, num_vectors, user_base_data, base_vector;
  1511. int ret = 0;
  1512. if (!plat_priv)
  1513. return -ENODEV;
  1514. cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n",
  1515. plat_priv->driver_state);
  1516. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1517. if (!req)
  1518. return -ENOMEM;
  1519. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1520. if (!resp) {
  1521. kfree(req);
  1522. return -ENOMEM;
  1523. }
  1524. req->host_version_valid = 1;
  1525. strlcpy(req->host_version, host_version,
  1526. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  1527. req->tgt_cfg_valid = 1;
  1528. if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01)
  1529. req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1530. else
  1531. req->tgt_cfg_len = config->num_ce_tgt_cfg;
  1532. for (i = 0; i < req->tgt_cfg_len; i++) {
  1533. req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num;
  1534. req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir;
  1535. req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries;
  1536. req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max;
  1537. req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags;
  1538. }
  1539. req->svc_cfg_valid = 1;
  1540. if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01)
  1541. req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01;
  1542. else
  1543. req->svc_cfg_len = config->num_ce_svc_pipe_cfg;
  1544. for (i = 0; i < req->svc_cfg_len; i++) {
  1545. req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id;
  1546. req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir;
  1547. req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
  1548. }
  1549. if (plat_priv->device_id != KIWI_DEVICE_ID &&
  1550. plat_priv->device_id != MANGO_DEVICE_ID &&
  1551. plat_priv->device_id != PEACH_DEVICE_ID) {
  1552. if (plat_priv->device_id == QCN7605_DEVICE_ID &&
  1553. config->num_shadow_reg_cfg) {
  1554. req->shadow_reg_valid = 1;
  1555. if (config->num_shadow_reg_cfg >
  1556. QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
  1557. req->shadow_reg_len =
  1558. QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
  1559. else
  1560. req->shadow_reg_len =
  1561. config->num_shadow_reg_cfg;
  1562. memcpy(req->shadow_reg, config->shadow_reg_cfg,
  1563. sizeof(struct wlfw_shadow_reg_cfg_s_v01) *
  1564. req->shadow_reg_len);
  1565. } else {
  1566. req->shadow_reg_v2_valid = 1;
  1567. if (config->num_shadow_reg_v2_cfg >
  1568. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
  1569. req->shadow_reg_v2_len =
  1570. QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01;
  1571. else
  1572. req->shadow_reg_v2_len =
  1573. config->num_shadow_reg_v2_cfg;
  1574. memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg,
  1575. sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) *
  1576. req->shadow_reg_v2_len);
  1577. }
  1578. } else {
  1579. req->shadow_reg_v3_valid = 1;
  1580. if (config->num_shadow_reg_v3_cfg >
  1581. MAX_NUM_SHADOW_REG_V3)
  1582. req->shadow_reg_v3_len = MAX_NUM_SHADOW_REG_V3;
  1583. else
  1584. req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg;
  1585. plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len;
  1586. cnss_pr_dbg("Shadow reg v3 len: %d\n",
  1587. plat_priv->num_shadow_regs_v3);
  1588. memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg,
  1589. sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) *
  1590. req->shadow_reg_v3_len);
  1591. }
  1592. if (config->rri_over_ddr_cfg_valid) {
  1593. req->rri_over_ddr_cfg_valid = 1;
  1594. req->rri_over_ddr_cfg.base_addr_low =
  1595. config->rri_over_ddr_cfg.base_addr_low;
  1596. req->rri_over_ddr_cfg.base_addr_high =
  1597. config->rri_over_ddr_cfg.base_addr_high;
  1598. }
  1599. if (config->send_msi_ce) {
  1600. ret = cnss_bus_get_msi_assignment(plat_priv,
  1601. CE_MSI_NAME,
  1602. &num_vectors,
  1603. &user_base_data,
  1604. &base_vector);
  1605. if (!ret) {
  1606. req->msi_cfg_valid = 1;
  1607. req->msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
  1608. for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
  1609. ce_id++) {
  1610. req->msi_cfg[ce_id].ce_id = ce_id;
  1611. req->msi_cfg[ce_id].msi_vector =
  1612. (ce_id % num_vectors) + base_vector;
  1613. }
  1614. }
  1615. }
  1616. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1617. wlfw_wlan_cfg_resp_msg_v01_ei, resp);
  1618. if (ret < 0) {
  1619. cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n",
  1620. ret);
  1621. goto out;
  1622. }
  1623. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1624. QMI_WLFW_WLAN_CFG_REQ_V01,
  1625. WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN,
  1626. wlfw_wlan_cfg_req_msg_v01_ei, req);
  1627. if (ret < 0) {
  1628. qmi_txn_cancel(&txn);
  1629. cnss_pr_err("Failed to send WLAN config request, err: %d\n",
  1630. ret);
  1631. goto out;
  1632. }
  1633. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1634. if (ret < 0) {
  1635. cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n",
  1636. ret);
  1637. goto out;
  1638. }
  1639. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1640. cnss_pr_err("WLAN config request failed, result: %d, err: %d\n",
  1641. resp->resp.result, resp->resp.error);
  1642. ret = -resp->resp.result;
  1643. goto out;
  1644. }
  1645. kfree(req);
  1646. kfree(resp);
  1647. return 0;
  1648. out:
  1649. CNSS_QMI_ASSERT();
  1650. kfree(req);
  1651. kfree(resp);
  1652. return ret;
  1653. }
  1654. int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv,
  1655. u32 offset, u32 mem_type,
  1656. u32 data_len, u8 *data)
  1657. {
  1658. struct wlfw_athdiag_read_req_msg_v01 *req;
  1659. struct wlfw_athdiag_read_resp_msg_v01 *resp;
  1660. struct qmi_txn txn;
  1661. int ret = 0;
  1662. if (!plat_priv)
  1663. return -ENODEV;
  1664. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1665. cnss_pr_err("Invalid parameters for athdiag read: data %pK, data_len %u\n",
  1666. data, data_len);
  1667. return -EINVAL;
  1668. }
  1669. cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n",
  1670. plat_priv->driver_state, offset, mem_type, data_len);
  1671. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1672. if (!req)
  1673. return -ENOMEM;
  1674. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1675. if (!resp) {
  1676. kfree(req);
  1677. return -ENOMEM;
  1678. }
  1679. req->offset = offset;
  1680. req->mem_type = mem_type;
  1681. req->data_len = data_len;
  1682. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1683. wlfw_athdiag_read_resp_msg_v01_ei, resp);
  1684. if (ret < 0) {
  1685. cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n",
  1686. ret);
  1687. goto out;
  1688. }
  1689. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1690. QMI_WLFW_ATHDIAG_READ_REQ_V01,
  1691. WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN,
  1692. wlfw_athdiag_read_req_msg_v01_ei, req);
  1693. if (ret < 0) {
  1694. qmi_txn_cancel(&txn);
  1695. cnss_pr_err("Failed to send athdiag read request, err: %d\n",
  1696. ret);
  1697. goto out;
  1698. }
  1699. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1700. if (ret < 0) {
  1701. cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n",
  1702. ret);
  1703. goto out;
  1704. }
  1705. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1706. cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n",
  1707. resp->resp.result, resp->resp.error);
  1708. ret = -resp->resp.result;
  1709. goto out;
  1710. }
  1711. if (!resp->data_valid || resp->data_len != data_len) {
  1712. cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n",
  1713. resp->data_valid, resp->data_len);
  1714. ret = -EINVAL;
  1715. goto out;
  1716. }
  1717. memcpy(data, resp->data, resp->data_len);
  1718. kfree(req);
  1719. kfree(resp);
  1720. return 0;
  1721. out:
  1722. kfree(req);
  1723. kfree(resp);
  1724. return ret;
  1725. }
  1726. int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv,
  1727. u32 offset, u32 mem_type,
  1728. u32 data_len, u8 *data)
  1729. {
  1730. struct wlfw_athdiag_write_req_msg_v01 *req;
  1731. struct wlfw_athdiag_write_resp_msg_v01 *resp;
  1732. struct qmi_txn txn;
  1733. int ret = 0;
  1734. if (!plat_priv)
  1735. return -ENODEV;
  1736. if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) {
  1737. cnss_pr_err("Invalid parameters for athdiag write: data %pK, data_len %u\n",
  1738. data, data_len);
  1739. return -EINVAL;
  1740. }
  1741. cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %pK\n",
  1742. plat_priv->driver_state, offset, mem_type, data_len, data);
  1743. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1744. if (!req)
  1745. return -ENOMEM;
  1746. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1747. if (!resp) {
  1748. kfree(req);
  1749. return -ENOMEM;
  1750. }
  1751. req->offset = offset;
  1752. req->mem_type = mem_type;
  1753. req->data_len = data_len;
  1754. memcpy(req->data, data, data_len);
  1755. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1756. wlfw_athdiag_write_resp_msg_v01_ei, resp);
  1757. if (ret < 0) {
  1758. cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n",
  1759. ret);
  1760. goto out;
  1761. }
  1762. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1763. QMI_WLFW_ATHDIAG_WRITE_REQ_V01,
  1764. WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN,
  1765. wlfw_athdiag_write_req_msg_v01_ei, req);
  1766. if (ret < 0) {
  1767. qmi_txn_cancel(&txn);
  1768. cnss_pr_err("Failed to send athdiag write request, err: %d\n",
  1769. ret);
  1770. goto out;
  1771. }
  1772. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1773. if (ret < 0) {
  1774. cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n",
  1775. ret);
  1776. goto out;
  1777. }
  1778. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1779. cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n",
  1780. resp->resp.result, resp->resp.error);
  1781. ret = -resp->resp.result;
  1782. goto out;
  1783. }
  1784. kfree(req);
  1785. kfree(resp);
  1786. return 0;
  1787. out:
  1788. kfree(req);
  1789. kfree(resp);
  1790. return ret;
  1791. }
  1792. int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv,
  1793. u8 fw_log_mode)
  1794. {
  1795. struct wlfw_ini_req_msg_v01 *req;
  1796. struct wlfw_ini_resp_msg_v01 *resp;
  1797. struct qmi_txn txn;
  1798. int ret = 0;
  1799. if (!plat_priv)
  1800. return -ENODEV;
  1801. cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n",
  1802. plat_priv->driver_state, fw_log_mode);
  1803. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1804. if (!req)
  1805. return -ENOMEM;
  1806. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1807. if (!resp) {
  1808. kfree(req);
  1809. return -ENOMEM;
  1810. }
  1811. req->enablefwlog_valid = 1;
  1812. req->enablefwlog = fw_log_mode;
  1813. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1814. wlfw_ini_resp_msg_v01_ei, resp);
  1815. if (ret < 0) {
  1816. cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n",
  1817. fw_log_mode, ret);
  1818. goto out;
  1819. }
  1820. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1821. QMI_WLFW_INI_REQ_V01,
  1822. WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN,
  1823. wlfw_ini_req_msg_v01_ei, req);
  1824. if (ret < 0) {
  1825. qmi_txn_cancel(&txn);
  1826. cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n",
  1827. fw_log_mode, ret);
  1828. goto out;
  1829. }
  1830. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1831. if (ret < 0) {
  1832. cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n",
  1833. fw_log_mode, ret);
  1834. goto out;
  1835. }
  1836. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1837. cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n",
  1838. fw_log_mode, resp->resp.result, resp->resp.error);
  1839. ret = -resp->resp.result;
  1840. goto out;
  1841. }
  1842. kfree(req);
  1843. kfree(resp);
  1844. return 0;
  1845. out:
  1846. kfree(req);
  1847. kfree(resp);
  1848. return ret;
  1849. }
  1850. int cnss_wlfw_send_pcie_gen_speed_sync(struct cnss_plat_data *plat_priv)
  1851. {
  1852. struct wlfw_pcie_gen_switch_req_msg_v01 req;
  1853. struct wlfw_pcie_gen_switch_resp_msg_v01 resp = {0};
  1854. struct qmi_txn txn;
  1855. int ret = 0;
  1856. if (!plat_priv)
  1857. return -ENODEV;
  1858. if (plat_priv->pcie_gen_speed == QMI_PCIE_GEN_SPEED_INVALID_V01 ||
  1859. !plat_priv->fw_pcie_gen_switch) {
  1860. cnss_pr_dbg("PCIE Gen speed not setup\n");
  1861. return 0;
  1862. }
  1863. cnss_pr_dbg("Sending PCIE Gen speed: %d state: 0x%lx\n",
  1864. plat_priv->pcie_gen_speed, plat_priv->driver_state);
  1865. req.pcie_speed = (enum wlfw_pcie_gen_speed_v01)
  1866. plat_priv->pcie_gen_speed;
  1867. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1868. wlfw_pcie_gen_switch_resp_msg_v01_ei, &resp);
  1869. if (ret < 0) {
  1870. cnss_pr_err("Failed to initialize txn for PCIE speed switch err: %d\n",
  1871. ret);
  1872. goto out;
  1873. }
  1874. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1875. QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01,
  1876. WLFW_PCIE_GEN_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1877. wlfw_pcie_gen_switch_req_msg_v01_ei, &req);
  1878. if (ret < 0) {
  1879. qmi_txn_cancel(&txn);
  1880. cnss_pr_err("Failed to send PCIE speed switch, err: %d\n", ret);
  1881. goto out;
  1882. }
  1883. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1884. if (ret < 0) {
  1885. cnss_pr_err("Failed to wait for PCIE Gen switch resp, err: %d\n",
  1886. ret);
  1887. goto out;
  1888. }
  1889. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  1890. cnss_pr_err("PCIE Gen Switch req failed, Speed: %d, result: %d, err: %d\n",
  1891. plat_priv->pcie_gen_speed, resp.resp.result,
  1892. resp.resp.error);
  1893. ret = -resp.resp.result;
  1894. }
  1895. out:
  1896. /* Reset PCIE Gen speed after one time use */
  1897. plat_priv->pcie_gen_speed = QMI_PCIE_GEN_SPEED_INVALID_V01;
  1898. return ret;
  1899. }
  1900. int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv)
  1901. {
  1902. struct wlfw_antenna_switch_req_msg_v01 *req;
  1903. struct wlfw_antenna_switch_resp_msg_v01 *resp;
  1904. struct qmi_txn txn;
  1905. int ret = 0;
  1906. if (!plat_priv)
  1907. return -ENODEV;
  1908. cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n",
  1909. plat_priv->driver_state);
  1910. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1911. if (!req)
  1912. return -ENOMEM;
  1913. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1914. if (!resp) {
  1915. kfree(req);
  1916. return -ENOMEM;
  1917. }
  1918. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1919. wlfw_antenna_switch_resp_msg_v01_ei, resp);
  1920. if (ret < 0) {
  1921. cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n",
  1922. ret);
  1923. goto out;
  1924. }
  1925. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1926. QMI_WLFW_ANTENNA_SWITCH_REQ_V01,
  1927. WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN,
  1928. wlfw_antenna_switch_req_msg_v01_ei, req);
  1929. if (ret < 0) {
  1930. qmi_txn_cancel(&txn);
  1931. cnss_pr_err("Failed to send antenna switch request, err: %d\n",
  1932. ret);
  1933. goto out;
  1934. }
  1935. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1936. if (ret < 0) {
  1937. cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n",
  1938. ret);
  1939. goto out;
  1940. }
  1941. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  1942. cnss_pr_dbg("Antenna switch request failed, result: %d, err: %d\n",
  1943. resp->resp.result, resp->resp.error);
  1944. ret = -resp->resp.result;
  1945. goto out;
  1946. }
  1947. if (resp->antenna_valid)
  1948. plat_priv->antenna = resp->antenna;
  1949. cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n",
  1950. resp->antenna_valid, resp->antenna);
  1951. kfree(req);
  1952. kfree(resp);
  1953. return 0;
  1954. out:
  1955. kfree(req);
  1956. kfree(resp);
  1957. return ret;
  1958. }
  1959. int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv)
  1960. {
  1961. struct wlfw_antenna_grant_req_msg_v01 *req;
  1962. struct wlfw_antenna_grant_resp_msg_v01 *resp;
  1963. struct qmi_txn txn;
  1964. int ret = 0;
  1965. if (!plat_priv)
  1966. return -ENODEV;
  1967. cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n",
  1968. plat_priv->driver_state, plat_priv->grant);
  1969. req = kzalloc(sizeof(*req), GFP_KERNEL);
  1970. if (!req)
  1971. return -ENOMEM;
  1972. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  1973. if (!resp) {
  1974. kfree(req);
  1975. return -ENOMEM;
  1976. }
  1977. req->grant_valid = 1;
  1978. req->grant = plat_priv->grant;
  1979. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  1980. wlfw_antenna_grant_resp_msg_v01_ei, resp);
  1981. if (ret < 0) {
  1982. cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n",
  1983. ret);
  1984. goto out;
  1985. }
  1986. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  1987. QMI_WLFW_ANTENNA_GRANT_REQ_V01,
  1988. WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN,
  1989. wlfw_antenna_grant_req_msg_v01_ei, req);
  1990. if (ret < 0) {
  1991. qmi_txn_cancel(&txn);
  1992. cnss_pr_err("Failed to send antenna grant request, err: %d\n",
  1993. ret);
  1994. goto out;
  1995. }
  1996. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  1997. if (ret < 0) {
  1998. cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n",
  1999. ret);
  2000. goto out;
  2001. }
  2002. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2003. cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n",
  2004. resp->resp.result, resp->resp.error);
  2005. ret = -resp->resp.result;
  2006. goto out;
  2007. }
  2008. kfree(req);
  2009. kfree(resp);
  2010. return 0;
  2011. out:
  2012. kfree(req);
  2013. kfree(resp);
  2014. return ret;
  2015. }
  2016. int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv)
  2017. {
  2018. struct wlfw_qdss_trace_mem_info_req_msg_v01 *req;
  2019. struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp;
  2020. struct qmi_txn txn;
  2021. struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem;
  2022. int ret = 0;
  2023. int i;
  2024. cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n",
  2025. plat_priv->driver_state);
  2026. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2027. if (!req)
  2028. return -ENOMEM;
  2029. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2030. if (!resp) {
  2031. kfree(req);
  2032. return -ENOMEM;
  2033. }
  2034. if (plat_priv->qdss_mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2035. cnss_pr_err("Invalid seg len %u\n", plat_priv->qdss_mem_seg_len);
  2036. ret = -EINVAL;
  2037. goto out;
  2038. }
  2039. req->mem_seg_len = plat_priv->qdss_mem_seg_len;
  2040. for (i = 0; i < req->mem_seg_len; i++) {
  2041. cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n",
  2042. qdss_mem[i].va, &qdss_mem[i].pa,
  2043. qdss_mem[i].size, qdss_mem[i].type);
  2044. req->mem_seg[i].addr = qdss_mem[i].pa;
  2045. req->mem_seg[i].size = qdss_mem[i].size;
  2046. req->mem_seg[i].type = qdss_mem[i].type;
  2047. }
  2048. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2049. wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp);
  2050. if (ret < 0) {
  2051. cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n",
  2052. ret);
  2053. goto out;
  2054. }
  2055. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2056. QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01,
  2057. WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2058. wlfw_qdss_trace_mem_info_req_msg_v01_ei, req);
  2059. if (ret < 0) {
  2060. qmi_txn_cancel(&txn);
  2061. cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n",
  2062. ret);
  2063. goto out;
  2064. }
  2065. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2066. if (ret < 0) {
  2067. cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n",
  2068. ret);
  2069. goto out;
  2070. }
  2071. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2072. cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n",
  2073. resp->resp.result, resp->resp.error);
  2074. ret = -resp->resp.result;
  2075. goto out;
  2076. }
  2077. kfree(req);
  2078. kfree(resp);
  2079. return 0;
  2080. out:
  2081. kfree(req);
  2082. kfree(resp);
  2083. return ret;
  2084. }
  2085. int cnss_wlfw_send_host_wfc_call_status(struct cnss_plat_data *plat_priv,
  2086. struct cnss_wfc_cfg cfg)
  2087. {
  2088. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2089. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2090. struct qmi_txn txn;
  2091. int ret = 0;
  2092. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2093. cnss_pr_err("Drop host WFC indication as FW not initialized\n");
  2094. return -EINVAL;
  2095. }
  2096. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2097. if (!req)
  2098. return -ENOMEM;
  2099. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2100. if (!resp) {
  2101. kfree(req);
  2102. return -ENOMEM;
  2103. }
  2104. req->wfc_call_active_valid = 1;
  2105. req->wfc_call_active = cfg.mode;
  2106. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2107. plat_priv->driver_state);
  2108. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2109. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2110. if (ret < 0) {
  2111. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2112. ret);
  2113. goto out;
  2114. }
  2115. cnss_pr_dbg("Send WFC Mode: %d\n", cfg.mode);
  2116. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2117. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2118. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2119. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2120. if (ret < 0) {
  2121. qmi_txn_cancel(&txn);
  2122. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2123. ret);
  2124. goto out;
  2125. }
  2126. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2127. if (ret < 0) {
  2128. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2129. ret);
  2130. goto out;
  2131. }
  2132. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2133. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2134. resp->resp.result, resp->resp.error);
  2135. ret = -EINVAL;
  2136. goto out;
  2137. }
  2138. ret = 0;
  2139. out:
  2140. kfree(req);
  2141. kfree(resp);
  2142. return ret;
  2143. }
  2144. static int cnss_wlfw_wfc_call_status_send_sync
  2145. (struct cnss_plat_data *plat_priv,
  2146. const struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg)
  2147. {
  2148. struct wlfw_wfc_call_status_req_msg_v01 *req;
  2149. struct wlfw_wfc_call_status_resp_msg_v01 *resp;
  2150. struct qmi_txn txn;
  2151. int ret = 0;
  2152. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  2153. cnss_pr_err("Drop IMS WFC indication as FW not initialized\n");
  2154. return -EINVAL;
  2155. }
  2156. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2157. if (!req)
  2158. return -ENOMEM;
  2159. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2160. if (!resp) {
  2161. kfree(req);
  2162. return -ENOMEM;
  2163. }
  2164. /**
  2165. * WFC Call r1 design has CNSS as pass thru using opaque hex buffer.
  2166. * But in r2 update QMI structure is expanded and as an effect qmi
  2167. * decoded structures have padding. Thus we cannot use buffer design.
  2168. * For backward compatibility for r1 design copy only wfc_call_active
  2169. * value in hex buffer.
  2170. */
  2171. req->wfc_call_status_len = sizeof(ind_msg->wfc_call_active);
  2172. req->wfc_call_status[0] = ind_msg->wfc_call_active;
  2173. /* wfc_call_active is mandatory in IMS indication */
  2174. req->wfc_call_active_valid = 1;
  2175. req->wfc_call_active = ind_msg->wfc_call_active;
  2176. req->all_wfc_calls_held_valid = ind_msg->all_wfc_calls_held_valid;
  2177. req->all_wfc_calls_held = ind_msg->all_wfc_calls_held;
  2178. req->is_wfc_emergency_valid = ind_msg->is_wfc_emergency_valid;
  2179. req->is_wfc_emergency = ind_msg->is_wfc_emergency;
  2180. req->twt_ims_start_valid = ind_msg->twt_ims_start_valid;
  2181. req->twt_ims_start = ind_msg->twt_ims_start;
  2182. req->twt_ims_int_valid = ind_msg->twt_ims_int_valid;
  2183. req->twt_ims_int = ind_msg->twt_ims_int;
  2184. req->media_quality_valid = ind_msg->media_quality_valid;
  2185. req->media_quality =
  2186. (enum wlfw_wfc_media_quality_v01)ind_msg->media_quality;
  2187. cnss_pr_dbg("CNSS->FW: WFC_CALL_REQ: state: 0x%lx\n",
  2188. plat_priv->driver_state);
  2189. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2190. wlfw_wfc_call_status_resp_msg_v01_ei, resp);
  2191. if (ret < 0) {
  2192. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Txn Init: Err %d\n",
  2193. ret);
  2194. goto out;
  2195. }
  2196. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2197. QMI_WLFW_WFC_CALL_STATUS_REQ_V01,
  2198. WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN,
  2199. wlfw_wfc_call_status_req_msg_v01_ei, req);
  2200. if (ret < 0) {
  2201. qmi_txn_cancel(&txn);
  2202. cnss_pr_err("CNSS->FW: WFC_CALL_REQ: QMI Send Err: %d\n",
  2203. ret);
  2204. goto out;
  2205. }
  2206. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2207. if (ret < 0) {
  2208. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: QMI Wait Err: %d\n",
  2209. ret);
  2210. goto out;
  2211. }
  2212. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2213. cnss_pr_err("FW->CNSS: WFC_CALL_RSP: Result: %d Err: %d\n",
  2214. resp->resp.result, resp->resp.error);
  2215. ret = -resp->resp.result;
  2216. goto out;
  2217. }
  2218. ret = 0;
  2219. out:
  2220. kfree(req);
  2221. kfree(resp);
  2222. return ret;
  2223. }
  2224. int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv)
  2225. {
  2226. struct wlfw_dynamic_feature_mask_req_msg_v01 *req;
  2227. struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp;
  2228. struct qmi_txn txn;
  2229. int ret = 0;
  2230. cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n",
  2231. plat_priv->dynamic_feature,
  2232. plat_priv->driver_state);
  2233. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2234. if (!req)
  2235. return -ENOMEM;
  2236. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2237. if (!resp) {
  2238. kfree(req);
  2239. return -ENOMEM;
  2240. }
  2241. req->mask_valid = 1;
  2242. req->mask = plat_priv->dynamic_feature;
  2243. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2244. wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp);
  2245. if (ret < 0) {
  2246. cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n",
  2247. ret);
  2248. goto out;
  2249. }
  2250. ret = qmi_send_request
  2251. (&plat_priv->qmi_wlfw, NULL, &txn,
  2252. QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01,
  2253. WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN,
  2254. wlfw_dynamic_feature_mask_req_msg_v01_ei, req);
  2255. if (ret < 0) {
  2256. qmi_txn_cancel(&txn);
  2257. cnss_pr_err("Fail to send dynamic feature mask request: err %d\n",
  2258. ret);
  2259. goto out;
  2260. }
  2261. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2262. if (ret < 0) {
  2263. cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n",
  2264. ret);
  2265. goto out;
  2266. }
  2267. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2268. cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n",
  2269. resp->resp.result, resp->resp.error);
  2270. ret = -resp->resp.result;
  2271. goto out;
  2272. }
  2273. out:
  2274. kfree(req);
  2275. kfree(resp);
  2276. return ret;
  2277. }
  2278. int cnss_wlfw_get_info_send_sync(struct cnss_plat_data *plat_priv, int type,
  2279. void *cmd, int cmd_len)
  2280. {
  2281. struct wlfw_get_info_req_msg_v01 *req;
  2282. struct wlfw_get_info_resp_msg_v01 *resp;
  2283. struct qmi_txn txn;
  2284. int ret = 0;
  2285. cnss_pr_buf("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
  2286. type, cmd_len, plat_priv->driver_state);
  2287. if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
  2288. return -EINVAL;
  2289. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2290. if (!req)
  2291. return -ENOMEM;
  2292. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2293. if (!resp) {
  2294. kfree(req);
  2295. return -ENOMEM;
  2296. }
  2297. req->type = type;
  2298. req->data_len = cmd_len;
  2299. memcpy(req->data, cmd, req->data_len);
  2300. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2301. wlfw_get_info_resp_msg_v01_ei, resp);
  2302. if (ret < 0) {
  2303. cnss_pr_err("Failed to initialize txn for get info request, err: %d\n",
  2304. ret);
  2305. goto out;
  2306. }
  2307. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2308. QMI_WLFW_GET_INFO_REQ_V01,
  2309. WLFW_GET_INFO_REQ_MSG_V01_MAX_MSG_LEN,
  2310. wlfw_get_info_req_msg_v01_ei, req);
  2311. if (ret < 0) {
  2312. qmi_txn_cancel(&txn);
  2313. cnss_pr_err("Failed to send get info request, err: %d\n",
  2314. ret);
  2315. goto out;
  2316. }
  2317. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2318. if (ret < 0) {
  2319. cnss_pr_err("Failed to wait for response of get info request, err: %d\n",
  2320. ret);
  2321. goto out;
  2322. }
  2323. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2324. cnss_pr_err("Get info request failed, result: %d, err: %d\n",
  2325. resp->resp.result, resp->resp.error);
  2326. ret = -resp->resp.result;
  2327. goto out;
  2328. }
  2329. kfree(req);
  2330. kfree(resp);
  2331. return 0;
  2332. out:
  2333. kfree(req);
  2334. kfree(resp);
  2335. return ret;
  2336. }
  2337. unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv)
  2338. {
  2339. return QMI_WLFW_TIMEOUT_MS;
  2340. }
  2341. static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2342. struct sockaddr_qrtr *sq,
  2343. struct qmi_txn *txn, const void *data)
  2344. {
  2345. struct cnss_plat_data *plat_priv =
  2346. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2347. const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data;
  2348. int i;
  2349. cnss_pr_dbg("Received QMI WLFW request memory indication\n");
  2350. if (!txn) {
  2351. cnss_pr_err("Spurious indication\n");
  2352. return;
  2353. }
  2354. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2355. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2356. return;
  2357. }
  2358. plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len;
  2359. for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
  2360. cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n",
  2361. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2362. plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
  2363. plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
  2364. if (!plat_priv->fw_mem[i].va &&
  2365. plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
  2366. plat_priv->fw_mem[i].attrs |=
  2367. DMA_ATTR_FORCE_CONTIGUOUS;
  2368. if (plat_priv->fw_mem[i].type == CNSS_MEM_CAL_V01)
  2369. plat_priv->cal_mem = &plat_priv->fw_mem[i];
  2370. }
  2371. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM,
  2372. 0, NULL);
  2373. }
  2374. static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2375. struct sockaddr_qrtr *sq,
  2376. struct qmi_txn *txn, const void *data)
  2377. {
  2378. struct cnss_plat_data *plat_priv =
  2379. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2380. cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n");
  2381. if (!txn) {
  2382. cnss_pr_err("Spurious indication\n");
  2383. return;
  2384. }
  2385. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY,
  2386. 0, NULL);
  2387. }
  2388. /**
  2389. * cnss_wlfw_fw_ready_ind_cb: FW ready indication handler (Helium arch)
  2390. *
  2391. * This event is not required for HST/ HSP as FW calibration done is
  2392. * provided in QMI_WLFW_CAL_DONE_IND_V01
  2393. */
  2394. static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw,
  2395. struct sockaddr_qrtr *sq,
  2396. struct qmi_txn *txn, const void *data)
  2397. {
  2398. struct cnss_plat_data *plat_priv =
  2399. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2400. struct cnss_cal_info *cal_info;
  2401. if (!txn) {
  2402. cnss_pr_err("Spurious indication\n");
  2403. return;
  2404. }
  2405. if (plat_priv->device_id == QCA6390_DEVICE_ID ||
  2406. plat_priv->device_id == QCA6490_DEVICE_ID) {
  2407. cnss_pr_dbg("Ignore FW Ready Indication for HST/HSP");
  2408. return;
  2409. }
  2410. cnss_pr_dbg("Received QMI WLFW FW ready indication.\n");
  2411. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2412. if (!cal_info)
  2413. return;
  2414. cal_info->cal_status = CNSS_CAL_DONE;
  2415. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2416. 0, cal_info);
  2417. }
  2418. static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2419. struct sockaddr_qrtr *sq,
  2420. struct qmi_txn *txn, const void *data)
  2421. {
  2422. struct cnss_plat_data *plat_priv =
  2423. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2424. cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n");
  2425. if (!txn) {
  2426. cnss_pr_err("Spurious indication\n");
  2427. return;
  2428. }
  2429. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL);
  2430. }
  2431. static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw,
  2432. struct sockaddr_qrtr *sq,
  2433. struct qmi_txn *txn, const void *data)
  2434. {
  2435. struct cnss_plat_data *plat_priv =
  2436. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2437. const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data;
  2438. cnss_pr_dbg("Received QMI WLFW pin connect result indication\n");
  2439. if (!txn) {
  2440. cnss_pr_err("Spurious indication\n");
  2441. return;
  2442. }
  2443. if (ind_msg->pwr_pin_result_valid)
  2444. plat_priv->pin_result.fw_pwr_pin_result =
  2445. ind_msg->pwr_pin_result;
  2446. if (ind_msg->phy_io_pin_result_valid)
  2447. plat_priv->pin_result.fw_phy_io_pin_result =
  2448. ind_msg->phy_io_pin_result;
  2449. if (ind_msg->rf_pin_result_valid)
  2450. plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result;
  2451. cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n",
  2452. ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result,
  2453. ind_msg->rf_pin_result);
  2454. }
  2455. int cnss_wlfw_cal_report_req_send_sync(struct cnss_plat_data *plat_priv,
  2456. u32 cal_file_download_size)
  2457. {
  2458. struct wlfw_cal_report_req_msg_v01 req = {0};
  2459. struct wlfw_cal_report_resp_msg_v01 resp = {0};
  2460. struct qmi_txn txn;
  2461. int ret = 0;
  2462. cnss_pr_dbg("Sending cal file report request. File size: %d, state: 0x%lx\n",
  2463. cal_file_download_size, plat_priv->driver_state);
  2464. req.cal_file_download_size_valid = 1;
  2465. req.cal_file_download_size = cal_file_download_size;
  2466. ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn,
  2467. wlfw_cal_report_resp_msg_v01_ei, &resp);
  2468. if (ret < 0) {
  2469. cnss_pr_err("Failed to initialize txn for Cal Report request, err: %d\n",
  2470. ret);
  2471. goto out;
  2472. }
  2473. ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn,
  2474. QMI_WLFW_CAL_REPORT_REQ_V01,
  2475. WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN,
  2476. wlfw_cal_report_req_msg_v01_ei, &req);
  2477. if (ret < 0) {
  2478. qmi_txn_cancel(&txn);
  2479. cnss_pr_err("Failed to send Cal Report request, err: %d\n",
  2480. ret);
  2481. goto out;
  2482. }
  2483. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2484. if (ret < 0) {
  2485. cnss_pr_err("Failed to wait for response of Cal Report request, err: %d\n",
  2486. ret);
  2487. goto out;
  2488. }
  2489. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  2490. cnss_pr_err("Cal Report request failed, result: %d, err: %d\n",
  2491. resp.resp.result, resp.resp.error);
  2492. ret = -resp.resp.result;
  2493. goto out;
  2494. }
  2495. out:
  2496. return ret;
  2497. }
  2498. static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw,
  2499. struct sockaddr_qrtr *sq,
  2500. struct qmi_txn *txn, const void *data)
  2501. {
  2502. struct cnss_plat_data *plat_priv =
  2503. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2504. const struct wlfw_cal_done_ind_msg_v01 *ind = data;
  2505. struct cnss_cal_info *cal_info;
  2506. cnss_pr_dbg("Received Cal done indication. File size: %d\n",
  2507. ind->cal_file_upload_size);
  2508. cnss_pr_info("Calibration took %d ms\n",
  2509. jiffies_to_msecs(jiffies - plat_priv->cal_time));
  2510. if (!txn) {
  2511. cnss_pr_err("Spurious indication\n");
  2512. return;
  2513. }
  2514. if (ind->cal_file_upload_size_valid)
  2515. plat_priv->cal_file_size = ind->cal_file_upload_size;
  2516. cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);
  2517. if (!cal_info)
  2518. return;
  2519. cal_info->cal_status = CNSS_CAL_DONE;
  2520. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
  2521. 0, cal_info);
  2522. }
  2523. static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw,
  2524. struct sockaddr_qrtr *sq,
  2525. struct qmi_txn *txn,
  2526. const void *data)
  2527. {
  2528. struct cnss_plat_data *plat_priv =
  2529. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2530. const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data;
  2531. int i;
  2532. cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n");
  2533. if (!txn) {
  2534. cnss_pr_err("Spurious indication\n");
  2535. return;
  2536. }
  2537. if (plat_priv->qdss_mem_seg_len) {
  2538. cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n",
  2539. plat_priv->qdss_mem_seg_len);
  2540. return;
  2541. }
  2542. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_NUM_MEM_SEG_V01) {
  2543. cnss_pr_err("Invalid seg len %u\n", ind_msg->mem_seg_len);
  2544. return;
  2545. }
  2546. plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len;
  2547. for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) {
  2548. cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n",
  2549. ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
  2550. plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type;
  2551. plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size;
  2552. }
  2553. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
  2554. 0, NULL);
  2555. }
  2556. /**
  2557. * cnss_wlfw_fw_mem_file_save_ind_cb: Save given FW mem to filesystem
  2558. *
  2559. * QDSS_TRACE_SAVE_IND feature is overloaded to provide any host allocated
  2560. * fw memory segment for dumping to file system. Only one type of mem can be
  2561. * saved per indication and is provided in mem seg index 0.
  2562. *
  2563. * Return: None
  2564. */
  2565. static void cnss_wlfw_fw_mem_file_save_ind_cb(struct qmi_handle *qmi_wlfw,
  2566. struct sockaddr_qrtr *sq,
  2567. struct qmi_txn *txn,
  2568. const void *data)
  2569. {
  2570. struct cnss_plat_data *plat_priv =
  2571. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2572. const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data;
  2573. struct cnss_qmi_event_fw_mem_file_save_data *event_data;
  2574. int i = 0;
  2575. if (!txn || !data) {
  2576. cnss_pr_err("Spurious indication\n");
  2577. return;
  2578. }
  2579. cnss_pr_dbg_buf("QMI fw_mem_file_save: source: %d mem_seg: %d type: %u len: %u\n",
  2580. ind_msg->source, ind_msg->mem_seg_valid,
  2581. ind_msg->mem_seg[0].type, ind_msg->mem_seg_len);
  2582. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2583. if (!event_data)
  2584. return;
  2585. event_data->mem_type = ind_msg->mem_seg[0].type;
  2586. event_data->mem_seg_len = ind_msg->mem_seg_len;
  2587. event_data->total_size = ind_msg->total_size;
  2588. if (ind_msg->mem_seg_valid) {
  2589. if (ind_msg->mem_seg_len > QMI_WLFW_MAX_STR_LEN_V01) {
  2590. cnss_pr_err("Invalid seg len indication\n");
  2591. goto free_event_data;
  2592. }
  2593. for (i = 0; i < ind_msg->mem_seg_len; i++) {
  2594. event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr;
  2595. event_data->mem_seg[i].size = ind_msg->mem_seg[i].size;
  2596. if (event_data->mem_type != ind_msg->mem_seg[i].type) {
  2597. cnss_pr_err("FW Mem file save ind cannot have multiple mem types\n");
  2598. goto free_event_data;
  2599. }
  2600. cnss_pr_dbg_buf("seg-%d: addr 0x%llx size 0x%x\n",
  2601. i, ind_msg->mem_seg[i].addr,
  2602. ind_msg->mem_seg[i].size);
  2603. }
  2604. }
  2605. if (ind_msg->file_name_valid)
  2606. strlcpy(event_data->file_name, ind_msg->file_name,
  2607. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2608. if (ind_msg->source == 1) {
  2609. if (!ind_msg->file_name_valid)
  2610. strlcpy(event_data->file_name, "qdss_trace_wcss_etb",
  2611. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2612. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
  2613. 0, event_data);
  2614. } else {
  2615. if (event_data->mem_type == QMI_WLFW_MEM_QDSS_V01) {
  2616. if (!ind_msg->file_name_valid)
  2617. strlcpy(event_data->file_name, "qdss_trace_ddr",
  2618. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2619. } else {
  2620. if (!ind_msg->file_name_valid)
  2621. strlcpy(event_data->file_name, "fw_mem_dump",
  2622. QMI_WLFW_MAX_STR_LEN_V01 + 1);
  2623. }
  2624. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
  2625. 0, event_data);
  2626. }
  2627. return;
  2628. free_event_data:
  2629. kfree(event_data);
  2630. }
  2631. static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw,
  2632. struct sockaddr_qrtr *sq,
  2633. struct qmi_txn *txn,
  2634. const void *data)
  2635. {
  2636. struct cnss_plat_data *plat_priv =
  2637. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2638. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
  2639. 0, NULL);
  2640. }
  2641. static void cnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi_wlfw,
  2642. struct sockaddr_qrtr *sq,
  2643. struct qmi_txn *txn,
  2644. const void *data)
  2645. {
  2646. struct cnss_plat_data *plat_priv =
  2647. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2648. const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
  2649. cnss_pr_buf("Received QMI WLFW respond get info indication\n");
  2650. if (!txn) {
  2651. cnss_pr_err("Spurious indication\n");
  2652. return;
  2653. }
  2654. cnss_pr_buf("Extract message with event length: %d, type: %d, is last: %d, seq no: %d\n",
  2655. ind_msg->data_len, ind_msg->type,
  2656. ind_msg->is_last, ind_msg->seq_no);
  2657. if (plat_priv->get_info_cb_ctx && plat_priv->get_info_cb)
  2658. plat_priv->get_info_cb(plat_priv->get_info_cb_ctx,
  2659. (void *)ind_msg->data,
  2660. ind_msg->data_len);
  2661. }
  2662. static int cnss_ims_wfc_call_twt_cfg_send_sync
  2663. (struct cnss_plat_data *plat_priv,
  2664. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg)
  2665. {
  2666. struct ims_private_service_wfc_call_twt_config_req_msg_v01 *req;
  2667. struct ims_private_service_wfc_call_twt_config_rsp_msg_v01 *resp;
  2668. struct qmi_txn txn;
  2669. int ret = 0;
  2670. if (!test_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state)) {
  2671. cnss_pr_err("Drop FW WFC indication as IMS QMI not connected\n");
  2672. return -EINVAL;
  2673. }
  2674. req = kzalloc(sizeof(*req), GFP_KERNEL);
  2675. if (!req)
  2676. return -ENOMEM;
  2677. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  2678. if (!resp) {
  2679. kfree(req);
  2680. return -ENOMEM;
  2681. }
  2682. req->twt_sta_start_valid = ind_msg->twt_sta_start_valid;
  2683. req->twt_sta_start = ind_msg->twt_sta_start;
  2684. req->twt_sta_int_valid = ind_msg->twt_sta_int_valid;
  2685. req->twt_sta_int = ind_msg->twt_sta_int;
  2686. req->twt_sta_upo_valid = ind_msg->twt_sta_upo_valid;
  2687. req->twt_sta_upo = ind_msg->twt_sta_upo;
  2688. req->twt_sta_sp_valid = ind_msg->twt_sta_sp_valid;
  2689. req->twt_sta_sp = ind_msg->twt_sta_sp;
  2690. req->twt_sta_dl_valid = req->twt_sta_dl_valid;
  2691. req->twt_sta_dl = req->twt_sta_dl;
  2692. req->twt_sta_config_changed_valid =
  2693. ind_msg->twt_sta_config_changed_valid;
  2694. req->twt_sta_config_changed = ind_msg->twt_sta_config_changed;
  2695. cnss_pr_dbg("CNSS->IMS: TWT_CFG_REQ: state: 0x%lx\n",
  2696. plat_priv->driver_state);
  2697. ret =
  2698. qmi_txn_init(&plat_priv->ims_qmi, &txn,
  2699. ims_private_service_wfc_call_twt_config_rsp_msg_v01_ei,
  2700. resp);
  2701. if (ret < 0) {
  2702. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Txn Init Err: %d\n",
  2703. ret);
  2704. goto out;
  2705. }
  2706. ret =
  2707. qmi_send_request(&plat_priv->ims_qmi, NULL, &txn,
  2708. QMI_IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_V01,
  2709. IMS_PRIVATE_SERVICE_WFC_CALL_TWT_CONFIG_REQ_MSG_V01_MAX_MSG_LEN,
  2710. ims_private_service_wfc_call_twt_config_req_msg_v01_ei, req);
  2711. if (ret < 0) {
  2712. qmi_txn_cancel(&txn);
  2713. cnss_pr_err("CNSS->IMS: TWT_CFG_REQ: QMI Send Err: %d\n", ret);
  2714. goto out;
  2715. }
  2716. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  2717. if (ret < 0) {
  2718. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: QMI Wait Err: %d\n", ret);
  2719. goto out;
  2720. }
  2721. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  2722. cnss_pr_err("IMS->CNSS: TWT_CFG_RSP: Result: %d Err: %d\n",
  2723. resp->resp.result, resp->resp.error);
  2724. ret = -resp->resp.result;
  2725. goto out;
  2726. }
  2727. ret = 0;
  2728. out:
  2729. kfree(req);
  2730. kfree(resp);
  2731. return ret;
  2732. }
  2733. int cnss_process_twt_cfg_ind_event(struct cnss_plat_data *plat_priv,
  2734. void *data)
  2735. {
  2736. int ret;
  2737. struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2738. ret = cnss_ims_wfc_call_twt_cfg_send_sync(plat_priv, ind_msg);
  2739. kfree(data);
  2740. return ret;
  2741. }
  2742. static void cnss_wlfw_process_twt_cfg_ind(struct qmi_handle *qmi_wlfw,
  2743. struct sockaddr_qrtr *sq,
  2744. struct qmi_txn *txn,
  2745. const void *data)
  2746. {
  2747. struct cnss_plat_data *plat_priv =
  2748. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2749. const struct wlfw_wfc_call_twt_config_ind_msg_v01 *ind_msg = data;
  2750. struct wlfw_wfc_call_twt_config_ind_msg_v01 *event_data;
  2751. if (!txn) {
  2752. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Spurious indication\n");
  2753. return;
  2754. }
  2755. if (!ind_msg) {
  2756. cnss_pr_err("FW->CNSS: TWT_CFG_IND: Invalid indication\n");
  2757. return;
  2758. }
  2759. cnss_pr_dbg("FW->CNSS: TWT_CFG_IND: %x %llx, %x %x, %x %x, %x %x, %x %x, %x %x\n",
  2760. ind_msg->twt_sta_start_valid, ind_msg->twt_sta_start,
  2761. ind_msg->twt_sta_int_valid, ind_msg->twt_sta_int,
  2762. ind_msg->twt_sta_upo_valid, ind_msg->twt_sta_upo,
  2763. ind_msg->twt_sta_sp_valid, ind_msg->twt_sta_sp,
  2764. ind_msg->twt_sta_dl_valid, ind_msg->twt_sta_dl,
  2765. ind_msg->twt_sta_config_changed_valid,
  2766. ind_msg->twt_sta_config_changed);
  2767. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  2768. if (!event_data)
  2769. return;
  2770. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 0,
  2771. event_data);
  2772. }
  2773. static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = {
  2774. {
  2775. .type = QMI_INDICATION,
  2776. .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01,
  2777. .ei = wlfw_request_mem_ind_msg_v01_ei,
  2778. .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01),
  2779. .fn = cnss_wlfw_request_mem_ind_cb
  2780. },
  2781. {
  2782. .type = QMI_INDICATION,
  2783. .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01,
  2784. .ei = wlfw_fw_mem_ready_ind_msg_v01_ei,
  2785. .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01),
  2786. .fn = cnss_wlfw_fw_mem_ready_ind_cb
  2787. },
  2788. {
  2789. .type = QMI_INDICATION,
  2790. .msg_id = QMI_WLFW_FW_READY_IND_V01,
  2791. .ei = wlfw_fw_ready_ind_msg_v01_ei,
  2792. .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01),
  2793. .fn = cnss_wlfw_fw_ready_ind_cb
  2794. },
  2795. {
  2796. .type = QMI_INDICATION,
  2797. .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01,
  2798. .ei = wlfw_fw_init_done_ind_msg_v01_ei,
  2799. .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01),
  2800. .fn = cnss_wlfw_fw_init_done_ind_cb
  2801. },
  2802. {
  2803. .type = QMI_INDICATION,
  2804. .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01,
  2805. .ei = wlfw_pin_connect_result_ind_msg_v01_ei,
  2806. .decoded_size =
  2807. sizeof(struct wlfw_pin_connect_result_ind_msg_v01),
  2808. .fn = cnss_wlfw_pin_result_ind_cb
  2809. },
  2810. {
  2811. .type = QMI_INDICATION,
  2812. .msg_id = QMI_WLFW_CAL_DONE_IND_V01,
  2813. .ei = wlfw_cal_done_ind_msg_v01_ei,
  2814. .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01),
  2815. .fn = cnss_wlfw_cal_done_ind_cb
  2816. },
  2817. {
  2818. .type = QMI_INDICATION,
  2819. .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01,
  2820. .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei,
  2821. .decoded_size =
  2822. sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01),
  2823. .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb
  2824. },
  2825. {
  2826. .type = QMI_INDICATION,
  2827. .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01,
  2828. .ei = wlfw_qdss_trace_save_ind_msg_v01_ei,
  2829. .decoded_size =
  2830. sizeof(struct wlfw_qdss_trace_save_ind_msg_v01),
  2831. .fn = cnss_wlfw_fw_mem_file_save_ind_cb
  2832. },
  2833. {
  2834. .type = QMI_INDICATION,
  2835. .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01,
  2836. .ei = wlfw_qdss_trace_free_ind_msg_v01_ei,
  2837. .decoded_size =
  2838. sizeof(struct wlfw_qdss_trace_free_ind_msg_v01),
  2839. .fn = cnss_wlfw_qdss_trace_free_ind_cb
  2840. },
  2841. {
  2842. .type = QMI_INDICATION,
  2843. .msg_id = QMI_WLFW_RESPOND_GET_INFO_IND_V01,
  2844. .ei = wlfw_respond_get_info_ind_msg_v01_ei,
  2845. .decoded_size =
  2846. sizeof(struct wlfw_respond_get_info_ind_msg_v01),
  2847. .fn = cnss_wlfw_respond_get_info_ind_cb
  2848. },
  2849. {
  2850. .type = QMI_INDICATION,
  2851. .msg_id = QMI_WLFW_WFC_CALL_TWT_CONFIG_IND_V01,
  2852. .ei = wlfw_wfc_call_twt_config_ind_msg_v01_ei,
  2853. .decoded_size =
  2854. sizeof(struct wlfw_wfc_call_twt_config_ind_msg_v01),
  2855. .fn = cnss_wlfw_process_twt_cfg_ind
  2856. },
  2857. {}
  2858. };
  2859. static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv,
  2860. void *data)
  2861. {
  2862. struct cnss_qmi_event_server_arrive_data *event_data = data;
  2863. struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw;
  2864. struct sockaddr_qrtr sq = { 0 };
  2865. int ret = 0;
  2866. if (!event_data)
  2867. return -EINVAL;
  2868. sq.sq_family = AF_QIPCRTR;
  2869. sq.sq_node = event_data->node;
  2870. sq.sq_port = event_data->port;
  2871. ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq,
  2872. sizeof(sq), 0);
  2873. if (ret < 0) {
  2874. cnss_pr_err("Failed to connect to QMI WLFW remote service port\n");
  2875. goto out;
  2876. }
  2877. set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2878. cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n",
  2879. plat_priv->driver_state);
  2880. kfree(data);
  2881. return 0;
  2882. out:
  2883. CNSS_QMI_ASSERT();
  2884. kfree(data);
  2885. return ret;
  2886. }
  2887. int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data)
  2888. {
  2889. int ret = 0;
  2890. if (!plat_priv)
  2891. return -ENODEV;
  2892. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  2893. cnss_pr_err("Unexpected WLFW server arrive\n");
  2894. CNSS_ASSERT(0);
  2895. return -EINVAL;
  2896. }
  2897. cnss_ignore_qmi_failure(false);
  2898. ret = cnss_wlfw_connect_to_server(plat_priv, data);
  2899. if (ret < 0)
  2900. goto out;
  2901. ret = cnss_wlfw_ind_register_send_sync(plat_priv);
  2902. if (ret < 0) {
  2903. if (ret == -EALREADY)
  2904. ret = 0;
  2905. goto out;
  2906. }
  2907. ret = cnss_wlfw_host_cap_send_sync(plat_priv);
  2908. if (ret < 0)
  2909. goto out;
  2910. return 0;
  2911. out:
  2912. return ret;
  2913. }
  2914. int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv)
  2915. {
  2916. int ret;
  2917. if (!plat_priv)
  2918. return -ENODEV;
  2919. clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state);
  2920. cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n",
  2921. plat_priv->driver_state);
  2922. cnss_qmi_deinit(plat_priv);
  2923. clear_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2924. ret = cnss_qmi_init(plat_priv);
  2925. if (ret < 0) {
  2926. cnss_pr_err("QMI WLFW service registraton failed, ret\n", ret);
  2927. CNSS_ASSERT(0);
  2928. }
  2929. return 0;
  2930. }
  2931. static int wlfw_new_server(struct qmi_handle *qmi_wlfw,
  2932. struct qmi_service *service)
  2933. {
  2934. struct cnss_plat_data *plat_priv =
  2935. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2936. struct cnss_qmi_event_server_arrive_data *event_data;
  2937. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2938. cnss_pr_info("WLFW server delete in progress, Ignore server arrive, state: 0x%lx\n",
  2939. plat_priv->driver_state);
  2940. return 0;
  2941. }
  2942. cnss_pr_dbg("WLFW server arriving: node %u port %u\n",
  2943. service->node, service->port);
  2944. event_data = kzalloc(sizeof(*event_data), GFP_KERNEL);
  2945. if (!event_data)
  2946. return -ENOMEM;
  2947. event_data->node = service->node;
  2948. event_data->port = service->port;
  2949. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE,
  2950. 0, event_data);
  2951. return 0;
  2952. }
  2953. static void wlfw_del_server(struct qmi_handle *qmi_wlfw,
  2954. struct qmi_service *service)
  2955. {
  2956. struct cnss_plat_data *plat_priv =
  2957. container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw);
  2958. if (plat_priv && test_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state)) {
  2959. cnss_pr_info("WLFW server delete in progress, Ignore server delete, state: 0x%lx\n",
  2960. plat_priv->driver_state);
  2961. return;
  2962. }
  2963. cnss_pr_dbg("WLFW server exiting\n");
  2964. if (plat_priv) {
  2965. cnss_ignore_qmi_failure(true);
  2966. set_bit(CNSS_QMI_DEL_SERVER, &plat_priv->driver_state);
  2967. }
  2968. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT,
  2969. 0, NULL);
  2970. }
  2971. static struct qmi_ops qmi_wlfw_ops = {
  2972. .new_server = wlfw_new_server,
  2973. .del_server = wlfw_del_server,
  2974. };
  2975. static int cnss_qmi_add_lookup(struct cnss_plat_data *plat_priv)
  2976. {
  2977. unsigned int id = WLFW_SERVICE_INS_ID_V01;
  2978. /* In order to support dual wlan card attach case,
  2979. * need separate qmi service instance id for each dev
  2980. */
  2981. if (cnss_is_dual_wlan_enabled() && plat_priv->qrtr_node_id != 0 &&
  2982. plat_priv->wlfw_service_instance_id != 0)
  2983. id = plat_priv->wlfw_service_instance_id;
  2984. return qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01,
  2985. WLFW_SERVICE_VERS_V01, id);
  2986. }
  2987. int cnss_qmi_init(struct cnss_plat_data *plat_priv)
  2988. {
  2989. int ret = 0;
  2990. cnss_get_qrtr_info(plat_priv);
  2991. ret = qmi_handle_init(&plat_priv->qmi_wlfw,
  2992. QMI_WLFW_MAX_RECV_BUF_SIZE,
  2993. &qmi_wlfw_ops, qmi_wlfw_msg_handlers);
  2994. if (ret < 0) {
  2995. cnss_pr_err("Failed to initialize WLFW QMI handle, err: %d\n",
  2996. ret);
  2997. goto out;
  2998. }
  2999. ret = cnss_qmi_add_lookup(plat_priv);
  3000. if (ret < 0)
  3001. cnss_pr_err("Failed to add WLFW QMI lookup, err: %d\n", ret);
  3002. out:
  3003. return ret;
  3004. }
  3005. void cnss_qmi_deinit(struct cnss_plat_data *plat_priv)
  3006. {
  3007. qmi_handle_release(&plat_priv->qmi_wlfw);
  3008. }
  3009. int cnss_qmi_get_dms_mac(struct cnss_plat_data *plat_priv)
  3010. {
  3011. struct dms_get_mac_address_req_msg_v01 req;
  3012. struct dms_get_mac_address_resp_msg_v01 resp;
  3013. struct qmi_txn txn;
  3014. int ret = 0;
  3015. if (!test_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state)) {
  3016. cnss_pr_err("DMS QMI connection not established\n");
  3017. return -EINVAL;
  3018. }
  3019. cnss_pr_dbg("Requesting DMS MAC address");
  3020. memset(&resp, 0, sizeof(resp));
  3021. ret = qmi_txn_init(&plat_priv->qmi_dms, &txn,
  3022. dms_get_mac_address_resp_msg_v01_ei, &resp);
  3023. if (ret < 0) {
  3024. cnss_pr_err("Failed to initialize txn for dms, err: %d\n",
  3025. ret);
  3026. goto out;
  3027. }
  3028. req.device = DMS_DEVICE_MAC_WLAN_V01;
  3029. ret = qmi_send_request(&plat_priv->qmi_dms, NULL, &txn,
  3030. QMI_DMS_GET_MAC_ADDRESS_REQ_V01,
  3031. DMS_GET_MAC_ADDRESS_REQ_MSG_V01_MAX_MSG_LEN,
  3032. dms_get_mac_address_req_msg_v01_ei, &req);
  3033. if (ret < 0) {
  3034. qmi_txn_cancel(&txn);
  3035. cnss_pr_err("Failed to send QMI_DMS_GET_MAC_ADDRESS_REQ_V01, err: %d\n",
  3036. ret);
  3037. goto out;
  3038. }
  3039. ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF);
  3040. if (ret < 0) {
  3041. cnss_pr_err("Failed to wait for QMI_DMS_GET_MAC_ADDRESS_RESP_V01, err: %d\n",
  3042. ret);
  3043. goto out;
  3044. }
  3045. if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
  3046. cnss_pr_err("QMI_DMS_GET_MAC_ADDRESS_REQ_V01 failed, result: %d, err: %d\n",
  3047. resp.resp.result, resp.resp.error);
  3048. ret = -resp.resp.result;
  3049. goto out;
  3050. }
  3051. if (!resp.mac_address_valid ||
  3052. resp.mac_address_len != QMI_WLFW_MAC_ADDR_SIZE_V01) {
  3053. cnss_pr_err("Invalid MAC address received from DMS\n");
  3054. plat_priv->dms.mac_valid = false;
  3055. goto out;
  3056. }
  3057. plat_priv->dms.mac_valid = true;
  3058. memcpy(plat_priv->dms.mac, resp.mac_address, QMI_WLFW_MAC_ADDR_SIZE_V01);
  3059. cnss_pr_info("Received DMS MAC: [%pM]\n", plat_priv->dms.mac);
  3060. out:
  3061. return ret;
  3062. }
  3063. static int cnss_dms_connect_to_server(struct cnss_plat_data *plat_priv,
  3064. unsigned int node, unsigned int port)
  3065. {
  3066. struct qmi_handle *qmi_dms = &plat_priv->qmi_dms;
  3067. struct sockaddr_qrtr sq = {0};
  3068. int ret = 0;
  3069. sq.sq_family = AF_QIPCRTR;
  3070. sq.sq_node = node;
  3071. sq.sq_port = port;
  3072. ret = kernel_connect(qmi_dms->sock, (struct sockaddr *)&sq,
  3073. sizeof(sq), 0);
  3074. if (ret < 0) {
  3075. cnss_pr_err("Failed to connect to QMI DMS remote service Node: %d Port: %d\n",
  3076. node, port);
  3077. goto out;
  3078. }
  3079. set_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3080. cnss_pr_info("QMI DMS service connected, state: 0x%lx\n",
  3081. plat_priv->driver_state);
  3082. out:
  3083. return ret;
  3084. }
  3085. static int dms_new_server(struct qmi_handle *qmi_dms,
  3086. struct qmi_service *service)
  3087. {
  3088. struct cnss_plat_data *plat_priv =
  3089. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3090. if (!service)
  3091. return -EINVAL;
  3092. return cnss_dms_connect_to_server(plat_priv, service->node,
  3093. service->port);
  3094. }
  3095. static void cnss_dms_server_exit_work(struct work_struct *work)
  3096. {
  3097. int ret;
  3098. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3099. cnss_dms_deinit(plat_priv);
  3100. cnss_pr_info("QMI DMS Server Exit");
  3101. clear_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3102. ret = cnss_dms_init(plat_priv);
  3103. if (ret < 0)
  3104. cnss_pr_err("QMI DMS service registraton failed, ret\n", ret);
  3105. }
  3106. static DECLARE_WORK(cnss_dms_del_work, cnss_dms_server_exit_work);
  3107. static void dms_del_server(struct qmi_handle *qmi_dms,
  3108. struct qmi_service *service)
  3109. {
  3110. struct cnss_plat_data *plat_priv =
  3111. container_of(qmi_dms, struct cnss_plat_data, qmi_dms);
  3112. if (!plat_priv)
  3113. return;
  3114. if (test_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state)) {
  3115. cnss_pr_info("DMS server delete or cnss remove in progress, Ignore server delete: 0x%lx\n",
  3116. plat_priv->driver_state);
  3117. return;
  3118. }
  3119. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3120. clear_bit(CNSS_QMI_DMS_CONNECTED, &plat_priv->driver_state);
  3121. cnss_pr_info("QMI DMS service disconnected, state: 0x%lx\n",
  3122. plat_priv->driver_state);
  3123. schedule_work(&cnss_dms_del_work);
  3124. }
  3125. void cnss_cancel_dms_work(void)
  3126. {
  3127. cancel_work_sync(&cnss_dms_del_work);
  3128. }
  3129. static struct qmi_ops qmi_dms_ops = {
  3130. .new_server = dms_new_server,
  3131. .del_server = dms_del_server,
  3132. };
  3133. int cnss_dms_init(struct cnss_plat_data *plat_priv)
  3134. {
  3135. int ret = 0;
  3136. ret = qmi_handle_init(&plat_priv->qmi_dms, DMS_QMI_MAX_MSG_LEN,
  3137. &qmi_dms_ops, NULL);
  3138. if (ret < 0) {
  3139. cnss_pr_err("Failed to initialize DMS handle, err: %d\n", ret);
  3140. goto out;
  3141. }
  3142. ret = qmi_add_lookup(&plat_priv->qmi_dms, DMS_SERVICE_ID_V01,
  3143. DMS_SERVICE_VERS_V01, 0);
  3144. if (ret < 0)
  3145. cnss_pr_err("Failed to add DMS lookup, err: %d\n", ret);
  3146. out:
  3147. return ret;
  3148. }
  3149. void cnss_dms_deinit(struct cnss_plat_data *plat_priv)
  3150. {
  3151. set_bit(CNSS_DMS_DEL_SERVER, &plat_priv->driver_state);
  3152. qmi_handle_release(&plat_priv->qmi_dms);
  3153. }
  3154. int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv)
  3155. {
  3156. int ret;
  3157. struct coex_antenna_switch_to_wlan_req_msg_v01 *req;
  3158. struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp;
  3159. struct qmi_txn txn;
  3160. if (!plat_priv)
  3161. return -ENODEV;
  3162. cnss_pr_dbg("Sending coex antenna switch_to_wlan\n");
  3163. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3164. if (!req)
  3165. return -ENOMEM;
  3166. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3167. if (!resp) {
  3168. kfree(req);
  3169. return -ENOMEM;
  3170. }
  3171. req->antenna = plat_priv->antenna;
  3172. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3173. coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp);
  3174. if (ret < 0) {
  3175. cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n",
  3176. ret);
  3177. goto out;
  3178. }
  3179. ret = qmi_send_request
  3180. (&plat_priv->coex_qmi, NULL, &txn,
  3181. QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01,
  3182. COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN,
  3183. coex_antenna_switch_to_wlan_req_msg_v01_ei, req);
  3184. if (ret < 0) {
  3185. qmi_txn_cancel(&txn);
  3186. cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n",
  3187. ret);
  3188. goto out;
  3189. }
  3190. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3191. if (ret < 0) {
  3192. cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n",
  3193. ret);
  3194. goto out;
  3195. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3196. cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n",
  3197. resp->resp.result, resp->resp.error);
  3198. ret = -resp->resp.result;
  3199. goto out;
  3200. }
  3201. if (resp->grant_valid)
  3202. plat_priv->grant = resp->grant;
  3203. cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant);
  3204. kfree(resp);
  3205. kfree(req);
  3206. return 0;
  3207. out:
  3208. kfree(resp);
  3209. kfree(req);
  3210. return ret;
  3211. }
  3212. int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv)
  3213. {
  3214. int ret;
  3215. struct coex_antenna_switch_to_mdm_req_msg_v01 *req;
  3216. struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp;
  3217. struct qmi_txn txn;
  3218. if (!plat_priv)
  3219. return -ENODEV;
  3220. cnss_pr_dbg("Sending coex antenna switch_to_mdm\n");
  3221. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3222. if (!req)
  3223. return -ENOMEM;
  3224. resp = kzalloc(sizeof(*resp), GFP_KERNEL);
  3225. if (!resp) {
  3226. kfree(req);
  3227. return -ENOMEM;
  3228. }
  3229. req->antenna = plat_priv->antenna;
  3230. ret = qmi_txn_init(&plat_priv->coex_qmi, &txn,
  3231. coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp);
  3232. if (ret < 0) {
  3233. cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n",
  3234. ret);
  3235. goto out;
  3236. }
  3237. ret = qmi_send_request
  3238. (&plat_priv->coex_qmi, NULL, &txn,
  3239. QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01,
  3240. COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN,
  3241. coex_antenna_switch_to_mdm_req_msg_v01_ei, req);
  3242. if (ret < 0) {
  3243. qmi_txn_cancel(&txn);
  3244. cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n",
  3245. ret);
  3246. goto out;
  3247. }
  3248. ret = qmi_txn_wait(&txn, COEX_TIMEOUT);
  3249. if (ret < 0) {
  3250. cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n",
  3251. ret);
  3252. goto out;
  3253. } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3254. cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n",
  3255. resp->resp.result, resp->resp.error);
  3256. ret = -resp->resp.result;
  3257. goto out;
  3258. }
  3259. kfree(resp);
  3260. kfree(req);
  3261. return 0;
  3262. out:
  3263. kfree(resp);
  3264. kfree(req);
  3265. return ret;
  3266. }
  3267. int cnss_send_subsys_restart_level_msg(struct cnss_plat_data *plat_priv)
  3268. {
  3269. int ret;
  3270. struct wlfw_subsys_restart_level_req_msg_v01 req;
  3271. struct wlfw_subsys_restart_level_resp_msg_v01 resp;
  3272. u8 pcss_enabled;
  3273. if (!plat_priv)
  3274. return -ENODEV;
  3275. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  3276. cnss_pr_dbg("Can't send pcss cmd before fw ready\n");
  3277. return 0;
  3278. }
  3279. pcss_enabled = plat_priv->recovery_pcss_enabled;
  3280. cnss_pr_dbg("Sending pcss recovery status: %d\n", pcss_enabled);
  3281. req.restart_level_type_valid = 1;
  3282. req.restart_level_type = pcss_enabled;
  3283. ret = qmi_send_wait(&plat_priv->qmi_wlfw, &req, &resp,
  3284. wlfw_subsys_restart_level_req_msg_v01_ei,
  3285. wlfw_subsys_restart_level_resp_msg_v01_ei,
  3286. QMI_WLFW_SUBSYS_RESTART_LEVEL_REQ_V01,
  3287. WLFW_SUBSYS_RESTART_LEVEL_REQ_MSG_V01_MAX_MSG_LEN,
  3288. QMI_WLFW_TIMEOUT_JF);
  3289. if (ret < 0)
  3290. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  3291. return ret;
  3292. }
  3293. static int coex_new_server(struct qmi_handle *qmi,
  3294. struct qmi_service *service)
  3295. {
  3296. struct cnss_plat_data *plat_priv =
  3297. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3298. struct sockaddr_qrtr sq = { 0 };
  3299. int ret = 0;
  3300. cnss_pr_dbg("COEX server arrive: node %u port %u\n",
  3301. service->node, service->port);
  3302. sq.sq_family = AF_QIPCRTR;
  3303. sq.sq_node = service->node;
  3304. sq.sq_port = service->port;
  3305. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3306. if (ret < 0) {
  3307. cnss_pr_err("Fail to connect to remote service port\n");
  3308. return ret;
  3309. }
  3310. set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3311. cnss_pr_dbg("COEX Server Connected: 0x%lx\n",
  3312. plat_priv->driver_state);
  3313. return 0;
  3314. }
  3315. static void coex_del_server(struct qmi_handle *qmi,
  3316. struct qmi_service *service)
  3317. {
  3318. struct cnss_plat_data *plat_priv =
  3319. container_of(qmi, struct cnss_plat_data, coex_qmi);
  3320. cnss_pr_dbg("COEX server exit\n");
  3321. clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state);
  3322. }
  3323. static struct qmi_ops coex_qmi_ops = {
  3324. .new_server = coex_new_server,
  3325. .del_server = coex_del_server,
  3326. };
  3327. int cnss_register_coex_service(struct cnss_plat_data *plat_priv)
  3328. { int ret;
  3329. ret = qmi_handle_init(&plat_priv->coex_qmi,
  3330. COEX_SERVICE_MAX_MSG_LEN,
  3331. &coex_qmi_ops, NULL);
  3332. if (ret < 0)
  3333. return ret;
  3334. ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01,
  3335. COEX_SERVICE_VERS_V01, 0);
  3336. return ret;
  3337. }
  3338. void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv)
  3339. {
  3340. qmi_handle_release(&plat_priv->coex_qmi);
  3341. }
  3342. /* IMS Service */
  3343. int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv)
  3344. {
  3345. int ret;
  3346. struct ims_private_service_subscribe_for_indications_req_msg_v01 *req;
  3347. struct qmi_txn *txn;
  3348. if (!plat_priv)
  3349. return -ENODEV;
  3350. cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n");
  3351. req = kzalloc(sizeof(*req), GFP_KERNEL);
  3352. if (!req)
  3353. return -ENOMEM;
  3354. req->wfc_call_status_valid = 1;
  3355. req->wfc_call_status = 1;
  3356. txn = &plat_priv->txn;
  3357. ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL);
  3358. if (ret < 0) {
  3359. cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n",
  3360. ret);
  3361. goto out;
  3362. }
  3363. ret = qmi_send_request
  3364. (&plat_priv->ims_qmi, NULL, txn,
  3365. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3366. IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN,
  3367. ims_private_service_subscribe_ind_req_msg_v01_ei, req);
  3368. if (ret < 0) {
  3369. qmi_txn_cancel(txn);
  3370. cnss_pr_err("Fail to send ims subscribe for indication req %d\n",
  3371. ret);
  3372. goto out;
  3373. }
  3374. kfree(req);
  3375. return 0;
  3376. out:
  3377. kfree(req);
  3378. return ret;
  3379. }
  3380. static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi,
  3381. struct sockaddr_qrtr *sq,
  3382. struct qmi_txn *txn,
  3383. const void *data)
  3384. {
  3385. const
  3386. struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp =
  3387. data;
  3388. cnss_pr_dbg("Received IMS subscribe indication response\n");
  3389. if (!txn) {
  3390. cnss_pr_err("spurious response\n");
  3391. return;
  3392. }
  3393. if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
  3394. cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n",
  3395. resp->resp.result, resp->resp.error);
  3396. txn->result = -resp->resp.result;
  3397. }
  3398. }
  3399. int cnss_process_wfc_call_ind_event(struct cnss_plat_data *plat_priv,
  3400. void *data)
  3401. {
  3402. int ret;
  3403. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3404. ret = cnss_wlfw_wfc_call_status_send_sync(plat_priv, ind_msg);
  3405. kfree(data);
  3406. return ret;
  3407. }
  3408. static void
  3409. cnss_ims_process_wfc_call_ind_cb(struct qmi_handle *ims_qmi,
  3410. struct sockaddr_qrtr *sq,
  3411. struct qmi_txn *txn, const void *data)
  3412. {
  3413. struct cnss_plat_data *plat_priv =
  3414. container_of(ims_qmi, struct cnss_plat_data, ims_qmi);
  3415. const
  3416. struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data;
  3417. struct ims_private_service_wfc_call_status_ind_msg_v01 *event_data;
  3418. if (!txn) {
  3419. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Spurious indication\n");
  3420. return;
  3421. }
  3422. if (!ind_msg) {
  3423. cnss_pr_err("IMS->CNSS: WFC_CALL_IND: Invalid indication\n");
  3424. return;
  3425. }
  3426. cnss_pr_dbg("IMS->CNSS: WFC_CALL_IND: %x, %x %x, %x %x, %x %llx, %x %x, %x %x\n",
  3427. ind_msg->wfc_call_active, ind_msg->all_wfc_calls_held_valid,
  3428. ind_msg->all_wfc_calls_held,
  3429. ind_msg->is_wfc_emergency_valid, ind_msg->is_wfc_emergency,
  3430. ind_msg->twt_ims_start_valid, ind_msg->twt_ims_start,
  3431. ind_msg->twt_ims_int_valid, ind_msg->twt_ims_int,
  3432. ind_msg->media_quality_valid, ind_msg->media_quality);
  3433. event_data = kmemdup(ind_msg, sizeof(*event_data), GFP_KERNEL);
  3434. if (!event_data)
  3435. return;
  3436. cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
  3437. 0, event_data);
  3438. }
  3439. static struct qmi_msg_handler qmi_ims_msg_handlers[] = {
  3440. {
  3441. .type = QMI_RESPONSE,
  3442. .msg_id =
  3443. QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01,
  3444. .ei =
  3445. ims_private_service_subscribe_ind_rsp_msg_v01_ei,
  3446. .decoded_size = sizeof(struct
  3447. ims_private_service_subscribe_for_indications_rsp_msg_v01),
  3448. .fn = ims_subscribe_for_indication_resp_cb
  3449. },
  3450. {
  3451. .type = QMI_INDICATION,
  3452. .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01,
  3453. .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei,
  3454. .decoded_size =
  3455. sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01),
  3456. .fn = cnss_ims_process_wfc_call_ind_cb
  3457. },
  3458. {}
  3459. };
  3460. static int ims_new_server(struct qmi_handle *qmi,
  3461. struct qmi_service *service)
  3462. {
  3463. struct cnss_plat_data *plat_priv =
  3464. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3465. struct sockaddr_qrtr sq = { 0 };
  3466. int ret = 0;
  3467. cnss_pr_dbg("IMS server arrive: node %u port %u\n",
  3468. service->node, service->port);
  3469. sq.sq_family = AF_QIPCRTR;
  3470. sq.sq_node = service->node;
  3471. sq.sq_port = service->port;
  3472. ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0);
  3473. if (ret < 0) {
  3474. cnss_pr_err("Fail to connect to remote service port\n");
  3475. return ret;
  3476. }
  3477. set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3478. cnss_pr_dbg("IMS Server Connected: 0x%lx\n",
  3479. plat_priv->driver_state);
  3480. ret = ims_subscribe_for_indication_send_async(plat_priv);
  3481. return ret;
  3482. }
  3483. static void ims_del_server(struct qmi_handle *qmi,
  3484. struct qmi_service *service)
  3485. {
  3486. struct cnss_plat_data *plat_priv =
  3487. container_of(qmi, struct cnss_plat_data, ims_qmi);
  3488. cnss_pr_dbg("IMS server exit\n");
  3489. clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state);
  3490. }
  3491. static struct qmi_ops ims_qmi_ops = {
  3492. .new_server = ims_new_server,
  3493. .del_server = ims_del_server,
  3494. };
  3495. int cnss_register_ims_service(struct cnss_plat_data *plat_priv)
  3496. { int ret;
  3497. ret = qmi_handle_init(&plat_priv->ims_qmi,
  3498. IMSPRIVATE_SERVICE_MAX_MSG_LEN,
  3499. &ims_qmi_ops, qmi_ims_msg_handlers);
  3500. if (ret < 0)
  3501. return ret;
  3502. ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01,
  3503. IMSPRIVATE_SERVICE_VERS_V01, 0);
  3504. return ret;
  3505. }
  3506. void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv)
  3507. {
  3508. qmi_handle_release(&plat_priv->ims_qmi);
  3509. }