cam_mem_mgr.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #include "cam_compat.h"
  13. #include "cam_req_mgr_util.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_smmu_api.h"
  16. #include "cam_debug_util.h"
  17. #include "cam_trace.h"
  18. #include "cam_common_util.h"
  19. static struct cam_mem_table tbl;
  20. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  21. static void cam_mem_mgr_print_tbl(void)
  22. {
  23. int i;
  24. uint64_t ms, tmp, hrs, min, sec;
  25. struct timespec64 *ts = NULL;
  26. struct timespec64 current_ts;
  27. ktime_get_real_ts64(&(current_ts));
  28. tmp = current_ts.tv_sec;
  29. ms = (current_ts.tv_nsec) / 1000000;
  30. sec = do_div(tmp, 60);
  31. min = do_div(tmp, 60);
  32. hrs = do_div(tmp, 24);
  33. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  34. hrs, min, sec, ms);
  35. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  36. if (tbl.bufq[i].active) {
  37. ts = &tbl.bufq[i].timestamp;
  38. tmp = ts->tv_sec;
  39. ms = (ts->tv_nsec) / 1000000;
  40. sec = do_div(tmp, 60);
  41. min = do_div(tmp, 60);
  42. hrs = do_div(tmp, 24);
  43. CAM_INFO(CAM_MEM,
  44. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  45. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  46. tbl.bufq[i].len);
  47. }
  48. }
  49. }
  50. static int cam_mem_util_get_dma_dir(uint32_t flags)
  51. {
  52. int rc = -EINVAL;
  53. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  54. rc = DMA_TO_DEVICE;
  55. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  56. rc = DMA_FROM_DEVICE;
  57. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  58. rc = DMA_BIDIRECTIONAL;
  59. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  60. rc = DMA_BIDIRECTIONAL;
  61. return rc;
  62. }
  63. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  64. uintptr_t *vaddr,
  65. size_t *len)
  66. {
  67. int i, j, rc;
  68. void *addr;
  69. /*
  70. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  71. * need to be called in pair to avoid stability issue.
  72. */
  73. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  74. if (rc) {
  75. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  76. return rc;
  77. }
  78. /*
  79. * Code could be simplified if ION support of dma_buf_vmap is
  80. * available. This workaround takes the avandaage that ion_alloc
  81. * returns a virtually contiguous memory region, so we just need
  82. * to _kmap each individual page and then only use the virtual
  83. * address returned from the first call to _kmap.
  84. */
  85. for (i = 0; i < PAGE_ALIGN(dmabuf->size) / PAGE_SIZE; i++) {
  86. addr = dma_buf_kmap(dmabuf, i);
  87. if (IS_ERR_OR_NULL(addr)) {
  88. CAM_ERR(CAM_MEM, "kernel map fail");
  89. for (j = 0; j < i; j++)
  90. dma_buf_kunmap(dmabuf,
  91. j,
  92. (void *)(*vaddr + (j * PAGE_SIZE)));
  93. *vaddr = 0;
  94. *len = 0;
  95. rc = -ENOSPC;
  96. goto fail;
  97. }
  98. if (i == 0)
  99. *vaddr = (uint64_t)addr;
  100. }
  101. *len = dmabuf->size;
  102. return 0;
  103. fail:
  104. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  105. return rc;
  106. }
  107. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  108. uint64_t vaddr)
  109. {
  110. int i, rc = 0, page_num;
  111. if (!dmabuf || !vaddr) {
  112. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  113. return -EINVAL;
  114. }
  115. page_num = PAGE_ALIGN(dmabuf->size) / PAGE_SIZE;
  116. for (i = 0; i < page_num; i++) {
  117. dma_buf_kunmap(dmabuf, i,
  118. (void *)(vaddr + (i * PAGE_SIZE)));
  119. }
  120. /*
  121. * dma_buf_begin_cpu_access() and
  122. * dma_buf_end_cpu_access() need to be called in pair
  123. * to avoid stability issue.
  124. */
  125. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  126. if (rc) {
  127. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  128. dmabuf);
  129. return rc;
  130. }
  131. return rc;
  132. }
  133. static int cam_mem_mgr_create_debug_fs(void)
  134. {
  135. int rc = 0;
  136. struct dentry *dbgfileptr = NULL;
  137. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  138. if (!dbgfileptr) {
  139. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  140. rc = -ENOENT;
  141. goto end;
  142. }
  143. /* Store parent inode for cleanup in caller */
  144. tbl.dentry = dbgfileptr;
  145. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  146. tbl.dentry, &tbl.alloc_profile_enable);
  147. if (IS_ERR(dbgfileptr)) {
  148. if (PTR_ERR(dbgfileptr) == -ENODEV)
  149. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  150. else
  151. rc = PTR_ERR(dbgfileptr);
  152. }
  153. end:
  154. return rc;
  155. }
  156. int cam_mem_mgr_init(void)
  157. {
  158. int i;
  159. int bitmap_size;
  160. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  161. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  162. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  163. if (!tbl.bitmap)
  164. return -ENOMEM;
  165. tbl.bits = bitmap_size * BITS_PER_BYTE;
  166. bitmap_zero(tbl.bitmap, tbl.bits);
  167. /* We need to reserve slot 0 because 0 is invalid */
  168. set_bit(0, tbl.bitmap);
  169. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  170. tbl.bufq[i].fd = -1;
  171. tbl.bufq[i].buf_handle = -1;
  172. }
  173. mutex_init(&tbl.m_lock);
  174. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  175. cam_mem_mgr_create_debug_fs();
  176. return 0;
  177. }
  178. static int32_t cam_mem_get_slot(void)
  179. {
  180. int32_t idx;
  181. mutex_lock(&tbl.m_lock);
  182. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  183. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  184. mutex_unlock(&tbl.m_lock);
  185. return -ENOMEM;
  186. }
  187. set_bit(idx, tbl.bitmap);
  188. tbl.bufq[idx].active = true;
  189. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  190. mutex_init(&tbl.bufq[idx].q_lock);
  191. mutex_unlock(&tbl.m_lock);
  192. return idx;
  193. }
  194. static void cam_mem_put_slot(int32_t idx)
  195. {
  196. mutex_lock(&tbl.m_lock);
  197. mutex_lock(&tbl.bufq[idx].q_lock);
  198. tbl.bufq[idx].active = false;
  199. tbl.bufq[idx].is_internal = false;
  200. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  201. mutex_unlock(&tbl.bufq[idx].q_lock);
  202. mutex_destroy(&tbl.bufq[idx].q_lock);
  203. clear_bit(idx, tbl.bitmap);
  204. mutex_unlock(&tbl.m_lock);
  205. }
  206. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  207. dma_addr_t *iova_ptr, size_t *len_ptr)
  208. {
  209. int rc = 0, idx;
  210. *len_ptr = 0;
  211. if (!atomic_read(&cam_mem_mgr_state)) {
  212. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  213. return -EINVAL;
  214. }
  215. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  216. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  217. return -ENOENT;
  218. if (!tbl.bufq[idx].active)
  219. return -EAGAIN;
  220. mutex_lock(&tbl.bufq[idx].q_lock);
  221. if (buf_handle != tbl.bufq[idx].buf_handle) {
  222. rc = -EINVAL;
  223. goto handle_mismatch;
  224. }
  225. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  226. rc = cam_smmu_get_stage2_iova(mmu_handle,
  227. tbl.bufq[idx].fd,
  228. iova_ptr,
  229. len_ptr);
  230. else
  231. rc = cam_smmu_get_iova(mmu_handle,
  232. tbl.bufq[idx].fd,
  233. iova_ptr,
  234. len_ptr);
  235. if (rc) {
  236. CAM_ERR(CAM_MEM,
  237. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  238. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  239. goto handle_mismatch;
  240. }
  241. CAM_DBG(CAM_MEM,
  242. "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu",
  243. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  244. handle_mismatch:
  245. mutex_unlock(&tbl.bufq[idx].q_lock);
  246. return rc;
  247. }
  248. EXPORT_SYMBOL(cam_mem_get_io_buf);
  249. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  250. {
  251. int idx;
  252. if (!atomic_read(&cam_mem_mgr_state)) {
  253. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  254. return -EINVAL;
  255. }
  256. if (!atomic_read(&cam_mem_mgr_state)) {
  257. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  258. return -EINVAL;
  259. }
  260. if (!buf_handle || !vaddr_ptr || !len)
  261. return -EINVAL;
  262. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  263. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  264. return -EINVAL;
  265. if (!tbl.bufq[idx].active)
  266. return -EPERM;
  267. if (buf_handle != tbl.bufq[idx].buf_handle)
  268. return -EINVAL;
  269. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  270. return -EINVAL;
  271. if (tbl.bufq[idx].kmdvaddr) {
  272. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  273. *len = tbl.bufq[idx].len;
  274. } else {
  275. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  276. buf_handle);
  277. return -EINVAL;
  278. }
  279. return 0;
  280. }
  281. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  282. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  283. {
  284. int rc = 0, idx;
  285. uint32_t cache_dir;
  286. unsigned long dmabuf_flag = 0;
  287. if (!atomic_read(&cam_mem_mgr_state)) {
  288. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  289. return -EINVAL;
  290. }
  291. if (!cmd)
  292. return -EINVAL;
  293. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  294. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  295. return -EINVAL;
  296. mutex_lock(&tbl.bufq[idx].q_lock);
  297. if (!tbl.bufq[idx].active) {
  298. rc = -EINVAL;
  299. goto end;
  300. }
  301. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  302. rc = -EINVAL;
  303. goto end;
  304. }
  305. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  306. if (rc) {
  307. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  308. goto end;
  309. }
  310. if (dmabuf_flag & ION_FLAG_CACHED) {
  311. switch (cmd->mem_cache_ops) {
  312. case CAM_MEM_CLEAN_CACHE:
  313. cache_dir = DMA_TO_DEVICE;
  314. break;
  315. case CAM_MEM_INV_CACHE:
  316. cache_dir = DMA_FROM_DEVICE;
  317. break;
  318. case CAM_MEM_CLEAN_INV_CACHE:
  319. cache_dir = DMA_BIDIRECTIONAL;
  320. break;
  321. default:
  322. CAM_ERR(CAM_MEM,
  323. "invalid cache ops :%d", cmd->mem_cache_ops);
  324. rc = -EINVAL;
  325. goto end;
  326. }
  327. } else {
  328. CAM_DBG(CAM_MEM, "BUF is not cached");
  329. goto end;
  330. }
  331. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  332. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  333. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  334. if (rc) {
  335. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  336. goto end;
  337. }
  338. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  339. cache_dir);
  340. if (rc) {
  341. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  342. goto end;
  343. }
  344. end:
  345. mutex_unlock(&tbl.bufq[idx].q_lock);
  346. return rc;
  347. }
  348. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  349. static int cam_mem_util_get_dma_buf(size_t len,
  350. unsigned int heap_id_mask,
  351. unsigned int flags,
  352. struct dma_buf **buf)
  353. {
  354. int rc = 0;
  355. if (!buf) {
  356. CAM_ERR(CAM_MEM, "Invalid params");
  357. return -EINVAL;
  358. }
  359. *buf = ion_alloc(len, heap_id_mask, flags);
  360. if (IS_ERR_OR_NULL(*buf))
  361. return -ENOMEM;
  362. return rc;
  363. }
  364. static int cam_mem_util_get_dma_buf_fd(size_t len,
  365. size_t align,
  366. unsigned int heap_id_mask,
  367. unsigned int flags,
  368. struct dma_buf **buf,
  369. int *fd)
  370. {
  371. struct dma_buf *dmabuf = NULL;
  372. int rc = 0;
  373. struct timespec64 ts1, ts2;
  374. long microsec = 0;
  375. if (!buf || !fd) {
  376. CAM_ERR(CAM_MEM, "Invalid params, buf=%pK, fd=%pK", buf, fd);
  377. return -EINVAL;
  378. }
  379. if (tbl.alloc_profile_enable)
  380. CAM_GET_TIMESTAMP(ts1);
  381. *buf = ion_alloc(len, heap_id_mask, flags);
  382. if (IS_ERR_OR_NULL(*buf))
  383. return -ENOMEM;
  384. *fd = dma_buf_fd(*buf, O_CLOEXEC);
  385. if (*fd < 0) {
  386. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  387. rc = -EINVAL;
  388. goto get_fd_fail;
  389. }
  390. /*
  391. * increment the ref count so that ref count becomes 2 here
  392. * when we close fd, refcount becomes 1 and when we do
  393. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  394. */
  395. dmabuf = dma_buf_get(*fd);
  396. if (IS_ERR_OR_NULL(dmabuf)) {
  397. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  398. rc = -EINVAL;
  399. }
  400. if (tbl.alloc_profile_enable) {
  401. CAM_GET_TIMESTAMP(ts2);
  402. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  403. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  404. len, microsec);
  405. }
  406. return rc;
  407. get_fd_fail:
  408. dma_buf_put(*buf);
  409. return rc;
  410. }
  411. static int cam_mem_util_ion_alloc(struct cam_mem_mgr_alloc_cmd *cmd,
  412. struct dma_buf **dmabuf,
  413. int *fd)
  414. {
  415. uint32_t heap_id;
  416. uint32_t ion_flag = 0;
  417. int rc;
  418. if ((cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  419. (cmd->flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  420. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  421. ion_flag |=
  422. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  423. } else if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  424. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  425. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  426. } else {
  427. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  428. ION_HEAP(ION_CAMERA_HEAP_ID);
  429. }
  430. if (cmd->flags & CAM_MEM_FLAG_CACHE)
  431. ion_flag |= ION_FLAG_CACHED;
  432. else
  433. ion_flag &= ~ION_FLAG_CACHED;
  434. rc = cam_mem_util_get_dma_buf_fd(cmd->len,
  435. cmd->align,
  436. heap_id,
  437. ion_flag,
  438. dmabuf,
  439. fd);
  440. return rc;
  441. }
  442. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  443. {
  444. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  445. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  446. CAM_MEM_MMU_MAX_HANDLE);
  447. return -EINVAL;
  448. }
  449. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  450. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  451. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  452. return -EINVAL;
  453. }
  454. return 0;
  455. }
  456. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  457. {
  458. if (!cmd->flags) {
  459. CAM_ERR(CAM_MEM, "Invalid flags");
  460. return -EINVAL;
  461. }
  462. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  463. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  464. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  465. return -EINVAL;
  466. }
  467. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  468. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  469. CAM_ERR(CAM_MEM,
  470. "Kernel mapping in secure mode not allowed, flags=0x%x",
  471. cmd->flags);
  472. return -EINVAL;
  473. }
  474. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  475. CAM_ERR(CAM_MEM,
  476. "Shared memory buffers are not allowed to be mapped");
  477. return -EINVAL;
  478. }
  479. return 0;
  480. }
  481. static int cam_mem_util_map_hw_va(uint32_t flags,
  482. int32_t *mmu_hdls,
  483. int32_t num_hdls,
  484. int fd,
  485. dma_addr_t *hw_vaddr,
  486. size_t *len,
  487. enum cam_smmu_region_id region,
  488. bool is_internal)
  489. {
  490. int i;
  491. int rc = -1;
  492. int dir = cam_mem_util_get_dma_dir(flags);
  493. bool dis_delayed_unmap = false;
  494. if (dir < 0) {
  495. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  496. return dir;
  497. }
  498. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  499. dis_delayed_unmap = true;
  500. CAM_DBG(CAM_MEM,
  501. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  502. fd, flags, dir, num_hdls);
  503. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  504. for (i = 0; i < num_hdls; i++) {
  505. rc = cam_smmu_map_stage2_iova(mmu_hdls[i],
  506. fd,
  507. dir,
  508. hw_vaddr,
  509. len);
  510. if (rc < 0) {
  511. CAM_ERR(CAM_MEM,
  512. "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  513. i, fd, dir, mmu_hdls[i], rc);
  514. goto multi_map_fail;
  515. }
  516. }
  517. } else {
  518. for (i = 0; i < num_hdls; i++) {
  519. rc = cam_smmu_map_user_iova(mmu_hdls[i],
  520. fd,
  521. dis_delayed_unmap,
  522. dir,
  523. (dma_addr_t *)hw_vaddr,
  524. len,
  525. region,
  526. is_internal);
  527. if (rc < 0) {
  528. CAM_ERR(CAM_MEM,
  529. "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d",
  530. i, fd, dir, mmu_hdls[i], region, rc);
  531. goto multi_map_fail;
  532. }
  533. }
  534. }
  535. return rc;
  536. multi_map_fail:
  537. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  538. for (--i; i > 0; i--)
  539. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  540. else
  541. for (--i; i > 0; i--)
  542. cam_smmu_unmap_user_iova(mmu_hdls[i],
  543. fd,
  544. CAM_SMMU_REGION_IO);
  545. return rc;
  546. }
  547. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  548. {
  549. int rc;
  550. int32_t idx;
  551. struct dma_buf *dmabuf = NULL;
  552. int fd = -1;
  553. dma_addr_t hw_vaddr = 0;
  554. size_t len;
  555. uintptr_t kvaddr = 0;
  556. size_t klen;
  557. if (!atomic_read(&cam_mem_mgr_state)) {
  558. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  559. return -EINVAL;
  560. }
  561. if (!cmd) {
  562. CAM_ERR(CAM_MEM, " Invalid argument");
  563. return -EINVAL;
  564. }
  565. len = cmd->len;
  566. rc = cam_mem_util_check_alloc_flags(cmd);
  567. if (rc) {
  568. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  569. cmd->flags, rc);
  570. return rc;
  571. }
  572. rc = cam_mem_util_ion_alloc(cmd,
  573. &dmabuf,
  574. &fd);
  575. if (rc) {
  576. CAM_ERR(CAM_MEM,
  577. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  578. cmd->len, cmd->align, cmd->flags, cmd->num_hdl);
  579. cam_mem_mgr_print_tbl();
  580. return rc;
  581. }
  582. idx = cam_mem_get_slot();
  583. if (idx < 0) {
  584. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  585. rc = -ENOMEM;
  586. goto slot_fail;
  587. }
  588. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  589. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  590. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  591. enum cam_smmu_region_id region;
  592. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  593. region = CAM_SMMU_REGION_IO;
  594. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  595. region = CAM_SMMU_REGION_SHARED;
  596. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  597. region = CAM_SMMU_REGION_SECHEAP;
  598. rc = cam_mem_util_map_hw_va(cmd->flags,
  599. cmd->mmu_hdls,
  600. cmd->num_hdl,
  601. fd,
  602. &hw_vaddr,
  603. &len,
  604. region,
  605. true);
  606. if (rc) {
  607. CAM_ERR(CAM_MEM,
  608. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  609. len, cmd->flags,
  610. fd, region, cmd->num_hdl, rc);
  611. if (rc == -EALREADY) {
  612. if ((size_t)dmabuf->size != len)
  613. rc = -EBADR;
  614. cam_mem_mgr_print_tbl();
  615. }
  616. goto map_hw_fail;
  617. }
  618. }
  619. mutex_lock(&tbl.bufq[idx].q_lock);
  620. tbl.bufq[idx].fd = fd;
  621. tbl.bufq[idx].dma_buf = NULL;
  622. tbl.bufq[idx].flags = cmd->flags;
  623. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  624. tbl.bufq[idx].is_internal = true;
  625. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  626. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  627. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  628. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  629. if (rc) {
  630. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  631. dmabuf, rc);
  632. goto map_kernel_fail;
  633. }
  634. }
  635. tbl.bufq[idx].kmdvaddr = kvaddr;
  636. tbl.bufq[idx].vaddr = hw_vaddr;
  637. tbl.bufq[idx].dma_buf = dmabuf;
  638. tbl.bufq[idx].len = cmd->len;
  639. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  640. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  641. sizeof(int32_t) * cmd->num_hdl);
  642. tbl.bufq[idx].is_imported = false;
  643. mutex_unlock(&tbl.bufq[idx].q_lock);
  644. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  645. cmd->out.fd = tbl.bufq[idx].fd;
  646. cmd->out.vaddr = 0;
  647. CAM_DBG(CAM_MEM,
  648. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  649. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  650. tbl.bufq[idx].len);
  651. return rc;
  652. map_kernel_fail:
  653. mutex_unlock(&tbl.bufq[idx].q_lock);
  654. map_hw_fail:
  655. cam_mem_put_slot(idx);
  656. slot_fail:
  657. dma_buf_put(dmabuf);
  658. return rc;
  659. }
  660. static bool cam_mem_util_is_map_internal(int32_t fd)
  661. {
  662. uint32_t i;
  663. bool is_internal = false;
  664. mutex_lock(&tbl.m_lock);
  665. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  666. if (tbl.bufq[i].fd == fd) {
  667. is_internal = tbl.bufq[i].is_internal;
  668. break;
  669. }
  670. }
  671. mutex_unlock(&tbl.m_lock);
  672. return is_internal;
  673. }
  674. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  675. {
  676. int32_t idx;
  677. int rc;
  678. struct dma_buf *dmabuf;
  679. dma_addr_t hw_vaddr = 0;
  680. size_t len = 0;
  681. bool is_internal = false;
  682. if (!atomic_read(&cam_mem_mgr_state)) {
  683. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  684. return -EINVAL;
  685. }
  686. if (!cmd || (cmd->fd < 0)) {
  687. CAM_ERR(CAM_MEM, "Invalid argument");
  688. return -EINVAL;
  689. }
  690. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  691. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  692. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  693. return -EINVAL;
  694. }
  695. rc = cam_mem_util_check_map_flags(cmd);
  696. if (rc) {
  697. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  698. return rc;
  699. }
  700. dmabuf = dma_buf_get(cmd->fd);
  701. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  702. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  703. return -EINVAL;
  704. }
  705. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  706. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  707. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  708. rc = cam_mem_util_map_hw_va(cmd->flags,
  709. cmd->mmu_hdls,
  710. cmd->num_hdl,
  711. cmd->fd,
  712. &hw_vaddr,
  713. &len,
  714. CAM_SMMU_REGION_IO,
  715. is_internal);
  716. if (rc) {
  717. CAM_ERR(CAM_MEM,
  718. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  719. cmd->flags, cmd->fd, len,
  720. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  721. if (rc == -EALREADY) {
  722. if ((size_t)dmabuf->size != len) {
  723. rc = -EBADR;
  724. cam_mem_mgr_print_tbl();
  725. }
  726. }
  727. goto map_fail;
  728. }
  729. }
  730. idx = cam_mem_get_slot();
  731. if (idx < 0) {
  732. rc = -ENOMEM;
  733. goto map_fail;
  734. }
  735. mutex_lock(&tbl.bufq[idx].q_lock);
  736. tbl.bufq[idx].fd = cmd->fd;
  737. tbl.bufq[idx].dma_buf = NULL;
  738. tbl.bufq[idx].flags = cmd->flags;
  739. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  740. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  741. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  742. tbl.bufq[idx].kmdvaddr = 0;
  743. if (cmd->num_hdl > 0)
  744. tbl.bufq[idx].vaddr = hw_vaddr;
  745. else
  746. tbl.bufq[idx].vaddr = 0;
  747. tbl.bufq[idx].dma_buf = dmabuf;
  748. tbl.bufq[idx].len = len;
  749. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  750. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  751. sizeof(int32_t) * cmd->num_hdl);
  752. tbl.bufq[idx].is_imported = true;
  753. tbl.bufq[idx].is_internal = is_internal;
  754. mutex_unlock(&tbl.bufq[idx].q_lock);
  755. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  756. cmd->out.vaddr = 0;
  757. cmd->out.size = (uint32_t)len;
  758. CAM_DBG(CAM_MEM,
  759. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  760. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  761. tbl.bufq[idx].len);
  762. return rc;
  763. map_fail:
  764. dma_buf_put(dmabuf);
  765. return rc;
  766. }
  767. static int cam_mem_util_unmap_hw_va(int32_t idx,
  768. enum cam_smmu_region_id region,
  769. enum cam_smmu_mapping_client client)
  770. {
  771. int i;
  772. uint32_t flags;
  773. int32_t *mmu_hdls;
  774. int num_hdls;
  775. int fd;
  776. int rc = 0;
  777. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  778. CAM_ERR(CAM_MEM, "Incorrect index");
  779. return -EINVAL;
  780. }
  781. flags = tbl.bufq[idx].flags;
  782. mmu_hdls = tbl.bufq[idx].hdls;
  783. num_hdls = tbl.bufq[idx].num_hdl;
  784. fd = tbl.bufq[idx].fd;
  785. CAM_DBG(CAM_MEM,
  786. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  787. idx, fd, flags, num_hdls, client);
  788. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  789. for (i = 0; i < num_hdls; i++) {
  790. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  791. if (rc < 0) {
  792. CAM_ERR(CAM_MEM,
  793. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  794. i, fd, mmu_hdls[i], rc);
  795. goto unmap_end;
  796. }
  797. }
  798. } else {
  799. for (i = 0; i < num_hdls; i++) {
  800. if (client == CAM_SMMU_MAPPING_USER) {
  801. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  802. fd, region);
  803. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  804. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  805. tbl.bufq[idx].dma_buf, region);
  806. } else {
  807. CAM_ERR(CAM_MEM,
  808. "invalid caller for unmapping : %d",
  809. client);
  810. rc = -EINVAL;
  811. }
  812. if (rc < 0) {
  813. CAM_ERR(CAM_MEM,
  814. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  815. i, fd, mmu_hdls[i], region, rc);
  816. goto unmap_end;
  817. }
  818. }
  819. }
  820. return rc;
  821. unmap_end:
  822. CAM_ERR(CAM_MEM, "unmapping failed");
  823. return rc;
  824. }
  825. static void cam_mem_mgr_unmap_active_buf(int idx)
  826. {
  827. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  828. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  829. region = CAM_SMMU_REGION_SHARED;
  830. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  831. region = CAM_SMMU_REGION_IO;
  832. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  833. }
  834. static int cam_mem_mgr_cleanup_table(void)
  835. {
  836. int i;
  837. mutex_lock(&tbl.m_lock);
  838. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  839. if (!tbl.bufq[i].active) {
  840. CAM_DBG(CAM_MEM,
  841. "Buffer inactive at idx=%d, continuing", i);
  842. continue;
  843. } else {
  844. CAM_DBG(CAM_MEM,
  845. "Active buffer at idx=%d, possible leak needs unmapping",
  846. i);
  847. cam_mem_mgr_unmap_active_buf(i);
  848. }
  849. mutex_lock(&tbl.bufq[i].q_lock);
  850. if (tbl.bufq[i].dma_buf) {
  851. dma_buf_put(tbl.bufq[i].dma_buf);
  852. tbl.bufq[i].dma_buf = NULL;
  853. }
  854. tbl.bufq[i].fd = -1;
  855. tbl.bufq[i].flags = 0;
  856. tbl.bufq[i].buf_handle = -1;
  857. tbl.bufq[i].vaddr = 0;
  858. tbl.bufq[i].len = 0;
  859. memset(tbl.bufq[i].hdls, 0,
  860. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  861. tbl.bufq[i].num_hdl = 0;
  862. tbl.bufq[i].dma_buf = NULL;
  863. tbl.bufq[i].active = false;
  864. tbl.bufq[i].is_internal = false;
  865. mutex_unlock(&tbl.bufq[i].q_lock);
  866. mutex_destroy(&tbl.bufq[i].q_lock);
  867. }
  868. bitmap_zero(tbl.bitmap, tbl.bits);
  869. /* We need to reserve slot 0 because 0 is invalid */
  870. set_bit(0, tbl.bitmap);
  871. mutex_unlock(&tbl.m_lock);
  872. return 0;
  873. }
  874. void cam_mem_mgr_deinit(void)
  875. {
  876. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  877. cam_mem_mgr_cleanup_table();
  878. debugfs_remove_recursive(tbl.dentry);
  879. mutex_lock(&tbl.m_lock);
  880. bitmap_zero(tbl.bitmap, tbl.bits);
  881. kfree(tbl.bitmap);
  882. tbl.bitmap = NULL;
  883. mutex_unlock(&tbl.m_lock);
  884. mutex_destroy(&tbl.m_lock);
  885. }
  886. static int cam_mem_util_unmap(int32_t idx,
  887. enum cam_smmu_mapping_client client)
  888. {
  889. int rc = 0;
  890. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  891. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  892. CAM_ERR(CAM_MEM, "Incorrect index");
  893. return -EINVAL;
  894. }
  895. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  896. mutex_lock(&tbl.m_lock);
  897. if ((!tbl.bufq[idx].active) &&
  898. (tbl.bufq[idx].vaddr) == 0) {
  899. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  900. idx);
  901. mutex_unlock(&tbl.m_lock);
  902. return 0;
  903. }
  904. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  905. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  906. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  907. tbl.bufq[idx].kmdvaddr);
  908. if (rc)
  909. CAM_ERR(CAM_MEM,
  910. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  911. tbl.bufq[idx].dma_buf,
  912. (void *) tbl.bufq[idx].kmdvaddr);
  913. }
  914. }
  915. /* SHARED flag gets precedence, all other flags after it */
  916. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  917. region = CAM_SMMU_REGION_SHARED;
  918. } else {
  919. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  920. region = CAM_SMMU_REGION_IO;
  921. }
  922. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  923. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  924. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  925. if (cam_mem_util_unmap_hw_va(idx, region, client))
  926. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  927. tbl.bufq[idx].dma_buf);
  928. if (client == CAM_SMMU_MAPPING_KERNEL)
  929. tbl.bufq[idx].dma_buf = NULL;
  930. }
  931. mutex_lock(&tbl.bufq[idx].q_lock);
  932. tbl.bufq[idx].flags = 0;
  933. tbl.bufq[idx].buf_handle = -1;
  934. tbl.bufq[idx].vaddr = 0;
  935. memset(tbl.bufq[idx].hdls, 0,
  936. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  937. CAM_DBG(CAM_MEM,
  938. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  939. idx, tbl.bufq[idx].fd,
  940. tbl.bufq[idx].is_imported,
  941. tbl.bufq[idx].dma_buf);
  942. if (tbl.bufq[idx].dma_buf)
  943. dma_buf_put(tbl.bufq[idx].dma_buf);
  944. tbl.bufq[idx].fd = -1;
  945. tbl.bufq[idx].dma_buf = NULL;
  946. tbl.bufq[idx].is_imported = false;
  947. tbl.bufq[idx].is_internal = false;
  948. tbl.bufq[idx].len = 0;
  949. tbl.bufq[idx].num_hdl = 0;
  950. tbl.bufq[idx].active = false;
  951. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  952. mutex_unlock(&tbl.bufq[idx].q_lock);
  953. mutex_destroy(&tbl.bufq[idx].q_lock);
  954. clear_bit(idx, tbl.bitmap);
  955. mutex_unlock(&tbl.m_lock);
  956. return rc;
  957. }
  958. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  959. {
  960. int idx;
  961. int rc;
  962. if (!atomic_read(&cam_mem_mgr_state)) {
  963. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  964. return -EINVAL;
  965. }
  966. if (!cmd) {
  967. CAM_ERR(CAM_MEM, "Invalid argument");
  968. return -EINVAL;
  969. }
  970. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  971. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  972. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  973. idx);
  974. return -EINVAL;
  975. }
  976. if (!tbl.bufq[idx].active) {
  977. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  978. return -EINVAL;
  979. }
  980. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  981. CAM_ERR(CAM_MEM,
  982. "Released buf handle %d not matching within table %d, idx=%d",
  983. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  984. return -EINVAL;
  985. }
  986. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  987. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  988. return rc;
  989. }
  990. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  991. struct cam_mem_mgr_memory_desc *out)
  992. {
  993. struct dma_buf *buf = NULL;
  994. int ion_fd = -1;
  995. int rc = 0;
  996. uint32_t heap_id;
  997. int32_t ion_flag = 0;
  998. uintptr_t kvaddr;
  999. dma_addr_t iova = 0;
  1000. size_t request_len = 0;
  1001. uint32_t mem_handle;
  1002. int32_t idx;
  1003. int32_t smmu_hdl = 0;
  1004. int32_t num_hdl = 0;
  1005. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1006. if (!atomic_read(&cam_mem_mgr_state)) {
  1007. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1008. return -EINVAL;
  1009. }
  1010. if (!inp || !out) {
  1011. CAM_ERR(CAM_MEM, "Invalid params");
  1012. return -EINVAL;
  1013. }
  1014. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1015. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1016. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1017. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1018. return -EINVAL;
  1019. }
  1020. if (inp->flags & CAM_MEM_FLAG_CACHE)
  1021. ion_flag |= ION_FLAG_CACHED;
  1022. else
  1023. ion_flag &= ~ION_FLAG_CACHED;
  1024. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  1025. ION_HEAP(ION_CAMERA_HEAP_ID);
  1026. rc = cam_mem_util_get_dma_buf(inp->size,
  1027. heap_id,
  1028. ion_flag,
  1029. &buf);
  1030. if (rc) {
  1031. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1032. goto ion_fail;
  1033. } else {
  1034. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1035. }
  1036. /*
  1037. * we are mapping kva always here,
  1038. * update flags so that we do unmap properly
  1039. */
  1040. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1041. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1042. if (rc) {
  1043. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1044. goto map_fail;
  1045. }
  1046. if (!inp->smmu_hdl) {
  1047. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1048. rc = -EINVAL;
  1049. goto smmu_fail;
  1050. }
  1051. /* SHARED flag gets precedence, all other flags after it */
  1052. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1053. region = CAM_SMMU_REGION_SHARED;
  1054. } else {
  1055. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1056. region = CAM_SMMU_REGION_IO;
  1057. }
  1058. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1059. buf,
  1060. CAM_SMMU_MAP_RW,
  1061. &iova,
  1062. &request_len,
  1063. region);
  1064. if (rc < 0) {
  1065. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1066. goto smmu_fail;
  1067. }
  1068. smmu_hdl = inp->smmu_hdl;
  1069. num_hdl = 1;
  1070. idx = cam_mem_get_slot();
  1071. if (idx < 0) {
  1072. rc = -ENOMEM;
  1073. goto slot_fail;
  1074. }
  1075. mutex_lock(&tbl.bufq[idx].q_lock);
  1076. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1077. tbl.bufq[idx].dma_buf = buf;
  1078. tbl.bufq[idx].fd = -1;
  1079. tbl.bufq[idx].flags = inp->flags;
  1080. tbl.bufq[idx].buf_handle = mem_handle;
  1081. tbl.bufq[idx].kmdvaddr = kvaddr;
  1082. tbl.bufq[idx].vaddr = iova;
  1083. tbl.bufq[idx].len = inp->size;
  1084. tbl.bufq[idx].num_hdl = num_hdl;
  1085. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1086. sizeof(int32_t));
  1087. tbl.bufq[idx].is_imported = false;
  1088. mutex_unlock(&tbl.bufq[idx].q_lock);
  1089. out->kva = kvaddr;
  1090. out->iova = (uint32_t)iova;
  1091. out->smmu_hdl = smmu_hdl;
  1092. out->mem_handle = mem_handle;
  1093. out->len = inp->size;
  1094. out->region = region;
  1095. return rc;
  1096. slot_fail:
  1097. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1098. buf, region);
  1099. smmu_fail:
  1100. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1101. map_fail:
  1102. dma_buf_put(buf);
  1103. ion_fail:
  1104. return rc;
  1105. }
  1106. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1107. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1108. {
  1109. int32_t idx;
  1110. int rc;
  1111. if (!atomic_read(&cam_mem_mgr_state)) {
  1112. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1113. return -EINVAL;
  1114. }
  1115. if (!inp) {
  1116. CAM_ERR(CAM_MEM, "Invalid argument");
  1117. return -EINVAL;
  1118. }
  1119. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1120. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1121. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1122. return -EINVAL;
  1123. }
  1124. if (!tbl.bufq[idx].active) {
  1125. if (tbl.bufq[idx].vaddr == 0) {
  1126. CAM_ERR(CAM_MEM, "buffer is released already");
  1127. return 0;
  1128. }
  1129. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1130. return -EINVAL;
  1131. }
  1132. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1133. CAM_ERR(CAM_MEM,
  1134. "Released buf handle not matching within table");
  1135. return -EINVAL;
  1136. }
  1137. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1138. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1139. return rc;
  1140. }
  1141. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1142. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1143. enum cam_smmu_region_id region,
  1144. struct cam_mem_mgr_memory_desc *out)
  1145. {
  1146. struct dma_buf *buf = NULL;
  1147. int rc = 0;
  1148. int ion_fd = -1;
  1149. uint32_t heap_id;
  1150. dma_addr_t iova = 0;
  1151. size_t request_len = 0;
  1152. uint32_t mem_handle;
  1153. int32_t idx;
  1154. int32_t smmu_hdl = 0;
  1155. int32_t num_hdl = 0;
  1156. if (!atomic_read(&cam_mem_mgr_state)) {
  1157. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1158. return -EINVAL;
  1159. }
  1160. if (!inp || !out) {
  1161. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1162. return -EINVAL;
  1163. }
  1164. if (!inp->smmu_hdl) {
  1165. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1166. return -EINVAL;
  1167. }
  1168. if (region != CAM_SMMU_REGION_SECHEAP) {
  1169. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1170. return -EINVAL;
  1171. }
  1172. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  1173. ION_HEAP(ION_CAMERA_HEAP_ID);
  1174. rc = cam_mem_util_get_dma_buf(inp->size,
  1175. heap_id,
  1176. 0,
  1177. &buf);
  1178. if (rc) {
  1179. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1180. goto ion_fail;
  1181. } else {
  1182. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1183. }
  1184. rc = cam_smmu_reserve_sec_heap(inp->smmu_hdl,
  1185. buf,
  1186. &iova,
  1187. &request_len);
  1188. if (rc) {
  1189. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1190. goto smmu_fail;
  1191. }
  1192. smmu_hdl = inp->smmu_hdl;
  1193. num_hdl = 1;
  1194. idx = cam_mem_get_slot();
  1195. if (idx < 0) {
  1196. rc = -ENOMEM;
  1197. goto slot_fail;
  1198. }
  1199. mutex_lock(&tbl.bufq[idx].q_lock);
  1200. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1201. tbl.bufq[idx].fd = -1;
  1202. tbl.bufq[idx].dma_buf = buf;
  1203. tbl.bufq[idx].flags = inp->flags;
  1204. tbl.bufq[idx].buf_handle = mem_handle;
  1205. tbl.bufq[idx].kmdvaddr = 0;
  1206. tbl.bufq[idx].vaddr = iova;
  1207. tbl.bufq[idx].len = request_len;
  1208. tbl.bufq[idx].num_hdl = num_hdl;
  1209. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1210. sizeof(int32_t));
  1211. tbl.bufq[idx].is_imported = false;
  1212. mutex_unlock(&tbl.bufq[idx].q_lock);
  1213. out->kva = 0;
  1214. out->iova = (uint32_t)iova;
  1215. out->smmu_hdl = smmu_hdl;
  1216. out->mem_handle = mem_handle;
  1217. out->len = request_len;
  1218. out->region = region;
  1219. return rc;
  1220. slot_fail:
  1221. cam_smmu_release_sec_heap(smmu_hdl);
  1222. smmu_fail:
  1223. dma_buf_put(buf);
  1224. ion_fail:
  1225. return rc;
  1226. }
  1227. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1228. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1229. {
  1230. int32_t idx;
  1231. int rc;
  1232. int32_t smmu_hdl;
  1233. if (!atomic_read(&cam_mem_mgr_state)) {
  1234. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1235. return -EINVAL;
  1236. }
  1237. if (!inp) {
  1238. CAM_ERR(CAM_MEM, "Invalid argument");
  1239. return -EINVAL;
  1240. }
  1241. if (inp->region != CAM_SMMU_REGION_SECHEAP) {
  1242. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1243. return -EINVAL;
  1244. }
  1245. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1246. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1247. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1248. return -EINVAL;
  1249. }
  1250. if (!tbl.bufq[idx].active) {
  1251. if (tbl.bufq[idx].vaddr == 0) {
  1252. CAM_ERR(CAM_MEM, "buffer is released already");
  1253. return 0;
  1254. }
  1255. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1256. return -EINVAL;
  1257. }
  1258. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1259. CAM_ERR(CAM_MEM,
  1260. "Released buf handle not matching within table");
  1261. return -EINVAL;
  1262. }
  1263. if (tbl.bufq[idx].num_hdl != 1) {
  1264. CAM_ERR(CAM_MEM,
  1265. "Sec heap region should have only one smmu hdl");
  1266. return -ENODEV;
  1267. }
  1268. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1269. sizeof(int32_t));
  1270. if (inp->smmu_hdl != smmu_hdl) {
  1271. CAM_ERR(CAM_MEM,
  1272. "Passed SMMU handle doesn't match with internal hdl");
  1273. return -ENODEV;
  1274. }
  1275. rc = cam_smmu_release_sec_heap(inp->smmu_hdl);
  1276. if (rc) {
  1277. CAM_ERR(CAM_MEM,
  1278. "Sec heap region release failed");
  1279. return -ENODEV;
  1280. }
  1281. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1282. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1283. if (rc)
  1284. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1285. return rc;
  1286. }
  1287. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);