dp_tx.c 73 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include <wlan_cfg.h>
  27. #ifdef MESH_MODE_SUPPORT
  28. #include "if_meta_hdr.h"
  29. #endif
  30. #ifdef TX_PER_PDEV_DESC_POOL
  31. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  32. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  33. #else /* QCA_LL_TX_FLOW_CONTROL_V2 */
  34. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->pdev->pdev_id)
  35. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  36. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  37. #else
  38. #ifdef TX_PER_VDEV_DESC_POOL
  39. #define DP_TX_GET_DESC_POOL_ID(vdev) (vdev->vdev_id)
  40. #define DP_TX_GET_RING_ID(vdev) (vdev->pdev->pdev_id)
  41. #else
  42. #define DP_TX_GET_DESC_POOL_ID(vdev) qdf_get_cpu()
  43. #define DP_TX_GET_RING_ID(vdev) vdev->pdev->soc->tx_ring_map[qdf_get_cpu()]
  44. #endif /* TX_PER_VDEV_DESC_POOL */
  45. #endif /* TX_PER_PDEV_DESC_POOL */
  46. /* TODO Add support in TSO */
  47. #define DP_DESC_NUM_FRAG(x) 0
  48. /* disable TQM_BYPASS */
  49. #define TQM_BYPASS_WAR 0
  50. /**
  51. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  52. * @vdev: DP Virtual device handle
  53. * @nbuf: Buffer pointer
  54. * @queue: queue ids container for nbuf
  55. *
  56. * TX packet queue has 2 instances, software descriptors id and dma ring id
  57. * Based on tx feature and hardware configuration queue id combination could be
  58. * different.
  59. * For example -
  60. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  61. * With no XPS,lock based resource protection, Descriptor pool ids are different
  62. * for each vdev, dma ring id will be same as single pdev id
  63. *
  64. * Return: None
  65. */
  66. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  67. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  68. {
  69. /* get flow id */
  70. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  71. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  72. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  73. "%s, pool_id:%d ring_id: %d\n",
  74. __func__, queue->desc_pool_id, queue->ring_id);
  75. return;
  76. }
  77. #if defined(FEATURE_TSO)
  78. /**
  79. * dp_tx_tso_desc_release() - Release the tso segment
  80. * after unmapping all the fragments
  81. *
  82. * @pdev - physical device handle
  83. * @tx_desc - Tx software descriptor
  84. */
  85. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  86. struct dp_tx_desc_s *tx_desc)
  87. {
  88. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  89. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  90. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  91. "%s %d TSO desc is NULL!",
  92. __func__, __LINE__);
  93. qdf_assert(0);
  94. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  95. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  96. "%s %d TSO common info is NULL!",
  97. __func__, __LINE__);
  98. qdf_assert(0);
  99. } else {
  100. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  101. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  102. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  103. tso_num_desc->num_seg.tso_cmn_num_seg--;
  104. qdf_nbuf_unmap_tso_segment(soc->osdev,
  105. tx_desc->tso_desc, false);
  106. } else {
  107. tso_num_desc->num_seg.tso_cmn_num_seg--;
  108. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  109. qdf_nbuf_unmap_tso_segment(soc->osdev,
  110. tx_desc->tso_desc, true);
  111. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  112. tx_desc->tso_num_desc);
  113. tx_desc->tso_num_desc = NULL;
  114. }
  115. dp_tx_tso_desc_free(soc,
  116. tx_desc->pool_id, tx_desc->tso_desc);
  117. tx_desc->tso_desc = NULL;
  118. }
  119. }
  120. #else
  121. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  122. struct dp_tx_desc_s *tx_desc)
  123. {
  124. return;
  125. }
  126. #endif
  127. /**
  128. * dp_tx_desc_release() - Release Tx Descriptor
  129. * @tx_desc : Tx Descriptor
  130. * @desc_pool_id: Descriptor Pool ID
  131. *
  132. * Deallocate all resources attached to Tx descriptor and free the Tx
  133. * descriptor.
  134. *
  135. * Return:
  136. */
  137. static void
  138. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  139. {
  140. struct dp_pdev *pdev = tx_desc->pdev;
  141. struct dp_soc *soc;
  142. uint8_t comp_status = 0;
  143. qdf_assert(pdev);
  144. soc = pdev->soc;
  145. if (tx_desc->frm_type == dp_tx_frm_tso)
  146. dp_tx_tso_desc_release(soc, tx_desc);
  147. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  148. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  149. qdf_atomic_dec(&pdev->num_tx_outstanding);
  150. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  151. qdf_atomic_dec(&pdev->num_tx_exception);
  152. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  153. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  154. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  155. else
  156. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  158. "Tx Completion Release desc %d status %d outstanding %d\n",
  159. tx_desc->id, comp_status,
  160. qdf_atomic_read(&pdev->num_tx_outstanding));
  161. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  162. return;
  163. }
  164. /**
  165. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  166. * @vdev: DP vdev Handle
  167. * @nbuf: skb
  168. *
  169. * Prepares and fills HTT metadata in the frame pre-header for special frames
  170. * that should be transmitted using varying transmit parameters.
  171. * There are 2 VDEV modes that currently needs this special metadata -
  172. * 1) Mesh Mode
  173. * 2) DSRC Mode
  174. *
  175. * Return: HTT metadata size
  176. *
  177. */
  178. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  179. uint32_t *meta_data)
  180. {
  181. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  182. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  183. uint8_t htt_desc_size;
  184. /* Size rounded of multiple of 8 bytes */
  185. uint8_t htt_desc_size_aligned;
  186. uint8_t *hdr = NULL;
  187. qdf_nbuf_unshare(nbuf);
  188. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  189. /*
  190. * Metadata - HTT MSDU Extension header
  191. */
  192. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  193. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  194. if (vdev->mesh_vdev) {
  195. /* Fill and add HTT metaheader */
  196. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  197. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  198. } else if (vdev->opmode == wlan_op_mode_ocb) {
  199. /* Todo - Add support for DSRC */
  200. }
  201. return htt_desc_size_aligned;
  202. }
  203. /**
  204. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  205. * @tso_seg: TSO segment to process
  206. * @ext_desc: Pointer to MSDU extension descriptor
  207. *
  208. * Return: void
  209. */
  210. #if defined(FEATURE_TSO)
  211. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  212. void *ext_desc)
  213. {
  214. uint8_t num_frag;
  215. uint32_t tso_flags;
  216. /*
  217. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  218. * tcp_flag_mask
  219. *
  220. * Checksum enable flags are set in TCL descriptor and not in Extension
  221. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  222. */
  223. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  224. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  225. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  226. tso_seg->tso_flags.ip_len);
  227. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  228. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  229. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  230. uint32_t lo = 0;
  231. uint32_t hi = 0;
  232. qdf_dmaaddr_to_32s(
  233. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  234. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  235. tso_seg->tso_frags[num_frag].length);
  236. }
  237. return;
  238. }
  239. #else
  240. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  241. void *ext_desc)
  242. {
  243. return;
  244. }
  245. #endif
  246. #if defined(FEATURE_TSO)
  247. /**
  248. * dp_tx_free_tso_seg() - Loop through the tso segments
  249. * allocated and free them
  250. *
  251. * @soc: soc handle
  252. * @free_seg: list of tso segments
  253. * @msdu_info: msdu descriptor
  254. *
  255. * Return - void
  256. */
  257. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  258. struct qdf_tso_seg_elem_t *free_seg,
  259. struct dp_tx_msdu_info_s *msdu_info)
  260. {
  261. struct qdf_tso_seg_elem_t *next_seg;
  262. while (free_seg) {
  263. next_seg = free_seg->next;
  264. dp_tx_tso_desc_free(soc,
  265. msdu_info->tx_queue.desc_pool_id,
  266. free_seg);
  267. free_seg = next_seg;
  268. }
  269. }
  270. /**
  271. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  272. * allocated and free them
  273. *
  274. * @soc: soc handle
  275. * @free_seg: list of tso segments
  276. * @msdu_info: msdu descriptor
  277. * Return - void
  278. */
  279. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  280. struct qdf_tso_num_seg_elem_t *free_seg,
  281. struct dp_tx_msdu_info_s *msdu_info)
  282. {
  283. struct qdf_tso_num_seg_elem_t *next_seg;
  284. while (free_seg) {
  285. next_seg = free_seg->next;
  286. dp_tso_num_seg_free(soc,
  287. msdu_info->tx_queue.desc_pool_id,
  288. free_seg);
  289. free_seg = next_seg;
  290. }
  291. }
  292. /**
  293. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  294. * @vdev: virtual device handle
  295. * @msdu: network buffer
  296. * @msdu_info: meta data associated with the msdu
  297. *
  298. * Return: QDF_STATUS_SUCCESS success
  299. */
  300. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  301. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  302. {
  303. struct qdf_tso_seg_elem_t *tso_seg;
  304. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  305. struct dp_soc *soc = vdev->pdev->soc;
  306. struct qdf_tso_info_t *tso_info;
  307. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  308. tso_info = &msdu_info->u.tso_info;
  309. tso_info->curr_seg = NULL;
  310. tso_info->tso_seg_list = NULL;
  311. tso_info->num_segs = num_seg;
  312. msdu_info->frm_type = dp_tx_frm_tso;
  313. tso_info->tso_num_seg_list = NULL;
  314. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  315. while (num_seg) {
  316. tso_seg = dp_tx_tso_desc_alloc(
  317. soc, msdu_info->tx_queue.desc_pool_id);
  318. if (tso_seg) {
  319. tso_seg->next = tso_info->tso_seg_list;
  320. tso_info->tso_seg_list = tso_seg;
  321. num_seg--;
  322. } else {
  323. struct qdf_tso_seg_elem_t *free_seg =
  324. tso_info->tso_seg_list;
  325. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  326. return QDF_STATUS_E_NOMEM;
  327. }
  328. }
  329. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  330. tso_num_seg = dp_tso_num_seg_alloc(soc,
  331. msdu_info->tx_queue.desc_pool_id);
  332. if (tso_num_seg) {
  333. tso_num_seg->next = tso_info->tso_num_seg_list;
  334. tso_info->tso_num_seg_list = tso_num_seg;
  335. } else {
  336. /* Bug: free tso_num_seg and tso_seg */
  337. /* Free the already allocated num of segments */
  338. struct qdf_tso_seg_elem_t *free_seg =
  339. tso_info->tso_seg_list;
  340. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  341. __func__);
  342. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  343. return QDF_STATUS_E_NOMEM;
  344. }
  345. msdu_info->num_seg =
  346. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  347. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  348. msdu_info->num_seg);
  349. if (!(msdu_info->num_seg)) {
  350. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  351. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  352. msdu_info);
  353. return QDF_STATUS_E_INVAL;
  354. }
  355. tso_info->curr_seg = tso_info->tso_seg_list;
  356. return QDF_STATUS_SUCCESS;
  357. }
  358. #else
  359. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  360. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  361. {
  362. return QDF_STATUS_E_NOMEM;
  363. }
  364. #endif
  365. /**
  366. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  367. * @vdev: DP Vdev handle
  368. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  369. * @desc_pool_id: Descriptor Pool ID
  370. *
  371. * Return:
  372. */
  373. static
  374. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  375. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  376. {
  377. uint8_t i;
  378. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  379. struct dp_tx_seg_info_s *seg_info;
  380. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  381. struct dp_soc *soc = vdev->pdev->soc;
  382. /* Allocate an extension descriptor */
  383. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  384. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  385. if (!msdu_ext_desc) {
  386. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  387. return NULL;
  388. }
  389. if (qdf_unlikely(vdev->mesh_vdev)) {
  390. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  391. &msdu_info->meta_data[0],
  392. sizeof(struct htt_tx_msdu_desc_ext2_t));
  393. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  394. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 1);
  395. }
  396. switch (msdu_info->frm_type) {
  397. case dp_tx_frm_sg:
  398. case dp_tx_frm_me:
  399. case dp_tx_frm_raw:
  400. seg_info = msdu_info->u.sg_info.curr_seg;
  401. /* Update the buffer pointers in MSDU Extension Descriptor */
  402. for (i = 0; i < seg_info->frag_cnt; i++) {
  403. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  404. seg_info->frags[i].paddr_lo,
  405. seg_info->frags[i].paddr_hi,
  406. seg_info->frags[i].len);
  407. }
  408. break;
  409. case dp_tx_frm_tso:
  410. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  411. &cached_ext_desc[0]);
  412. break;
  413. default:
  414. break;
  415. }
  416. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  417. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  418. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  419. msdu_ext_desc->vaddr);
  420. return msdu_ext_desc;
  421. }
  422. /**
  423. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  424. * @vdev: DP vdev handle
  425. * @nbuf: skb
  426. * @desc_pool_id: Descriptor pool ID
  427. * Allocate and prepare Tx descriptor with msdu information.
  428. *
  429. * Return: Pointer to Tx Descriptor on success,
  430. * NULL on failure
  431. */
  432. static
  433. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  434. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  435. uint32_t *meta_data)
  436. {
  437. uint8_t align_pad;
  438. uint8_t is_exception = 0;
  439. uint8_t htt_hdr_size;
  440. struct ether_header *eh;
  441. struct dp_tx_desc_s *tx_desc;
  442. struct dp_pdev *pdev = vdev->pdev;
  443. struct dp_soc *soc = pdev->soc;
  444. /* Allocate software Tx descriptor */
  445. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  446. if (qdf_unlikely(!tx_desc)) {
  447. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  448. "%s Tx Desc Alloc Failed\n", __func__);
  449. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  450. return NULL;
  451. }
  452. /* Flow control/Congestion Control counters */
  453. qdf_atomic_inc(&pdev->num_tx_outstanding);
  454. /* Initialize the SW tx descriptor */
  455. tx_desc->nbuf = nbuf;
  456. tx_desc->frm_type = dp_tx_frm_std;
  457. tx_desc->tx_encap_type = vdev->tx_encap_type;
  458. tx_desc->vdev = vdev;
  459. tx_desc->pdev = pdev;
  460. tx_desc->msdu_ext_desc = NULL;
  461. /**
  462. * For non-scatter regular frames, buffer pointer is directly
  463. * programmed in TCL input descriptor instead of using an MSDU
  464. * extension descriptor.For this cass, HW requirement is that
  465. * descriptor should always point to a 8-byte aligned address.
  466. *
  467. * So we add alignment pad to start of buffer, and specify the actual
  468. * start of data through pkt_offset
  469. */
  470. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  471. qdf_nbuf_push_head(nbuf, align_pad);
  472. tx_desc->pkt_offset = align_pad;
  473. /*
  474. * For special modes (vdev_type == ocb or mesh), data frames should be
  475. * transmitted using varying transmit parameters (tx spec) which include
  476. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  477. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  478. * These frames are sent as exception packets to firmware.
  479. *
  480. * HTT Metadata should be ensured to be multiple of 8-bytes,
  481. * to get 8-byte aligned start address along with align_pad added above
  482. *
  483. * |-----------------------------|
  484. * | |
  485. * |-----------------------------| <-----Buffer Pointer Address given
  486. * | | ^ in HW descriptor (aligned)
  487. * | HTT Metadata | |
  488. * | | |
  489. * | | | Packet Offset given in descriptor
  490. * | | |
  491. * |-----------------------------| |
  492. * | Alignment Pad | v
  493. * |-----------------------------| <----- Actual buffer start address
  494. * | SKB Data | (Unaligned)
  495. * | |
  496. * | |
  497. * | |
  498. * | |
  499. * | |
  500. * |-----------------------------|
  501. */
  502. if (qdf_unlikely(vdev->mesh_vdev ||
  503. (vdev->opmode == wlan_op_mode_ocb))) {
  504. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  505. meta_data);
  506. tx_desc->pkt_offset += htt_hdr_size;
  507. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  508. is_exception = 1;
  509. }
  510. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  511. qdf_nbuf_map(soc->osdev, nbuf,
  512. QDF_DMA_TO_DEVICE))) {
  513. /* Handle failure */
  514. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  515. "qdf_nbuf_map failed\n");
  516. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  517. goto failure;
  518. }
  519. if (qdf_unlikely(vdev->nawds_enabled)) {
  520. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  521. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  522. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  523. is_exception = 1;
  524. }
  525. }
  526. #if !TQM_BYPASS_WAR
  527. if (is_exception)
  528. #endif
  529. {
  530. /* Temporary WAR due to TQM VP issues */
  531. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  532. qdf_atomic_inc(&pdev->num_tx_exception);
  533. }
  534. return tx_desc;
  535. failure:
  536. dp_tx_desc_release(tx_desc, desc_pool_id);
  537. return NULL;
  538. }
  539. /**
  540. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  541. * @vdev: DP vdev handle
  542. * @nbuf: skb
  543. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  544. * @desc_pool_id : Descriptor Pool ID
  545. *
  546. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  547. * information. For frames wth fragments, allocate and prepare
  548. * an MSDU extension descriptor
  549. *
  550. * Return: Pointer to Tx Descriptor on success,
  551. * NULL on failure
  552. */
  553. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  554. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  555. uint8_t desc_pool_id)
  556. {
  557. struct dp_tx_desc_s *tx_desc;
  558. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  559. struct dp_pdev *pdev = vdev->pdev;
  560. struct dp_soc *soc = pdev->soc;
  561. /* Allocate software Tx descriptor */
  562. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  563. if (!tx_desc) {
  564. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  565. return NULL;
  566. }
  567. /* Flow control/Congestion Control counters */
  568. qdf_atomic_inc(&pdev->num_tx_outstanding);
  569. /* Initialize the SW tx descriptor */
  570. tx_desc->nbuf = nbuf;
  571. tx_desc->frm_type = msdu_info->frm_type;
  572. tx_desc->tx_encap_type = vdev->tx_encap_type;
  573. tx_desc->vdev = vdev;
  574. tx_desc->pdev = pdev;
  575. tx_desc->pkt_offset = 0;
  576. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  577. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  578. /* Handle scattered frames - TSO/SG/ME */
  579. /* Allocate and prepare an extension descriptor for scattered frames */
  580. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  581. if (!msdu_ext_desc) {
  582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  583. "%s Tx Extension Descriptor Alloc Fail\n",
  584. __func__);
  585. goto failure;
  586. }
  587. #if TQM_BYPASS_WAR
  588. /* Temporary WAR due to TQM VP issues */
  589. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  590. qdf_atomic_inc(&pdev->num_tx_exception);
  591. #endif
  592. if (qdf_unlikely(vdev->mesh_vdev))
  593. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  594. tx_desc->msdu_ext_desc = msdu_ext_desc;
  595. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  596. return tx_desc;
  597. failure:
  598. dp_tx_desc_release(tx_desc, desc_pool_id);
  599. return NULL;
  600. }
  601. /**
  602. * dp_tx_prepare_raw() - Prepare RAW packet TX
  603. * @vdev: DP vdev handle
  604. * @nbuf: buffer pointer
  605. * @seg_info: Pointer to Segment info Descriptor to be prepared
  606. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  607. * descriptor
  608. *
  609. * Return:
  610. */
  611. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  612. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  613. {
  614. qdf_nbuf_t curr_nbuf = NULL;
  615. uint16_t total_len = 0;
  616. int32_t i;
  617. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  618. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  619. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  620. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  621. if ((qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  622. && (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU)) {
  623. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  624. }
  625. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  626. QDF_DMA_TO_DEVICE)) {
  627. qdf_print("dma map error\n");
  628. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  629. qdf_nbuf_free(nbuf);
  630. return NULL;
  631. }
  632. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  633. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  634. seg_info->frags[i].paddr_lo =
  635. qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  636. seg_info->frags[i].paddr_hi = 0x0;
  637. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  638. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  639. total_len += qdf_nbuf_len(curr_nbuf);
  640. }
  641. seg_info->frag_cnt = i;
  642. seg_info->total_len = total_len;
  643. seg_info->next = NULL;
  644. sg_info->curr_seg = seg_info;
  645. msdu_info->frm_type = dp_tx_frm_raw;
  646. msdu_info->num_seg = 1;
  647. return nbuf;
  648. }
  649. /**
  650. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  651. * @soc: DP Soc Handle
  652. * @vdev: DP vdev handle
  653. * @tx_desc: Tx Descriptor Handle
  654. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  655. * @fw_metadata: Metadata to send to Target Firmware along with frame
  656. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  657. *
  658. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  659. * from software Tx descriptor
  660. *
  661. * Return:
  662. */
  663. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  664. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  665. uint16_t fw_metadata, uint8_t ring_id)
  666. {
  667. uint8_t type;
  668. uint16_t length;
  669. void *hal_tx_desc, *hal_tx_desc_cached;
  670. qdf_dma_addr_t dma_addr;
  671. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  672. /* Return Buffer Manager ID */
  673. uint8_t bm_id = ring_id;
  674. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  675. hal_tx_desc_cached = (void *) cached_desc;
  676. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  677. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  678. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  679. type = HAL_TX_BUF_TYPE_EXT_DESC;
  680. dma_addr = tx_desc->msdu_ext_desc->paddr;
  681. } else {
  682. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  683. type = HAL_TX_BUF_TYPE_BUFFER;
  684. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  685. }
  686. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  687. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  688. dma_addr , bm_id, tx_desc->id, type);
  689. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  690. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  691. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  692. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  693. vdev->dscp_tid_map_id);
  694. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  695. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u\n",
  696. __func__, length, type, (uint64_t)dma_addr,
  697. tx_desc->pkt_offset, tx_desc->id);
  698. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  699. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  700. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  701. vdev->hal_desc_addr_search_flags);
  702. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  703. || qdf_nbuf_is_tso(tx_desc->nbuf)) {
  704. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  705. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  706. }
  707. if (tid != HTT_TX_EXT_TID_INVALID)
  708. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  709. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  710. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  711. /* Sync cached descriptor with HW */
  712. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  713. if (!hal_tx_desc) {
  714. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  715. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  716. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  717. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  718. return QDF_STATUS_E_RESOURCES;
  719. }
  720. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  721. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  722. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  723. return QDF_STATUS_SUCCESS;
  724. }
  725. /**
  726. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  727. * @vdev: DP vdev handle
  728. * @nbuf: skb
  729. *
  730. * Extract the DSCP or PCP information from frame and map into TID value.
  731. * Software based TID classification is required when more than 2 DSCP-TID
  732. * mapping tables are needed.
  733. * Hardware supports 2 DSCP-TID mapping tables
  734. *
  735. * Return: void
  736. */
  737. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  738. struct dp_tx_msdu_info_s *msdu_info)
  739. {
  740. uint8_t tos = 0, dscp_tid_override = 0;
  741. uint8_t *hdr_ptr, *L3datap;
  742. uint8_t is_mcast = 0;
  743. struct ether_header *eh = NULL;
  744. qdf_ethervlan_header_t *evh = NULL;
  745. uint16_t ether_type;
  746. qdf_llc_t *llcHdr;
  747. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  748. /* for mesh packets don't do any classification */
  749. if (qdf_unlikely(vdev->mesh_vdev))
  750. return;
  751. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  752. eh = (struct ether_header *) nbuf->data;
  753. hdr_ptr = eh->ether_dhost;
  754. L3datap = hdr_ptr + sizeof(struct ether_header);
  755. } else {
  756. qdf_dot3_qosframe_t *qos_wh =
  757. (qdf_dot3_qosframe_t *) nbuf->data;
  758. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  759. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  760. return;
  761. }
  762. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  763. ether_type = eh->ether_type;
  764. /*
  765. * Check if packet is dot3 or eth2 type.
  766. */
  767. if (IS_LLC_PRESENT(ether_type)) {
  768. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  769. sizeof(*llcHdr));
  770. if (ether_type == htons(ETHERTYPE_8021Q)) {
  771. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  772. sizeof(*llcHdr);
  773. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  774. + sizeof(*llcHdr) +
  775. sizeof(qdf_net_vlanhdr_t));
  776. } else {
  777. L3datap = hdr_ptr + sizeof(struct ether_header) +
  778. sizeof(*llcHdr);
  779. }
  780. } else {
  781. if (ether_type == htons(ETHERTYPE_8021Q)) {
  782. evh = (qdf_ethervlan_header_t *) eh;
  783. ether_type = evh->ether_type;
  784. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  785. }
  786. }
  787. /*
  788. * Find priority from IP TOS DSCP field
  789. */
  790. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  791. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  792. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  793. /* Only for unicast frames */
  794. if (!is_mcast) {
  795. /* send it on VO queue */
  796. msdu_info->tid = DP_VO_TID;
  797. }
  798. } else {
  799. /*
  800. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  801. * from TOS byte.
  802. */
  803. tos = ip->ip_tos;
  804. dscp_tid_override = 1;
  805. }
  806. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  807. /* TODO
  808. * use flowlabel
  809. *igmpmld cases to be handled in phase 2
  810. */
  811. unsigned long ver_pri_flowlabel;
  812. unsigned long pri;
  813. ver_pri_flowlabel = *(unsigned long *) L3datap;
  814. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  815. DP_IPV6_PRIORITY_SHIFT;
  816. tos = pri;
  817. dscp_tid_override = 1;
  818. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  819. msdu_info->tid = DP_VO_TID;
  820. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  821. /* Only for unicast frames */
  822. if (!is_mcast) {
  823. /* send ucast arp on VO queue */
  824. msdu_info->tid = DP_VO_TID;
  825. }
  826. }
  827. /*
  828. * Assign all MCAST packets to BE
  829. */
  830. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  831. if (is_mcast) {
  832. tos = 0;
  833. dscp_tid_override = 1;
  834. }
  835. }
  836. if (dscp_tid_override == 1) {
  837. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  838. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  839. }
  840. return;
  841. }
  842. /**
  843. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  844. * @vdev: DP vdev handle
  845. * @nbuf: skb
  846. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  847. * @tx_q: Tx queue to be used for this Tx frame
  848. * @peer_id: peer_id of the peer in case of NAWDS frames
  849. *
  850. * Return: NULL on success,
  851. * nbuf when it fails to send
  852. */
  853. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  854. uint8_t tid, struct dp_tx_queue *tx_q,
  855. uint32_t *meta_data, uint16_t peer_id)
  856. {
  857. struct dp_pdev *pdev = vdev->pdev;
  858. struct dp_soc *soc = pdev->soc;
  859. struct dp_tx_desc_s *tx_desc;
  860. QDF_STATUS status;
  861. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  862. uint16_t htt_tcl_metadata = 0;
  863. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 0);
  864. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  865. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id, meta_data);
  866. if (!tx_desc) {
  867. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  868. "%s Tx_desc prepare Fail vdev %p queue %d\n",
  869. __func__, vdev, tx_q->desc_pool_id);
  870. return nbuf;
  871. }
  872. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  873. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  874. "%s %d : HAL RING Access Failed -- %p\n",
  875. __func__, __LINE__, hal_srng);
  876. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  877. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  878. goto fail_return;
  879. }
  880. if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  881. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  882. HTT_TCL_METADATA_TYPE_PEER_BASED);
  883. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  884. peer_id);
  885. } else
  886. htt_tcl_metadata = vdev->htt_tcl_metadata;
  887. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  888. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  889. htt_tcl_metadata, tx_q->ring_id);
  890. if (status != QDF_STATUS_SUCCESS) {
  891. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  892. "%s Tx_hw_enqueue Fail tx_desc %p queue %d\n",
  893. __func__, tx_desc, tx_q->ring_id);
  894. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  895. goto fail_return;
  896. }
  897. nbuf = NULL;
  898. fail_return:
  899. hal_srng_access_end(soc->hal_soc, hal_srng);
  900. return nbuf;
  901. }
  902. /**
  903. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  904. * @vdev: DP vdev handle
  905. * @nbuf: skb
  906. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  907. *
  908. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  909. *
  910. * Return: NULL on success,
  911. * nbuf when it fails to send
  912. */
  913. #if QDF_LOCK_STATS
  914. static noinline
  915. #else
  916. static
  917. #endif
  918. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  919. struct dp_tx_msdu_info_s *msdu_info)
  920. {
  921. uint8_t i;
  922. struct dp_pdev *pdev = vdev->pdev;
  923. struct dp_soc *soc = pdev->soc;
  924. struct dp_tx_desc_s *tx_desc;
  925. QDF_STATUS status;
  926. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  927. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  928. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  929. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  930. "%s %d : HAL RING Access Failed -- %p\n",
  931. __func__, __LINE__, hal_srng);
  932. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  933. return nbuf;
  934. }
  935. if (msdu_info->frm_type == dp_tx_frm_me)
  936. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  937. i = 0;
  938. /* Print statement to track i and num_seg */
  939. /*
  940. * For each segment (maps to 1 MSDU) , prepare software and hardware
  941. * descriptors using information in msdu_info
  942. */
  943. while (i < msdu_info->num_seg) {
  944. /*
  945. * Setup Tx descriptor for an MSDU, and MSDU extension
  946. * descriptor
  947. */
  948. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  949. tx_q->desc_pool_id);
  950. if (!tx_desc) {
  951. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  952. "%s Tx_desc prepare Fail vdev %p queue %d\n",
  953. __func__, vdev, tx_q->desc_pool_id);
  954. if (msdu_info->frm_type == dp_tx_frm_me) {
  955. dp_tx_me_free_buf(pdev,
  956. (void *)(msdu_info->u.sg_info
  957. .curr_seg->frags[0].vaddr));
  958. }
  959. goto done;
  960. }
  961. if (msdu_info->frm_type == dp_tx_frm_me) {
  962. tx_desc->me_buffer =
  963. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  964. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  965. }
  966. /*
  967. * Enqueue the Tx MSDU descriptor to HW for transmit
  968. */
  969. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  970. vdev->htt_tcl_metadata, tx_q->ring_id);
  971. if (status != QDF_STATUS_SUCCESS) {
  972. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  973. "%s Tx_hw_enqueue Fail tx_desc %p queue %d\n",
  974. __func__, tx_desc, tx_q->ring_id);
  975. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  976. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  977. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  978. goto done;
  979. }
  980. /*
  981. * TODO
  982. * if tso_info structure can be modified to have curr_seg
  983. * as first element, following 2 blocks of code (for TSO and SG)
  984. * can be combined into 1
  985. */
  986. /*
  987. * For frames with multiple segments (TSO, ME), jump to next
  988. * segment.
  989. */
  990. if (msdu_info->frm_type == dp_tx_frm_tso) {
  991. if (msdu_info->u.tso_info.curr_seg->next) {
  992. msdu_info->u.tso_info.curr_seg =
  993. msdu_info->u.tso_info.curr_seg->next;
  994. /*
  995. * If this is a jumbo nbuf, then increment the number of
  996. * nbuf users for each additional segment of the msdu.
  997. * This will ensure that the skb is freed only after
  998. * receiving tx completion for all segments of an nbuf
  999. */
  1000. qdf_nbuf_inc_users(nbuf);
  1001. /* Check with MCL if this is needed */
  1002. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1003. }
  1004. }
  1005. /*
  1006. * For Multicast-Unicast converted packets,
  1007. * each converted frame (for a client) is represented as
  1008. * 1 segment
  1009. */
  1010. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1011. (msdu_info->frm_type == dp_tx_frm_me)) {
  1012. if (msdu_info->u.sg_info.curr_seg->next) {
  1013. msdu_info->u.sg_info.curr_seg =
  1014. msdu_info->u.sg_info.curr_seg->next;
  1015. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1016. }
  1017. }
  1018. i++;
  1019. }
  1020. nbuf = NULL;
  1021. done:
  1022. hal_srng_access_end(soc->hal_soc, hal_srng);
  1023. return nbuf;
  1024. }
  1025. /**
  1026. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1027. * for SG frames
  1028. * @vdev: DP vdev handle
  1029. * @nbuf: skb
  1030. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1031. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1032. *
  1033. * Return: NULL on success,
  1034. * nbuf when it fails to send
  1035. */
  1036. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1037. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1038. {
  1039. uint32_t cur_frag, nr_frags;
  1040. qdf_dma_addr_t paddr;
  1041. struct dp_tx_sg_info_s *sg_info;
  1042. sg_info = &msdu_info->u.sg_info;
  1043. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1044. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1045. QDF_DMA_TO_DEVICE)) {
  1046. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1047. "dma map error\n");
  1048. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1049. qdf_nbuf_free(nbuf);
  1050. return NULL;
  1051. }
  1052. seg_info->frags[0].paddr_lo = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1053. seg_info->frags[0].paddr_hi = 0;
  1054. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1055. seg_info->frags[0].vaddr = (void *) nbuf;
  1056. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1057. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1058. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1059. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1060. "frag dma map error\n");
  1061. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1062. qdf_nbuf_free(nbuf);
  1063. return NULL;
  1064. }
  1065. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1066. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1067. seg_info->frags[cur_frag + 1].paddr_hi =
  1068. ((uint64_t) paddr) >> 32;
  1069. seg_info->frags[cur_frag + 1].len =
  1070. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1071. }
  1072. seg_info->frag_cnt = (cur_frag + 1);
  1073. seg_info->total_len = qdf_nbuf_len(nbuf);
  1074. seg_info->next = NULL;
  1075. sg_info->curr_seg = seg_info;
  1076. msdu_info->frm_type = dp_tx_frm_sg;
  1077. msdu_info->num_seg = 1;
  1078. return nbuf;
  1079. }
  1080. #ifdef MESH_MODE_SUPPORT
  1081. /**
  1082. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1083. and prepare msdu_info for mesh frames.
  1084. * @vdev: DP vdev handle
  1085. * @nbuf: skb
  1086. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1087. *
  1088. * Return: void
  1089. */
  1090. static
  1091. void dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1092. struct dp_tx_msdu_info_s *msdu_info)
  1093. {
  1094. struct meta_hdr_s *mhdr;
  1095. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1096. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1097. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1098. qdf_mem_set(meta_data, 0, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1099. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1100. meta_data->power = mhdr->power;
  1101. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1102. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1103. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1104. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1105. meta_data->dyn_bw = 1;
  1106. meta_data->valid_pwr = 1;
  1107. meta_data->valid_mcs_mask = 1;
  1108. meta_data->valid_nss_mask = 1;
  1109. meta_data->valid_preamble_type = 1;
  1110. meta_data->valid_retries = 1;
  1111. meta_data->valid_bw_info = 1;
  1112. }
  1113. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1114. meta_data->encrypt_type = 0;
  1115. meta_data->valid_encrypt_type = 1;
  1116. }
  1117. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1118. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1119. else
  1120. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1121. meta_data->valid_key_flags = 1;
  1122. meta_data->key_flags = (mhdr->keyix & 0x3);
  1123. qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s));
  1124. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1125. "%s , Meta hdr %0x %0x %0x %0x %0x\n",
  1126. __func__, msdu_info->meta_data[0],
  1127. msdu_info->meta_data[1],
  1128. msdu_info->meta_data[2],
  1129. msdu_info->meta_data[3],
  1130. msdu_info->meta_data[4]);
  1131. return;
  1132. }
  1133. #else
  1134. static
  1135. void dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1136. struct dp_tx_msdu_info_s *msdu_info)
  1137. {
  1138. }
  1139. #endif
  1140. /**
  1141. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1142. * @vdev: dp_vdev handle
  1143. * @nbuf: skb
  1144. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1145. * @tx_q: Tx queue to be used for this Tx frame
  1146. * @meta_data: Meta date for mesh
  1147. * @peer_id: peer_id of the peer in case of NAWDS frames
  1148. *
  1149. * return: NULL on success nbuf on failure
  1150. */
  1151. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1152. uint8_t tid, struct dp_tx_queue *tx_q, uint32_t *meta_data,
  1153. uint32_t peer_id)
  1154. {
  1155. struct dp_peer *peer = NULL;
  1156. qdf_nbuf_t nbuf_copy;
  1157. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1158. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1159. (peer->nawds_enabled || peer->bss_peer)) {
  1160. nbuf_copy = qdf_nbuf_copy(nbuf);
  1161. if (!nbuf_copy) {
  1162. QDF_TRACE(QDF_MODULE_ID_DP,
  1163. QDF_TRACE_LEVEL_ERROR,
  1164. "nbuf copy failed");
  1165. }
  1166. peer_id = peer->peer_ids[0];
  1167. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy, tid,
  1168. tx_q, meta_data, peer_id);
  1169. if (nbuf_copy != NULL) {
  1170. qdf_nbuf_free(nbuf);
  1171. return nbuf_copy;
  1172. }
  1173. }
  1174. }
  1175. if (peer_id == HTT_INVALID_PEER)
  1176. return nbuf;
  1177. qdf_nbuf_free(nbuf);
  1178. return NULL;
  1179. }
  1180. /**
  1181. * dp_tx_send() - Transmit a frame on a given VAP
  1182. * @vap_dev: DP vdev handle
  1183. * @nbuf: skb
  1184. *
  1185. * Entry point for Core Tx layer (DP_TX) invoked from
  1186. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1187. * cases
  1188. *
  1189. * Return: NULL on success,
  1190. * nbuf when it fails to send
  1191. */
  1192. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1193. {
  1194. struct ether_header *eh = NULL;
  1195. struct dp_tx_msdu_info_s msdu_info;
  1196. struct dp_tx_seg_info_s seg_info;
  1197. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1198. uint16_t peer_id = HTT_INVALID_PEER;
  1199. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1200. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1201. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1203. "%s , skb %0x:%0x:%0x:%0x:%0x:%0x\n",
  1204. __func__, nbuf->data[0], nbuf->data[1], nbuf->data[2],
  1205. nbuf->data[3], nbuf->data[4], nbuf->data[5]);
  1206. /*
  1207. * Set Default Host TID value to invalid TID
  1208. * (TID override disabled)
  1209. */
  1210. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1211. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1212. if (qdf_unlikely(vdev->mesh_vdev))
  1213. dp_tx_extract_mesh_meta_data(vdev, nbuf, &msdu_info);
  1214. /*
  1215. * Get HW Queue to use for this frame.
  1216. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1217. * dedicated for data and 1 for command.
  1218. * "queue_id" maps to one hardware ring.
  1219. * With each ring, we also associate a unique Tx descriptor pool
  1220. * to minimize lock contention for these resources.
  1221. */
  1222. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1223. /*
  1224. * TCL H/W supports 2 DSCP-TID mapping tables.
  1225. * Table 1 - Default DSCP-TID mapping table
  1226. * Table 2 - 1 DSCP-TID override table
  1227. *
  1228. * If we need a different DSCP-TID mapping for this vap,
  1229. * call tid_classify to extract DSCP/ToS from frame and
  1230. * map to a TID and store in msdu_info. This is later used
  1231. * to fill in TCL Input descriptor (per-packet TID override).
  1232. */
  1233. if (vdev->dscp_tid_map_id > 1)
  1234. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1235. /* Reset the control block */
  1236. qdf_nbuf_reset_ctxt(nbuf);
  1237. /*
  1238. * Classify the frame and call corresponding
  1239. * "prepare" function which extracts the segment (TSO)
  1240. * and fragmentation information (for TSO , SG, ME, or Raw)
  1241. * into MSDU_INFO structure which is later used to fill
  1242. * SW and HW descriptors.
  1243. */
  1244. if (qdf_nbuf_is_tso(nbuf)) {
  1245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1246. "%s TSO frame %p\n", __func__, vdev);
  1247. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1248. qdf_nbuf_len(nbuf));
  1249. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1250. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1251. "%s tso_prepare fail vdev_id:%d\n",
  1252. __func__, vdev->vdev_id);
  1253. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1254. return nbuf;
  1255. }
  1256. goto send_multiple;
  1257. }
  1258. /* SG */
  1259. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1260. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1261. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1262. "%s non-TSO SG frame %p\n", __func__, vdev);
  1263. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1264. qdf_nbuf_len(nbuf));
  1265. goto send_multiple;
  1266. }
  1267. #ifdef ATH_SUPPORT_IQUE
  1268. /* Mcast to Ucast Conversion*/
  1269. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1270. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1271. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1272. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1273. "%s Mcast frm for ME %p\n", __func__, vdev);
  1274. DP_STATS_INC_PKT(vdev,
  1275. tx_i.mcast_en.mcast_pkt, 1,
  1276. qdf_nbuf_len(nbuf));
  1277. if (dp_tx_prepare_send_me(vdev, nbuf)) {
  1278. qdf_nbuf_free(nbuf);
  1279. return NULL;
  1280. }
  1281. return nbuf;
  1282. }
  1283. }
  1284. #endif
  1285. /* RAW */
  1286. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1287. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1288. if (nbuf == NULL)
  1289. return NULL;
  1290. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1291. "%s Raw frame %p\n", __func__, vdev);
  1292. goto send_multiple;
  1293. }
  1294. if (vdev->nawds_enabled) {
  1295. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1296. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1297. nbuf = dp_tx_prepare_nawds(vdev, nbuf, msdu_info.tid,
  1298. &msdu_info.tx_queue,
  1299. msdu_info.meta_data, peer_id);
  1300. return nbuf;
  1301. }
  1302. }
  1303. /* Single linear frame */
  1304. /*
  1305. * If nbuf is a simple linear frame, use send_single function to
  1306. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1307. * SRNG. There is no need to setup a MSDU extension descriptor.
  1308. */
  1309. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info.tid,
  1310. &msdu_info.tx_queue, msdu_info.meta_data, peer_id);
  1311. return nbuf;
  1312. send_multiple:
  1313. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1314. return nbuf;
  1315. }
  1316. /**
  1317. * dp_tx_reinject_handler() - Tx Reinject Handler
  1318. * @tx_desc: software descriptor head pointer
  1319. * @status : Tx completion status from HTT descriptor
  1320. *
  1321. * This function reinjects frames back to Target.
  1322. * Todo - Host queue needs to be added
  1323. *
  1324. * Return: none
  1325. */
  1326. static
  1327. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1328. {
  1329. struct dp_vdev *vdev;
  1330. struct dp_peer *peer = NULL;
  1331. uint32_t peer_id = HTT_INVALID_PEER;
  1332. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1333. qdf_nbuf_t nbuf_copy = NULL;
  1334. struct dp_tx_msdu_info_s msdu_info;
  1335. vdev = tx_desc->vdev;
  1336. qdf_assert(vdev);
  1337. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1338. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1339. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1340. "%s Tx reinject path\n", __func__);
  1341. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1342. qdf_nbuf_len(tx_desc->nbuf));
  1343. if (!vdev->osif_proxy_arp) {
  1344. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1345. "function pointer to proxy arp not present\n");
  1346. return;
  1347. }
  1348. if (qdf_unlikely(vdev->mesh_vdev)) {
  1349. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1350. } else {
  1351. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1352. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1353. (peer->bss_peer || peer->nawds_enabled)
  1354. && !(vdev->osif_proxy_arp(
  1355. vdev->osif_vdev,
  1356. nbuf))) {
  1357. nbuf_copy = qdf_nbuf_copy(nbuf);
  1358. if (!nbuf_copy) {
  1359. QDF_TRACE(QDF_MODULE_ID_DP,
  1360. QDF_TRACE_LEVEL_ERROR,
  1361. FL("nbuf copy failed"));
  1362. break;
  1363. }
  1364. if (peer->nawds_enabled)
  1365. peer_id = peer->peer_ids[0];
  1366. else
  1367. peer_id = HTT_INVALID_PEER;
  1368. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1369. nbuf_copy, msdu_info.tid,
  1370. &msdu_info.tx_queue,
  1371. msdu_info.meta_data, peer_id);
  1372. if (nbuf_copy) {
  1373. QDF_TRACE(QDF_MODULE_ID_DP,
  1374. QDF_TRACE_LEVEL_ERROR,
  1375. FL("pkt send failed"));
  1376. qdf_nbuf_free(nbuf_copy);
  1377. }
  1378. }
  1379. }
  1380. }
  1381. qdf_nbuf_free(nbuf);
  1382. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1383. }
  1384. /**
  1385. * dp_tx_inspect_handler() - Tx Inspect Handler
  1386. * @tx_desc: software descriptor head pointer
  1387. * @status : Tx completion status from HTT descriptor
  1388. *
  1389. * Handles Tx frames sent back to Host for inspection
  1390. * (ProxyARP)
  1391. *
  1392. * Return: none
  1393. */
  1394. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1395. {
  1396. struct dp_soc *soc;
  1397. struct dp_pdev *pdev = tx_desc->pdev;
  1398. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1399. "%s Tx inspect path\n",
  1400. __func__);
  1401. qdf_assert(pdev);
  1402. soc = pdev->soc;
  1403. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1404. qdf_nbuf_len(tx_desc->nbuf));
  1405. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1406. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1407. }
  1408. /**
  1409. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1410. * @soc: Soc handle
  1411. * @desc: software Tx descriptor to be processed
  1412. *
  1413. * Return: none
  1414. */
  1415. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1416. struct dp_tx_desc_s *desc)
  1417. {
  1418. struct dp_vdev *vdev = desc->vdev;
  1419. qdf_nbuf_t nbuf = desc->nbuf;
  1420. /* 0 : MSDU buffer, 1 : MLE */
  1421. if (desc->msdu_ext_desc) {
  1422. /* TSO free */
  1423. if (hal_tx_ext_desc_get_tso_enable(
  1424. desc->msdu_ext_desc->vaddr)) {
  1425. /* If remaining number of segment is 0
  1426. * actual TSO may unmap and free */
  1427. if (!DP_DESC_NUM_FRAG(desc)) {
  1428. qdf_nbuf_unmap(soc->osdev, nbuf,
  1429. QDF_DMA_TO_DEVICE);
  1430. qdf_nbuf_free(nbuf);
  1431. return;
  1432. }
  1433. }
  1434. }
  1435. if (desc->flags & DP_TX_DESC_FLAG_ME)
  1436. dp_tx_me_free_buf(desc->pdev, desc->me_buffer);
  1437. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1438. if (!vdev->mesh_vdev) {
  1439. qdf_nbuf_free(nbuf);
  1440. } else {
  1441. vdev->osif_tx_free_ext((nbuf));
  1442. }
  1443. }
  1444. /**
  1445. * dp_tx_mec_handler() - Tx MEC Notify Handler
  1446. * @vdev: pointer to dp dev handler
  1447. * @status : Tx completion status from HTT descriptor
  1448. *
  1449. * Handles MEC notify event sent from fw to Host
  1450. *
  1451. * Return: none
  1452. */
  1453. #ifdef FEATURE_WDS
  1454. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1455. {
  1456. struct dp_soc *soc;
  1457. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  1458. struct dp_peer *peer;
  1459. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  1460. soc = vdev->pdev->soc;
  1461. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  1462. peer = TAILQ_FIRST(&vdev->peer_list);
  1463. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  1464. if (!peer) {
  1465. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1466. FL("peer is NULL"));
  1467. return;
  1468. }
  1469. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1470. "%s Tx MEC Handler\n",
  1471. __func__);
  1472. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  1473. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  1474. status[(DP_MAC_ADDR_LEN - 2) + i];
  1475. if (!dp_peer_add_ast(soc, peer, mac_addr, 2)) {
  1476. soc->cdp_soc.ol_ops->peer_add_wds_entry(
  1477. vdev->pdev->osif_pdev,
  1478. mac_addr,
  1479. vdev->mac_addr.raw,
  1480. flags);
  1481. }
  1482. }
  1483. #else
  1484. static void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  1485. {
  1486. }
  1487. #endif
  1488. /**
  1489. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  1490. * @tx_desc: software descriptor head pointer
  1491. * @status : Tx completion status from HTT descriptor
  1492. *
  1493. * This function will process HTT Tx indication messages from Target
  1494. *
  1495. * Return: none
  1496. */
  1497. static
  1498. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1499. {
  1500. uint8_t tx_status;
  1501. struct dp_pdev *pdev;
  1502. struct dp_vdev *vdev;
  1503. struct dp_soc *soc;
  1504. uint32_t *htt_status_word = (uint32_t *) status;
  1505. qdf_assert(tx_desc->pdev);
  1506. pdev = tx_desc->pdev;
  1507. vdev = tx_desc->vdev;
  1508. soc = pdev->soc;
  1509. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  1510. switch (tx_status) {
  1511. case HTT_TX_FW2WBM_TX_STATUS_OK:
  1512. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  1513. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  1514. {
  1515. dp_tx_comp_free_buf(soc, tx_desc);
  1516. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1517. break;
  1518. }
  1519. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  1520. {
  1521. dp_tx_reinject_handler(tx_desc, status);
  1522. break;
  1523. }
  1524. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  1525. {
  1526. dp_tx_inspect_handler(tx_desc, status);
  1527. break;
  1528. }
  1529. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  1530. {
  1531. dp_tx_mec_handler(vdev, status);
  1532. break;
  1533. }
  1534. default:
  1535. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1536. "%s Invalid HTT tx_status %d\n",
  1537. __func__, tx_status);
  1538. break;
  1539. }
  1540. }
  1541. #ifdef MESH_MODE_SUPPORT
  1542. /**
  1543. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  1544. * in mesh meta header
  1545. * @tx_desc: software descriptor head pointer
  1546. * @ts: pointer to tx completion stats
  1547. * Return: none
  1548. */
  1549. static
  1550. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1551. struct hal_tx_completion_status *ts)
  1552. {
  1553. struct meta_hdr_s *mhdr;
  1554. qdf_nbuf_t netbuf = tx_desc->nbuf;
  1555. if (!tx_desc->msdu_ext_desc) {
  1556. qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset);
  1557. }
  1558. qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s));
  1559. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  1560. mhdr->rssi = ts->ack_frame_rssi;
  1561. mhdr->channel = tx_desc->pdev->operating_channel;
  1562. }
  1563. #else
  1564. static
  1565. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  1566. struct hal_tx_completion_status *ts)
  1567. {
  1568. }
  1569. #endif
  1570. /**
  1571. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  1572. * @peer: Handle to DP peer
  1573. * @ts: pointer to HAL Tx completion stats
  1574. * @length: MSDU length
  1575. *
  1576. * Return: None
  1577. */
  1578. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  1579. struct hal_tx_completion_status *ts, uint32_t length)
  1580. {
  1581. struct dp_pdev *pdev = peer->vdev->pdev;
  1582. struct dp_soc *soc = pdev->soc;
  1583. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  1584. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  1585. return;
  1586. DP_STATS_INCC(peer, tx.tx_failed, 1,
  1587. !(ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  1588. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  1589. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  1590. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  1591. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  1592. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  1593. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  1594. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  1595. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  1596. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  1597. return;
  1598. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1599. ((ts->mcs >= MAX_MCS_11A) && (ts->pkt_type == DOT11_A)));
  1600. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1601. ((ts->mcs <= MAX_MCS_11A) && (ts->pkt_type == DOT11_A)));
  1602. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1603. ((ts->mcs >= MAX_MCS_11B) && (ts->pkt_type == DOT11_B)));
  1604. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1605. ((ts->mcs <= MAX_MCS_11B) && (ts->pkt_type == DOT11_B)));
  1606. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1607. ((ts->mcs >= MAX_MCS_11A) && (ts->pkt_type == DOT11_N)));
  1608. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1609. ((ts->mcs <= MAX_MCS_11A) && (ts->pkt_type == DOT11_N)));
  1610. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1611. ((ts->mcs >= MAX_MCS_11AC) && (ts->pkt_type == DOT11_AC)));
  1612. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1613. ((ts->mcs <= MAX_MCS_11AC) && (ts->pkt_type == DOT11_AC)));
  1614. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[MAX_MCS], 1,
  1615. ((ts->mcs >= (MAX_MCS-1)) && (ts->pkt_type == DOT11_AX)));
  1616. DP_STATS_INCC(peer, tx.pkt_type[ts->pkt_type].mcs_count[ts->mcs], 1,
  1617. ((ts->mcs <= (MAX_MCS-1)) && (ts->pkt_type == DOT11_AX)));
  1618. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  1619. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  1620. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  1621. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  1622. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  1623. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  1624. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  1625. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  1626. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  1627. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  1628. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  1629. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  1630. &peer->stats, ts->peer_id,
  1631. UPDATE_PEER_STATS);
  1632. }
  1633. }
  1634. /**
  1635. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  1636. * @tx_desc: software descriptor head pointer
  1637. * @length: packet length
  1638. *
  1639. * Return: none
  1640. */
  1641. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  1642. uint32_t length)
  1643. {
  1644. struct hal_tx_completion_status ts;
  1645. struct dp_soc *soc = NULL;
  1646. struct dp_vdev *vdev = tx_desc->vdev;
  1647. struct dp_peer *peer = NULL;
  1648. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1649. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1650. "-------------------- \n"
  1651. "Tx Completion Stats: \n"
  1652. "-------------------- \n"
  1653. "ack_frame_rssi = %d \n"
  1654. "first_msdu = %d \n"
  1655. "last_msdu = %d \n"
  1656. "msdu_part_of_amsdu = %d \n"
  1657. "rate_stats valid = %d \n"
  1658. "bw = %d \n"
  1659. "pkt_type = %d \n"
  1660. "stbc = %d \n"
  1661. "ldpc = %d \n"
  1662. "sgi = %d \n"
  1663. "mcs = %d \n"
  1664. "ofdma = %d \n"
  1665. "tones_in_ru = %d \n"
  1666. "tsf = %d \n"
  1667. "ppdu_id = %d \n"
  1668. "transmit_cnt = %d \n"
  1669. "tid = %d \n"
  1670. "peer_id = %d \n",
  1671. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  1672. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  1673. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  1674. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  1675. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  1676. ts.peer_id);
  1677. if (!vdev) {
  1678. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1679. "invalid vdev");
  1680. goto out;
  1681. }
  1682. soc = vdev->pdev->soc;
  1683. /* Update SoC level stats */
  1684. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  1685. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  1686. /* Update per-packet stats */
  1687. if (qdf_unlikely(vdev->mesh_vdev))
  1688. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  1689. /* Update peer level stats */
  1690. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1691. if (!peer) {
  1692. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1693. "invalid peer");
  1694. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  1695. goto out;
  1696. }
  1697. dp_tx_update_peer_stats(peer, &ts, length);
  1698. out:
  1699. return;
  1700. }
  1701. /**
  1702. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  1703. * @soc: core txrx main context
  1704. * @comp_head: software descriptor head pointer
  1705. *
  1706. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  1707. * and release the software descriptors after processing is complete
  1708. *
  1709. * Return: none
  1710. */
  1711. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  1712. struct dp_tx_desc_s *comp_head)
  1713. {
  1714. struct dp_tx_desc_s *desc;
  1715. struct dp_tx_desc_s *next;
  1716. struct hal_tx_completion_status ts = {0};
  1717. uint32_t length;
  1718. struct dp_peer *peer;
  1719. DP_HIST_INIT();
  1720. desc = comp_head;
  1721. while (desc) {
  1722. hal_tx_comp_get_status(&desc->comp, &ts);
  1723. peer = dp_peer_find_by_id(soc, ts.peer_id);
  1724. length = qdf_nbuf_len(desc->nbuf);
  1725. /* Process Tx status in descriptor */
  1726. if (soc->process_tx_status ||
  1727. (desc->vdev && desc->vdev->mesh_vdev))
  1728. dp_tx_comp_process_tx_status(desc, length);
  1729. dp_tx_comp_free_buf(soc, desc);
  1730. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  1731. next = desc->next;
  1732. dp_tx_desc_release(desc, desc->pool_id);
  1733. desc = next;
  1734. }
  1735. DP_TX_HIST_STATS_PER_PDEV();
  1736. }
  1737. /**
  1738. * dp_tx_comp_handler() - Tx completion handler
  1739. * @soc: core txrx main context
  1740. * @ring_id: completion ring id
  1741. * @budget: No. of packets/descriptors that can be serviced in one loop
  1742. *
  1743. * This function will collect hardware release ring element contents and
  1744. * handle descriptor contents. Based on contents, free packet or handle error
  1745. * conditions
  1746. *
  1747. * Return: none
  1748. */
  1749. uint32_t dp_tx_comp_handler(struct dp_soc *soc, uint32_t ring_id,
  1750. uint32_t budget)
  1751. {
  1752. void *tx_comp_hal_desc;
  1753. uint8_t buffer_src;
  1754. uint8_t pool_id;
  1755. uint32_t tx_desc_id;
  1756. struct dp_tx_desc_s *tx_desc = NULL;
  1757. struct dp_tx_desc_s *head_desc = NULL;
  1758. struct dp_tx_desc_s *tail_desc = NULL;
  1759. uint32_t num_processed;
  1760. void *hal_srng = soc->tx_comp_ring[ring_id].hal_srng;
  1761. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1762. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1763. "%s %d : HAL RING Access Failed -- %p\n",
  1764. __func__, __LINE__, hal_srng);
  1765. return 0;
  1766. }
  1767. num_processed = 0;
  1768. /* Find head descriptor from completion ring */
  1769. while (qdf_likely(tx_comp_hal_desc =
  1770. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  1771. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  1772. /* If this buffer was not released by TQM or FW, then it is not
  1773. * Tx completion indication, skip to next descriptor */
  1774. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  1775. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1776. QDF_TRACE(QDF_MODULE_ID_DP,
  1777. QDF_TRACE_LEVEL_ERROR,
  1778. "Tx comp release_src != TQM | FW");
  1779. /* TODO Handle Freeing of the buffer in descriptor */
  1780. continue;
  1781. }
  1782. /* Get descriptor id */
  1783. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  1784. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  1785. DP_TX_DESC_ID_POOL_OS;
  1786. /* Pool ID is out of limit. Error */
  1787. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  1788. soc->wlan_cfg_ctx)) {
  1789. QDF_TRACE(QDF_MODULE_ID_DP,
  1790. QDF_TRACE_LEVEL_FATAL,
  1791. "TX COMP pool id %d not valid",
  1792. pool_id);
  1793. /* Check if assert aborts execution, if not handle
  1794. * return here */
  1795. QDF_ASSERT(0);
  1796. }
  1797. /* Find Tx descriptor */
  1798. tx_desc = dp_tx_desc_find(soc, pool_id,
  1799. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  1800. DP_TX_DESC_ID_PAGE_OS,
  1801. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  1802. DP_TX_DESC_ID_OFFSET_OS);
  1803. /* Pool id is not matching. Error */
  1804. if (tx_desc && (tx_desc->pool_id != pool_id)) {
  1805. QDF_TRACE(QDF_MODULE_ID_DP,
  1806. QDF_TRACE_LEVEL_FATAL,
  1807. "Tx Comp pool id %d not matched %d",
  1808. pool_id, tx_desc->pool_id);
  1809. /* Check if assert aborts execution, if not handle
  1810. * return here */
  1811. QDF_ASSERT(0);
  1812. }
  1813. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  1814. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  1815. QDF_TRACE(QDF_MODULE_ID_DP,
  1816. QDF_TRACE_LEVEL_FATAL,
  1817. "Txdesc invalid, flgs = %x,id = %d",
  1818. tx_desc->flags, tx_desc_id);
  1819. qdf_assert_always(0);
  1820. }
  1821. /*
  1822. * If the release source is FW, process the HTT
  1823. * status
  1824. */
  1825. if (qdf_unlikely(buffer_src ==
  1826. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  1827. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1828. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  1829. htt_tx_status);
  1830. dp_tx_process_htt_completion(tx_desc,
  1831. htt_tx_status);
  1832. } else {
  1833. tx_desc->next = NULL;
  1834. /* First ring descriptor on the cycle */
  1835. if (!head_desc) {
  1836. head_desc = tx_desc;
  1837. } else {
  1838. tail_desc->next = tx_desc;
  1839. }
  1840. tail_desc = tx_desc;
  1841. /* Collect hw completion contents */
  1842. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  1843. &tx_desc->comp, soc->process_tx_status);
  1844. }
  1845. num_processed++;
  1846. /*
  1847. * Processed packet count is more than given quota
  1848. * stop to processing
  1849. */
  1850. if (num_processed >= budget)
  1851. break;
  1852. }
  1853. hal_srng_access_end(soc->hal_soc, hal_srng);
  1854. /* Process the reaped descriptors */
  1855. if (head_desc)
  1856. dp_tx_comp_process_desc(soc, head_desc);
  1857. return num_processed;
  1858. }
  1859. /**
  1860. * dp_tx_vdev_attach() - attach vdev to dp tx
  1861. * @vdev: virtual device instance
  1862. *
  1863. * Return: QDF_STATUS_SUCCESS: success
  1864. * QDF_STATUS_E_RESOURCES: Error return
  1865. */
  1866. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  1867. {
  1868. /*
  1869. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  1870. */
  1871. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  1872. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  1873. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  1874. vdev->vdev_id);
  1875. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  1876. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  1877. /*
  1878. * Set HTT Extension Valid bit to 0 by default
  1879. */
  1880. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  1881. dp_tx_vdev_update_search_flags(vdev);
  1882. return QDF_STATUS_SUCCESS;
  1883. }
  1884. /**
  1885. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  1886. * @vdev: virtual device instance
  1887. *
  1888. * Return: void
  1889. *
  1890. */
  1891. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  1892. {
  1893. /*
  1894. * Enable both AddrY (SA based search) and AddrX (Da based search)
  1895. * for TDLS link
  1896. *
  1897. * Enable AddrY (SA based search) only for non-WDS STA and
  1898. * ProxySTA VAP modes.
  1899. *
  1900. * In all other VAP modes, only DA based search should be
  1901. * enabled
  1902. */
  1903. if (vdev->opmode == wlan_op_mode_sta &&
  1904. vdev->tdls_link_connected)
  1905. vdev->hal_desc_addr_search_flags =
  1906. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  1907. else if ((vdev->opmode == wlan_op_mode_sta &&
  1908. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  1909. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  1910. else
  1911. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  1912. }
  1913. /**
  1914. * dp_tx_vdev_detach() - detach vdev from dp tx
  1915. * @vdev: virtual device instance
  1916. *
  1917. * Return: QDF_STATUS_SUCCESS: success
  1918. * QDF_STATUS_E_RESOURCES: Error return
  1919. */
  1920. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  1921. {
  1922. return QDF_STATUS_SUCCESS;
  1923. }
  1924. /**
  1925. * dp_tx_pdev_attach() - attach pdev to dp tx
  1926. * @pdev: physical device instance
  1927. *
  1928. * Return: QDF_STATUS_SUCCESS: success
  1929. * QDF_STATUS_E_RESOURCES: Error return
  1930. */
  1931. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  1932. {
  1933. struct dp_soc *soc = pdev->soc;
  1934. /* Initialize Flow control counters */
  1935. qdf_atomic_init(&pdev->num_tx_exception);
  1936. qdf_atomic_init(&pdev->num_tx_outstanding);
  1937. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1938. /* Initialize descriptors in TCL Ring */
  1939. hal_tx_init_data_ring(soc->hal_soc,
  1940. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  1941. }
  1942. return QDF_STATUS_SUCCESS;
  1943. }
  1944. /**
  1945. * dp_tx_pdev_detach() - detach pdev from dp tx
  1946. * @pdev: physical device instance
  1947. *
  1948. * Return: QDF_STATUS_SUCCESS: success
  1949. * QDF_STATUS_E_RESOURCES: Error return
  1950. */
  1951. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  1952. {
  1953. /* What should do here? */
  1954. return QDF_STATUS_SUCCESS;
  1955. }
  1956. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  1957. /* Pools will be allocated dynamically */
  1958. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  1959. int num_desc)
  1960. {
  1961. uint8_t i;
  1962. for (i = 0; i < num_pool; i++) {
  1963. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  1964. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  1965. }
  1966. return 0;
  1967. }
  1968. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  1969. {
  1970. uint8_t i;
  1971. for (i = 0; i < num_pool; i++)
  1972. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  1973. }
  1974. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  1975. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  1976. int num_desc)
  1977. {
  1978. uint8_t i;
  1979. /* Allocate software Tx descriptor pools */
  1980. for (i = 0; i < num_pool; i++) {
  1981. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  1982. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1983. "%s Tx Desc Pool alloc %d failed %p\n",
  1984. __func__, i, soc);
  1985. return ENOMEM;
  1986. }
  1987. }
  1988. return 0;
  1989. }
  1990. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  1991. {
  1992. uint8_t i;
  1993. for (i = 0; i < num_pool; i++) {
  1994. if (dp_tx_desc_pool_free(soc, i)) {
  1995. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1996. "%s Tx Desc Pool Free failed\n", __func__);
  1997. }
  1998. }
  1999. }
  2000. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2001. /**
  2002. * dp_tx_soc_detach() - detach soc from dp tx
  2003. * @soc: core txrx main context
  2004. *
  2005. * This function will detach dp tx into main device context
  2006. * will free dp tx resource and initialize resources
  2007. *
  2008. * Return: QDF_STATUS_SUCCESS: success
  2009. * QDF_STATUS_E_RESOURCES: Error return
  2010. */
  2011. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2012. {
  2013. uint8_t num_pool;
  2014. uint16_t num_desc;
  2015. uint16_t num_ext_desc;
  2016. uint8_t i;
  2017. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2018. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2019. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2020. dp_tx_flow_control_deinit(soc);
  2021. dp_tx_delete_static_pools(soc, num_pool);
  2022. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2023. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2024. __func__, num_pool, num_desc);
  2025. for (i = 0; i < num_pool; i++) {
  2026. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2027. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2028. "%s Tx Ext Desc Pool Free failed\n",
  2029. __func__);
  2030. return QDF_STATUS_E_RESOURCES;
  2031. }
  2032. }
  2033. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2034. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2035. __func__, num_pool, num_ext_desc);
  2036. for (i = 0; i < num_pool; i++) {
  2037. dp_tx_tso_desc_pool_free(soc, i);
  2038. }
  2039. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2040. "%s TSO Desc Pool %d Free descs = %d\n",
  2041. __func__, num_pool, num_desc);
  2042. for (i = 0; i < num_pool; i++)
  2043. dp_tx_tso_num_seg_pool_free(soc, i);
  2044. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2045. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2046. __func__, num_pool, num_desc);
  2047. return QDF_STATUS_SUCCESS;
  2048. }
  2049. /**
  2050. * dp_tx_soc_attach() - attach soc to dp tx
  2051. * @soc: core txrx main context
  2052. *
  2053. * This function will attach dp tx into main device context
  2054. * will allocate dp tx resource and initialize resources
  2055. *
  2056. * Return: QDF_STATUS_SUCCESS: success
  2057. * QDF_STATUS_E_RESOURCES: Error return
  2058. */
  2059. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2060. {
  2061. uint8_t i;
  2062. uint8_t num_pool;
  2063. uint32_t num_desc;
  2064. uint32_t num_ext_desc;
  2065. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2066. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2067. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2068. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2069. goto fail;
  2070. dp_tx_flow_control_init(soc);
  2071. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2072. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2073. __func__, num_pool, num_desc);
  2074. /* Allocate extension tx descriptor pools */
  2075. for (i = 0; i < num_pool; i++) {
  2076. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2077. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2078. "MSDU Ext Desc Pool alloc %d failed %p\n",
  2079. i, soc);
  2080. goto fail;
  2081. }
  2082. }
  2083. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2084. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2085. __func__, num_pool, num_ext_desc);
  2086. for (i = 0; i < num_pool; i++) {
  2087. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2088. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2089. "TSO Desc Pool alloc %d failed %p\n",
  2090. i, soc);
  2091. goto fail;
  2092. }
  2093. }
  2094. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2095. "%s TSO Desc Alloc %d, descs = %d\n",
  2096. __func__, num_pool, num_desc);
  2097. for (i = 0; i < num_pool; i++) {
  2098. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2099. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2100. "TSO Num of seg Pool alloc %d failed %p\n",
  2101. i, soc);
  2102. goto fail;
  2103. }
  2104. }
  2105. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2106. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2107. __func__, num_pool, num_desc);
  2108. /* Initialize descriptors in TCL Rings */
  2109. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2110. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2111. hal_tx_init_data_ring(soc->hal_soc,
  2112. soc->tcl_data_ring[i].hal_srng);
  2113. }
  2114. }
  2115. /*
  2116. * todo - Add a runtime config option to enable this.
  2117. */
  2118. /*
  2119. * Due to multiple issues on NPR EMU, enable it selectively
  2120. * only for NPR EMU, should be removed, once NPR platforms
  2121. * are stable.
  2122. */
  2123. soc->process_tx_status = 1;
  2124. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2125. "%s HAL Tx init Success\n", __func__);
  2126. return QDF_STATUS_SUCCESS;
  2127. fail:
  2128. /* Detach will take care of freeing only allocated resources */
  2129. dp_tx_soc_detach(soc);
  2130. return QDF_STATUS_E_RESOURCES;
  2131. }
  2132. /*
  2133. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2134. * pdev: pointer to DP PDEV structure
  2135. * seg_info_head: Pointer to the head of list
  2136. *
  2137. * return: void
  2138. */
  2139. static inline void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2140. struct dp_tx_seg_info_s *seg_info_head)
  2141. {
  2142. struct dp_tx_me_buf_t *mc_uc_buf;
  2143. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2144. qdf_nbuf_t nbuf = NULL;
  2145. uint64_t phy_addr;
  2146. while (seg_info_head) {
  2147. nbuf = seg_info_head->nbuf;
  2148. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2149. seg_info_new->frags[0].vaddr;
  2150. phy_addr = seg_info_head->frags[0].paddr_hi;
  2151. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2152. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2153. phy_addr,
  2154. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2155. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2156. qdf_nbuf_free(nbuf);
  2157. seg_info_new = seg_info_head;
  2158. seg_info_head = seg_info_head->next;
  2159. qdf_mem_free(seg_info_new);
  2160. }
  2161. }
  2162. /**
  2163. * dp_tx_me_send_convert_ucast(): fuction to convert multicast to unicast
  2164. * @vdev: DP VDEV handle
  2165. * @nbuf: Multicast nbuf
  2166. * @newmac: Table of the clients to which packets have to be sent
  2167. * @new_mac_cnt: No of clients
  2168. *
  2169. * return: no of converted packets
  2170. */
  2171. uint16_t
  2172. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2173. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2174. {
  2175. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2176. struct dp_pdev *pdev = vdev->pdev;
  2177. struct ether_header *eh;
  2178. uint8_t *data;
  2179. uint16_t len;
  2180. /* reference to frame dst addr */
  2181. uint8_t *dstmac;
  2182. /* copy of original frame src addr */
  2183. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2184. /* local index into newmac */
  2185. uint8_t new_mac_idx = 0;
  2186. struct dp_tx_me_buf_t *mc_uc_buf;
  2187. qdf_nbuf_t nbuf_clone;
  2188. struct dp_tx_msdu_info_s msdu_info;
  2189. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2190. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2191. struct dp_tx_seg_info_s *seg_info_new;
  2192. struct dp_tx_frag_info_s data_frag;
  2193. qdf_dma_addr_t paddr_data;
  2194. qdf_dma_addr_t paddr_mcbuf = 0;
  2195. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2196. QDF_STATUS status;
  2197. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2198. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2199. eh = (struct ether_header *) nbuf;
  2200. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2201. len = qdf_nbuf_len(nbuf);
  2202. data = qdf_nbuf_data(nbuf);
  2203. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2204. QDF_DMA_TO_DEVICE);
  2205. if (status) {
  2206. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2207. "Mapping failure Error:%d", status);
  2208. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2209. return 0;
  2210. }
  2211. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2212. /*preparing data fragment*/
  2213. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2214. data_frag.paddr_lo = (uint32_t)paddr_data;
  2215. data_frag.paddr_hi = ((uint64_t)paddr_data & 0xffffffff00000000) >> 32;
  2216. data_frag.len = len - DP_MAC_ADDR_LEN;
  2217. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2218. dstmac = newmac[new_mac_idx];
  2219. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2220. "added mac addr (%pM)", dstmac);
  2221. /* Check for NULL Mac Address */
  2222. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2223. continue;
  2224. /* frame to self mac. skip */
  2225. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2226. continue;
  2227. /*
  2228. * TODO: optimize to avoid malloc in per-packet path
  2229. * For eg. seg_pool can be made part of vdev structure
  2230. */
  2231. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2232. if (!seg_info_new) {
  2233. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2234. "alloc failed");
  2235. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2236. goto fail_seg_alloc;
  2237. }
  2238. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2239. if (mc_uc_buf == NULL)
  2240. goto fail_buf_alloc;
  2241. /*
  2242. * TODO: Check if we need to clone the nbuf
  2243. * Or can we just use the reference for all cases
  2244. */
  2245. if (new_mac_idx < (new_mac_cnt - 1)) {
  2246. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2247. if (nbuf_clone == NULL) {
  2248. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2249. goto fail_clone;
  2250. }
  2251. } else {
  2252. /*
  2253. * Update the ref
  2254. * to account for frame sent without cloning
  2255. */
  2256. qdf_nbuf_ref(nbuf);
  2257. nbuf_clone = nbuf;
  2258. }
  2259. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2260. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2261. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2262. &paddr_mcbuf);
  2263. if (status) {
  2264. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2265. "Mapping failure Error:%d", status);
  2266. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2267. goto fail_map;
  2268. }
  2269. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2270. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2271. seg_info_new->frags[0].paddr_hi =
  2272. ((u64)paddr_mcbuf & 0xffffffff00000000) >> 32;
  2273. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2274. seg_info_new->frags[1] = data_frag;
  2275. seg_info_new->nbuf = nbuf_clone;
  2276. seg_info_new->frag_cnt = 2;
  2277. seg_info_new->total_len = len;
  2278. seg_info_new->next = NULL;
  2279. if (seg_info_head == NULL)
  2280. seg_info_head = seg_info_new;
  2281. else
  2282. seg_info_tail->next = seg_info_new;
  2283. seg_info_tail = seg_info_new;
  2284. }
  2285. if (!seg_info_head)
  2286. return 0;
  2287. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2288. msdu_info.num_seg = new_mac_cnt;
  2289. msdu_info.frm_type = dp_tx_frm_me;
  2290. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2291. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2292. while (seg_info_head->next) {
  2293. seg_info_new = seg_info_head;
  2294. seg_info_head = seg_info_head->next;
  2295. qdf_mem_free(seg_info_new);
  2296. }
  2297. qdf_mem_free(seg_info_head);
  2298. return new_mac_cnt;
  2299. fail_map:
  2300. qdf_nbuf_free(nbuf_clone);
  2301. fail_clone:
  2302. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2303. fail_buf_alloc:
  2304. qdf_mem_free(seg_info_new);
  2305. fail_seg_alloc:
  2306. dp_tx_me_mem_free(pdev, seg_info_head);
  2307. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2308. return 0;
  2309. }