wcd938x.c 118 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/slab.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/kernel.h>
  11. #include <linux/component.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/wcdcal-hwdep.h>
  19. #include <asoc/msm-cdc-pinctrl.h>
  20. #include <asoc/msm-cdc-supply.h>
  21. #include <dt-bindings/sound/audio-codec-port-types.h>
  22. #include "wcd938x-registers.h"
  23. #include "wcd938x.h"
  24. #include "internal.h"
  25. #define NUM_SWRS_DT_PARAMS 5
  26. #define WCD938X_VARIANT_ENTRY_SIZE 32
  27. #define WCD938X_VERSION_1_0 1
  28. #define WCD938X_VERSION_ENTRY_SIZE 32
  29. #define EAR_RX_PATH_AUX 1
  30. #define ADC_MODE_VAL_HIFI 0x01
  31. #define ADC_MODE_VAL_LO_HIF 0x02
  32. #define ADC_MODE_VAL_NORMAL 0x03
  33. #define ADC_MODE_VAL_LP 0x05
  34. #define ADC_MODE_VAL_ULP1 0x09
  35. #define ADC_MODE_VAL_ULP2 0x0B
  36. #define NUM_ATTEMPTS 5
  37. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  38. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  39. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  40. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  41. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  42. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  43. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  44. SNDRV_PCM_RATE_384000)
  45. /* Fractional Rates */
  46. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  47. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  48. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  49. SNDRV_PCM_FMTBIT_S24_LE |\
  50. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  51. enum {
  52. CODEC_TX = 0,
  53. CODEC_RX,
  54. };
  55. enum {
  56. WCD_ADC1 = 0,
  57. WCD_ADC2,
  58. WCD_ADC3,
  59. WCD_ADC4,
  60. ALLOW_BUCK_DISABLE,
  61. HPH_COMP_DELAY,
  62. HPH_PA_DELAY,
  63. AMIC2_BCS_ENABLE,
  64. };
  65. enum {
  66. ADC_MODE_INVALID = 0,
  67. ADC_MODE_HIFI,
  68. ADC_MODE_LO_HIF,
  69. ADC_MODE_NORMAL,
  70. ADC_MODE_LP,
  71. ADC_MODE_ULP1,
  72. ADC_MODE_ULP2,
  73. };
  74. static u8 tx_mode_bit[] = {
  75. [ADC_MODE_INVALID] = 0x00,
  76. [ADC_MODE_HIFI] = 0x01,
  77. [ADC_MODE_LO_HIF] = 0x02,
  78. [ADC_MODE_NORMAL] = 0x04,
  79. [ADC_MODE_LP] = 0x08,
  80. [ADC_MODE_ULP1] = 0x10,
  81. [ADC_MODE_ULP2] = 0x20,
  82. };
  83. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  84. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  85. static int wcd938x_handle_post_irq(void *data);
  86. static int wcd938x_reset(struct device *dev);
  87. static int wcd938x_reset_low(struct device *dev);
  88. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  89. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  90. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  91. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  92. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  93. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  94. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  95. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  96. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  97. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  98. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  109. };
  110. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  111. .name = "wcd938x",
  112. .irqs = wcd938x_irqs,
  113. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  114. .num_regs = 3,
  115. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  116. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  117. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  118. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  119. .use_ack = 1,
  120. .runtime_pm = false,
  121. .handle_post_irq = wcd938x_handle_post_irq,
  122. .irq_drv_data = NULL,
  123. };
  124. static int wcd938x_handle_post_irq(void *data)
  125. {
  126. struct wcd938x_priv *wcd938x = data;
  127. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  128. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  129. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  130. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  131. wcd938x->tx_swr_dev->slave_irq_pending =
  132. ((sts1 || sts2 || sts3) ? true : false);
  133. return IRQ_HANDLED;
  134. }
  135. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  136. {
  137. int ret = 0;
  138. int bank = 0;
  139. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  140. if (ret)
  141. return -EINVAL;
  142. return ((bank & 0x40) ? 1: 0);
  143. }
  144. static int wcd938x_get_clk_rate(int mode)
  145. {
  146. int rate;
  147. switch (mode) {
  148. case ADC_MODE_ULP2:
  149. rate = SWR_CLK_RATE_0P6MHZ;
  150. break;
  151. case ADC_MODE_ULP1:
  152. rate = SWR_CLK_RATE_1P2MHZ;
  153. break;
  154. case ADC_MODE_LP:
  155. rate = SWR_CLK_RATE_4P8MHZ;
  156. break;
  157. case ADC_MODE_NORMAL:
  158. case ADC_MODE_LO_HIF:
  159. case ADC_MODE_HIFI:
  160. case ADC_MODE_INVALID:
  161. default:
  162. rate = SWR_CLK_RATE_9P6MHZ;
  163. break;
  164. }
  165. return rate;
  166. }
  167. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  168. int rate, int bank)
  169. {
  170. u8 mask = (bank ? 0xF0 : 0x0F);
  171. u8 val = 0;
  172. switch (rate) {
  173. case SWR_CLK_RATE_0P6MHZ:
  174. val = (bank ? 0x60 : 0x06);
  175. break;
  176. case SWR_CLK_RATE_1P2MHZ:
  177. val = (bank ? 0x50 : 0x05);
  178. break;
  179. case SWR_CLK_RATE_2P4MHZ:
  180. val = (bank ? 0x30 : 0x03);
  181. break;
  182. case SWR_CLK_RATE_4P8MHZ:
  183. val = (bank ? 0x10 : 0x01);
  184. break;
  185. case SWR_CLK_RATE_9P6MHZ:
  186. default:
  187. val = 0x00;
  188. break;
  189. }
  190. snd_soc_component_update_bits(component,
  191. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  192. mask, val);
  193. return 0;
  194. }
  195. static int wcd938x_init_reg(struct snd_soc_component *component)
  196. {
  197. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  198. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  199. /* 1 msec delay as per HW requirement */
  200. usleep_range(1000, 1010);
  201. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  202. /* 1 msec delay as per HW requirement */
  203. usleep_range(1000, 1010);
  204. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  205. 0x10, 0x00);
  206. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  207. 0xF0, 0x80);
  208. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  209. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  210. /* 10 msec delay as per HW requirement */
  211. usleep_range(10000, 10010);
  212. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  213. snd_soc_component_update_bits(component,
  214. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  215. 0xF0, 0x00);
  216. snd_soc_component_update_bits(component,
  217. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  218. 0x1F, 0x15);
  219. snd_soc_component_update_bits(component,
  220. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  221. 0x1F, 0x15);
  222. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  223. 0xC0, 0x80);
  224. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  225. 0x02, 0x02);
  226. snd_soc_component_update_bits(component,
  227. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  228. 0xFF, 0x14);
  229. snd_soc_component_update_bits(component,
  230. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  231. 0x1F, 0x08);
  232. snd_soc_component_update_bits(component,
  233. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  234. snd_soc_component_update_bits(component,
  235. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  236. snd_soc_component_update_bits(component,
  237. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  238. snd_soc_component_update_bits(component,
  239. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  240. snd_soc_component_update_bits(component,
  241. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  242. snd_soc_component_update_bits(component,
  243. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  244. snd_soc_component_update_bits(component,
  245. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  246. snd_soc_component_update_bits(component,
  247. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  248. snd_soc_component_update_bits(component,
  249. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  250. snd_soc_component_update_bits(component,
  251. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  252. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  253. ((snd_soc_component_read32(component,
  254. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  255. snd_soc_component_update_bits(component,
  256. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  257. return 0;
  258. }
  259. static int wcd938x_set_port_params(struct snd_soc_component *component,
  260. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  261. u8 *ch_mask, u32 *ch_rate,
  262. u8 *port_type, u8 path)
  263. {
  264. int i, j;
  265. u8 num_ports = 0;
  266. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  267. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  268. switch (path) {
  269. case CODEC_RX:
  270. map = &wcd938x->rx_port_mapping;
  271. num_ports = wcd938x->num_rx_ports;
  272. break;
  273. case CODEC_TX:
  274. map = &wcd938x->tx_port_mapping;
  275. num_ports = wcd938x->num_tx_ports;
  276. break;
  277. default:
  278. dev_err(component->dev, "%s Invalid path selected %u\n",
  279. __func__, path);
  280. return -EINVAL;
  281. }
  282. for (i = 0; i <= num_ports; i++) {
  283. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  284. if ((*map)[i][j].slave_port_type == slv_prt_type)
  285. goto found;
  286. }
  287. }
  288. found:
  289. if (i > num_ports || j == MAX_CH_PER_PORT) {
  290. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  291. __func__, slv_prt_type);
  292. return -EINVAL;
  293. }
  294. *port_id = i;
  295. *num_ch = (*map)[i][j].num_ch;
  296. *ch_mask = (*map)[i][j].ch_mask;
  297. *ch_rate = (*map)[i][j].ch_rate;
  298. *port_type = (*map)[i][j].master_port_type;
  299. return 0;
  300. }
  301. static int wcd938x_parse_port_mapping(struct device *dev,
  302. char *prop, u8 path)
  303. {
  304. u32 *dt_array, map_size, map_length;
  305. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  306. u32 slave_port_type, master_port_type;
  307. u32 i, ch_iter = 0;
  308. int ret = 0;
  309. u8 *num_ports = NULL;
  310. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  311. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  312. switch (path) {
  313. case CODEC_RX:
  314. map = &wcd938x->rx_port_mapping;
  315. num_ports = &wcd938x->num_rx_ports;
  316. break;
  317. case CODEC_TX:
  318. map = &wcd938x->tx_port_mapping;
  319. num_ports = &wcd938x->num_tx_ports;
  320. break;
  321. default:
  322. dev_err(dev, "%s Invalid path selected %u\n",
  323. __func__, path);
  324. return -EINVAL;
  325. }
  326. if (!of_find_property(dev->of_node, prop,
  327. &map_size)) {
  328. dev_err(dev, "missing port mapping prop %s\n", prop);
  329. ret = -EINVAL;
  330. goto err_port_map;
  331. }
  332. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  333. dt_array = kzalloc(map_size, GFP_KERNEL);
  334. if (!dt_array) {
  335. ret = -ENOMEM;
  336. goto err_alloc;
  337. }
  338. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  339. NUM_SWRS_DT_PARAMS * map_length);
  340. if (ret) {
  341. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  342. __func__, prop);
  343. goto err_pdata_fail;
  344. }
  345. for (i = 0; i < map_length; i++) {
  346. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  347. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  348. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  349. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  350. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  351. if (port_num != old_port_num)
  352. ch_iter = 0;
  353. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  354. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  355. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  356. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  357. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  358. old_port_num = port_num;
  359. }
  360. *num_ports = port_num;
  361. kfree(dt_array);
  362. return 0;
  363. err_pdata_fail:
  364. kfree(dt_array);
  365. err_alloc:
  366. err_port_map:
  367. return ret;
  368. }
  369. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  370. u8 slv_port_type, int clk_rate,
  371. u8 enable)
  372. {
  373. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  374. u8 port_id, num_ch, ch_mask;
  375. u8 ch_type = 0;
  376. u32 ch_rate;
  377. int slave_ch_idx;
  378. u8 num_port = 1;
  379. int ret = 0;
  380. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  381. &num_ch, &ch_mask, &ch_rate,
  382. &ch_type, CODEC_TX);
  383. if (ret)
  384. return ret;
  385. if (clk_rate)
  386. ch_rate = clk_rate;
  387. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  388. if (slave_ch_idx != -EINVAL)
  389. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  390. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  391. __func__, slave_ch_idx, ch_type);
  392. if (enable)
  393. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  394. num_port, &ch_mask, &ch_rate,
  395. &num_ch, &ch_type);
  396. else
  397. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  398. num_port, &ch_mask, &ch_type);
  399. return ret;
  400. }
  401. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  402. u8 slv_port_type, u8 enable)
  403. {
  404. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  405. u8 port_id, num_ch, ch_mask, port_type;
  406. u32 ch_rate;
  407. u8 num_port = 1;
  408. int ret = 0;
  409. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  410. &num_ch, &ch_mask, &ch_rate,
  411. &port_type, CODEC_RX);
  412. if (ret)
  413. return ret;
  414. if (enable)
  415. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  416. num_port, &ch_mask, &ch_rate,
  417. &num_ch, &port_type);
  418. else
  419. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  420. num_port, &ch_mask, &port_type);
  421. return ret;
  422. }
  423. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  424. {
  425. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  426. if (wcd938x->rx_clk_cnt == 0) {
  427. snd_soc_component_update_bits(component,
  428. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  429. snd_soc_component_update_bits(component,
  430. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  431. snd_soc_component_update_bits(component,
  432. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  433. snd_soc_component_update_bits(component,
  434. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  435. snd_soc_component_update_bits(component,
  436. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  437. snd_soc_component_update_bits(component,
  438. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  439. snd_soc_component_update_bits(component,
  440. WCD938X_AUX_AUXPA, 0x10, 0x10);
  441. }
  442. wcd938x->rx_clk_cnt++;
  443. return 0;
  444. }
  445. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  446. {
  447. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  448. wcd938x->rx_clk_cnt--;
  449. if (wcd938x->rx_clk_cnt == 0) {
  450. snd_soc_component_update_bits(component,
  451. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  452. snd_soc_component_update_bits(component,
  453. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  454. snd_soc_component_update_bits(component,
  455. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  456. snd_soc_component_update_bits(component,
  457. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  458. snd_soc_component_update_bits(component,
  459. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  460. }
  461. return 0;
  462. }
  463. /*
  464. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  465. * @component: handle to snd_soc_component *
  466. *
  467. * return wcd938x_mbhc handle or error code in case of failure
  468. */
  469. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  470. {
  471. struct wcd938x_priv *wcd938x;
  472. if (!component) {
  473. pr_err("%s: Invalid params, NULL component\n", __func__);
  474. return NULL;
  475. }
  476. wcd938x = snd_soc_component_get_drvdata(component);
  477. if (!wcd938x) {
  478. pr_err("%s: wcd938x is NULL\n", __func__);
  479. return NULL;
  480. }
  481. return wcd938x->mbhc;
  482. }
  483. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  484. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  485. struct snd_kcontrol *kcontrol,
  486. int event)
  487. {
  488. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  489. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  490. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  491. w->name, event);
  492. switch (event) {
  493. case SND_SOC_DAPM_PRE_PMU:
  494. wcd938x_rx_clk_enable(component);
  495. snd_soc_component_update_bits(component,
  496. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  497. snd_soc_component_update_bits(component,
  498. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  499. snd_soc_component_update_bits(component,
  500. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  501. break;
  502. case SND_SOC_DAPM_POST_PMU:
  503. snd_soc_component_update_bits(component,
  504. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  505. if (wcd938x->comp1_enable) {
  506. snd_soc_component_update_bits(component,
  507. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  508. /* 5msec compander delay as per HW requirement */
  509. if (!wcd938x->comp2_enable ||
  510. (snd_soc_component_read32(component,
  511. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  512. usleep_range(5000, 5010);
  513. snd_soc_component_update_bits(component,
  514. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  515. } else {
  516. snd_soc_component_update_bits(component,
  517. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  518. 0x02, 0x00);
  519. snd_soc_component_update_bits(component,
  520. WCD938X_HPH_L_EN, 0x20, 0x20);
  521. }
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. snd_soc_component_update_bits(component,
  525. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  526. 0x0F, 0x01);
  527. break;
  528. }
  529. return 0;
  530. }
  531. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  532. struct snd_kcontrol *kcontrol,
  533. int event)
  534. {
  535. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  536. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  537. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  538. w->name, event);
  539. switch (event) {
  540. case SND_SOC_DAPM_PRE_PMU:
  541. wcd938x_rx_clk_enable(component);
  542. snd_soc_component_update_bits(component,
  543. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  544. snd_soc_component_update_bits(component,
  545. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  546. snd_soc_component_update_bits(component,
  547. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  548. break;
  549. case SND_SOC_DAPM_POST_PMU:
  550. snd_soc_component_update_bits(component,
  551. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  552. if (wcd938x->comp2_enable) {
  553. snd_soc_component_update_bits(component,
  554. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  555. /* 5msec compander delay as per HW requirement */
  556. if (!wcd938x->comp1_enable ||
  557. (snd_soc_component_read32(component,
  558. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  559. usleep_range(5000, 5010);
  560. snd_soc_component_update_bits(component,
  561. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  562. } else {
  563. snd_soc_component_update_bits(component,
  564. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  565. 0x01, 0x00);
  566. snd_soc_component_update_bits(component,
  567. WCD938X_HPH_R_EN, 0x20, 0x20);
  568. }
  569. break;
  570. case SND_SOC_DAPM_POST_PMD:
  571. snd_soc_component_update_bits(component,
  572. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  573. 0x0F, 0x01);
  574. break;
  575. }
  576. return 0;
  577. }
  578. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  579. struct snd_kcontrol *kcontrol,
  580. int event)
  581. {
  582. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  583. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  584. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  585. w->name, event);
  586. switch (event) {
  587. case SND_SOC_DAPM_PRE_PMU:
  588. wcd938x_rx_clk_enable(component);
  589. wcd938x->ear_rx_path =
  590. snd_soc_component_read32(
  591. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  592. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  593. snd_soc_component_update_bits(component,
  594. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  595. snd_soc_component_update_bits(component,
  596. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  597. snd_soc_component_update_bits(component,
  598. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  599. snd_soc_component_update_bits(component,
  600. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  601. } else {
  602. snd_soc_component_update_bits(component,
  603. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  604. snd_soc_component_update_bits(component,
  605. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  606. snd_soc_component_update_bits(component,
  607. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  608. }
  609. /* 5 msec delay as per HW requirement */
  610. usleep_range(5000, 5010);
  611. if (wcd938x->flyback_cur_det_disable == 0)
  612. snd_soc_component_update_bits(component,
  613. WCD938X_FLYBACK_EN,
  614. 0x04, 0x00);
  615. wcd938x->flyback_cur_det_disable++;
  616. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  617. WCD_CLSH_EVENT_PRE_DAC,
  618. WCD_CLSH_STATE_EAR,
  619. wcd938x->hph_mode);
  620. break;
  621. case SND_SOC_DAPM_POST_PMD:
  622. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  623. snd_soc_component_update_bits(component,
  624. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  625. snd_soc_component_update_bits(component,
  626. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  627. } else {
  628. snd_soc_component_update_bits(component,
  629. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  630. snd_soc_component_update_bits(component,
  631. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  632. snd_soc_component_update_bits(component,
  633. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x00);
  634. }
  635. snd_soc_component_update_bits(component,
  636. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  637. snd_soc_component_update_bits(component,
  638. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  639. break;
  640. };
  641. return 0;
  642. }
  643. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  644. struct snd_kcontrol *kcontrol,
  645. int event)
  646. {
  647. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  648. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  649. int ret = 0;
  650. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  651. w->name, event);
  652. switch (event) {
  653. case SND_SOC_DAPM_PRE_PMU:
  654. wcd938x_rx_clk_enable(component);
  655. snd_soc_component_update_bits(component,
  656. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  657. snd_soc_component_update_bits(component,
  658. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  659. snd_soc_component_update_bits(component,
  660. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  661. if (wcd938x->flyback_cur_det_disable == 0)
  662. snd_soc_component_update_bits(component,
  663. WCD938X_FLYBACK_EN,
  664. 0x04, 0x00);
  665. wcd938x->flyback_cur_det_disable++;
  666. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  667. WCD_CLSH_EVENT_PRE_DAC,
  668. WCD_CLSH_STATE_AUX,
  669. wcd938x->hph_mode);
  670. break;
  671. case SND_SOC_DAPM_POST_PMD:
  672. snd_soc_component_update_bits(component,
  673. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  674. break;
  675. };
  676. return ret;
  677. }
  678. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  679. struct snd_kcontrol *kcontrol,
  680. int event)
  681. {
  682. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  683. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  684. int ret = 0;
  685. int hph_mode = wcd938x->hph_mode;
  686. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  687. w->name, event);
  688. switch (event) {
  689. case SND_SOC_DAPM_PRE_PMU:
  690. if (wcd938x->ldoh)
  691. snd_soc_component_update_bits(component,
  692. WCD938X_LDOH_MODE,
  693. 0x80, 0x80);
  694. if (wcd938x->update_wcd_event)
  695. wcd938x->update_wcd_event(wcd938x->handle,
  696. WCD_BOLERO_EVT_RX_MUTE,
  697. (WCD_RX2 << 0x10 | 0x1));
  698. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  699. wcd938x->rx_swr_dev->dev_num,
  700. true);
  701. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  702. WCD_CLSH_EVENT_PRE_DAC,
  703. WCD_CLSH_STATE_HPHR,
  704. hph_mode);
  705. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  706. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  707. hph_mode == CLS_H_ULP) {
  708. snd_soc_component_update_bits(component,
  709. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  710. }
  711. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  712. 0x10, 0x10);
  713. wcd_clsh_set_hph_mode(component, hph_mode);
  714. /* 100 usec delay as per HW requirement */
  715. usleep_range(100, 110);
  716. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  717. snd_soc_component_update_bits(component,
  718. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x13);
  719. break;
  720. case SND_SOC_DAPM_POST_PMU:
  721. /*
  722. * 7ms sleep is required if compander is enabled as per
  723. * HW requirement. If compander is disabled, then
  724. * 20ms delay is required.
  725. */
  726. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  727. if (!wcd938x->comp2_enable)
  728. usleep_range(20000, 20100);
  729. else
  730. usleep_range(7000, 7100);
  731. if (hph_mode == CLS_H_LP ||
  732. hph_mode == CLS_H_LOHIFI ||
  733. hph_mode == CLS_H_ULP)
  734. snd_soc_component_update_bits(component,
  735. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  736. 0x00);
  737. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  738. }
  739. snd_soc_component_update_bits(component,
  740. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  741. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  742. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  743. snd_soc_component_update_bits(component,
  744. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  745. if (wcd938x->update_wcd_event)
  746. wcd938x->update_wcd_event(wcd938x->handle,
  747. WCD_BOLERO_EVT_RX_MUTE,
  748. (WCD_RX2 << 0x10));
  749. wcd_enable_irq(&wcd938x->irq_info,
  750. WCD938X_IRQ_HPHR_PDM_WD_INT);
  751. break;
  752. case SND_SOC_DAPM_PRE_PMD:
  753. if (wcd938x->update_wcd_event)
  754. wcd938x->update_wcd_event(wcd938x->handle,
  755. WCD_BOLERO_EVT_RX_MUTE,
  756. (WCD_RX2 << 0x10 | 0x1));
  757. wcd_disable_irq(&wcd938x->irq_info,
  758. WCD938X_IRQ_HPHR_PDM_WD_INT);
  759. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  760. wcd938x->update_wcd_event(wcd938x->handle,
  761. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  762. (WCD_RX2 << 0x10));
  763. /*
  764. * 7ms sleep is required if compander is enabled as per
  765. * HW requirement. If compander is disabled, then
  766. * 20ms delay is required.
  767. */
  768. if (!wcd938x->comp2_enable)
  769. usleep_range(20000, 20100);
  770. else
  771. usleep_range(7000, 7100);
  772. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  773. 0x40, 0x00);
  774. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  775. WCD_EVENT_PRE_HPHR_PA_OFF,
  776. &wcd938x->mbhc->wcd_mbhc);
  777. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  778. break;
  779. case SND_SOC_DAPM_POST_PMD:
  780. /*
  781. * 7ms sleep is required if compander is enabled as per
  782. * HW requirement. If compander is disabled, then
  783. * 20ms delay is required.
  784. */
  785. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  786. if (!wcd938x->comp2_enable)
  787. usleep_range(20000, 20100);
  788. else
  789. usleep_range(7000, 7100);
  790. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  791. }
  792. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  793. WCD_EVENT_POST_HPHR_PA_OFF,
  794. &wcd938x->mbhc->wcd_mbhc);
  795. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  796. 0x10, 0x00);
  797. snd_soc_component_update_bits(component,
  798. WCD938X_DIGITAL_PDM_WD_CTL1, 0x17, 0x00);
  799. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  800. WCD_CLSH_EVENT_POST_PA,
  801. WCD_CLSH_STATE_HPHR,
  802. hph_mode);
  803. if (wcd938x->ldoh)
  804. snd_soc_component_update_bits(component,
  805. WCD938X_LDOH_MODE,
  806. 0x80, 0x00);
  807. break;
  808. };
  809. return ret;
  810. }
  811. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  812. struct snd_kcontrol *kcontrol,
  813. int event)
  814. {
  815. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  816. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  817. int ret = 0;
  818. int hph_mode = wcd938x->hph_mode;
  819. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  820. w->name, event);
  821. switch (event) {
  822. case SND_SOC_DAPM_PRE_PMU:
  823. if (wcd938x->ldoh)
  824. snd_soc_component_update_bits(component,
  825. WCD938X_LDOH_MODE,
  826. 0x80, 0x80);
  827. if (wcd938x->update_wcd_event)
  828. wcd938x->update_wcd_event(wcd938x->handle,
  829. WCD_BOLERO_EVT_RX_MUTE,
  830. (WCD_RX1 << 0x10 | 0x01));
  831. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  832. wcd938x->rx_swr_dev->dev_num,
  833. true);
  834. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  835. WCD_CLSH_EVENT_PRE_DAC,
  836. WCD_CLSH_STATE_HPHL,
  837. hph_mode);
  838. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  839. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  840. hph_mode == CLS_H_ULP) {
  841. snd_soc_component_update_bits(component,
  842. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  843. }
  844. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  845. 0x20, 0x20);
  846. wcd_clsh_set_hph_mode(component, hph_mode);
  847. /* 100 usec delay as per HW requirement */
  848. usleep_range(100, 110);
  849. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  850. snd_soc_component_update_bits(component,
  851. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13);
  852. break;
  853. case SND_SOC_DAPM_POST_PMU:
  854. /*
  855. * 7ms sleep is required if compander is enabled as per
  856. * HW requirement. If compander is disabled, then
  857. * 20ms delay is required.
  858. */
  859. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  860. if (!wcd938x->comp1_enable)
  861. usleep_range(20000, 20100);
  862. else
  863. usleep_range(7000, 7100);
  864. if (hph_mode == CLS_H_LP ||
  865. hph_mode == CLS_H_LOHIFI ||
  866. hph_mode == CLS_H_ULP)
  867. snd_soc_component_update_bits(component,
  868. WCD938X_HPH_REFBUFF_LP_CTL,
  869. 0x01, 0x00);
  870. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  871. }
  872. snd_soc_component_update_bits(component,
  873. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  874. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  875. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  876. snd_soc_component_update_bits(component,
  877. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  878. if (wcd938x->update_wcd_event)
  879. wcd938x->update_wcd_event(wcd938x->handle,
  880. WCD_BOLERO_EVT_RX_MUTE,
  881. (WCD_RX1 << 0x10));
  882. wcd_enable_irq(&wcd938x->irq_info,
  883. WCD938X_IRQ_HPHL_PDM_WD_INT);
  884. break;
  885. case SND_SOC_DAPM_PRE_PMD:
  886. if (wcd938x->update_wcd_event)
  887. wcd938x->update_wcd_event(wcd938x->handle,
  888. WCD_BOLERO_EVT_RX_MUTE,
  889. (WCD_RX1 << 0x10 | 0x1));
  890. wcd_disable_irq(&wcd938x->irq_info,
  891. WCD938X_IRQ_HPHL_PDM_WD_INT);
  892. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  893. wcd938x->update_wcd_event(wcd938x->handle,
  894. WCD_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  895. (WCD_RX1 << 0x10));
  896. /*
  897. * 7ms sleep is required if compander is enabled as per
  898. * HW requirement. If compander is disabled, then
  899. * 20ms delay is required.
  900. */
  901. if (!wcd938x->comp1_enable)
  902. usleep_range(20000, 20100);
  903. else
  904. usleep_range(7000, 7100);
  905. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  906. 0x80, 0x00);
  907. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  908. WCD_EVENT_PRE_HPHL_PA_OFF,
  909. &wcd938x->mbhc->wcd_mbhc);
  910. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  911. break;
  912. case SND_SOC_DAPM_POST_PMD:
  913. /*
  914. * 7ms sleep is required if compander is enabled as per
  915. * HW requirement. If compander is disabled, then
  916. * 20ms delay is required.
  917. */
  918. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  919. if (!wcd938x->comp1_enable)
  920. usleep_range(21000, 21100);
  921. else
  922. usleep_range(7000, 7100);
  923. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  924. }
  925. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  926. WCD_EVENT_POST_HPHL_PA_OFF,
  927. &wcd938x->mbhc->wcd_mbhc);
  928. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  929. 0x20, 0x00);
  930. snd_soc_component_update_bits(component,
  931. WCD938X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00);
  932. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  933. WCD_CLSH_EVENT_POST_PA,
  934. WCD_CLSH_STATE_HPHL,
  935. hph_mode);
  936. if (wcd938x->ldoh)
  937. snd_soc_component_update_bits(component,
  938. WCD938X_LDOH_MODE,
  939. 0x80, 0x00);
  940. break;
  941. };
  942. return ret;
  943. }
  944. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  945. struct snd_kcontrol *kcontrol,
  946. int event)
  947. {
  948. struct snd_soc_component *component =
  949. snd_soc_dapm_to_component(w->dapm);
  950. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  951. int hph_mode = wcd938x->hph_mode;
  952. int ret = 0;
  953. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  954. w->name, event);
  955. switch (event) {
  956. case SND_SOC_DAPM_PRE_PMU:
  957. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  958. wcd938x->rx_swr_dev->dev_num,
  959. true);
  960. snd_soc_component_update_bits(component,
  961. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05);
  962. break;
  963. case SND_SOC_DAPM_POST_PMU:
  964. /* 1 msec delay as per HW requirement */
  965. usleep_range(1000, 1010);
  966. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  967. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  968. snd_soc_component_update_bits(component,
  969. WCD938X_ANA_RX_SUPPLIES,
  970. 0x02, 0x02);
  971. if (wcd938x->update_wcd_event)
  972. wcd938x->update_wcd_event(wcd938x->handle,
  973. WCD_BOLERO_EVT_RX_MUTE,
  974. (WCD_RX3 << 0x10));
  975. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  976. break;
  977. case SND_SOC_DAPM_PRE_PMD:
  978. wcd_disable_irq(&wcd938x->irq_info,
  979. WCD938X_IRQ_AUX_PDM_WD_INT);
  980. if (wcd938x->update_wcd_event)
  981. wcd938x->update_wcd_event(wcd938x->handle,
  982. WCD_BOLERO_EVT_RX_MUTE,
  983. (WCD_RX3 << 0x10 | 0x1));
  984. break;
  985. case SND_SOC_DAPM_POST_PMD:
  986. /* 1 msec delay as per HW requirement */
  987. usleep_range(1000, 1010);
  988. snd_soc_component_update_bits(component,
  989. WCD938X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00);
  990. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  991. WCD_CLSH_EVENT_POST_PA,
  992. WCD_CLSH_STATE_AUX,
  993. hph_mode);
  994. wcd938x->flyback_cur_det_disable--;
  995. if (wcd938x->flyback_cur_det_disable == 0)
  996. snd_soc_component_update_bits(component,
  997. WCD938X_FLYBACK_EN,
  998. 0x04, 0x04);
  999. break;
  1000. };
  1001. return ret;
  1002. }
  1003. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1004. struct snd_kcontrol *kcontrol,
  1005. int event)
  1006. {
  1007. struct snd_soc_component *component =
  1008. snd_soc_dapm_to_component(w->dapm);
  1009. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1010. int hph_mode = wcd938x->hph_mode;
  1011. int ret = 0;
  1012. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1013. w->name, event);
  1014. switch (event) {
  1015. case SND_SOC_DAPM_PRE_PMU:
  1016. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1017. wcd938x->rx_swr_dev->dev_num,
  1018. true);
  1019. /*
  1020. * Enable watchdog interrupt for HPHL or AUX
  1021. * depending on mux value
  1022. */
  1023. wcd938x->ear_rx_path =
  1024. snd_soc_component_read32(
  1025. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1026. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1027. snd_soc_component_update_bits(component,
  1028. WCD938X_DIGITAL_PDM_WD_CTL2,
  1029. 0x05, 0x05);
  1030. else
  1031. snd_soc_component_update_bits(component,
  1032. WCD938X_DIGITAL_PDM_WD_CTL0,
  1033. 0x17, 0x13);
  1034. if (!wcd938x->comp1_enable)
  1035. snd_soc_component_update_bits(component,
  1036. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1037. break;
  1038. case SND_SOC_DAPM_POST_PMU:
  1039. /* 6 msec delay as per HW requirement */
  1040. usleep_range(6000, 6010);
  1041. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1042. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1043. snd_soc_component_update_bits(component,
  1044. WCD938X_ANA_RX_SUPPLIES,
  1045. 0x02, 0x02);
  1046. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1047. if (wcd938x->update_wcd_event)
  1048. wcd938x->update_wcd_event(wcd938x->handle,
  1049. WCD_BOLERO_EVT_RX_MUTE,
  1050. (WCD_RX3 << 0x10));
  1051. wcd_enable_irq(&wcd938x->irq_info,
  1052. WCD938X_IRQ_AUX_PDM_WD_INT);
  1053. } else {
  1054. if (wcd938x->update_wcd_event)
  1055. wcd938x->update_wcd_event(wcd938x->handle,
  1056. WCD_BOLERO_EVT_RX_MUTE,
  1057. (WCD_RX1 << 0x10));
  1058. wcd_enable_irq(&wcd938x->irq_info,
  1059. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1060. }
  1061. break;
  1062. case SND_SOC_DAPM_PRE_PMD:
  1063. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1064. wcd_disable_irq(&wcd938x->irq_info,
  1065. WCD938X_IRQ_AUX_PDM_WD_INT);
  1066. if (wcd938x->update_wcd_event)
  1067. wcd938x->update_wcd_event(wcd938x->handle,
  1068. WCD_BOLERO_EVT_RX_MUTE,
  1069. (WCD_RX3 << 0x10 | 0x1));
  1070. } else {
  1071. wcd_disable_irq(&wcd938x->irq_info,
  1072. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1073. if (wcd938x->update_wcd_event)
  1074. wcd938x->update_wcd_event(wcd938x->handle,
  1075. WCD_BOLERO_EVT_RX_MUTE,
  1076. (WCD_RX1 << 0x10 | 0x1));
  1077. }
  1078. break;
  1079. case SND_SOC_DAPM_POST_PMD:
  1080. if (!wcd938x->comp1_enable)
  1081. snd_soc_component_update_bits(component,
  1082. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1083. /* 7 msec delay as per HW requirement */
  1084. usleep_range(7000, 7010);
  1085. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1086. snd_soc_component_update_bits(component,
  1087. WCD938X_DIGITAL_PDM_WD_CTL2,
  1088. 0x05, 0x00);
  1089. else
  1090. snd_soc_component_update_bits(component,
  1091. WCD938X_DIGITAL_PDM_WD_CTL0,
  1092. 0x17, 0x00);
  1093. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1094. WCD_CLSH_EVENT_POST_PA,
  1095. WCD_CLSH_STATE_EAR,
  1096. hph_mode);
  1097. wcd938x->flyback_cur_det_disable--;
  1098. if (wcd938x->flyback_cur_det_disable == 0)
  1099. snd_soc_component_update_bits(component,
  1100. WCD938X_FLYBACK_EN,
  1101. 0x04, 0x04);
  1102. break;
  1103. };
  1104. return ret;
  1105. }
  1106. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1107. struct snd_kcontrol *kcontrol,
  1108. int event)
  1109. {
  1110. struct snd_soc_component *component =
  1111. snd_soc_dapm_to_component(w->dapm);
  1112. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1113. int mode = wcd938x->hph_mode;
  1114. int ret = 0;
  1115. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1116. w->name, event);
  1117. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1118. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1119. wcd938x_rx_connect_port(component, CLSH,
  1120. SND_SOC_DAPM_EVENT_ON(event));
  1121. }
  1122. if (SND_SOC_DAPM_EVENT_OFF(event))
  1123. ret = swr_slvdev_datapath_control(
  1124. wcd938x->rx_swr_dev,
  1125. wcd938x->rx_swr_dev->dev_num,
  1126. false);
  1127. return ret;
  1128. }
  1129. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1130. struct snd_kcontrol *kcontrol,
  1131. int event)
  1132. {
  1133. struct snd_soc_component *component =
  1134. snd_soc_dapm_to_component(w->dapm);
  1135. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1136. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1137. w->name, event);
  1138. switch (event) {
  1139. case SND_SOC_DAPM_PRE_PMU:
  1140. wcd938x_rx_connect_port(component, HPH_L, true);
  1141. if (wcd938x->comp1_enable)
  1142. wcd938x_rx_connect_port(component, COMP_L, true);
  1143. break;
  1144. case SND_SOC_DAPM_POST_PMD:
  1145. wcd938x_rx_connect_port(component, HPH_L, false);
  1146. if (wcd938x->comp1_enable)
  1147. wcd938x_rx_connect_port(component, COMP_L, false);
  1148. wcd938x_rx_clk_disable(component);
  1149. snd_soc_component_update_bits(component,
  1150. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1151. 0x01, 0x00);
  1152. break;
  1153. };
  1154. return 0;
  1155. }
  1156. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1157. struct snd_kcontrol *kcontrol, int event)
  1158. {
  1159. struct snd_soc_component *component =
  1160. snd_soc_dapm_to_component(w->dapm);
  1161. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1162. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1163. w->name, event);
  1164. switch (event) {
  1165. case SND_SOC_DAPM_PRE_PMU:
  1166. wcd938x_rx_connect_port(component, HPH_R, true);
  1167. if (wcd938x->comp2_enable)
  1168. wcd938x_rx_connect_port(component, COMP_R, true);
  1169. break;
  1170. case SND_SOC_DAPM_POST_PMD:
  1171. wcd938x_rx_connect_port(component, HPH_R, false);
  1172. if (wcd938x->comp2_enable)
  1173. wcd938x_rx_connect_port(component, COMP_R, false);
  1174. wcd938x_rx_clk_disable(component);
  1175. snd_soc_component_update_bits(component,
  1176. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1177. 0x02, 0x00);
  1178. break;
  1179. };
  1180. return 0;
  1181. }
  1182. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1183. struct snd_kcontrol *kcontrol,
  1184. int event)
  1185. {
  1186. struct snd_soc_component *component =
  1187. snd_soc_dapm_to_component(w->dapm);
  1188. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1189. w->name, event);
  1190. switch (event) {
  1191. case SND_SOC_DAPM_PRE_PMU:
  1192. wcd938x_rx_connect_port(component, LO, true);
  1193. break;
  1194. case SND_SOC_DAPM_POST_PMD:
  1195. wcd938x_rx_connect_port(component, LO, false);
  1196. /* 6 msec delay as per HW requirement */
  1197. usleep_range(6000, 6010);
  1198. wcd938x_rx_clk_disable(component);
  1199. snd_soc_component_update_bits(component,
  1200. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1201. break;
  1202. }
  1203. return 0;
  1204. }
  1205. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1206. struct snd_kcontrol *kcontrol,
  1207. int event)
  1208. {
  1209. struct snd_soc_component *component =
  1210. snd_soc_dapm_to_component(w->dapm);
  1211. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1212. u16 dmic_clk_reg, dmic_clk_en_reg;
  1213. s32 *dmic_clk_cnt;
  1214. u8 dmic_ctl_shift = 0;
  1215. u8 dmic_clk_shift = 0;
  1216. u8 dmic_clk_mask = 0;
  1217. u16 dmic2_left_en = 0;
  1218. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1219. w->name, event);
  1220. switch (w->shift) {
  1221. case 0:
  1222. case 1:
  1223. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1224. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1225. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1226. dmic_clk_mask = 0x0F;
  1227. dmic_clk_shift = 0x00;
  1228. dmic_ctl_shift = 0x00;
  1229. break;
  1230. case 2:
  1231. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1232. case 3:
  1233. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1234. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1235. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1236. dmic_clk_mask = 0xF0;
  1237. dmic_clk_shift = 0x04;
  1238. dmic_ctl_shift = 0x01;
  1239. break;
  1240. case 4:
  1241. case 5:
  1242. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1243. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1244. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1245. dmic_clk_mask = 0x0F;
  1246. dmic_clk_shift = 0x00;
  1247. dmic_ctl_shift = 0x02;
  1248. break;
  1249. case 6:
  1250. case 7:
  1251. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1252. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1253. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1254. dmic_clk_mask = 0xF0;
  1255. dmic_clk_shift = 0x04;
  1256. dmic_ctl_shift = 0x03;
  1257. break;
  1258. default:
  1259. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  1260. __func__);
  1261. return -EINVAL;
  1262. };
  1263. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1264. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1265. switch (event) {
  1266. case SND_SOC_DAPM_PRE_PMU:
  1267. snd_soc_component_update_bits(component,
  1268. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1269. (0x01 << dmic_ctl_shift), 0x00);
  1270. /* 250us sleep as per HW requirement */
  1271. usleep_range(250, 260);
  1272. if (dmic2_left_en)
  1273. snd_soc_component_update_bits(component,
  1274. dmic2_left_en, 0x80, 0x80);
  1275. /* Setting DMIC clock rate to 2.4MHz */
  1276. snd_soc_component_update_bits(component,
  1277. dmic_clk_reg, dmic_clk_mask,
  1278. (0x03 << dmic_clk_shift));
  1279. snd_soc_component_update_bits(component,
  1280. dmic_clk_en_reg, 0x08, 0x08);
  1281. /* enable clock scaling */
  1282. snd_soc_component_update_bits(component,
  1283. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1284. wcd938x_tx_connect_port(component, DMIC0 + (w->shift),
  1285. SWR_CLK_RATE_2P4MHZ, true);
  1286. break;
  1287. case SND_SOC_DAPM_POST_PMD:
  1288. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1289. false);
  1290. snd_soc_component_update_bits(component,
  1291. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1292. (0x01 << dmic_ctl_shift),
  1293. (0x01 << dmic_ctl_shift));
  1294. if (dmic2_left_en)
  1295. snd_soc_component_update_bits(component,
  1296. dmic2_left_en, 0x80, 0x00);
  1297. snd_soc_component_update_bits(component,
  1298. dmic_clk_en_reg, 0x08, 0x00);
  1299. break;
  1300. };
  1301. return 0;
  1302. }
  1303. /*
  1304. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1305. * @micb_mv: micbias in mv
  1306. *
  1307. * return register value converted
  1308. */
  1309. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1310. {
  1311. /* min micbias voltage is 1V and maximum is 2.85V */
  1312. if (micb_mv < 1000 || micb_mv > 2850) {
  1313. pr_err("%s: unsupported micbias voltage\n", __func__);
  1314. return -EINVAL;
  1315. }
  1316. return (micb_mv - 1000) / 50;
  1317. }
  1318. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1319. /*
  1320. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1321. * @component: handle to snd_soc_component *
  1322. * @req_volt: micbias voltage to be set
  1323. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1324. *
  1325. * return 0 if adjustment is success or error code in case of failure
  1326. */
  1327. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1328. int req_volt, int micb_num)
  1329. {
  1330. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1331. int cur_vout_ctl, req_vout_ctl;
  1332. int micb_reg, micb_val, micb_en;
  1333. int ret = 0;
  1334. switch (micb_num) {
  1335. case MIC_BIAS_1:
  1336. micb_reg = WCD938X_ANA_MICB1;
  1337. break;
  1338. case MIC_BIAS_2:
  1339. micb_reg = WCD938X_ANA_MICB2;
  1340. break;
  1341. case MIC_BIAS_3:
  1342. micb_reg = WCD938X_ANA_MICB3;
  1343. break;
  1344. case MIC_BIAS_4:
  1345. micb_reg = WCD938X_ANA_MICB4;
  1346. break;
  1347. default:
  1348. return -EINVAL;
  1349. }
  1350. mutex_lock(&wcd938x->micb_lock);
  1351. /*
  1352. * If requested micbias voltage is same as current micbias
  1353. * voltage, then just return. Otherwise, adjust voltage as
  1354. * per requested value. If micbias is already enabled, then
  1355. * to avoid slow micbias ramp-up or down enable pull-up
  1356. * momentarily, change the micbias value and then re-enable
  1357. * micbias.
  1358. */
  1359. micb_val = snd_soc_component_read32(component, micb_reg);
  1360. micb_en = (micb_val & 0xC0) >> 6;
  1361. cur_vout_ctl = micb_val & 0x3F;
  1362. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1363. if (req_vout_ctl < 0) {
  1364. ret = -EINVAL;
  1365. goto exit;
  1366. }
  1367. if (cur_vout_ctl == req_vout_ctl) {
  1368. ret = 0;
  1369. goto exit;
  1370. }
  1371. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1372. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1373. req_volt, micb_en);
  1374. if (micb_en == 0x1)
  1375. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1376. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1377. if (micb_en == 0x1) {
  1378. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1379. /*
  1380. * Add 2ms delay as per HW requirement after enabling
  1381. * micbias
  1382. */
  1383. usleep_range(2000, 2100);
  1384. }
  1385. exit:
  1386. mutex_unlock(&wcd938x->micb_lock);
  1387. return ret;
  1388. }
  1389. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1390. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1391. struct snd_kcontrol *kcontrol,
  1392. int event)
  1393. {
  1394. struct snd_soc_component *component =
  1395. snd_soc_dapm_to_component(w->dapm);
  1396. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1397. int ret = 0;
  1398. int bank = 0;
  1399. u8 mode = 0;
  1400. int i = 0;
  1401. int rate = 0;
  1402. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1403. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1404. switch (event) {
  1405. case SND_SOC_DAPM_PRE_PMU:
  1406. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1407. if (test_bit(WCD_ADC1, &wcd938x->status_mask))
  1408. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1409. if (test_bit(WCD_ADC2, &wcd938x->status_mask))
  1410. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1411. if (test_bit(WCD_ADC3, &wcd938x->status_mask))
  1412. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1413. if (test_bit(WCD_ADC4, &wcd938x->status_mask))
  1414. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1415. if (mode != 0) {
  1416. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1417. if (mode & (1 << i)) {
  1418. i++;
  1419. break;
  1420. }
  1421. }
  1422. }
  1423. rate = wcd938x_get_clk_rate(i);
  1424. wcd938x_set_swr_clk_rate(component, rate, bank);
  1425. }
  1426. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1427. wcd938x->tx_swr_dev->dev_num,
  1428. true);
  1429. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1430. /* Copy clk settings to active bank */
  1431. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1432. }
  1433. break;
  1434. case SND_SOC_DAPM_POST_PMD:
  1435. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1436. rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
  1437. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1438. }
  1439. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1440. wcd938x->tx_swr_dev->dev_num,
  1441. false);
  1442. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1443. wcd938x_set_swr_clk_rate(component, rate, bank);
  1444. break;
  1445. };
  1446. return ret;
  1447. }
  1448. static int wcd938x_get_adc_mode(int val)
  1449. {
  1450. int ret = 0;
  1451. switch (val) {
  1452. case ADC_MODE_INVALID:
  1453. ret = ADC_MODE_VAL_NORMAL;
  1454. break;
  1455. case ADC_MODE_HIFI:
  1456. ret = ADC_MODE_VAL_HIFI;
  1457. break;
  1458. case ADC_MODE_LO_HIF:
  1459. ret = ADC_MODE_VAL_LO_HIF;
  1460. break;
  1461. case ADC_MODE_NORMAL:
  1462. ret = ADC_MODE_VAL_NORMAL;
  1463. break;
  1464. case ADC_MODE_LP:
  1465. ret = ADC_MODE_VAL_LP;
  1466. break;
  1467. case ADC_MODE_ULP1:
  1468. ret = ADC_MODE_VAL_ULP1;
  1469. break;
  1470. case ADC_MODE_ULP2:
  1471. ret = ADC_MODE_VAL_ULP2;
  1472. break;
  1473. default:
  1474. ret = -EINVAL;
  1475. pr_err("%s: invalid ADC mode value %d\n", __func__, val);
  1476. break;
  1477. }
  1478. return ret;
  1479. }
  1480. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1481. struct snd_kcontrol *kcontrol,
  1482. int event){
  1483. struct snd_soc_component *component =
  1484. snd_soc_dapm_to_component(w->dapm);
  1485. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1486. int clk_rate = 0;
  1487. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1488. w->name, event);
  1489. switch (event) {
  1490. case SND_SOC_DAPM_PRE_PMU:
  1491. snd_soc_component_update_bits(component,
  1492. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1493. snd_soc_component_update_bits(component,
  1494. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1495. set_bit(w->shift, &wcd938x->status_mask);
  1496. clk_rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift]);
  1497. /* Enable BCS for Headset mic */
  1498. if (w->shift == 1 && !(snd_soc_component_read32(component,
  1499. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1500. if (!wcd938x->bcs_dis)
  1501. wcd938x_tx_connect_port(component, MBHC,
  1502. SWR_CLK_RATE_4P8MHZ, true);
  1503. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1504. }
  1505. wcd938x_tx_connect_port(component, ADC1 + (w->shift), clk_rate,
  1506. true);
  1507. break;
  1508. case SND_SOC_DAPM_POST_PMD:
  1509. wcd938x_tx_connect_port(component, ADC1 + (w->shift), 0, false);
  1510. if (w->shift == 1 &&
  1511. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1512. if (!wcd938x->bcs_dis)
  1513. wcd938x_tx_connect_port(component, MBHC, 0,
  1514. false);
  1515. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1516. }
  1517. snd_soc_component_update_bits(component,
  1518. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1519. clear_bit(w->shift, &wcd938x->status_mask);
  1520. break;
  1521. };
  1522. return 0;
  1523. }
  1524. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1525. bool bcs_disable)
  1526. {
  1527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1528. if (wcd938x->update_wcd_event) {
  1529. if (bcs_disable)
  1530. wcd938x->update_wcd_event(wcd938x->handle,
  1531. WCD_BOLERO_EVT_BCS_CLK_OFF, 0);
  1532. else
  1533. wcd938x->update_wcd_event(wcd938x->handle,
  1534. WCD_BOLERO_EVT_BCS_CLK_OFF, 1);
  1535. }
  1536. }
  1537. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1538. int channel, int mode)
  1539. {
  1540. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1541. int ret = 0;
  1542. switch (channel) {
  1543. case 0:
  1544. reg = WCD938X_ANA_TX_CH2;
  1545. mask = 0x40;
  1546. break;
  1547. case 1:
  1548. reg = WCD938X_ANA_TX_CH2;
  1549. mask = 0x20;
  1550. break;
  1551. case 2:
  1552. reg = WCD938X_ANA_TX_CH4;
  1553. mask = 0x40;
  1554. break;
  1555. case 3:
  1556. reg = WCD938X_ANA_TX_CH4;
  1557. mask = 0x20;
  1558. break;
  1559. default:
  1560. pr_err("%s: Invalid channel num %d\n", __func__, channel);
  1561. ret = -EINVAL;
  1562. break;
  1563. }
  1564. if (!mode)
  1565. val = 0x00;
  1566. else
  1567. val = mask;
  1568. if (!ret)
  1569. snd_soc_component_update_bits(component, reg, mask, val);
  1570. return ret;
  1571. }
  1572. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1573. struct snd_kcontrol *kcontrol, int event)
  1574. {
  1575. struct snd_soc_component *component =
  1576. snd_soc_dapm_to_component(w->dapm);
  1577. int mode;
  1578. int ret = 0;
  1579. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1580. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1581. w->name, event);
  1582. switch (event) {
  1583. case SND_SOC_DAPM_PRE_PMU:
  1584. snd_soc_component_update_bits(component,
  1585. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1586. snd_soc_component_update_bits(component,
  1587. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1588. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1589. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1590. if (mode < 0) {
  1591. dev_info(component->dev,
  1592. "%s: invalid mode, setting to normal mode\n",
  1593. __func__);
  1594. mode = ADC_MODE_VAL_NORMAL;
  1595. }
  1596. switch (w->shift) {
  1597. case 0:
  1598. snd_soc_component_update_bits(component,
  1599. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1600. mode);
  1601. snd_soc_component_update_bits(component,
  1602. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1603. break;
  1604. case 1:
  1605. snd_soc_component_update_bits(component,
  1606. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1607. mode << 4);
  1608. snd_soc_component_update_bits(component,
  1609. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1610. break;
  1611. case 2:
  1612. snd_soc_component_update_bits(component,
  1613. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1614. mode);
  1615. snd_soc_component_update_bits(component,
  1616. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1617. break;
  1618. case 3:
  1619. snd_soc_component_update_bits(component,
  1620. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1621. mode << 4);
  1622. snd_soc_component_update_bits(component,
  1623. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1624. break;
  1625. default:
  1626. break;
  1627. }
  1628. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1629. break;
  1630. case SND_SOC_DAPM_POST_PMD:
  1631. switch (w->shift) {
  1632. case 0:
  1633. snd_soc_component_update_bits(component,
  1634. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1635. 0x00);
  1636. snd_soc_component_update_bits(component,
  1637. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1638. break;
  1639. case 1:
  1640. snd_soc_component_update_bits(component,
  1641. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1642. 0x00);
  1643. snd_soc_component_update_bits(component,
  1644. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1645. break;
  1646. case 2:
  1647. snd_soc_component_update_bits(component,
  1648. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1649. 0x00);
  1650. snd_soc_component_update_bits(component,
  1651. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1652. break;
  1653. case 3:
  1654. snd_soc_component_update_bits(component,
  1655. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1656. 0x00);
  1657. snd_soc_component_update_bits(component,
  1658. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1659. break;
  1660. default:
  1661. break;
  1662. }
  1663. snd_soc_component_update_bits(component,
  1664. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1665. break;
  1666. };
  1667. return ret;
  1668. }
  1669. int wcd938x_micbias_control(struct snd_soc_component *component,
  1670. int micb_num, int req, bool is_dapm)
  1671. {
  1672. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1673. int micb_index = micb_num - 1;
  1674. u16 micb_reg;
  1675. int pre_off_event = 0, post_off_event = 0;
  1676. int post_on_event = 0, post_dapm_off = 0;
  1677. int post_dapm_on = 0;
  1678. int ret = 0;
  1679. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1680. dev_err(component->dev,
  1681. "%s: Invalid micbias index, micb_ind:%d\n",
  1682. __func__, micb_index);
  1683. return -EINVAL;
  1684. }
  1685. if (NULL == wcd938x) {
  1686. dev_err(component->dev,
  1687. "%s: wcd938x private data is NULL\n", __func__);
  1688. return -EINVAL;
  1689. }
  1690. switch (micb_num) {
  1691. case MIC_BIAS_1:
  1692. micb_reg = WCD938X_ANA_MICB1;
  1693. break;
  1694. case MIC_BIAS_2:
  1695. micb_reg = WCD938X_ANA_MICB2;
  1696. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1697. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1698. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1699. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1700. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1701. break;
  1702. case MIC_BIAS_3:
  1703. micb_reg = WCD938X_ANA_MICB3;
  1704. break;
  1705. case MIC_BIAS_4:
  1706. micb_reg = WCD938X_ANA_MICB4;
  1707. break;
  1708. default:
  1709. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1710. __func__, micb_num);
  1711. return -EINVAL;
  1712. };
  1713. mutex_lock(&wcd938x->micb_lock);
  1714. switch (req) {
  1715. case MICB_PULLUP_ENABLE:
  1716. if (!wcd938x->dev_up) {
  1717. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1718. __func__, req);
  1719. ret = -ENODEV;
  1720. goto done;
  1721. }
  1722. wcd938x->pullup_ref[micb_index]++;
  1723. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1724. (wcd938x->micb_ref[micb_index] == 0))
  1725. snd_soc_component_update_bits(component, micb_reg,
  1726. 0xC0, 0x80);
  1727. break;
  1728. case MICB_PULLUP_DISABLE:
  1729. if (wcd938x->pullup_ref[micb_index] > 0)
  1730. wcd938x->pullup_ref[micb_index]--;
  1731. if (!wcd938x->dev_up) {
  1732. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1733. __func__, req);
  1734. ret = -ENODEV;
  1735. goto done;
  1736. }
  1737. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1738. (wcd938x->micb_ref[micb_index] == 0))
  1739. snd_soc_component_update_bits(component, micb_reg,
  1740. 0xC0, 0x00);
  1741. break;
  1742. case MICB_ENABLE:
  1743. if (!wcd938x->dev_up) {
  1744. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1745. __func__, req);
  1746. ret = -ENODEV;
  1747. goto done;
  1748. }
  1749. wcd938x->micb_ref[micb_index]++;
  1750. if (wcd938x->micb_ref[micb_index] == 1) {
  1751. snd_soc_component_update_bits(component,
  1752. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1753. snd_soc_component_update_bits(component,
  1754. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1755. snd_soc_component_update_bits(component,
  1756. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1757. snd_soc_component_update_bits(component,
  1758. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1759. snd_soc_component_update_bits(component,
  1760. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1761. snd_soc_component_update_bits(component,
  1762. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1763. snd_soc_component_update_bits(component,
  1764. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1765. snd_soc_component_update_bits(component,
  1766. micb_reg, 0xC0, 0x40);
  1767. if (post_on_event)
  1768. blocking_notifier_call_chain(
  1769. &wcd938x->mbhc->notifier,
  1770. post_on_event,
  1771. &wcd938x->mbhc->wcd_mbhc);
  1772. }
  1773. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1774. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1775. post_dapm_on,
  1776. &wcd938x->mbhc->wcd_mbhc);
  1777. break;
  1778. case MICB_DISABLE:
  1779. if (wcd938x->micb_ref[micb_index] > 0)
  1780. wcd938x->micb_ref[micb_index]--;
  1781. if (!wcd938x->dev_up) {
  1782. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1783. __func__, req);
  1784. ret = -ENODEV;
  1785. goto done;
  1786. }
  1787. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1788. (wcd938x->pullup_ref[micb_index] > 0))
  1789. snd_soc_component_update_bits(component, micb_reg,
  1790. 0xC0, 0x80);
  1791. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1792. (wcd938x->pullup_ref[micb_index] == 0)) {
  1793. if (pre_off_event && wcd938x->mbhc)
  1794. blocking_notifier_call_chain(
  1795. &wcd938x->mbhc->notifier,
  1796. pre_off_event,
  1797. &wcd938x->mbhc->wcd_mbhc);
  1798. snd_soc_component_update_bits(component, micb_reg,
  1799. 0xC0, 0x00);
  1800. if (post_off_event && wcd938x->mbhc)
  1801. blocking_notifier_call_chain(
  1802. &wcd938x->mbhc->notifier,
  1803. post_off_event,
  1804. &wcd938x->mbhc->wcd_mbhc);
  1805. }
  1806. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1807. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1808. post_dapm_off,
  1809. &wcd938x->mbhc->wcd_mbhc);
  1810. break;
  1811. };
  1812. dev_dbg(component->dev,
  1813. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1814. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1815. wcd938x->pullup_ref[micb_index]);
  1816. done:
  1817. mutex_unlock(&wcd938x->micb_lock);
  1818. return ret;
  1819. }
  1820. EXPORT_SYMBOL(wcd938x_micbias_control);
  1821. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1822. {
  1823. int ret = 0;
  1824. uint8_t devnum = 0;
  1825. int num_retry = NUM_ATTEMPTS;
  1826. do {
  1827. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1828. if (ret) {
  1829. dev_err(&swr_dev->dev,
  1830. "%s get devnum %d for dev addr %lx failed\n",
  1831. __func__, devnum, swr_dev->addr);
  1832. /* retry after 1ms */
  1833. usleep_range(1000, 1010);
  1834. }
  1835. } while (ret && --num_retry);
  1836. swr_dev->dev_num = devnum;
  1837. return 0;
  1838. }
  1839. static int wcd938x_event_notify(struct notifier_block *block,
  1840. unsigned long val,
  1841. void *data)
  1842. {
  1843. u16 event = (val & 0xffff);
  1844. int ret = 0;
  1845. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  1846. struct snd_soc_component *component = wcd938x->component;
  1847. struct wcd_mbhc *mbhc;
  1848. switch (event) {
  1849. case BOLERO_WCD_EVT_TX_CH_HOLD_CLEAR:
  1850. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  1851. snd_soc_component_update_bits(component,
  1852. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  1853. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1854. }
  1855. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  1856. snd_soc_component_update_bits(component,
  1857. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  1858. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1859. }
  1860. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  1861. snd_soc_component_update_bits(component,
  1862. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  1863. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1864. }
  1865. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  1866. snd_soc_component_update_bits(component,
  1867. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  1868. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1869. }
  1870. break;
  1871. case BOLERO_WCD_EVT_PA_OFF_PRE_SSR:
  1872. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1873. 0xC0, 0x00);
  1874. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  1875. 0x80, 0x00);
  1876. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  1877. 0x80, 0x00);
  1878. break;
  1879. case BOLERO_WCD_EVT_SSR_DOWN:
  1880. wcd938x->dev_up = false;
  1881. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  1882. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1883. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  1884. wcd938x_reset_low(wcd938x->dev);
  1885. break;
  1886. case BOLERO_WCD_EVT_SSR_UP:
  1887. wcd938x_reset(wcd938x->dev);
  1888. /* allow reset to take effect */
  1889. usleep_range(10000, 10010);
  1890. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  1891. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  1892. wcd938x_init_reg(component);
  1893. regcache_mark_dirty(wcd938x->regmap);
  1894. regcache_sync(wcd938x->regmap);
  1895. /* Initialize MBHC module */
  1896. mbhc = &wcd938x->mbhc->wcd_mbhc;
  1897. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  1898. if (ret) {
  1899. dev_err(component->dev, "%s: mbhc initialization failed\n",
  1900. __func__);
  1901. } else {
  1902. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  1903. }
  1904. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  1905. wcd938x->dev_up = true;
  1906. break;
  1907. case BOLERO_WCD_EVT_CLK_NOTIFY:
  1908. snd_soc_component_update_bits(component,
  1909. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  1910. ((val >> 0x10) << 0x01));
  1911. break;
  1912. default:
  1913. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  1914. break;
  1915. }
  1916. return 0;
  1917. }
  1918. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1919. int event)
  1920. {
  1921. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1922. int micb_num;
  1923. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1924. __func__, w->name, event);
  1925. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1926. micb_num = MIC_BIAS_1;
  1927. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1928. micb_num = MIC_BIAS_2;
  1929. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1930. micb_num = MIC_BIAS_3;
  1931. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  1932. micb_num = MIC_BIAS_4;
  1933. else
  1934. return -EINVAL;
  1935. switch (event) {
  1936. case SND_SOC_DAPM_PRE_PMU:
  1937. wcd938x_micbias_control(component, micb_num,
  1938. MICB_ENABLE, true);
  1939. break;
  1940. case SND_SOC_DAPM_POST_PMU:
  1941. /* 1 msec delay as per HW requirement */
  1942. usleep_range(1000, 1100);
  1943. break;
  1944. case SND_SOC_DAPM_POST_PMD:
  1945. wcd938x_micbias_control(component, micb_num,
  1946. MICB_DISABLE, true);
  1947. break;
  1948. };
  1949. return 0;
  1950. }
  1951. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1952. struct snd_kcontrol *kcontrol,
  1953. int event)
  1954. {
  1955. return __wcd938x_codec_enable_micbias(w, event);
  1956. }
  1957. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1958. int event)
  1959. {
  1960. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1961. int micb_num;
  1962. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1963. __func__, w->name, event);
  1964. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1965. micb_num = MIC_BIAS_1;
  1966. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1967. micb_num = MIC_BIAS_2;
  1968. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1969. micb_num = MIC_BIAS_3;
  1970. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  1971. micb_num = MIC_BIAS_4;
  1972. else
  1973. return -EINVAL;
  1974. switch (event) {
  1975. case SND_SOC_DAPM_PRE_PMU:
  1976. wcd938x_micbias_control(component, micb_num,
  1977. MICB_PULLUP_ENABLE, true);
  1978. break;
  1979. case SND_SOC_DAPM_POST_PMU:
  1980. /* 1 msec delay as per HW requirement */
  1981. usleep_range(1000, 1100);
  1982. break;
  1983. case SND_SOC_DAPM_POST_PMD:
  1984. wcd938x_micbias_control(component, micb_num,
  1985. MICB_PULLUP_DISABLE, true);
  1986. break;
  1987. };
  1988. return 0;
  1989. }
  1990. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1991. struct snd_kcontrol *kcontrol,
  1992. int event)
  1993. {
  1994. return __wcd938x_codec_enable_micbias_pullup(w, event);
  1995. }
  1996. static int wcd938x_wakeup(void *handle, bool enable)
  1997. {
  1998. struct wcd938x_priv *priv;
  1999. int ret = 0;
  2000. if (!handle) {
  2001. pr_err("%s: NULL handle\n", __func__);
  2002. return -EINVAL;
  2003. }
  2004. priv = (struct wcd938x_priv *)handle;
  2005. if (!priv->tx_swr_dev) {
  2006. pr_err("%s: tx swr dev is NULL\n", __func__);
  2007. return -EINVAL;
  2008. }
  2009. mutex_lock(&priv->wakeup_lock);
  2010. if (enable)
  2011. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2012. else
  2013. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2014. mutex_unlock(&priv->wakeup_lock);
  2015. return ret;
  2016. }
  2017. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2018. struct snd_kcontrol *kcontrol,
  2019. int event)
  2020. {
  2021. int ret = 0;
  2022. struct snd_soc_component *component =
  2023. snd_soc_dapm_to_component(w->dapm);
  2024. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2025. switch (event) {
  2026. case SND_SOC_DAPM_PRE_PMU:
  2027. wcd938x_wakeup(wcd938x, true);
  2028. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2029. wcd938x_wakeup(wcd938x, false);
  2030. break;
  2031. case SND_SOC_DAPM_POST_PMD:
  2032. wcd938x_wakeup(wcd938x, true);
  2033. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2034. wcd938x_wakeup(wcd938x, false);
  2035. break;
  2036. }
  2037. return ret;
  2038. }
  2039. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2040. int micb_num, int req)
  2041. {
  2042. int micb_index = micb_num - 1;
  2043. u16 micb_reg;
  2044. if (NULL == wcd938x) {
  2045. pr_err("%s: wcd938x private data is NULL\n", __func__);
  2046. return -EINVAL;
  2047. }
  2048. switch (micb_num) {
  2049. case MIC_BIAS_1:
  2050. micb_reg = WCD938X_ANA_MICB1;
  2051. break;
  2052. case MIC_BIAS_2:
  2053. micb_reg = WCD938X_ANA_MICB2;
  2054. break;
  2055. case MIC_BIAS_3:
  2056. micb_reg = WCD938X_ANA_MICB3;
  2057. break;
  2058. case MIC_BIAS_4:
  2059. micb_reg = WCD938X_ANA_MICB4;
  2060. break;
  2061. default:
  2062. pr_err("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2063. return -EINVAL;
  2064. };
  2065. mutex_lock(&wcd938x->micb_lock);
  2066. switch (req) {
  2067. case MICB_ENABLE:
  2068. wcd938x->micb_ref[micb_index]++;
  2069. if (wcd938x->micb_ref[micb_index] == 1) {
  2070. regmap_update_bits(wcd938x->regmap,
  2071. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2072. regmap_update_bits(wcd938x->regmap,
  2073. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2074. regmap_update_bits(wcd938x->regmap,
  2075. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2076. regmap_update_bits(wcd938x->regmap,
  2077. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2078. regmap_update_bits(wcd938x->regmap,
  2079. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2080. regmap_update_bits(wcd938x->regmap,
  2081. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2082. regmap_update_bits(wcd938x->regmap,
  2083. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2084. regmap_update_bits(wcd938x->regmap,
  2085. micb_reg, 0xC0, 0x40);
  2086. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2087. }
  2088. break;
  2089. case MICB_PULLUP_ENABLE:
  2090. wcd938x->pullup_ref[micb_index]++;
  2091. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2092. (wcd938x->micb_ref[micb_index] == 0))
  2093. regmap_update_bits(wcd938x->regmap, micb_reg,
  2094. 0xC0, 0x80);
  2095. break;
  2096. case MICB_PULLUP_DISABLE:
  2097. if (wcd938x->pullup_ref[micb_index] > 0)
  2098. wcd938x->pullup_ref[micb_index]--;
  2099. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2100. (wcd938x->micb_ref[micb_index] == 0))
  2101. regmap_update_bits(wcd938x->regmap, micb_reg,
  2102. 0xC0, 0x00);
  2103. break;
  2104. case MICB_DISABLE:
  2105. if (wcd938x->micb_ref[micb_index] > 0)
  2106. wcd938x->micb_ref[micb_index]--;
  2107. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2108. (wcd938x->pullup_ref[micb_index] > 0))
  2109. regmap_update_bits(wcd938x->regmap, micb_reg,
  2110. 0xC0, 0x80);
  2111. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2112. (wcd938x->pullup_ref[micb_index] == 0))
  2113. regmap_update_bits(wcd938x->regmap, micb_reg,
  2114. 0xC0, 0x00);
  2115. break;
  2116. };
  2117. mutex_unlock(&wcd938x->micb_lock);
  2118. return 0;
  2119. }
  2120. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2121. int event, int micb_num)
  2122. {
  2123. struct wcd938x_priv *wcd938x_priv = NULL;
  2124. if(NULL == component) {
  2125. pr_err("%s: wcd938x component is NULL\n", __func__);
  2126. return -EINVAL;
  2127. }
  2128. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2129. pr_err("%s: invalid event: %d\n", __func__, event);
  2130. return -EINVAL;
  2131. }
  2132. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2133. pr_err("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2134. return -EINVAL;
  2135. }
  2136. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2137. switch (event) {
  2138. case SND_SOC_DAPM_PRE_PMU:
  2139. wcd938x_wakeup(wcd938x_priv, true);
  2140. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2141. wcd938x_wakeup(wcd938x_priv, false);
  2142. break;
  2143. case SND_SOC_DAPM_POST_PMD:
  2144. wcd938x_wakeup(wcd938x_priv, true);
  2145. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2146. wcd938x_wakeup(wcd938x_priv, false);
  2147. break;
  2148. }
  2149. return 0;
  2150. }
  2151. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2152. static inline int wcd938x_tx_path_get(const char *wname,
  2153. unsigned int *path_num)
  2154. {
  2155. int ret = 0;
  2156. char *widget_name = NULL;
  2157. char *w_name = NULL;
  2158. char *path_num_char = NULL;
  2159. char *path_name = NULL;
  2160. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2161. if (!widget_name)
  2162. return -EINVAL;
  2163. w_name = widget_name;
  2164. path_name = strsep(&widget_name, " ");
  2165. if (!path_name) {
  2166. pr_err("%s: Invalid widget name = %s\n",
  2167. __func__, widget_name);
  2168. ret = -EINVAL;
  2169. goto err;
  2170. }
  2171. path_num_char = strpbrk(path_name, "0123");
  2172. if (!path_num_char) {
  2173. pr_err("%s: tx path index not found\n",
  2174. __func__);
  2175. ret = -EINVAL;
  2176. goto err;
  2177. }
  2178. ret = kstrtouint(path_num_char, 10, path_num);
  2179. if (ret < 0)
  2180. pr_err("%s: Invalid tx path = %s\n",
  2181. __func__, w_name);
  2182. err:
  2183. kfree(w_name);
  2184. return ret;
  2185. }
  2186. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2187. struct snd_ctl_elem_value *ucontrol)
  2188. {
  2189. struct snd_soc_component *component =
  2190. snd_soc_kcontrol_component(kcontrol);
  2191. struct wcd938x_priv *wcd938x = NULL;
  2192. int ret = 0;
  2193. unsigned int path = 0;
  2194. if (!component)
  2195. return -EINVAL;
  2196. wcd938x = snd_soc_component_get_drvdata(component);
  2197. if (!wcd938x)
  2198. return -EINVAL;
  2199. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2200. if (ret < 0)
  2201. return ret;
  2202. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2203. return 0;
  2204. }
  2205. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2206. struct snd_ctl_elem_value *ucontrol)
  2207. {
  2208. struct snd_soc_component *component =
  2209. snd_soc_kcontrol_component(kcontrol);
  2210. struct wcd938x_priv *wcd938x = NULL;
  2211. u32 mode_val;
  2212. unsigned int path = 0;
  2213. int ret = 0;
  2214. if (!component)
  2215. return -EINVAL;
  2216. wcd938x = snd_soc_component_get_drvdata(component);
  2217. if (!wcd938x)
  2218. return -EINVAL;
  2219. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2220. if (ret)
  2221. return ret;
  2222. mode_val = ucontrol->value.enumerated.item[0];
  2223. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2224. wcd938x->tx_mode[path] = mode_val;
  2225. return 0;
  2226. }
  2227. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2228. struct snd_ctl_elem_value *ucontrol)
  2229. {
  2230. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2231. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2232. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2233. return 0;
  2234. }
  2235. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2236. struct snd_ctl_elem_value *ucontrol)
  2237. {
  2238. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2239. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2240. u32 mode_val;
  2241. mode_val = ucontrol->value.enumerated.item[0];
  2242. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2243. if (wcd938x->variant == WCD9380) {
  2244. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2245. dev_info(component->dev,
  2246. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2247. __func__);
  2248. mode_val = CLS_H_ULP;
  2249. }
  2250. }
  2251. if (mode_val == CLS_H_NORMAL) {
  2252. dev_info(component->dev,
  2253. "%s:Invalid HPH Mode, default to class_AB\n",
  2254. __func__);
  2255. mode_val = CLS_H_ULP;
  2256. }
  2257. wcd938x->hph_mode = mode_val;
  2258. return 0;
  2259. }
  2260. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2261. struct snd_ctl_elem_value *ucontrol)
  2262. {
  2263. u8 ear_pa_gain = 0;
  2264. struct snd_soc_component *component =
  2265. snd_soc_kcontrol_component(kcontrol);
  2266. ear_pa_gain = snd_soc_component_read32(component,
  2267. WCD938X_ANA_EAR_COMPANDER_CTL);
  2268. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2269. ucontrol->value.integer.value[0] = ear_pa_gain;
  2270. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2271. ear_pa_gain);
  2272. return 0;
  2273. }
  2274. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2275. struct snd_ctl_elem_value *ucontrol)
  2276. {
  2277. u8 ear_pa_gain = 0;
  2278. struct snd_soc_component *component =
  2279. snd_soc_kcontrol_component(kcontrol);
  2280. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2281. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2282. __func__, ucontrol->value.integer.value[0]);
  2283. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2284. if (!wcd938x->comp1_enable) {
  2285. snd_soc_component_update_bits(component,
  2286. WCD938X_ANA_EAR_COMPANDER_CTL,
  2287. 0x7C, ear_pa_gain);
  2288. }
  2289. return 0;
  2290. }
  2291. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2292. struct snd_ctl_elem_value *ucontrol)
  2293. {
  2294. struct snd_soc_component *component =
  2295. snd_soc_kcontrol_component(kcontrol);
  2296. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2297. bool hphr;
  2298. struct soc_multi_mixer_control *mc;
  2299. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2300. hphr = mc->shift;
  2301. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2302. wcd938x->comp1_enable;
  2303. return 0;
  2304. }
  2305. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2306. struct snd_ctl_elem_value *ucontrol)
  2307. {
  2308. struct snd_soc_component *component =
  2309. snd_soc_kcontrol_component(kcontrol);
  2310. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2311. int value = ucontrol->value.integer.value[0];
  2312. bool hphr;
  2313. struct soc_multi_mixer_control *mc;
  2314. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2315. hphr = mc->shift;
  2316. if (hphr)
  2317. wcd938x->comp2_enable = value;
  2318. else
  2319. wcd938x->comp1_enable = value;
  2320. return 0;
  2321. }
  2322. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2323. struct snd_ctl_elem_value *ucontrol)
  2324. {
  2325. struct snd_soc_component *component =
  2326. snd_soc_kcontrol_component(kcontrol);
  2327. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2328. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2329. return 0;
  2330. }
  2331. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2332. struct snd_ctl_elem_value *ucontrol)
  2333. {
  2334. struct snd_soc_component *component =
  2335. snd_soc_kcontrol_component(kcontrol);
  2336. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2337. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2338. return 0;
  2339. }
  2340. const char * const tx_master_ch_text[] = {
  2341. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2342. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2343. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2344. "SWRM_PCM_IN",
  2345. };
  2346. const struct soc_enum tx_master_ch_enum =
  2347. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2348. tx_master_ch_text);
  2349. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2350. {
  2351. u8 ch_type = 0;
  2352. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2353. ch_type = ADC1;
  2354. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2355. ch_type = ADC2;
  2356. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2357. ch_type = ADC3;
  2358. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2359. ch_type = ADC4;
  2360. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2361. ch_type = DMIC0;
  2362. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2363. ch_type = DMIC1;
  2364. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2365. ch_type = MBHC;
  2366. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2367. ch_type = DMIC2;
  2368. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2369. ch_type = DMIC3;
  2370. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2371. ch_type = DMIC4;
  2372. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2373. ch_type = DMIC5;
  2374. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2375. ch_type = DMIC6;
  2376. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2377. ch_type = DMIC7;
  2378. else
  2379. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2380. if (ch_type)
  2381. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2382. else
  2383. *ch_idx = -EINVAL;
  2384. }
  2385. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2386. struct snd_ctl_elem_value *ucontrol)
  2387. {
  2388. struct snd_soc_component *component =
  2389. snd_soc_kcontrol_component(kcontrol);
  2390. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2391. int slave_ch_idx;
  2392. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2393. if (slave_ch_idx != -EINVAL)
  2394. ucontrol->value.integer.value[0] =
  2395. wcd938x_slave_get_master_ch_val(
  2396. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2397. return 0;
  2398. }
  2399. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2400. struct snd_ctl_elem_value *ucontrol)
  2401. {
  2402. struct snd_soc_component *component =
  2403. snd_soc_kcontrol_component(kcontrol);
  2404. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2405. int slave_ch_idx;
  2406. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2407. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2408. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2409. __func__, ucontrol->value.enumerated.item[0]);
  2410. if (slave_ch_idx != -EINVAL)
  2411. wcd938x->tx_master_ch_map[slave_ch_idx] =
  2412. wcd938x_slave_get_master_ch(
  2413. ucontrol->value.enumerated.item[0]);
  2414. return 0;
  2415. }
  2416. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2417. struct snd_ctl_elem_value *ucontrol)
  2418. {
  2419. struct snd_soc_component *component =
  2420. snd_soc_kcontrol_component(kcontrol);
  2421. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2422. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2423. return 0;
  2424. }
  2425. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2426. struct snd_ctl_elem_value *ucontrol)
  2427. {
  2428. struct snd_soc_component *component =
  2429. snd_soc_kcontrol_component(kcontrol);
  2430. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2431. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2432. return 0;
  2433. }
  2434. static const char * const tx_mode_mux_text_wcd9380[] = {
  2435. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2436. };
  2437. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2438. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2439. tx_mode_mux_text_wcd9380);
  2440. static const char * const tx_mode_mux_text[] = {
  2441. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2442. "ADC_ULP1", "ADC_ULP2",
  2443. };
  2444. static const struct soc_enum tx_mode_mux_enum =
  2445. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2446. tx_mode_mux_text);
  2447. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2448. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2449. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2450. "CLS_AB_LOHIFI",
  2451. };
  2452. static const char * const wcd938x_ear_pa_gain_text[] = {
  2453. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2454. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2455. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2456. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2457. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2458. };
  2459. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2460. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2461. rx_hph_mode_mux_text_wcd9380);
  2462. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2463. wcd938x_ear_pa_gain_text);
  2464. static const char * const rx_hph_mode_mux_text[] = {
  2465. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2466. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2467. };
  2468. static const struct soc_enum rx_hph_mode_mux_enum =
  2469. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2470. rx_hph_mode_mux_text);
  2471. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2472. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2473. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2474. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2475. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2476. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2477. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2478. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2479. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2480. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2481. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2482. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2483. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2484. };
  2485. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2486. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2487. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2488. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2489. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2490. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2491. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2492. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2493. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2494. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2495. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2496. };
  2497. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2498. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2499. wcd938x_get_compander, wcd938x_set_compander),
  2500. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2501. wcd938x_get_compander, wcd938x_set_compander),
  2502. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2503. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2504. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2505. wcd938x_bcs_get, wcd938x_bcs_put),
  2506. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2507. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2508. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2509. analog_gain),
  2510. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2511. analog_gain),
  2512. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2513. analog_gain),
  2514. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2515. analog_gain),
  2516. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2517. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2518. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2519. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2520. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2521. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2522. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2523. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2524. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2525. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2526. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2527. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2528. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2529. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2530. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2531. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2532. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2533. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2534. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2535. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2536. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2537. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2538. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2539. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2540. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2541. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2542. };
  2543. static const struct snd_kcontrol_new adc1_switch[] = {
  2544. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2545. };
  2546. static const struct snd_kcontrol_new adc2_switch[] = {
  2547. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2548. };
  2549. static const struct snd_kcontrol_new adc3_switch[] = {
  2550. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2551. };
  2552. static const struct snd_kcontrol_new adc4_switch[] = {
  2553. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2554. };
  2555. static const struct snd_kcontrol_new dmic1_switch[] = {
  2556. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2557. };
  2558. static const struct snd_kcontrol_new dmic2_switch[] = {
  2559. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2560. };
  2561. static const struct snd_kcontrol_new dmic3_switch[] = {
  2562. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2563. };
  2564. static const struct snd_kcontrol_new dmic4_switch[] = {
  2565. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2566. };
  2567. static const struct snd_kcontrol_new dmic5_switch[] = {
  2568. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2569. };
  2570. static const struct snd_kcontrol_new dmic6_switch[] = {
  2571. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2572. };
  2573. static const struct snd_kcontrol_new dmic7_switch[] = {
  2574. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2575. };
  2576. static const struct snd_kcontrol_new dmic8_switch[] = {
  2577. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2578. };
  2579. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2580. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2581. };
  2582. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2583. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2584. };
  2585. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2586. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2587. };
  2588. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2589. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2590. };
  2591. static const char * const adc2_mux_text[] = {
  2592. "INP2", "INP3"
  2593. };
  2594. static const struct soc_enum adc2_enum =
  2595. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2596. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2597. static const struct snd_kcontrol_new tx_adc2_mux =
  2598. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2599. static const char * const adc3_mux_text[] = {
  2600. "INP4", "INP6"
  2601. };
  2602. static const struct soc_enum adc3_enum =
  2603. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2604. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2605. static const struct snd_kcontrol_new tx_adc3_mux =
  2606. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2607. static const char * const adc4_mux_text[] = {
  2608. "INP5", "INP7"
  2609. };
  2610. static const struct soc_enum adc4_enum =
  2611. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2612. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2613. static const struct snd_kcontrol_new tx_adc4_mux =
  2614. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2615. static const char * const rdac3_mux_text[] = {
  2616. "RX1", "RX3"
  2617. };
  2618. static const char * const hdr12_mux_text[] = {
  2619. "NO_HDR12", "HDR12"
  2620. };
  2621. static const struct soc_enum hdr12_enum =
  2622. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2623. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2624. static const struct snd_kcontrol_new tx_hdr12_mux =
  2625. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2626. static const char * const hdr34_mux_text[] = {
  2627. "NO_HDR34", "HDR34"
  2628. };
  2629. static const struct soc_enum hdr34_enum =
  2630. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2631. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2632. static const struct snd_kcontrol_new tx_hdr34_mux =
  2633. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2634. static const struct soc_enum rdac3_enum =
  2635. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2636. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2637. static const struct snd_kcontrol_new rx_rdac3_mux =
  2638. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2639. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2640. /*input widgets*/
  2641. SND_SOC_DAPM_INPUT("AMIC1"),
  2642. SND_SOC_DAPM_INPUT("AMIC2"),
  2643. SND_SOC_DAPM_INPUT("AMIC3"),
  2644. SND_SOC_DAPM_INPUT("AMIC4"),
  2645. SND_SOC_DAPM_INPUT("AMIC5"),
  2646. SND_SOC_DAPM_INPUT("AMIC6"),
  2647. SND_SOC_DAPM_INPUT("AMIC7"),
  2648. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2649. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2650. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2651. /*tx widgets*/
  2652. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2653. wcd938x_codec_enable_adc,
  2654. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2655. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2656. wcd938x_codec_enable_adc,
  2657. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2658. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2659. wcd938x_codec_enable_adc,
  2660. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2661. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  2662. wcd938x_codec_enable_adc,
  2663. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2664. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2665. wcd938x_codec_enable_dmic,
  2666. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2667. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2668. wcd938x_codec_enable_dmic,
  2669. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2670. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2671. wcd938x_codec_enable_dmic,
  2672. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2673. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2674. wcd938x_codec_enable_dmic,
  2675. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2676. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2677. wcd938x_codec_enable_dmic,
  2678. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2679. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2680. wcd938x_codec_enable_dmic,
  2681. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2682. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  2683. wcd938x_codec_enable_dmic,
  2684. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2685. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  2686. wcd938x_codec_enable_dmic,
  2687. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2688. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  2689. NULL, 0, wcd938x_enable_req,
  2690. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2691. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  2692. NULL, 0, wcd938x_enable_req,
  2693. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2694. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  2695. NULL, 0, wcd938x_enable_req,
  2696. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2697. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  2698. NULL, 0, wcd938x_enable_req,
  2699. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2700. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2701. &tx_adc2_mux),
  2702. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2703. &tx_adc3_mux),
  2704. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  2705. &tx_adc4_mux),
  2706. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  2707. &tx_hdr12_mux),
  2708. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  2709. &tx_hdr34_mux),
  2710. /*tx mixers*/
  2711. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
  2712. adc1_switch, ARRAY_SIZE(adc1_switch),
  2713. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2714. SND_SOC_DAPM_POST_PMD),
  2715. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
  2716. adc2_switch, ARRAY_SIZE(adc2_switch),
  2717. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2718. SND_SOC_DAPM_POST_PMD),
  2719. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
  2720. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  2721. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2722. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
  2723. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  2724. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2725. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
  2726. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2727. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2728. SND_SOC_DAPM_POST_PMD),
  2729. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0,
  2730. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2731. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2732. SND_SOC_DAPM_POST_PMD),
  2733. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0,
  2734. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2735. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2736. SND_SOC_DAPM_POST_PMD),
  2737. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0,
  2738. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2739. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2740. SND_SOC_DAPM_POST_PMD),
  2741. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0,
  2742. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2743. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2744. SND_SOC_DAPM_POST_PMD),
  2745. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0,
  2746. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2747. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2748. SND_SOC_DAPM_POST_PMD),
  2749. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0,
  2750. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  2751. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2752. SND_SOC_DAPM_POST_PMD),
  2753. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0,
  2754. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  2755. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2756. SND_SOC_DAPM_POST_PMD),
  2757. /* micbias widgets*/
  2758. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2759. wcd938x_codec_enable_micbias,
  2760. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2761. SND_SOC_DAPM_POST_PMD),
  2762. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2763. wcd938x_codec_enable_micbias,
  2764. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2765. SND_SOC_DAPM_POST_PMD),
  2766. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2767. wcd938x_codec_enable_micbias,
  2768. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2769. SND_SOC_DAPM_POST_PMD),
  2770. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2771. wcd938x_codec_enable_micbias,
  2772. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2773. SND_SOC_DAPM_POST_PMD),
  2774. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  2775. wcd938x_codec_force_enable_micbias,
  2776. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2777. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  2778. wcd938x_codec_force_enable_micbias,
  2779. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2780. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  2781. wcd938x_codec_force_enable_micbias,
  2782. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2783. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  2784. wcd938x_codec_force_enable_micbias,
  2785. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2786. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2787. wcd938x_enable_clsh,
  2788. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2789. /*rx widgets*/
  2790. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  2791. wcd938x_codec_enable_ear_pa,
  2792. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2793. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2794. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  2795. wcd938x_codec_enable_aux_pa,
  2796. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2797. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2798. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  2799. wcd938x_codec_enable_hphl_pa,
  2800. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2801. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2802. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  2803. wcd938x_codec_enable_hphr_pa,
  2804. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2805. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2806. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2807. wcd938x_codec_hphl_dac_event,
  2808. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2809. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2810. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2811. wcd938x_codec_hphr_dac_event,
  2812. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2813. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2814. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  2815. wcd938x_codec_ear_dac_event,
  2816. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2817. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2818. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  2819. wcd938x_codec_aux_dac_event,
  2820. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2821. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  2822. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  2823. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  2824. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  2825. SND_SOC_DAPM_POST_PMD),
  2826. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  2827. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  2828. SND_SOC_DAPM_POST_PMD),
  2829. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  2830. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  2831. SND_SOC_DAPM_POST_PMD),
  2832. /* rx mixer widgets*/
  2833. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  2834. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  2835. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  2836. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  2837. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  2838. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  2839. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  2840. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  2841. /*output widgets tx*/
  2842. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  2843. /*output widgets rx*/
  2844. SND_SOC_DAPM_OUTPUT("EAR"),
  2845. SND_SOC_DAPM_OUTPUT("AUX"),
  2846. SND_SOC_DAPM_OUTPUT("HPHL"),
  2847. SND_SOC_DAPM_OUTPUT("HPHR"),
  2848. /* micbias pull up widgets*/
  2849. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  2850. wcd938x_codec_enable_micbias_pullup,
  2851. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2852. SND_SOC_DAPM_POST_PMD),
  2853. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  2854. wcd938x_codec_enable_micbias_pullup,
  2855. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2856. SND_SOC_DAPM_POST_PMD),
  2857. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  2858. wcd938x_codec_enable_micbias_pullup,
  2859. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2860. SND_SOC_DAPM_POST_PMD),
  2861. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  2862. wcd938x_codec_enable_micbias_pullup,
  2863. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  2864. SND_SOC_DAPM_POST_PMD),
  2865. };
  2866. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  2867. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  2868. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  2869. {"ADC1 REQ", NULL, "ADC1"},
  2870. {"ADC1", NULL, "AMIC1"},
  2871. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  2872. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  2873. {"ADC2 REQ", NULL, "ADC2"},
  2874. {"ADC2", NULL, "HDR12 MUX"},
  2875. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  2876. {"HDR12 MUX", "HDR12", "AMIC1"},
  2877. {"ADC2 MUX", "INP3", "AMIC3"},
  2878. {"ADC2 MUX", "INP2", "AMIC2"},
  2879. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  2880. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  2881. {"ADC3 REQ", NULL, "ADC3"},
  2882. {"ADC3", NULL, "HDR34 MUX"},
  2883. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  2884. {"HDR34 MUX", "HDR34", "AMIC5"},
  2885. {"ADC3 MUX", "INP4", "AMIC4"},
  2886. {"ADC3 MUX", "INP6", "AMIC6"},
  2887. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  2888. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  2889. {"ADC4 REQ", NULL, "ADC4"},
  2890. {"ADC4", NULL, "ADC4 MUX"},
  2891. {"ADC4 MUX", "INP5", "AMIC5"},
  2892. {"ADC4 MUX", "INP7", "AMIC7"},
  2893. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  2894. {"DMIC1_MIXER", "Switch", "DMIC1"},
  2895. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  2896. {"DMIC2_MIXER", "Switch", "DMIC2"},
  2897. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  2898. {"DMIC3_MIXER", "Switch", "DMIC3"},
  2899. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  2900. {"DMIC4_MIXER", "Switch", "DMIC4"},
  2901. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  2902. {"DMIC5_MIXER", "Switch", "DMIC5"},
  2903. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  2904. {"DMIC6_MIXER", "Switch", "DMIC6"},
  2905. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  2906. {"DMIC7_MIXER", "Switch", "DMIC7"},
  2907. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  2908. {"DMIC8_MIXER", "Switch", "DMIC8"},
  2909. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  2910. {"RX1", NULL, "IN1_HPHL"},
  2911. {"RDAC1", NULL, "RX1"},
  2912. {"HPHL_RDAC", "Switch", "RDAC1"},
  2913. {"HPHL PGA", NULL, "HPHL_RDAC"},
  2914. {"HPHL", NULL, "HPHL PGA"},
  2915. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  2916. {"RX2", NULL, "IN2_HPHR"},
  2917. {"RDAC2", NULL, "RX2"},
  2918. {"HPHR_RDAC", "Switch", "RDAC2"},
  2919. {"HPHR PGA", NULL, "HPHR_RDAC"},
  2920. {"HPHR", NULL, "HPHR PGA"},
  2921. {"IN3_AUX", NULL, "CLS_H_PORT"},
  2922. {"RX3", NULL, "IN3_AUX"},
  2923. {"RDAC4", NULL, "RX3"},
  2924. {"AUX_RDAC", "Switch", "RDAC4"},
  2925. {"AUX PGA", NULL, "AUX_RDAC"},
  2926. {"AUX", NULL, "AUX PGA"},
  2927. {"RDAC3_MUX", "RX3", "RX3"},
  2928. {"RDAC3_MUX", "RX1", "RX1"},
  2929. {"RDAC3", NULL, "RDAC3_MUX"},
  2930. {"EAR_RDAC", "Switch", "RDAC3"},
  2931. {"EAR PGA", NULL, "EAR_RDAC"},
  2932. {"EAR", NULL, "EAR PGA"},
  2933. };
  2934. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  2935. void *file_private_data,
  2936. struct file *file,
  2937. char __user *buf, size_t count,
  2938. loff_t pos)
  2939. {
  2940. struct wcd938x_priv *priv;
  2941. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  2942. int len = 0;
  2943. priv = (struct wcd938x_priv *) entry->private_data;
  2944. if (!priv) {
  2945. pr_err("%s: wcd938x priv is null\n", __func__);
  2946. return -EINVAL;
  2947. }
  2948. switch (priv->version) {
  2949. case WCD938X_VERSION_1_0:
  2950. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  2951. break;
  2952. default:
  2953. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2954. }
  2955. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2956. }
  2957. static struct snd_info_entry_ops wcd938x_info_ops = {
  2958. .read = wcd938x_version_read,
  2959. };
  2960. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  2961. void *file_private_data,
  2962. struct file *file,
  2963. char __user *buf, size_t count,
  2964. loff_t pos)
  2965. {
  2966. struct wcd938x_priv *priv;
  2967. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  2968. int len = 0;
  2969. priv = (struct wcd938x_priv *) entry->private_data;
  2970. if (!priv) {
  2971. pr_err("%s: wcd938x priv is null\n", __func__);
  2972. return -EINVAL;
  2973. }
  2974. switch (priv->variant) {
  2975. case WCD9380:
  2976. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  2977. break;
  2978. case WCD9385:
  2979. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  2980. break;
  2981. default:
  2982. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  2983. }
  2984. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  2985. }
  2986. static struct snd_info_entry_ops wcd938x_variant_ops = {
  2987. .read = wcd938x_variant_read,
  2988. };
  2989. /*
  2990. * wcd938x_get_codec_variant
  2991. * @component: component instance
  2992. *
  2993. * Return: codec variant or -EINVAL in error.
  2994. */
  2995. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  2996. {
  2997. struct wcd938x_priv *priv = NULL;
  2998. if (!component)
  2999. return -EINVAL;
  3000. priv = snd_soc_component_get_drvdata(component);
  3001. if (!priv) {
  3002. dev_err(component->dev,
  3003. "%s:wcd938x not probed\n", __func__);
  3004. return 0;
  3005. }
  3006. return priv->variant;
  3007. }
  3008. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3009. /*
  3010. * wcd938x_info_create_codec_entry - creates wcd938x module
  3011. * @codec_root: The parent directory
  3012. * @component: component instance
  3013. *
  3014. * Creates wcd938x module, variant and version entry under the given
  3015. * parent directory.
  3016. *
  3017. * Return: 0 on success or negative error code on failure.
  3018. */
  3019. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3020. struct snd_soc_component *component)
  3021. {
  3022. struct snd_info_entry *version_entry;
  3023. struct snd_info_entry *variant_entry;
  3024. struct wcd938x_priv *priv;
  3025. struct snd_soc_card *card;
  3026. if (!codec_root || !component)
  3027. return -EINVAL;
  3028. priv = snd_soc_component_get_drvdata(component);
  3029. if (priv->entry) {
  3030. dev_dbg(priv->dev,
  3031. "%s:wcd938x module already created\n", __func__);
  3032. return 0;
  3033. }
  3034. card = component->card;
  3035. priv->entry = snd_info_create_module_entry(codec_root->module,
  3036. "wcd938x", codec_root);
  3037. if (!priv->entry) {
  3038. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3039. __func__);
  3040. return -ENOMEM;
  3041. }
  3042. priv->entry->mode = S_IFDIR | 0555;
  3043. if (snd_info_register(priv->entry) < 0) {
  3044. snd_info_free_entry(priv->entry);
  3045. return -ENOMEM;
  3046. }
  3047. version_entry = snd_info_create_card_entry(card->snd_card,
  3048. "version",
  3049. priv->entry);
  3050. if (!version_entry) {
  3051. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3052. __func__);
  3053. snd_info_free_entry(priv->entry);
  3054. return -ENOMEM;
  3055. }
  3056. version_entry->private_data = priv;
  3057. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3058. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3059. version_entry->c.ops = &wcd938x_info_ops;
  3060. if (snd_info_register(version_entry) < 0) {
  3061. snd_info_free_entry(version_entry);
  3062. snd_info_free_entry(priv->entry);
  3063. return -ENOMEM;
  3064. }
  3065. priv->version_entry = version_entry;
  3066. variant_entry = snd_info_create_card_entry(card->snd_card,
  3067. "variant",
  3068. priv->entry);
  3069. if (!variant_entry) {
  3070. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3071. __func__);
  3072. snd_info_free_entry(version_entry);
  3073. snd_info_free_entry(priv->entry);
  3074. return -ENOMEM;
  3075. }
  3076. variant_entry->private_data = priv;
  3077. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3078. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3079. variant_entry->c.ops = &wcd938x_variant_ops;
  3080. if (snd_info_register(variant_entry) < 0) {
  3081. snd_info_free_entry(variant_entry);
  3082. snd_info_free_entry(version_entry);
  3083. snd_info_free_entry(priv->entry);
  3084. return -ENOMEM;
  3085. }
  3086. priv->variant_entry = variant_entry;
  3087. return 0;
  3088. }
  3089. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3090. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3091. struct wcd938x_pdata *pdata)
  3092. {
  3093. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3094. int rc = 0;
  3095. if (!pdata) {
  3096. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3097. return -ENODEV;
  3098. }
  3099. /* set micbias voltage */
  3100. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3101. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3102. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3103. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3104. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3105. vout_ctl_4 < 0) {
  3106. rc = -EINVAL;
  3107. goto done;
  3108. }
  3109. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3110. vout_ctl_1);
  3111. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3112. vout_ctl_2);
  3113. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3114. vout_ctl_3);
  3115. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3116. vout_ctl_4);
  3117. done:
  3118. return rc;
  3119. }
  3120. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3121. {
  3122. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3123. struct snd_soc_dapm_context *dapm =
  3124. snd_soc_component_get_dapm(component);
  3125. int variant;
  3126. int ret = -EINVAL;
  3127. dev_info(component->dev, "%s()\n", __func__);
  3128. wcd938x = snd_soc_component_get_drvdata(component);
  3129. if (!wcd938x)
  3130. return -EINVAL;
  3131. wcd938x->component = component;
  3132. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3133. variant = (snd_soc_component_read32(component,
  3134. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3135. wcd938x->variant = variant;
  3136. wcd938x->fw_data = devm_kzalloc(component->dev,
  3137. sizeof(*(wcd938x->fw_data)),
  3138. GFP_KERNEL);
  3139. if (!wcd938x->fw_data) {
  3140. dev_err(component->dev, "Failed to allocate fw_data\n");
  3141. ret = -ENOMEM;
  3142. goto err;
  3143. }
  3144. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3145. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3146. WCD9XXX_CODEC_HWDEP_NODE, component);
  3147. if (ret < 0) {
  3148. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3149. goto err_hwdep;
  3150. }
  3151. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3152. if (ret) {
  3153. pr_err("%s: mbhc initialization failed\n", __func__);
  3154. goto err_hwdep;
  3155. }
  3156. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3157. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3158. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3159. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3160. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3161. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3162. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3163. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3164. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3165. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3166. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3167. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3168. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3169. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3170. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3171. snd_soc_dapm_sync(dapm);
  3172. wcd_cls_h_init(&wcd938x->clsh_info);
  3173. wcd938x_init_reg(component);
  3174. if (wcd938x->variant == WCD9380) {
  3175. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3176. ARRAY_SIZE(wcd9380_snd_controls));
  3177. if (ret < 0) {
  3178. dev_err(component->dev,
  3179. "%s: Failed to add snd ctrls for variant: %d\n",
  3180. __func__, wcd938x->variant);
  3181. goto err_hwdep;
  3182. }
  3183. }
  3184. if (wcd938x->variant == WCD9385) {
  3185. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3186. ARRAY_SIZE(wcd9385_snd_controls));
  3187. if (ret < 0) {
  3188. dev_err(component->dev,
  3189. "%s: Failed to add snd ctrls for variant: %d\n",
  3190. __func__, wcd938x->variant);
  3191. goto err_hwdep;
  3192. }
  3193. }
  3194. wcd938x->version = WCD938X_VERSION_1_0;
  3195. /* Register event notifier */
  3196. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3197. if (wcd938x->register_notifier) {
  3198. ret = wcd938x->register_notifier(wcd938x->handle,
  3199. &wcd938x->nblock,
  3200. true);
  3201. if (ret) {
  3202. dev_err(component->dev,
  3203. "%s: Failed to register notifier %d\n",
  3204. __func__, ret);
  3205. return ret;
  3206. }
  3207. }
  3208. wcd938x->dev_up = true;
  3209. return ret;
  3210. err_hwdep:
  3211. wcd938x->fw_data = NULL;
  3212. err:
  3213. return ret;
  3214. }
  3215. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3216. {
  3217. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3218. if (!wcd938x) {
  3219. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3220. __func__);
  3221. return;
  3222. }
  3223. if (wcd938x->register_notifier)
  3224. wcd938x->register_notifier(wcd938x->handle,
  3225. &wcd938x->nblock,
  3226. false);
  3227. }
  3228. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3229. .name = WCD938X_DRV_NAME,
  3230. .probe = wcd938x_soc_codec_probe,
  3231. .remove = wcd938x_soc_codec_remove,
  3232. .controls = wcd938x_snd_controls,
  3233. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3234. .dapm_widgets = wcd938x_dapm_widgets,
  3235. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3236. .dapm_routes = wcd938x_audio_map,
  3237. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3238. };
  3239. static int wcd938x_reset(struct device *dev)
  3240. {
  3241. struct wcd938x_priv *wcd938x = NULL;
  3242. int rc = 0;
  3243. int value = 0;
  3244. if (!dev)
  3245. return -ENODEV;
  3246. wcd938x = dev_get_drvdata(dev);
  3247. if (!wcd938x)
  3248. return -EINVAL;
  3249. if (!wcd938x->rst_np) {
  3250. dev_err(dev, "%s: reset gpio device node not specified\n",
  3251. __func__);
  3252. return -EINVAL;
  3253. }
  3254. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3255. if (value > 0)
  3256. return 0;
  3257. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3258. if (rc) {
  3259. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3260. __func__);
  3261. return rc;
  3262. }
  3263. /* 20us sleep required after pulling the reset gpio to LOW */
  3264. usleep_range(20, 30);
  3265. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3266. if (rc) {
  3267. dev_err(dev, "%s: wcd active state request fail!\n",
  3268. __func__);
  3269. return rc;
  3270. }
  3271. /* 20us sleep required after pulling the reset gpio to HIGH */
  3272. usleep_range(20, 30);
  3273. return rc;
  3274. }
  3275. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3276. u32 *val)
  3277. {
  3278. int rc = 0;
  3279. rc = of_property_read_u32(dev->of_node, name, val);
  3280. if (rc)
  3281. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3282. __func__, name, dev->of_node->full_name);
  3283. return rc;
  3284. }
  3285. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3286. struct wcd938x_micbias_setting *mb)
  3287. {
  3288. u32 prop_val = 0;
  3289. int rc = 0;
  3290. /* MB1 */
  3291. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3292. NULL)) {
  3293. rc = wcd938x_read_of_property_u32(dev,
  3294. "qcom,cdc-micbias1-mv",
  3295. &prop_val);
  3296. if (!rc)
  3297. mb->micb1_mv = prop_val;
  3298. } else {
  3299. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3300. __func__);
  3301. }
  3302. /* MB2 */
  3303. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3304. NULL)) {
  3305. rc = wcd938x_read_of_property_u32(dev,
  3306. "qcom,cdc-micbias2-mv",
  3307. &prop_val);
  3308. if (!rc)
  3309. mb->micb2_mv = prop_val;
  3310. } else {
  3311. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3312. __func__);
  3313. }
  3314. /* MB3 */
  3315. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3316. NULL)) {
  3317. rc = wcd938x_read_of_property_u32(dev,
  3318. "qcom,cdc-micbias3-mv",
  3319. &prop_val);
  3320. if (!rc)
  3321. mb->micb3_mv = prop_val;
  3322. } else {
  3323. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3324. __func__);
  3325. }
  3326. /* MB4 */
  3327. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3328. NULL)) {
  3329. rc = wcd938x_read_of_property_u32(dev,
  3330. "qcom,cdc-micbias4-mv",
  3331. &prop_val);
  3332. if (!rc)
  3333. mb->micb4_mv = prop_val;
  3334. } else {
  3335. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3336. __func__);
  3337. }
  3338. }
  3339. static int wcd938x_reset_low(struct device *dev)
  3340. {
  3341. struct wcd938x_priv *wcd938x = NULL;
  3342. int rc = 0;
  3343. if (!dev)
  3344. return -ENODEV;
  3345. wcd938x = dev_get_drvdata(dev);
  3346. if (!wcd938x)
  3347. return -EINVAL;
  3348. if (!wcd938x->rst_np) {
  3349. dev_err(dev, "%s: reset gpio device node not specified\n",
  3350. __func__);
  3351. return -EINVAL;
  3352. }
  3353. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3354. if (rc) {
  3355. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3356. __func__);
  3357. return rc;
  3358. }
  3359. /* 20us sleep required after pulling the reset gpio to LOW */
  3360. usleep_range(20, 30);
  3361. return rc;
  3362. }
  3363. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3364. {
  3365. struct wcd938x_pdata *pdata = NULL;
  3366. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3367. GFP_KERNEL);
  3368. if (!pdata)
  3369. return NULL;
  3370. pdata->rst_np = of_parse_phandle(dev->of_node,
  3371. "qcom,wcd-rst-gpio-node", 0);
  3372. if (!pdata->rst_np) {
  3373. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3374. __func__, "qcom,wcd-rst-gpio-node",
  3375. dev->of_node->full_name);
  3376. return NULL;
  3377. }
  3378. /* Parse power supplies */
  3379. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3380. &pdata->num_supplies);
  3381. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3382. dev_err(dev, "%s: no power supplies defined for codec\n",
  3383. __func__);
  3384. return NULL;
  3385. }
  3386. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3387. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3388. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3389. return pdata;
  3390. }
  3391. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3392. {
  3393. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3394. __func__, irq);
  3395. return IRQ_HANDLED;
  3396. }
  3397. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3398. {
  3399. .name = "wcd938x_cdc",
  3400. .playback = {
  3401. .stream_name = "WCD938X_AIF Playback",
  3402. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3403. .formats = WCD938X_FORMATS,
  3404. .rate_max = 192000,
  3405. .rate_min = 8000,
  3406. .channels_min = 1,
  3407. .channels_max = 4,
  3408. },
  3409. .capture = {
  3410. .stream_name = "WCD938X_AIF Capture",
  3411. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3412. .formats = WCD938X_FORMATS,
  3413. .rate_max = 192000,
  3414. .rate_min = 8000,
  3415. .channels_min = 1,
  3416. .channels_max = 4,
  3417. },
  3418. },
  3419. };
  3420. static int wcd938x_bind(struct device *dev)
  3421. {
  3422. int ret = 0, i = 0;
  3423. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3424. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3425. /*
  3426. * Add 5msec delay to provide sufficient time for
  3427. * soundwire auto enumeration of slave devices as
  3428. * as per HW requirement.
  3429. */
  3430. usleep_range(5000, 5010);
  3431. ret = component_bind_all(dev, wcd938x);
  3432. if (ret) {
  3433. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3434. __func__, ret);
  3435. return ret;
  3436. }
  3437. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3438. if (!wcd938x->rx_swr_dev) {
  3439. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3440. __func__);
  3441. ret = -ENODEV;
  3442. goto err;
  3443. }
  3444. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3445. if (!wcd938x->tx_swr_dev) {
  3446. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3447. __func__);
  3448. ret = -ENODEV;
  3449. goto err;
  3450. }
  3451. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3452. &wcd938x_regmap_config);
  3453. if (!wcd938x->regmap) {
  3454. dev_err(dev, "%s: Regmap init failed\n",
  3455. __func__);
  3456. goto err;
  3457. }
  3458. /* Set all interupts as edge triggered */
  3459. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3460. regmap_write(wcd938x->regmap,
  3461. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3462. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3463. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3464. wcd938x->irq_info.codec_name = "WCD938X";
  3465. wcd938x->irq_info.regmap = wcd938x->regmap;
  3466. wcd938x->irq_info.dev = dev;
  3467. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3468. if (ret) {
  3469. dev_err(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3470. __func__, ret);
  3471. goto err;
  3472. }
  3473. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3474. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3475. if (ret < 0) {
  3476. dev_err(dev, "%s: bad micbias pdata\n", __func__);
  3477. goto err_irq;
  3478. }
  3479. /* Request for watchdog interrupt */
  3480. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3481. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3482. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3483. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3484. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3485. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3486. /* Disable watchdog interrupt for HPH and AUX */
  3487. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3488. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3489. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3490. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3491. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3492. if (ret) {
  3493. dev_err(dev, "%s: Codec registration failed\n",
  3494. __func__);
  3495. goto err_irq;
  3496. }
  3497. return ret;
  3498. err_irq:
  3499. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3500. err:
  3501. component_unbind_all(dev, wcd938x);
  3502. return ret;
  3503. }
  3504. static void wcd938x_unbind(struct device *dev)
  3505. {
  3506. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3507. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3508. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3509. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3510. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3511. snd_soc_unregister_component(dev);
  3512. component_unbind_all(dev, wcd938x);
  3513. }
  3514. static const struct of_device_id wcd938x_dt_match[] = {
  3515. { .compatible = "qcom,wcd938x-codec" },
  3516. {}
  3517. };
  3518. static const struct component_master_ops wcd938x_comp_ops = {
  3519. .bind = wcd938x_bind,
  3520. .unbind = wcd938x_unbind,
  3521. };
  3522. static int wcd938x_compare_of(struct device *dev, void *data)
  3523. {
  3524. return dev->of_node == data;
  3525. }
  3526. static void wcd938x_release_of(struct device *dev, void *data)
  3527. {
  3528. of_node_put(data);
  3529. }
  3530. static int wcd938x_add_slave_components(struct device *dev,
  3531. struct component_match **matchptr)
  3532. {
  3533. struct device_node *np, *rx_node, *tx_node;
  3534. np = dev->of_node;
  3535. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3536. if (!rx_node) {
  3537. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3538. return -ENODEV;
  3539. }
  3540. of_node_get(rx_node);
  3541. component_match_add_release(dev, matchptr,
  3542. wcd938x_release_of,
  3543. wcd938x_compare_of,
  3544. rx_node);
  3545. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3546. if (!tx_node) {
  3547. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3548. return -ENODEV;
  3549. }
  3550. of_node_get(tx_node);
  3551. component_match_add_release(dev, matchptr,
  3552. wcd938x_release_of,
  3553. wcd938x_compare_of,
  3554. tx_node);
  3555. return 0;
  3556. }
  3557. static int wcd938x_probe(struct platform_device *pdev)
  3558. {
  3559. struct component_match *match = NULL;
  3560. struct wcd938x_priv *wcd938x = NULL;
  3561. struct wcd938x_pdata *pdata = NULL;
  3562. struct wcd_ctrl_platform_data *plat_data = NULL;
  3563. struct device *dev = &pdev->dev;
  3564. int ret;
  3565. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  3566. GFP_KERNEL);
  3567. if (!wcd938x)
  3568. return -ENOMEM;
  3569. dev_set_drvdata(dev, wcd938x);
  3570. wcd938x->dev = dev;
  3571. pdata = wcd938x_populate_dt_data(dev);
  3572. if (!pdata) {
  3573. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3574. return -EINVAL;
  3575. }
  3576. dev->platform_data = pdata;
  3577. wcd938x->rst_np = pdata->rst_np;
  3578. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  3579. pdata->regulator, pdata->num_supplies);
  3580. if (!wcd938x->supplies) {
  3581. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3582. __func__);
  3583. return ret;
  3584. }
  3585. plat_data = dev_get_platdata(dev->parent);
  3586. if (!plat_data) {
  3587. dev_err(dev, "%s: platform data from parent is NULL\n",
  3588. __func__);
  3589. return -EINVAL;
  3590. }
  3591. wcd938x->handle = (void *)plat_data->handle;
  3592. if (!wcd938x->handle) {
  3593. dev_err(dev, "%s: handle is NULL\n", __func__);
  3594. return -EINVAL;
  3595. }
  3596. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  3597. if (!wcd938x->update_wcd_event) {
  3598. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3599. __func__);
  3600. return -EINVAL;
  3601. }
  3602. wcd938x->register_notifier = plat_data->register_notifier;
  3603. if (!wcd938x->register_notifier) {
  3604. dev_err(dev, "%s: register_notifier api is null!\n",
  3605. __func__);
  3606. return -EINVAL;
  3607. }
  3608. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  3609. pdata->regulator,
  3610. pdata->num_supplies);
  3611. if (ret) {
  3612. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3613. __func__);
  3614. return ret;
  3615. }
  3616. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3617. CODEC_RX);
  3618. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3619. CODEC_TX);
  3620. if (ret) {
  3621. dev_err(dev, "Failed to read port mapping\n");
  3622. goto err;
  3623. }
  3624. mutex_init(&wcd938x->wakeup_lock);
  3625. mutex_init(&wcd938x->micb_lock);
  3626. ret = wcd938x_add_slave_components(dev, &match);
  3627. if (ret)
  3628. goto err_lock_init;
  3629. wcd938x_reset(dev);
  3630. wcd938x->wakeup = wcd938x_wakeup;
  3631. return component_master_add_with_match(dev,
  3632. &wcd938x_comp_ops, match);
  3633. err_lock_init:
  3634. mutex_destroy(&wcd938x->micb_lock);
  3635. mutex_destroy(&wcd938x->wakeup_lock);
  3636. err:
  3637. return ret;
  3638. }
  3639. static int wcd938x_remove(struct platform_device *pdev)
  3640. {
  3641. struct wcd938x_priv *wcd938x = NULL;
  3642. wcd938x = platform_get_drvdata(pdev);
  3643. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  3644. mutex_destroy(&wcd938x->micb_lock);
  3645. mutex_destroy(&wcd938x->wakeup_lock);
  3646. dev_set_drvdata(&pdev->dev, NULL);
  3647. return 0;
  3648. }
  3649. #ifdef CONFIG_PM_SLEEP
  3650. static int wcd938x_suspend(struct device *dev)
  3651. {
  3652. return 0;
  3653. }
  3654. static int wcd938x_resume(struct device *dev)
  3655. {
  3656. return 0;
  3657. }
  3658. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  3659. SET_SYSTEM_SLEEP_PM_OPS(
  3660. wcd938x_suspend,
  3661. wcd938x_resume
  3662. )
  3663. };
  3664. #endif
  3665. static struct platform_driver wcd938x_codec_driver = {
  3666. .probe = wcd938x_probe,
  3667. .remove = wcd938x_remove,
  3668. .driver = {
  3669. .name = "wcd938x_codec",
  3670. .owner = THIS_MODULE,
  3671. .of_match_table = of_match_ptr(wcd938x_dt_match),
  3672. #ifdef CONFIG_PM_SLEEP
  3673. .pm = &wcd938x_dev_pm_ops,
  3674. #endif
  3675. .suppress_bind_attrs = true,
  3676. },
  3677. };
  3678. module_platform_driver(wcd938x_codec_driver);
  3679. MODULE_DESCRIPTION("WCD938X Codec driver");
  3680. MODULE_LICENSE("GPL v2");