dp_tx.c 98 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "qdf_net_types.h"
  27. #include <wlan_cfg.h>
  28. #ifdef MESH_MODE_SUPPORT
  29. #include "if_meta_hdr.h"
  30. #endif
  31. #define DP_TX_QUEUE_MASK 0x3
  32. /* TODO Add support in TSO */
  33. #define DP_DESC_NUM_FRAG(x) 0
  34. /* disable TQM_BYPASS */
  35. #define TQM_BYPASS_WAR 0
  36. /* invalid peer id for reinject*/
  37. #define DP_INVALID_PEER 0XFFFE
  38. /*mapping between hal encrypt type and cdp_sec_type*/
  39. #define MAX_CDP_SEC_TYPE 12
  40. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  41. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  42. HAL_TX_ENCRYPT_TYPE_WEP_128,
  43. HAL_TX_ENCRYPT_TYPE_WEP_104,
  44. HAL_TX_ENCRYPT_TYPE_WEP_40,
  45. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  47. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  48. HAL_TX_ENCRYPT_TYPE_WAPI,
  49. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  50. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  52. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  53. /**
  54. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  55. * @vdev: DP Virtual device handle
  56. * @nbuf: Buffer pointer
  57. * @queue: queue ids container for nbuf
  58. *
  59. * TX packet queue has 2 instances, software descriptors id and dma ring id
  60. * Based on tx feature and hardware configuration queue id combination could be
  61. * different.
  62. * For example -
  63. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  64. * With no XPS,lock based resource protection, Descriptor pool ids are different
  65. * for each vdev, dma ring id will be same as single pdev id
  66. *
  67. * Return: None
  68. */
  69. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  70. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  71. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  72. {
  73. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  74. queue->desc_pool_id = queue_offset;
  75. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  76. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  77. "%s, pool_id:%d ring_id: %d",
  78. __func__, queue->desc_pool_id, queue->ring_id);
  79. return;
  80. }
  81. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  82. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  83. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  84. {
  85. /* get flow id */
  86. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  87. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  89. "%s, pool_id:%d ring_id: %d",
  90. __func__, queue->desc_pool_id, queue->ring_id);
  91. return;
  92. }
  93. #endif
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  97. *
  98. * @soc - core txrx main context
  99. * @tx_desc - Tx software descriptor
  100. */
  101. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  102. struct dp_tx_desc_s *tx_desc)
  103. {
  104. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  105. if (qdf_unlikely(!tx_desc->tso_desc)) {
  106. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  107. "%s %d TSO desc is NULL!",
  108. __func__, __LINE__);
  109. qdf_assert(0);
  110. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  111. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  112. "%s %d TSO num desc is NULL!",
  113. __func__, __LINE__);
  114. qdf_assert(0);
  115. } else {
  116. bool is_last_seg;
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1)
  120. is_last_seg = false;
  121. else
  122. is_last_seg = true;
  123. tso_num_desc->num_seg.tso_cmn_num_seg--;
  124. qdf_nbuf_unmap_tso_segment(soc->osdev,
  125. tx_desc->tso_desc, is_last_seg);
  126. }
  127. }
  128. /**
  129. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  130. * back to the freelist
  131. *
  132. * @soc - soc device handle
  133. * @tx_desc - Tx software descriptor
  134. */
  135. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  136. struct dp_tx_desc_s *tx_desc)
  137. {
  138. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  139. if (qdf_unlikely(!tx_desc->tso_desc)) {
  140. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  141. "%s %d TSO desc is NULL!",
  142. __func__, __LINE__);
  143. qdf_assert(0);
  144. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  145. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  146. "%s %d TSO num desc is NULL!",
  147. __func__, __LINE__);
  148. qdf_assert(0);
  149. } else {
  150. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  151. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  152. /* Add the tso num segment into the free list */
  153. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  154. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  155. tx_desc->tso_num_desc);
  156. tx_desc->tso_num_desc = NULL;
  157. }
  158. /* Add the tso segment into the free list*/
  159. dp_tx_tso_desc_free(soc,
  160. tx_desc->pool_id, tx_desc->tso_desc);
  161. tx_desc->tso_desc = NULL;
  162. }
  163. }
  164. #else
  165. static void dp_tx_tso_unmap_segment(struct dp_soc *soc,
  166. struct dp_tx_desc_s *tx_desc)
  167. {
  168. }
  169. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  170. struct dp_tx_desc_s *tx_desc)
  171. {
  172. }
  173. #endif
  174. /**
  175. * dp_tx_desc_release() - Release Tx Descriptor
  176. * @tx_desc : Tx Descriptor
  177. * @desc_pool_id: Descriptor Pool ID
  178. *
  179. * Deallocate all resources attached to Tx descriptor and free the Tx
  180. * descriptor.
  181. *
  182. * Return:
  183. */
  184. static void
  185. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  186. {
  187. struct dp_pdev *pdev = tx_desc->pdev;
  188. struct dp_soc *soc;
  189. uint8_t comp_status = 0;
  190. qdf_assert(pdev);
  191. soc = pdev->soc;
  192. if (tx_desc->frm_type == dp_tx_frm_tso)
  193. dp_tx_tso_desc_release(soc, tx_desc);
  194. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  195. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  196. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  197. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  198. qdf_atomic_dec(&pdev->num_tx_outstanding);
  199. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  200. qdf_atomic_dec(&pdev->num_tx_exception);
  201. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  202. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  203. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  204. else
  205. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  206. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  207. "Tx Completion Release desc %d status %d outstanding %d",
  208. tx_desc->id, comp_status,
  209. qdf_atomic_read(&pdev->num_tx_outstanding));
  210. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  211. return;
  212. }
  213. /**
  214. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  215. * @vdev: DP vdev Handle
  216. * @nbuf: skb
  217. *
  218. * Prepares and fills HTT metadata in the frame pre-header for special frames
  219. * that should be transmitted using varying transmit parameters.
  220. * There are 2 VDEV modes that currently needs this special metadata -
  221. * 1) Mesh Mode
  222. * 2) DSRC Mode
  223. *
  224. * Return: HTT metadata size
  225. *
  226. */
  227. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  228. uint32_t *meta_data)
  229. {
  230. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  231. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  232. uint8_t htt_desc_size;
  233. /* Size rounded of multiple of 8 bytes */
  234. uint8_t htt_desc_size_aligned;
  235. uint8_t *hdr = NULL;
  236. /*
  237. * Metadata - HTT MSDU Extension header
  238. */
  239. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  240. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  241. if (vdev->mesh_vdev) {
  242. /* Fill and add HTT metaheader */
  243. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  244. if (hdr == NULL) {
  245. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  246. "Error in filling HTT metadata\n");
  247. return 0;
  248. }
  249. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  250. } else if (vdev->opmode == wlan_op_mode_ocb) {
  251. /* Todo - Add support for DSRC */
  252. }
  253. return htt_desc_size_aligned;
  254. }
  255. /**
  256. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  257. * @tso_seg: TSO segment to process
  258. * @ext_desc: Pointer to MSDU extension descriptor
  259. *
  260. * Return: void
  261. */
  262. #if defined(FEATURE_TSO)
  263. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  264. void *ext_desc)
  265. {
  266. uint8_t num_frag;
  267. uint32_t tso_flags;
  268. /*
  269. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  270. * tcp_flag_mask
  271. *
  272. * Checksum enable flags are set in TCL descriptor and not in Extension
  273. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  274. */
  275. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  276. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  277. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  278. tso_seg->tso_flags.ip_len);
  279. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  280. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  281. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  282. uint32_t lo = 0;
  283. uint32_t hi = 0;
  284. qdf_dmaaddr_to_32s(
  285. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  286. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  287. tso_seg->tso_frags[num_frag].length);
  288. }
  289. return;
  290. }
  291. #else
  292. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  293. void *ext_desc)
  294. {
  295. return;
  296. }
  297. #endif
  298. #if defined(FEATURE_TSO)
  299. /**
  300. * dp_tx_free_tso_seg() - Loop through the tso segments
  301. * allocated and free them
  302. *
  303. * @soc: soc handle
  304. * @free_seg: list of tso segments
  305. * @msdu_info: msdu descriptor
  306. *
  307. * Return - void
  308. */
  309. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  310. struct qdf_tso_seg_elem_t *free_seg,
  311. struct dp_tx_msdu_info_s *msdu_info)
  312. {
  313. struct qdf_tso_seg_elem_t *next_seg;
  314. while (free_seg) {
  315. next_seg = free_seg->next;
  316. dp_tx_tso_desc_free(soc,
  317. msdu_info->tx_queue.desc_pool_id,
  318. free_seg);
  319. free_seg = next_seg;
  320. }
  321. }
  322. /**
  323. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  324. * allocated and free them
  325. *
  326. * @soc: soc handle
  327. * @free_seg: list of tso segments
  328. * @msdu_info: msdu descriptor
  329. * Return - void
  330. */
  331. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  332. struct qdf_tso_num_seg_elem_t *free_seg,
  333. struct dp_tx_msdu_info_s *msdu_info)
  334. {
  335. struct qdf_tso_num_seg_elem_t *next_seg;
  336. while (free_seg) {
  337. next_seg = free_seg->next;
  338. dp_tso_num_seg_free(soc,
  339. msdu_info->tx_queue.desc_pool_id,
  340. free_seg);
  341. free_seg = next_seg;
  342. }
  343. }
  344. /**
  345. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  346. * @vdev: virtual device handle
  347. * @msdu: network buffer
  348. * @msdu_info: meta data associated with the msdu
  349. *
  350. * Return: QDF_STATUS_SUCCESS success
  351. */
  352. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  353. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  354. {
  355. struct qdf_tso_seg_elem_t *tso_seg;
  356. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  357. struct dp_soc *soc = vdev->pdev->soc;
  358. struct qdf_tso_info_t *tso_info;
  359. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  360. tso_info = &msdu_info->u.tso_info;
  361. tso_info->curr_seg = NULL;
  362. tso_info->tso_seg_list = NULL;
  363. tso_info->num_segs = num_seg;
  364. msdu_info->frm_type = dp_tx_frm_tso;
  365. tso_info->tso_num_seg_list = NULL;
  366. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  367. while (num_seg) {
  368. tso_seg = dp_tx_tso_desc_alloc(
  369. soc, msdu_info->tx_queue.desc_pool_id);
  370. if (tso_seg) {
  371. tso_seg->next = tso_info->tso_seg_list;
  372. tso_info->tso_seg_list = tso_seg;
  373. num_seg--;
  374. } else {
  375. struct qdf_tso_seg_elem_t *free_seg =
  376. tso_info->tso_seg_list;
  377. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  378. return QDF_STATUS_E_NOMEM;
  379. }
  380. }
  381. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  382. tso_num_seg = dp_tso_num_seg_alloc(soc,
  383. msdu_info->tx_queue.desc_pool_id);
  384. if (tso_num_seg) {
  385. tso_num_seg->next = tso_info->tso_num_seg_list;
  386. tso_info->tso_num_seg_list = tso_num_seg;
  387. } else {
  388. /* Bug: free tso_num_seg and tso_seg */
  389. /* Free the already allocated num of segments */
  390. struct qdf_tso_seg_elem_t *free_seg =
  391. tso_info->tso_seg_list;
  392. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  393. __func__);
  394. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  395. return QDF_STATUS_E_NOMEM;
  396. }
  397. msdu_info->num_seg =
  398. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  399. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  400. msdu_info->num_seg);
  401. if (!(msdu_info->num_seg)) {
  402. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  403. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  404. msdu_info);
  405. return QDF_STATUS_E_INVAL;
  406. }
  407. tso_info->curr_seg = tso_info->tso_seg_list;
  408. return QDF_STATUS_SUCCESS;
  409. }
  410. #else
  411. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  412. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  413. {
  414. return QDF_STATUS_E_NOMEM;
  415. }
  416. #endif
  417. /**
  418. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  419. * @vdev: DP Vdev handle
  420. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  421. * @desc_pool_id: Descriptor Pool ID
  422. *
  423. * Return:
  424. */
  425. static
  426. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  427. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  428. {
  429. uint8_t i;
  430. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  431. struct dp_tx_seg_info_s *seg_info;
  432. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  433. struct dp_soc *soc = vdev->pdev->soc;
  434. /* Allocate an extension descriptor */
  435. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  436. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  437. if (!msdu_ext_desc) {
  438. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  439. return NULL;
  440. }
  441. if (msdu_info->exception_fw &&
  442. qdf_unlikely(vdev->mesh_vdev)) {
  443. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  444. &msdu_info->meta_data[0],
  445. sizeof(struct htt_tx_msdu_desc_ext2_t));
  446. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  447. }
  448. switch (msdu_info->frm_type) {
  449. case dp_tx_frm_sg:
  450. case dp_tx_frm_me:
  451. case dp_tx_frm_raw:
  452. seg_info = msdu_info->u.sg_info.curr_seg;
  453. /* Update the buffer pointers in MSDU Extension Descriptor */
  454. for (i = 0; i < seg_info->frag_cnt; i++) {
  455. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  456. seg_info->frags[i].paddr_lo,
  457. seg_info->frags[i].paddr_hi,
  458. seg_info->frags[i].len);
  459. }
  460. break;
  461. case dp_tx_frm_tso:
  462. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  463. &cached_ext_desc[0]);
  464. break;
  465. default:
  466. break;
  467. }
  468. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  469. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  470. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  471. msdu_ext_desc->vaddr);
  472. return msdu_ext_desc;
  473. }
  474. /**
  475. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  476. *
  477. * @skb: skb to be traced
  478. * @msdu_id: msdu_id of the packet
  479. * @vdev_id: vdev_id of the packet
  480. *
  481. * Return: None
  482. */
  483. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  484. uint8_t vdev_id)
  485. {
  486. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  487. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  488. DPTRACE(qdf_dp_trace_ptr(skb,
  489. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  490. QDF_TRACE_DEFAULT_PDEV_ID,
  491. qdf_nbuf_data_addr(skb),
  492. sizeof(qdf_nbuf_data(skb)),
  493. msdu_id, vdev_id));
  494. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  495. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  496. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  497. msdu_id, QDF_TX));
  498. }
  499. /**
  500. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  501. * @vdev: DP vdev handle
  502. * @nbuf: skb
  503. * @desc_pool_id: Descriptor pool ID
  504. * @meta_data: Metadata to the fw
  505. * @tx_exc_metadata: Handle that holds exception path metadata
  506. * Allocate and prepare Tx descriptor with msdu information.
  507. *
  508. * Return: Pointer to Tx Descriptor on success,
  509. * NULL on failure
  510. */
  511. static
  512. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  513. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  514. struct dp_tx_msdu_info_s *msdu_info,
  515. struct cdp_tx_exception_metadata *tx_exc_metadata)
  516. {
  517. uint8_t align_pad;
  518. uint8_t is_exception = 0;
  519. uint8_t htt_hdr_size;
  520. struct ether_header *eh;
  521. struct dp_tx_desc_s *tx_desc;
  522. struct dp_pdev *pdev = vdev->pdev;
  523. struct dp_soc *soc = pdev->soc;
  524. /* Allocate software Tx descriptor */
  525. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  526. if (qdf_unlikely(!tx_desc)) {
  527. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  528. return NULL;
  529. }
  530. /* Flow control/Congestion Control counters */
  531. qdf_atomic_inc(&pdev->num_tx_outstanding);
  532. /* Initialize the SW tx descriptor */
  533. tx_desc->nbuf = nbuf;
  534. tx_desc->frm_type = dp_tx_frm_std;
  535. tx_desc->tx_encap_type = (tx_exc_metadata ?
  536. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  537. tx_desc->vdev = vdev;
  538. tx_desc->pdev = pdev;
  539. tx_desc->msdu_ext_desc = NULL;
  540. tx_desc->pkt_offset = 0;
  541. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  542. /*
  543. * For special modes (vdev_type == ocb or mesh), data frames should be
  544. * transmitted using varying transmit parameters (tx spec) which include
  545. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  546. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  547. * These frames are sent as exception packets to firmware.
  548. *
  549. * HW requirement is that metadata should always point to a
  550. * 8-byte aligned address. So we add alignment pad to start of buffer.
  551. * HTT Metadata should be ensured to be multiple of 8-bytes,
  552. * to get 8-byte aligned start address along with align_pad added
  553. *
  554. * |-----------------------------|
  555. * | |
  556. * |-----------------------------| <-----Buffer Pointer Address given
  557. * | | ^ in HW descriptor (aligned)
  558. * | HTT Metadata | |
  559. * | | |
  560. * | | | Packet Offset given in descriptor
  561. * | | |
  562. * |-----------------------------| |
  563. * | Alignment Pad | v
  564. * |-----------------------------| <----- Actual buffer start address
  565. * | SKB Data | (Unaligned)
  566. * | |
  567. * | |
  568. * | |
  569. * | |
  570. * | |
  571. * |-----------------------------|
  572. */
  573. if (qdf_unlikely((msdu_info->exception_fw)) ||
  574. (vdev->opmode == wlan_op_mode_ocb)) {
  575. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  576. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  577. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  578. "qdf_nbuf_push_head failed\n");
  579. goto failure;
  580. }
  581. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  582. msdu_info->meta_data);
  583. if (htt_hdr_size == 0)
  584. goto failure;
  585. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  586. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  587. is_exception = 1;
  588. }
  589. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  590. qdf_nbuf_map(soc->osdev, nbuf,
  591. QDF_DMA_TO_DEVICE))) {
  592. /* Handle failure */
  593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  594. "qdf_nbuf_map failed\n");
  595. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  596. goto failure;
  597. }
  598. if (qdf_unlikely(vdev->nawds_enabled)) {
  599. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  600. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  601. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  602. is_exception = 1;
  603. }
  604. }
  605. #if !TQM_BYPASS_WAR
  606. if (is_exception || tx_exc_metadata)
  607. #endif
  608. {
  609. /* Temporary WAR due to TQM VP issues */
  610. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  611. qdf_atomic_inc(&pdev->num_tx_exception);
  612. }
  613. return tx_desc;
  614. failure:
  615. dp_tx_desc_release(tx_desc, desc_pool_id);
  616. return NULL;
  617. }
  618. /**
  619. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  620. * @vdev: DP vdev handle
  621. * @nbuf: skb
  622. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  623. * @desc_pool_id : Descriptor Pool ID
  624. *
  625. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  626. * information. For frames wth fragments, allocate and prepare
  627. * an MSDU extension descriptor
  628. *
  629. * Return: Pointer to Tx Descriptor on success,
  630. * NULL on failure
  631. */
  632. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  633. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  634. uint8_t desc_pool_id)
  635. {
  636. struct dp_tx_desc_s *tx_desc;
  637. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  638. struct dp_pdev *pdev = vdev->pdev;
  639. struct dp_soc *soc = pdev->soc;
  640. /* Allocate software Tx descriptor */
  641. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  642. if (!tx_desc) {
  643. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  644. return NULL;
  645. }
  646. /* Flow control/Congestion Control counters */
  647. qdf_atomic_inc(&pdev->num_tx_outstanding);
  648. /* Initialize the SW tx descriptor */
  649. tx_desc->nbuf = nbuf;
  650. tx_desc->frm_type = msdu_info->frm_type;
  651. tx_desc->tx_encap_type = vdev->tx_encap_type;
  652. tx_desc->vdev = vdev;
  653. tx_desc->pdev = pdev;
  654. tx_desc->pkt_offset = 0;
  655. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  656. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  657. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  658. /* Handle scattered frames - TSO/SG/ME */
  659. /* Allocate and prepare an extension descriptor for scattered frames */
  660. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  661. if (!msdu_ext_desc) {
  662. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  663. "%s Tx Extension Descriptor Alloc Fail\n",
  664. __func__);
  665. goto failure;
  666. }
  667. #if TQM_BYPASS_WAR
  668. /* Temporary WAR due to TQM VP issues */
  669. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  670. qdf_atomic_inc(&pdev->num_tx_exception);
  671. #endif
  672. if (qdf_unlikely(msdu_info->exception_fw))
  673. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  674. tx_desc->msdu_ext_desc = msdu_ext_desc;
  675. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  676. return tx_desc;
  677. failure:
  678. dp_tx_desc_release(tx_desc, desc_pool_id);
  679. return NULL;
  680. }
  681. /**
  682. * dp_tx_prepare_raw() - Prepare RAW packet TX
  683. * @vdev: DP vdev handle
  684. * @nbuf: buffer pointer
  685. * @seg_info: Pointer to Segment info Descriptor to be prepared
  686. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  687. * descriptor
  688. *
  689. * Return:
  690. */
  691. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  692. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  693. {
  694. qdf_nbuf_t curr_nbuf = NULL;
  695. uint16_t total_len = 0;
  696. qdf_dma_addr_t paddr;
  697. int32_t i;
  698. int32_t mapped_buf_num = 0;
  699. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  700. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  701. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  702. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  703. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  704. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  705. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  706. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  707. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  708. QDF_DMA_TO_DEVICE)) {
  709. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  710. "%s dma map error \n", __func__);
  711. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  712. mapped_buf_num = i;
  713. goto error;
  714. }
  715. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  716. seg_info->frags[i].paddr_lo = paddr;
  717. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  718. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  719. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  720. total_len += qdf_nbuf_len(curr_nbuf);
  721. }
  722. seg_info->frag_cnt = i;
  723. seg_info->total_len = total_len;
  724. seg_info->next = NULL;
  725. sg_info->curr_seg = seg_info;
  726. msdu_info->frm_type = dp_tx_frm_raw;
  727. msdu_info->num_seg = 1;
  728. return nbuf;
  729. error:
  730. i = 0;
  731. while (nbuf) {
  732. curr_nbuf = nbuf;
  733. if (i < mapped_buf_num) {
  734. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  735. i++;
  736. }
  737. nbuf = qdf_nbuf_next(nbuf);
  738. qdf_nbuf_free(curr_nbuf);
  739. }
  740. return NULL;
  741. }
  742. /**
  743. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  744. * @soc: DP Soc Handle
  745. * @vdev: DP vdev handle
  746. * @tx_desc: Tx Descriptor Handle
  747. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  748. * @fw_metadata: Metadata to send to Target Firmware along with frame
  749. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  750. * @tx_exc_metadata: Handle that holds exception path meta data
  751. *
  752. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  753. * from software Tx descriptor
  754. *
  755. * Return:
  756. */
  757. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  758. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  759. uint16_t fw_metadata, uint8_t ring_id,
  760. struct cdp_tx_exception_metadata
  761. *tx_exc_metadata)
  762. {
  763. uint8_t type;
  764. uint16_t length;
  765. void *hal_tx_desc, *hal_tx_desc_cached;
  766. qdf_dma_addr_t dma_addr;
  767. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  768. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  769. tx_exc_metadata->sec_type : vdev->sec_type);
  770. /* Return Buffer Manager ID */
  771. uint8_t bm_id = ring_id;
  772. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  773. hal_tx_desc_cached = (void *) cached_desc;
  774. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  775. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  776. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  777. type = HAL_TX_BUF_TYPE_EXT_DESC;
  778. dma_addr = tx_desc->msdu_ext_desc->paddr;
  779. } else {
  780. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  781. type = HAL_TX_BUF_TYPE_BUFFER;
  782. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  783. }
  784. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  785. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  786. dma_addr , bm_id, tx_desc->id, type);
  787. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id))
  788. return QDF_STATUS_E_RESOURCES;
  789. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  790. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  791. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  792. hal_tx_desc_set_lmac_id(hal_tx_desc_cached,
  793. HAL_TX_DESC_DEFAULT_LMAC_ID);
  794. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  795. vdev->dscp_tid_map_id);
  796. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  797. sec_type_map[sec_type]);
  798. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  799. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  800. __func__, length, type, (uint64_t)dma_addr,
  801. tx_desc->pkt_offset, tx_desc->id);
  802. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  803. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  804. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  805. vdev->hal_desc_addr_search_flags);
  806. /* verify checksum offload configuration*/
  807. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  808. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  809. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  810. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  811. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  812. }
  813. if (tid != HTT_TX_EXT_TID_INVALID)
  814. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  815. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  816. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  817. /* Sync cached descriptor with HW */
  818. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  819. if (!hal_tx_desc) {
  820. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  821. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  822. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  823. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  824. return QDF_STATUS_E_RESOURCES;
  825. }
  826. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  827. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  828. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  829. /*
  830. * If one packet is enqueued in HW, PM usage count needs to be
  831. * incremented by one to prevent future runtime suspend. This
  832. * should be tied with the success of enqueuing. It will be
  833. * decremented after the packet has been sent.
  834. */
  835. hif_pm_runtime_get_noresume(soc->hif_handle);
  836. return QDF_STATUS_SUCCESS;
  837. }
  838. /**
  839. * dp_cce_classify() - Classify the frame based on CCE rules
  840. * @vdev: DP vdev handle
  841. * @nbuf: skb
  842. *
  843. * Classify frames based on CCE rules
  844. * Return: bool( true if classified,
  845. * else false)
  846. */
  847. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  848. {
  849. struct ether_header *eh = NULL;
  850. uint16_t ether_type;
  851. qdf_llc_t *llcHdr;
  852. qdf_nbuf_t nbuf_clone = NULL;
  853. qdf_dot3_qosframe_t *qos_wh = NULL;
  854. /* for mesh packets don't do any classification */
  855. if (qdf_unlikely(vdev->mesh_vdev))
  856. return false;
  857. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  858. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  859. ether_type = eh->ether_type;
  860. llcHdr = (qdf_llc_t *)(nbuf->data +
  861. sizeof(struct ether_header));
  862. } else {
  863. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  864. /* For encrypted packets don't do any classification */
  865. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  866. return false;
  867. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  868. if (qdf_unlikely(
  869. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  870. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  871. ether_type = *(uint16_t *)(nbuf->data
  872. + QDF_IEEE80211_4ADDR_HDR_LEN
  873. + sizeof(qdf_llc_t)
  874. - sizeof(ether_type));
  875. llcHdr = (qdf_llc_t *)(nbuf->data +
  876. QDF_IEEE80211_4ADDR_HDR_LEN);
  877. } else {
  878. ether_type = *(uint16_t *)(nbuf->data
  879. + QDF_IEEE80211_3ADDR_HDR_LEN
  880. + sizeof(qdf_llc_t)
  881. - sizeof(ether_type));
  882. llcHdr = (qdf_llc_t *)(nbuf->data +
  883. QDF_IEEE80211_3ADDR_HDR_LEN);
  884. }
  885. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  886. && (ether_type ==
  887. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  888. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  889. return true;
  890. }
  891. }
  892. return false;
  893. }
  894. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  895. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  896. sizeof(*llcHdr));
  897. nbuf_clone = qdf_nbuf_clone(nbuf);
  898. if (qdf_unlikely(nbuf_clone)) {
  899. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  900. if (ether_type == htons(ETHERTYPE_8021Q)) {
  901. qdf_nbuf_pull_head(nbuf_clone,
  902. sizeof(qdf_net_vlanhdr_t));
  903. }
  904. }
  905. } else {
  906. if (ether_type == htons(ETHERTYPE_8021Q)) {
  907. nbuf_clone = qdf_nbuf_clone(nbuf);
  908. if (qdf_unlikely(nbuf_clone)) {
  909. qdf_nbuf_pull_head(nbuf_clone,
  910. sizeof(qdf_net_vlanhdr_t));
  911. }
  912. }
  913. }
  914. if (qdf_unlikely(nbuf_clone))
  915. nbuf = nbuf_clone;
  916. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  917. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  918. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  919. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  920. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  921. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  922. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  923. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  924. if (qdf_unlikely(nbuf_clone != NULL))
  925. qdf_nbuf_free(nbuf_clone);
  926. return true;
  927. }
  928. if (qdf_unlikely(nbuf_clone != NULL))
  929. qdf_nbuf_free(nbuf_clone);
  930. return false;
  931. }
  932. /**
  933. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  934. * @vdev: DP vdev handle
  935. * @nbuf: skb
  936. *
  937. * Extract the DSCP or PCP information from frame and map into TID value.
  938. * Software based TID classification is required when more than 2 DSCP-TID
  939. * mapping tables are needed.
  940. * Hardware supports 2 DSCP-TID mapping tables
  941. *
  942. * Return: void
  943. */
  944. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  945. struct dp_tx_msdu_info_s *msdu_info)
  946. {
  947. uint8_t tos = 0, dscp_tid_override = 0;
  948. uint8_t *hdr_ptr, *L3datap;
  949. uint8_t is_mcast = 0;
  950. struct ether_header *eh = NULL;
  951. qdf_ethervlan_header_t *evh = NULL;
  952. uint16_t ether_type;
  953. qdf_llc_t *llcHdr;
  954. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  955. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  956. if (vdev->dscp_tid_map_id <= 1)
  957. return;
  958. /* for mesh packets don't do any classification */
  959. if (qdf_unlikely(vdev->mesh_vdev))
  960. return;
  961. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  962. eh = (struct ether_header *) nbuf->data;
  963. hdr_ptr = eh->ether_dhost;
  964. L3datap = hdr_ptr + sizeof(struct ether_header);
  965. } else {
  966. qdf_dot3_qosframe_t *qos_wh =
  967. (qdf_dot3_qosframe_t *) nbuf->data;
  968. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  969. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  970. return;
  971. }
  972. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  973. ether_type = eh->ether_type;
  974. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  975. /*
  976. * Check if packet is dot3 or eth2 type.
  977. */
  978. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  979. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  980. sizeof(*llcHdr));
  981. if (ether_type == htons(ETHERTYPE_8021Q)) {
  982. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  983. sizeof(*llcHdr);
  984. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  985. + sizeof(*llcHdr) +
  986. sizeof(qdf_net_vlanhdr_t));
  987. } else {
  988. L3datap = hdr_ptr + sizeof(struct ether_header) +
  989. sizeof(*llcHdr);
  990. }
  991. } else {
  992. if (ether_type == htons(ETHERTYPE_8021Q)) {
  993. evh = (qdf_ethervlan_header_t *) eh;
  994. ether_type = evh->ether_type;
  995. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  996. }
  997. }
  998. /*
  999. * Find priority from IP TOS DSCP field
  1000. */
  1001. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1002. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1003. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1004. /* Only for unicast frames */
  1005. if (!is_mcast) {
  1006. /* send it on VO queue */
  1007. msdu_info->tid = DP_VO_TID;
  1008. }
  1009. } else {
  1010. /*
  1011. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1012. * from TOS byte.
  1013. */
  1014. tos = ip->ip_tos;
  1015. dscp_tid_override = 1;
  1016. }
  1017. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1018. /* TODO
  1019. * use flowlabel
  1020. *igmpmld cases to be handled in phase 2
  1021. */
  1022. unsigned long ver_pri_flowlabel;
  1023. unsigned long pri;
  1024. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1025. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1026. DP_IPV6_PRIORITY_SHIFT;
  1027. tos = pri;
  1028. dscp_tid_override = 1;
  1029. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1030. msdu_info->tid = DP_VO_TID;
  1031. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1032. /* Only for unicast frames */
  1033. if (!is_mcast) {
  1034. /* send ucast arp on VO queue */
  1035. msdu_info->tid = DP_VO_TID;
  1036. }
  1037. }
  1038. /*
  1039. * Assign all MCAST packets to BE
  1040. */
  1041. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1042. if (is_mcast) {
  1043. tos = 0;
  1044. dscp_tid_override = 1;
  1045. }
  1046. }
  1047. if (dscp_tid_override == 1) {
  1048. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1049. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1050. }
  1051. return;
  1052. }
  1053. #ifdef CONVERGED_TDLS_ENABLE
  1054. /**
  1055. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1056. * @tx_desc: TX descriptor
  1057. *
  1058. * Return: None
  1059. */
  1060. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1061. {
  1062. if (tx_desc->vdev) {
  1063. if (tx_desc->vdev->is_tdls_frame)
  1064. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1065. tx_desc->vdev->is_tdls_frame = false;
  1066. }
  1067. }
  1068. /**
  1069. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1070. * @tx_desc: TX descriptor
  1071. * @vdev: datapath vdev handle
  1072. *
  1073. * Return: None
  1074. */
  1075. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1076. struct dp_vdev *vdev)
  1077. {
  1078. struct hal_tx_completion_status ts = {0};
  1079. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1080. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1081. if (vdev->tx_non_std_data_callback.func) {
  1082. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1083. vdev->tx_non_std_data_callback.func(
  1084. vdev->tx_non_std_data_callback.ctxt,
  1085. nbuf, ts.status);
  1086. return;
  1087. }
  1088. }
  1089. #endif
  1090. /**
  1091. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1092. * @vdev: DP vdev handle
  1093. * @nbuf: skb
  1094. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1095. * @meta_data: Metadata to the fw
  1096. * @tx_q: Tx queue to be used for this Tx frame
  1097. * @peer_id: peer_id of the peer in case of NAWDS frames
  1098. * @tx_exc_metadata: Handle that holds exception path metadata
  1099. *
  1100. * Return: NULL on success,
  1101. * nbuf when it fails to send
  1102. */
  1103. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1104. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1105. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1106. {
  1107. struct dp_pdev *pdev = vdev->pdev;
  1108. struct dp_soc *soc = pdev->soc;
  1109. struct dp_tx_desc_s *tx_desc;
  1110. QDF_STATUS status;
  1111. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1112. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1113. uint16_t htt_tcl_metadata = 0;
  1114. uint8_t tid = msdu_info->tid;
  1115. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1116. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1117. msdu_info, tx_exc_metadata);
  1118. if (!tx_desc) {
  1119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1120. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1121. __func__, vdev, tx_q->desc_pool_id);
  1122. return nbuf;
  1123. }
  1124. if (qdf_unlikely(soc->cce_disable)) {
  1125. if (dp_cce_classify(vdev, nbuf) == true) {
  1126. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1127. tid = DP_VO_TID;
  1128. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1129. }
  1130. }
  1131. dp_tx_update_tdls_flags(tx_desc);
  1132. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1133. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1134. "%s %d : HAL RING Access Failed -- %pK\n",
  1135. __func__, __LINE__, hal_srng);
  1136. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1137. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1138. goto fail_return;
  1139. }
  1140. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1141. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1142. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1143. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1144. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1145. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1146. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1147. peer_id);
  1148. } else
  1149. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1150. if (msdu_info->exception_fw) {
  1151. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1152. }
  1153. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1154. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1155. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1156. if (status != QDF_STATUS_SUCCESS) {
  1157. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1158. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1159. __func__, tx_desc, tx_q->ring_id);
  1160. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1161. goto fail_return;
  1162. }
  1163. nbuf = NULL;
  1164. fail_return:
  1165. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1166. hal_srng_access_end(soc->hal_soc, hal_srng);
  1167. hif_pm_runtime_put(soc->hif_handle);
  1168. } else {
  1169. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1170. }
  1171. return nbuf;
  1172. }
  1173. /**
  1174. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1175. * @vdev: DP vdev handle
  1176. * @nbuf: skb
  1177. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1178. *
  1179. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1180. *
  1181. * Return: NULL on success,
  1182. * nbuf when it fails to send
  1183. */
  1184. #if QDF_LOCK_STATS
  1185. static noinline
  1186. #else
  1187. static
  1188. #endif
  1189. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1190. struct dp_tx_msdu_info_s *msdu_info)
  1191. {
  1192. uint8_t i;
  1193. struct dp_pdev *pdev = vdev->pdev;
  1194. struct dp_soc *soc = pdev->soc;
  1195. struct dp_tx_desc_s *tx_desc;
  1196. bool is_cce_classified = false;
  1197. QDF_STATUS status;
  1198. uint16_t htt_tcl_metadata = 0;
  1199. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1200. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1201. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1202. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1203. "%s %d : HAL RING Access Failed -- %pK\n",
  1204. __func__, __LINE__, hal_srng);
  1205. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1206. return nbuf;
  1207. }
  1208. if (qdf_unlikely(soc->cce_disable)) {
  1209. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1210. if (is_cce_classified) {
  1211. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1212. msdu_info->tid = DP_VO_TID;
  1213. }
  1214. }
  1215. if (msdu_info->frm_type == dp_tx_frm_me)
  1216. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1217. i = 0;
  1218. /* Print statement to track i and num_seg */
  1219. /*
  1220. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1221. * descriptors using information in msdu_info
  1222. */
  1223. while (i < msdu_info->num_seg) {
  1224. /*
  1225. * Setup Tx descriptor for an MSDU, and MSDU extension
  1226. * descriptor
  1227. */
  1228. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1229. tx_q->desc_pool_id);
  1230. if (!tx_desc) {
  1231. if (msdu_info->frm_type == dp_tx_frm_me) {
  1232. dp_tx_me_free_buf(pdev,
  1233. (void *)(msdu_info->u.sg_info
  1234. .curr_seg->frags[0].vaddr));
  1235. }
  1236. goto done;
  1237. }
  1238. if (msdu_info->frm_type == dp_tx_frm_me) {
  1239. tx_desc->me_buffer =
  1240. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1241. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1242. }
  1243. if (is_cce_classified)
  1244. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1245. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1246. if (msdu_info->exception_fw) {
  1247. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1248. }
  1249. /*
  1250. * Enqueue the Tx MSDU descriptor to HW for transmit
  1251. */
  1252. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1253. htt_tcl_metadata, tx_q->ring_id, NULL);
  1254. if (status != QDF_STATUS_SUCCESS) {
  1255. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1256. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1257. __func__, tx_desc, tx_q->ring_id);
  1258. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1259. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1260. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1261. goto done;
  1262. }
  1263. /*
  1264. * TODO
  1265. * if tso_info structure can be modified to have curr_seg
  1266. * as first element, following 2 blocks of code (for TSO and SG)
  1267. * can be combined into 1
  1268. */
  1269. /*
  1270. * For frames with multiple segments (TSO, ME), jump to next
  1271. * segment.
  1272. */
  1273. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1274. if (msdu_info->u.tso_info.curr_seg->next) {
  1275. msdu_info->u.tso_info.curr_seg =
  1276. msdu_info->u.tso_info.curr_seg->next;
  1277. /*
  1278. * If this is a jumbo nbuf, then increment the number of
  1279. * nbuf users for each additional segment of the msdu.
  1280. * This will ensure that the skb is freed only after
  1281. * receiving tx completion for all segments of an nbuf
  1282. */
  1283. qdf_nbuf_inc_users(nbuf);
  1284. /* Check with MCL if this is needed */
  1285. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1286. }
  1287. }
  1288. /*
  1289. * For Multicast-Unicast converted packets,
  1290. * each converted frame (for a client) is represented as
  1291. * 1 segment
  1292. */
  1293. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1294. (msdu_info->frm_type == dp_tx_frm_me)) {
  1295. if (msdu_info->u.sg_info.curr_seg->next) {
  1296. msdu_info->u.sg_info.curr_seg =
  1297. msdu_info->u.sg_info.curr_seg->next;
  1298. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1299. }
  1300. }
  1301. i++;
  1302. }
  1303. nbuf = NULL;
  1304. done:
  1305. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1306. hal_srng_access_end(soc->hal_soc, hal_srng);
  1307. hif_pm_runtime_put(soc->hif_handle);
  1308. } else {
  1309. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1310. }
  1311. return nbuf;
  1312. }
  1313. /**
  1314. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1315. * for SG frames
  1316. * @vdev: DP vdev handle
  1317. * @nbuf: skb
  1318. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1319. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1320. *
  1321. * Return: NULL on success,
  1322. * nbuf when it fails to send
  1323. */
  1324. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1325. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1326. {
  1327. uint32_t cur_frag, nr_frags;
  1328. qdf_dma_addr_t paddr;
  1329. struct dp_tx_sg_info_s *sg_info;
  1330. sg_info = &msdu_info->u.sg_info;
  1331. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1332. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1333. QDF_DMA_TO_DEVICE)) {
  1334. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1335. "dma map error\n");
  1336. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1337. qdf_nbuf_free(nbuf);
  1338. return NULL;
  1339. }
  1340. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1341. seg_info->frags[0].paddr_lo = paddr;
  1342. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1343. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1344. seg_info->frags[0].vaddr = (void *) nbuf;
  1345. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1346. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1347. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1348. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1349. "frag dma map error\n");
  1350. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1351. qdf_nbuf_free(nbuf);
  1352. return NULL;
  1353. }
  1354. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1355. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1356. seg_info->frags[cur_frag + 1].paddr_hi =
  1357. ((uint64_t) paddr) >> 32;
  1358. seg_info->frags[cur_frag + 1].len =
  1359. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1360. }
  1361. seg_info->frag_cnt = (cur_frag + 1);
  1362. seg_info->total_len = qdf_nbuf_len(nbuf);
  1363. seg_info->next = NULL;
  1364. sg_info->curr_seg = seg_info;
  1365. msdu_info->frm_type = dp_tx_frm_sg;
  1366. msdu_info->num_seg = 1;
  1367. return nbuf;
  1368. }
  1369. #ifdef MESH_MODE_SUPPORT
  1370. /**
  1371. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1372. and prepare msdu_info for mesh frames.
  1373. * @vdev: DP vdev handle
  1374. * @nbuf: skb
  1375. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1376. *
  1377. * Return: NULL on failure,
  1378. * nbuf when extracted successfully
  1379. */
  1380. static
  1381. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1382. struct dp_tx_msdu_info_s *msdu_info)
  1383. {
  1384. struct meta_hdr_s *mhdr;
  1385. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1386. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1387. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1388. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1389. msdu_info->exception_fw = 0;
  1390. goto remove_meta_hdr;
  1391. }
  1392. msdu_info->exception_fw = 1;
  1393. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1394. meta_data->host_tx_desc_pool = 1;
  1395. meta_data->update_peer_cache = 1;
  1396. meta_data->learning_frame = 1;
  1397. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1398. meta_data->power = mhdr->power;
  1399. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1400. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1401. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1402. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1403. meta_data->dyn_bw = 1;
  1404. meta_data->valid_pwr = 1;
  1405. meta_data->valid_mcs_mask = 1;
  1406. meta_data->valid_nss_mask = 1;
  1407. meta_data->valid_preamble_type = 1;
  1408. meta_data->valid_retries = 1;
  1409. meta_data->valid_bw_info = 1;
  1410. }
  1411. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1412. meta_data->encrypt_type = 0;
  1413. meta_data->valid_encrypt_type = 1;
  1414. meta_data->learning_frame = 0;
  1415. }
  1416. meta_data->valid_key_flags = 1;
  1417. meta_data->key_flags = (mhdr->keyix & 0x3);
  1418. remove_meta_hdr:
  1419. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1420. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1421. "qdf_nbuf_pull_head failed\n");
  1422. qdf_nbuf_free(nbuf);
  1423. return NULL;
  1424. }
  1425. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1426. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1427. else
  1428. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1429. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1430. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1431. " tid %d to_fw %d\n",
  1432. __func__, msdu_info->meta_data[0],
  1433. msdu_info->meta_data[1],
  1434. msdu_info->meta_data[2],
  1435. msdu_info->meta_data[3],
  1436. msdu_info->meta_data[4],
  1437. msdu_info->meta_data[5],
  1438. msdu_info->tid, msdu_info->exception_fw);
  1439. return nbuf;
  1440. }
  1441. #else
  1442. static
  1443. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1444. struct dp_tx_msdu_info_s *msdu_info)
  1445. {
  1446. return nbuf;
  1447. }
  1448. #endif
  1449. #ifdef DP_FEATURE_NAWDS_TX
  1450. /**
  1451. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1452. * @vdev: dp_vdev handle
  1453. * @nbuf: skb
  1454. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1455. * @tx_q: Tx queue to be used for this Tx frame
  1456. * @meta_data: Meta date for mesh
  1457. * @peer_id: peer_id of the peer in case of NAWDS frames
  1458. *
  1459. * return: NULL on success nbuf on failure
  1460. */
  1461. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1462. struct dp_tx_msdu_info_s *msdu_info)
  1463. {
  1464. struct dp_peer *peer = NULL;
  1465. struct dp_soc *soc = vdev->pdev->soc;
  1466. struct dp_ast_entry *ast_entry = NULL;
  1467. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1468. uint16_t peer_id = HTT_INVALID_PEER;
  1469. struct dp_peer *sa_peer = NULL;
  1470. qdf_nbuf_t nbuf_copy;
  1471. qdf_spin_lock_bh(&(soc->ast_lock));
  1472. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1473. if (ast_entry)
  1474. sa_peer = ast_entry->peer;
  1475. qdf_spin_unlock_bh(&(soc->ast_lock));
  1476. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1477. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1478. (peer->nawds_enabled)) {
  1479. if (sa_peer == peer) {
  1480. QDF_TRACE(QDF_MODULE_ID_DP,
  1481. QDF_TRACE_LEVEL_DEBUG,
  1482. " %s: broadcast multicast packet",
  1483. __func__);
  1484. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1485. continue;
  1486. }
  1487. nbuf_copy = qdf_nbuf_copy(nbuf);
  1488. if (!nbuf_copy) {
  1489. QDF_TRACE(QDF_MODULE_ID_DP,
  1490. QDF_TRACE_LEVEL_ERROR,
  1491. "nbuf copy failed");
  1492. }
  1493. peer_id = peer->peer_ids[0];
  1494. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1495. msdu_info, peer_id, NULL);
  1496. if (nbuf_copy != NULL) {
  1497. qdf_nbuf_free(nbuf_copy);
  1498. continue;
  1499. }
  1500. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1501. 1, qdf_nbuf_len(nbuf));
  1502. }
  1503. }
  1504. if (peer_id == HTT_INVALID_PEER)
  1505. return nbuf;
  1506. return NULL;
  1507. }
  1508. #endif
  1509. /**
  1510. * dp_check_exc_metadata() - Checks if parameters are valid
  1511. * @tx_exc - holds all exception path parameters
  1512. *
  1513. * Returns true when all the parameters are valid else false
  1514. *
  1515. */
  1516. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1517. {
  1518. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1519. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1520. tx_exc->sec_type > cdp_num_sec_types) {
  1521. return false;
  1522. }
  1523. return true;
  1524. }
  1525. /**
  1526. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1527. * @vap_dev: DP vdev handle
  1528. * @nbuf: skb
  1529. * @tx_exc_metadata: Handle that holds exception path meta data
  1530. *
  1531. * Entry point for Core Tx layer (DP_TX) invoked from
  1532. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1533. *
  1534. * Return: NULL on success,
  1535. * nbuf when it fails to send
  1536. */
  1537. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1538. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1539. {
  1540. struct ether_header *eh = NULL;
  1541. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1542. struct dp_tx_msdu_info_s msdu_info;
  1543. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1544. msdu_info.tid = tx_exc_metadata->tid;
  1545. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1546. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1547. "%s , skb %pM",
  1548. __func__, nbuf->data);
  1549. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1550. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1552. "Invalid parameters in exception path");
  1553. goto fail;
  1554. }
  1555. /* Basic sanity checks for unsupported packets */
  1556. /* MESH mode */
  1557. if (qdf_unlikely(vdev->mesh_vdev)) {
  1558. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1559. "Mesh mode is not supported in exception path");
  1560. goto fail;
  1561. }
  1562. /* TSO or SG */
  1563. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1564. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1565. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1566. "TSO and SG are not supported in exception path");
  1567. goto fail;
  1568. }
  1569. /* RAW */
  1570. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1571. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1572. "Raw frame is not supported in exception path");
  1573. goto fail;
  1574. }
  1575. /* Mcast enhancement*/
  1576. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1577. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1578. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1579. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1580. }
  1581. }
  1582. /*
  1583. * Get HW Queue to use for this frame.
  1584. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1585. * dedicated for data and 1 for command.
  1586. * "queue_id" maps to one hardware ring.
  1587. * With each ring, we also associate a unique Tx descriptor pool
  1588. * to minimize lock contention for these resources.
  1589. */
  1590. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1591. /* Reset the control block */
  1592. qdf_nbuf_reset_ctxt(nbuf);
  1593. /* Single linear frame */
  1594. /*
  1595. * If nbuf is a simple linear frame, use send_single function to
  1596. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1597. * SRNG. There is no need to setup a MSDU extension descriptor.
  1598. */
  1599. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1600. tx_exc_metadata->peer_id, tx_exc_metadata);
  1601. return nbuf;
  1602. fail:
  1603. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1604. "pkt send failed");
  1605. return nbuf;
  1606. }
  1607. /**
  1608. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1609. * @vap_dev: DP vdev handle
  1610. * @nbuf: skb
  1611. *
  1612. * Entry point for Core Tx layer (DP_TX) invoked from
  1613. * hard_start_xmit in OSIF/HDD
  1614. *
  1615. * Return: NULL on success,
  1616. * nbuf when it fails to send
  1617. */
  1618. #ifdef MESH_MODE_SUPPORT
  1619. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1620. {
  1621. struct meta_hdr_s *mhdr;
  1622. qdf_nbuf_t nbuf_mesh = NULL;
  1623. qdf_nbuf_t nbuf_clone = NULL;
  1624. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1625. uint8_t no_enc_frame = 0;
  1626. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1627. if (nbuf_mesh == NULL) {
  1628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1629. "qdf_nbuf_unshare failed\n");
  1630. return nbuf;
  1631. }
  1632. nbuf = nbuf_mesh;
  1633. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1634. if ((vdev->sec_type != cdp_sec_type_none) &&
  1635. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1636. no_enc_frame = 1;
  1637. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1638. !no_enc_frame) {
  1639. nbuf_clone = qdf_nbuf_clone(nbuf);
  1640. if (nbuf_clone == NULL) {
  1641. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1642. "qdf_nbuf_clone failed\n");
  1643. return nbuf;
  1644. }
  1645. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1646. }
  1647. if (nbuf_clone) {
  1648. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1649. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1650. } else {
  1651. qdf_nbuf_free(nbuf_clone);
  1652. }
  1653. }
  1654. if (no_enc_frame)
  1655. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1656. else
  1657. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1658. nbuf = dp_tx_send(vap_dev, nbuf);
  1659. if ((nbuf == NULL) && no_enc_frame) {
  1660. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1661. }
  1662. return nbuf;
  1663. }
  1664. #else
  1665. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1666. {
  1667. return dp_tx_send(vap_dev, nbuf);
  1668. }
  1669. #endif
  1670. /**
  1671. * dp_tx_send() - Transmit a frame on a given VAP
  1672. * @vap_dev: DP vdev handle
  1673. * @nbuf: skb
  1674. *
  1675. * Entry point for Core Tx layer (DP_TX) invoked from
  1676. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1677. * cases
  1678. *
  1679. * Return: NULL on success,
  1680. * nbuf when it fails to send
  1681. */
  1682. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1683. {
  1684. struct ether_header *eh = NULL;
  1685. struct dp_tx_msdu_info_s msdu_info;
  1686. struct dp_tx_seg_info_s seg_info;
  1687. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1688. uint16_t peer_id = HTT_INVALID_PEER;
  1689. qdf_nbuf_t nbuf_mesh = NULL;
  1690. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1691. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1692. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1693. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1694. "%s , skb %pM",
  1695. __func__, nbuf->data);
  1696. /*
  1697. * Set Default Host TID value to invalid TID
  1698. * (TID override disabled)
  1699. */
  1700. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1701. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1702. if (qdf_unlikely(vdev->mesh_vdev)) {
  1703. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1704. &msdu_info);
  1705. if (nbuf_mesh == NULL) {
  1706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1707. "Extracting mesh metadata failed\n");
  1708. return nbuf;
  1709. }
  1710. nbuf = nbuf_mesh;
  1711. }
  1712. /*
  1713. * Get HW Queue to use for this frame.
  1714. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1715. * dedicated for data and 1 for command.
  1716. * "queue_id" maps to one hardware ring.
  1717. * With each ring, we also associate a unique Tx descriptor pool
  1718. * to minimize lock contention for these resources.
  1719. */
  1720. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1721. /*
  1722. * TCL H/W supports 2 DSCP-TID mapping tables.
  1723. * Table 1 - Default DSCP-TID mapping table
  1724. * Table 2 - 1 DSCP-TID override table
  1725. *
  1726. * If we need a different DSCP-TID mapping for this vap,
  1727. * call tid_classify to extract DSCP/ToS from frame and
  1728. * map to a TID and store in msdu_info. This is later used
  1729. * to fill in TCL Input descriptor (per-packet TID override).
  1730. */
  1731. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1732. /* Reset the control block */
  1733. qdf_nbuf_reset_ctxt(nbuf);
  1734. /*
  1735. * Classify the frame and call corresponding
  1736. * "prepare" function which extracts the segment (TSO)
  1737. * and fragmentation information (for TSO , SG, ME, or Raw)
  1738. * into MSDU_INFO structure which is later used to fill
  1739. * SW and HW descriptors.
  1740. */
  1741. if (qdf_nbuf_is_tso(nbuf)) {
  1742. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1743. "%s TSO frame %pK\n", __func__, vdev);
  1744. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1745. qdf_nbuf_len(nbuf));
  1746. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1747. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1748. return nbuf;
  1749. }
  1750. goto send_multiple;
  1751. }
  1752. /* SG */
  1753. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1754. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1755. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1756. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1757. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1758. qdf_nbuf_len(nbuf));
  1759. goto send_multiple;
  1760. }
  1761. #ifdef ATH_SUPPORT_IQUE
  1762. /* Mcast to Ucast Conversion*/
  1763. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1764. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1765. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1766. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1767. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1768. DP_STATS_INC_PKT(vdev,
  1769. tx_i.mcast_en.mcast_pkt, 1,
  1770. qdf_nbuf_len(nbuf));
  1771. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1772. QDF_STATUS_SUCCESS) {
  1773. return NULL;
  1774. }
  1775. }
  1776. }
  1777. #endif
  1778. /* RAW */
  1779. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1780. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1781. if (nbuf == NULL)
  1782. return NULL;
  1783. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1784. "%s Raw frame %pK\n", __func__, vdev);
  1785. goto send_multiple;
  1786. }
  1787. /* Single linear frame */
  1788. /*
  1789. * If nbuf is a simple linear frame, use send_single function to
  1790. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1791. * SRNG. There is no need to setup a MSDU extension descriptor.
  1792. */
  1793. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1794. return nbuf;
  1795. send_multiple:
  1796. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1797. return nbuf;
  1798. }
  1799. /**
  1800. * dp_tx_reinject_handler() - Tx Reinject Handler
  1801. * @tx_desc: software descriptor head pointer
  1802. * @status : Tx completion status from HTT descriptor
  1803. *
  1804. * This function reinjects frames back to Target.
  1805. * Todo - Host queue needs to be added
  1806. *
  1807. * Return: none
  1808. */
  1809. static
  1810. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1811. {
  1812. struct dp_vdev *vdev;
  1813. struct dp_peer *peer = NULL;
  1814. uint32_t peer_id = HTT_INVALID_PEER;
  1815. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1816. qdf_nbuf_t nbuf_copy = NULL;
  1817. struct dp_tx_msdu_info_s msdu_info;
  1818. struct dp_peer *sa_peer = NULL;
  1819. struct dp_ast_entry *ast_entry = NULL;
  1820. struct dp_soc *soc = NULL;
  1821. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1822. #ifdef WDS_VENDOR_EXTENSION
  1823. int is_mcast = 0, is_ucast = 0;
  1824. int num_peers_3addr = 0;
  1825. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1826. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1827. #endif
  1828. vdev = tx_desc->vdev;
  1829. soc = vdev->pdev->soc;
  1830. qdf_assert(vdev);
  1831. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1832. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1833. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1834. "%s Tx reinject path\n", __func__);
  1835. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1836. qdf_nbuf_len(tx_desc->nbuf));
  1837. qdf_spin_lock_bh(&(soc->ast_lock));
  1838. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1839. if (ast_entry)
  1840. sa_peer = ast_entry->peer;
  1841. qdf_spin_unlock_bh(&(soc->ast_lock));
  1842. #ifdef WDS_VENDOR_EXTENSION
  1843. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1844. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1845. } else {
  1846. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1847. }
  1848. is_ucast = !is_mcast;
  1849. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1850. if (peer->bss_peer)
  1851. continue;
  1852. /* Detect wds peers that use 3-addr framing for mcast.
  1853. * if there are any, the bss_peer is used to send the
  1854. * the mcast frame using 3-addr format. all wds enabled
  1855. * peers that use 4-addr framing for mcast frames will
  1856. * be duplicated and sent as 4-addr frames below.
  1857. */
  1858. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1859. num_peers_3addr = 1;
  1860. break;
  1861. }
  1862. }
  1863. #endif
  1864. if (qdf_unlikely(vdev->mesh_vdev)) {
  1865. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1866. } else {
  1867. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1868. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1869. #ifdef WDS_VENDOR_EXTENSION
  1870. /*
  1871. * . if 3-addr STA, then send on BSS Peer
  1872. * . if Peer WDS enabled and accept 4-addr mcast,
  1873. * send mcast on that peer only
  1874. * . if Peer WDS enabled and accept 4-addr ucast,
  1875. * send ucast on that peer only
  1876. */
  1877. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1878. (peer->wds_enabled &&
  1879. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1880. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1881. #else
  1882. ((peer->bss_peer &&
  1883. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1884. peer->nawds_enabled)) {
  1885. #endif
  1886. peer_id = DP_INVALID_PEER;
  1887. if (peer->nawds_enabled) {
  1888. peer_id = peer->peer_ids[0];
  1889. if (sa_peer == peer) {
  1890. QDF_TRACE(
  1891. QDF_MODULE_ID_DP,
  1892. QDF_TRACE_LEVEL_DEBUG,
  1893. " %s: multicast packet",
  1894. __func__);
  1895. DP_STATS_INC(peer,
  1896. tx.nawds_mcast_drop, 1);
  1897. continue;
  1898. }
  1899. }
  1900. nbuf_copy = qdf_nbuf_copy(nbuf);
  1901. if (!nbuf_copy) {
  1902. QDF_TRACE(QDF_MODULE_ID_DP,
  1903. QDF_TRACE_LEVEL_DEBUG,
  1904. FL("nbuf copy failed"));
  1905. break;
  1906. }
  1907. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1908. nbuf_copy,
  1909. &msdu_info,
  1910. peer_id,
  1911. NULL);
  1912. if (nbuf_copy) {
  1913. QDF_TRACE(QDF_MODULE_ID_DP,
  1914. QDF_TRACE_LEVEL_DEBUG,
  1915. FL("pkt send failed"));
  1916. qdf_nbuf_free(nbuf_copy);
  1917. } else {
  1918. if (peer_id != DP_INVALID_PEER)
  1919. DP_STATS_INC_PKT(peer,
  1920. tx.nawds_mcast,
  1921. 1, qdf_nbuf_len(nbuf));
  1922. }
  1923. }
  1924. }
  1925. }
  1926. if (vdev->nawds_enabled) {
  1927. peer_id = DP_INVALID_PEER;
  1928. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1929. 1, qdf_nbuf_len(nbuf));
  1930. nbuf = dp_tx_send_msdu_single(vdev,
  1931. nbuf,
  1932. &msdu_info,
  1933. peer_id, NULL);
  1934. if (nbuf) {
  1935. QDF_TRACE(QDF_MODULE_ID_DP,
  1936. QDF_TRACE_LEVEL_DEBUG,
  1937. FL("pkt send failed"));
  1938. qdf_nbuf_free(nbuf);
  1939. }
  1940. } else
  1941. qdf_nbuf_free(nbuf);
  1942. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1943. }
  1944. /**
  1945. * dp_tx_inspect_handler() - Tx Inspect Handler
  1946. * @tx_desc: software descriptor head pointer
  1947. * @status : Tx completion status from HTT descriptor
  1948. *
  1949. * Handles Tx frames sent back to Host for inspection
  1950. * (ProxyARP)
  1951. *
  1952. * Return: none
  1953. */
  1954. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1955. {
  1956. struct dp_soc *soc;
  1957. struct dp_pdev *pdev = tx_desc->pdev;
  1958. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1959. "%s Tx inspect path\n",
  1960. __func__);
  1961. qdf_assert(pdev);
  1962. soc = pdev->soc;
  1963. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1964. qdf_nbuf_len(tx_desc->nbuf));
  1965. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1966. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1967. }
  1968. #ifdef FEATURE_PERPKT_INFO
  1969. /**
  1970. * dp_get_completion_indication_for_stack() - send completion to stack
  1971. * @soc : dp_soc handle
  1972. * @pdev: dp_pdev handle
  1973. * @peer_id: peer_id of the peer for which completion came
  1974. * @ppdu_id: ppdu_id
  1975. * @first_msdu: first msdu
  1976. * @last_msdu: last msdu
  1977. * @netbuf: Buffer pointer for free
  1978. *
  1979. * This function is used for indication whether buffer needs to be
  1980. * send to stack for free or not
  1981. */
  1982. QDF_STATUS
  1983. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1984. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1985. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1986. {
  1987. struct tx_capture_hdr *ppdu_hdr;
  1988. struct dp_peer *peer = NULL;
  1989. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1990. return QDF_STATUS_E_NOSUPPORT;
  1991. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1992. dp_peer_find_by_id(soc, peer_id);
  1993. if (!peer) {
  1994. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1995. FL("Peer Invalid"));
  1996. return QDF_STATUS_E_INVAL;
  1997. }
  1998. if (pdev->mcopy_mode) {
  1999. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2000. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2001. return QDF_STATUS_E_INVAL;
  2002. }
  2003. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2004. pdev->m_copy_id.tx_peer_id = peer_id;
  2005. }
  2006. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  2007. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2008. FL("No headroom"));
  2009. return QDF_STATUS_E_NOMEM;
  2010. }
  2011. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2012. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2013. IEEE80211_ADDR_LEN);
  2014. ppdu_hdr->ppdu_id = ppdu_id;
  2015. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2016. IEEE80211_ADDR_LEN);
  2017. ppdu_hdr->peer_id = peer_id;
  2018. ppdu_hdr->first_msdu = first_msdu;
  2019. ppdu_hdr->last_msdu = last_msdu;
  2020. return QDF_STATUS_SUCCESS;
  2021. }
  2022. /**
  2023. * dp_send_completion_to_stack() - send completion to stack
  2024. * @soc : dp_soc handle
  2025. * @pdev: dp_pdev handle
  2026. * @peer_id: peer_id of the peer for which completion came
  2027. * @ppdu_id: ppdu_id
  2028. * @netbuf: Buffer pointer for free
  2029. *
  2030. * This function is used to send completion to stack
  2031. * to free buffer
  2032. */
  2033. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2034. uint16_t peer_id, uint32_t ppdu_id,
  2035. qdf_nbuf_t netbuf)
  2036. {
  2037. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2038. netbuf, peer_id,
  2039. WDI_NO_VAL, pdev->pdev_id);
  2040. }
  2041. #else
  2042. static QDF_STATUS
  2043. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2044. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  2045. uint8_t last_msdu, qdf_nbuf_t netbuf)
  2046. {
  2047. return QDF_STATUS_E_NOSUPPORT;
  2048. }
  2049. static void
  2050. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2051. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2052. {
  2053. }
  2054. #endif
  2055. /**
  2056. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2057. * @soc: Soc handle
  2058. * @desc: software Tx descriptor to be processed
  2059. *
  2060. * Return: none
  2061. */
  2062. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2063. struct dp_tx_desc_s *desc)
  2064. {
  2065. struct dp_vdev *vdev = desc->vdev;
  2066. qdf_nbuf_t nbuf = desc->nbuf;
  2067. /* If it is TDLS mgmt, don't unmap or free the frame */
  2068. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2069. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2070. /* 0 : MSDU buffer, 1 : MLE */
  2071. if (desc->msdu_ext_desc) {
  2072. /* TSO free */
  2073. if (hal_tx_ext_desc_get_tso_enable(
  2074. desc->msdu_ext_desc->vaddr)) {
  2075. /* unmap eash TSO seg before free the nbuf */
  2076. dp_tx_tso_unmap_segment(soc, desc);
  2077. qdf_nbuf_free(nbuf);
  2078. return;
  2079. }
  2080. }
  2081. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2082. if (qdf_likely(!vdev->mesh_vdev))
  2083. qdf_nbuf_free(nbuf);
  2084. else {
  2085. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2086. qdf_nbuf_free(nbuf);
  2087. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2088. } else
  2089. vdev->osif_tx_free_ext((nbuf));
  2090. }
  2091. }
  2092. /**
  2093. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2094. * @vdev: pointer to dp dev handler
  2095. * @status : Tx completion status from HTT descriptor
  2096. *
  2097. * Handles MEC notify event sent from fw to Host
  2098. *
  2099. * Return: none
  2100. */
  2101. #ifdef FEATURE_WDS
  2102. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2103. {
  2104. struct dp_soc *soc;
  2105. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2106. struct dp_peer *peer;
  2107. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2108. if (!vdev->wds_enabled)
  2109. return;
  2110. soc = vdev->pdev->soc;
  2111. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2112. peer = TAILQ_FIRST(&vdev->peer_list);
  2113. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2114. if (!peer) {
  2115. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2116. FL("peer is NULL"));
  2117. return;
  2118. }
  2119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2120. "%s Tx MEC Handler\n",
  2121. __func__);
  2122. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2123. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2124. status[(DP_MAC_ADDR_LEN - 2) + i];
  2125. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2126. dp_peer_add_ast(soc,
  2127. peer,
  2128. mac_addr,
  2129. CDP_TXRX_AST_TYPE_MEC,
  2130. flags);
  2131. }
  2132. #endif
  2133. /**
  2134. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2135. * @tx_desc: software descriptor head pointer
  2136. * @status : Tx completion status from HTT descriptor
  2137. *
  2138. * This function will process HTT Tx indication messages from Target
  2139. *
  2140. * Return: none
  2141. */
  2142. static
  2143. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2144. {
  2145. uint8_t tx_status;
  2146. struct dp_pdev *pdev;
  2147. struct dp_vdev *vdev;
  2148. struct dp_soc *soc;
  2149. uint32_t *htt_status_word = (uint32_t *) status;
  2150. qdf_assert(tx_desc->pdev);
  2151. pdev = tx_desc->pdev;
  2152. vdev = tx_desc->vdev;
  2153. soc = pdev->soc;
  2154. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2155. switch (tx_status) {
  2156. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2157. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2158. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2159. {
  2160. dp_tx_comp_free_buf(soc, tx_desc);
  2161. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2162. break;
  2163. }
  2164. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2165. {
  2166. dp_tx_reinject_handler(tx_desc, status);
  2167. break;
  2168. }
  2169. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2170. {
  2171. dp_tx_inspect_handler(tx_desc, status);
  2172. break;
  2173. }
  2174. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2175. {
  2176. dp_tx_mec_handler(vdev, status);
  2177. break;
  2178. }
  2179. default:
  2180. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2181. "%s Invalid HTT tx_status %d\n",
  2182. __func__, tx_status);
  2183. break;
  2184. }
  2185. }
  2186. #ifdef MESH_MODE_SUPPORT
  2187. /**
  2188. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2189. * in mesh meta header
  2190. * @tx_desc: software descriptor head pointer
  2191. * @ts: pointer to tx completion stats
  2192. * Return: none
  2193. */
  2194. static
  2195. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2196. struct hal_tx_completion_status *ts)
  2197. {
  2198. struct meta_hdr_s *mhdr;
  2199. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2200. if (!tx_desc->msdu_ext_desc) {
  2201. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2203. "netbuf %pK offset %d\n",
  2204. netbuf, tx_desc->pkt_offset);
  2205. return;
  2206. }
  2207. }
  2208. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2210. "netbuf %pK offset %d\n", netbuf,
  2211. sizeof(struct meta_hdr_s));
  2212. return;
  2213. }
  2214. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2215. mhdr->rssi = ts->ack_frame_rssi;
  2216. mhdr->channel = tx_desc->pdev->operating_channel;
  2217. }
  2218. #else
  2219. static
  2220. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2221. struct hal_tx_completion_status *ts)
  2222. {
  2223. }
  2224. #endif
  2225. /**
  2226. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2227. * @peer: Handle to DP peer
  2228. * @ts: pointer to HAL Tx completion stats
  2229. * @length: MSDU length
  2230. *
  2231. * Return: None
  2232. */
  2233. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2234. struct hal_tx_completion_status *ts, uint32_t length)
  2235. {
  2236. struct dp_pdev *pdev = peer->vdev->pdev;
  2237. struct dp_soc *soc = pdev->soc;
  2238. uint8_t mcs, pkt_type;
  2239. mcs = ts->mcs;
  2240. pkt_type = ts->pkt_type;
  2241. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2242. return;
  2243. if (peer->bss_peer) {
  2244. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2245. } else {
  2246. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2247. }
  2248. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2249. DP_STATS_INCC_PKT(peer, tx.tx_success, 1, length,
  2250. (ts->status == HAL_TX_TQM_RR_FRAME_ACKED));
  2251. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2252. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2253. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2254. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2255. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2256. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2257. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2258. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2259. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2260. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2261. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2262. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2263. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2264. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2265. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2266. return;
  2267. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2268. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2269. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2270. if (!(soc->process_tx_status))
  2271. return;
  2272. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2273. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2274. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2275. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2276. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2277. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2278. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2279. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2280. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2281. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2282. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2283. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2284. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2285. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2286. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2287. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2288. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2289. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2290. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2291. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2292. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2293. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2294. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2295. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2296. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2297. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2298. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2299. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2300. soc->cdp_soc.ol_ops->update_dp_stats(pdev->ctrl_pdev,
  2301. &peer->stats, ts->peer_id,
  2302. UPDATE_PEER_STATS);
  2303. }
  2304. }
  2305. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2306. /**
  2307. * dp_tx_flow_pool_lock() - take flow pool lock
  2308. * @soc: core txrx main context
  2309. * @tx_desc: tx desc
  2310. *
  2311. * Return: None
  2312. */
  2313. static inline
  2314. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2315. struct dp_tx_desc_s *tx_desc)
  2316. {
  2317. struct dp_tx_desc_pool_s *pool;
  2318. uint8_t desc_pool_id;
  2319. desc_pool_id = tx_desc->pool_id;
  2320. pool = &soc->tx_desc[desc_pool_id];
  2321. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2322. }
  2323. /**
  2324. * dp_tx_flow_pool_unlock() - release flow pool lock
  2325. * @soc: core txrx main context
  2326. * @tx_desc: tx desc
  2327. *
  2328. * Return: None
  2329. */
  2330. static inline
  2331. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2332. struct dp_tx_desc_s *tx_desc)
  2333. {
  2334. struct dp_tx_desc_pool_s *pool;
  2335. uint8_t desc_pool_id;
  2336. desc_pool_id = tx_desc->pool_id;
  2337. pool = &soc->tx_desc[desc_pool_id];
  2338. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2339. }
  2340. #else
  2341. static inline
  2342. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2343. {
  2344. }
  2345. static inline
  2346. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2347. {
  2348. }
  2349. #endif
  2350. /**
  2351. * dp_tx_notify_completion() - Notify tx completion for this desc
  2352. * @soc: core txrx main context
  2353. * @tx_desc: tx desc
  2354. * @netbuf: buffer
  2355. *
  2356. * Return: none
  2357. */
  2358. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2359. struct dp_tx_desc_s *tx_desc,
  2360. qdf_nbuf_t netbuf)
  2361. {
  2362. void *osif_dev;
  2363. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2364. qdf_assert(tx_desc);
  2365. dp_tx_flow_pool_lock(soc, tx_desc);
  2366. if (!tx_desc->vdev ||
  2367. !tx_desc->vdev->osif_vdev) {
  2368. dp_tx_flow_pool_unlock(soc, tx_desc);
  2369. return;
  2370. }
  2371. osif_dev = tx_desc->vdev->osif_vdev;
  2372. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2373. dp_tx_flow_pool_unlock(soc, tx_desc);
  2374. if (tx_compl_cbk)
  2375. tx_compl_cbk(netbuf, osif_dev);
  2376. }
  2377. /**
  2378. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2379. * @tx_desc: software descriptor head pointer
  2380. * @length: packet length
  2381. *
  2382. * Return: none
  2383. */
  2384. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2385. uint32_t length)
  2386. {
  2387. struct hal_tx_completion_status ts;
  2388. struct dp_soc *soc = NULL;
  2389. struct dp_vdev *vdev = tx_desc->vdev;
  2390. struct dp_peer *peer = NULL;
  2391. struct ether_header *eh =
  2392. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2393. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2394. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2395. "-------------------- \n"
  2396. "Tx Completion Stats: \n"
  2397. "-------------------- \n"
  2398. "ack_frame_rssi = %d \n"
  2399. "first_msdu = %d \n"
  2400. "last_msdu = %d \n"
  2401. "msdu_part_of_amsdu = %d \n"
  2402. "rate_stats valid = %d \n"
  2403. "bw = %d \n"
  2404. "pkt_type = %d \n"
  2405. "stbc = %d \n"
  2406. "ldpc = %d \n"
  2407. "sgi = %d \n"
  2408. "mcs = %d \n"
  2409. "ofdma = %d \n"
  2410. "tones_in_ru = %d \n"
  2411. "tsf = %d \n"
  2412. "ppdu_id = %d \n"
  2413. "transmit_cnt = %d \n"
  2414. "tid = %d \n"
  2415. "peer_id = %d \n",
  2416. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2417. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2418. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2419. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2420. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2421. ts.peer_id);
  2422. if (!vdev) {
  2423. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2424. "invalid vdev");
  2425. goto out;
  2426. }
  2427. soc = vdev->pdev->soc;
  2428. /* Update SoC level stats */
  2429. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2430. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2431. /* Update per-packet stats */
  2432. if (qdf_unlikely(vdev->mesh_vdev) &&
  2433. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2434. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2435. /* Update peer level stats */
  2436. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2437. if (!peer) {
  2438. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2439. "invalid peer");
  2440. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2441. goto out;
  2442. }
  2443. if (qdf_likely(peer->vdev->tx_encap_type ==
  2444. htt_cmn_pkt_type_ethernet)) {
  2445. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2446. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2447. }
  2448. dp_tx_update_peer_stats(peer, &ts, length);
  2449. out:
  2450. return;
  2451. }
  2452. /**
  2453. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2454. * @soc: core txrx main context
  2455. * @comp_head: software descriptor head pointer
  2456. *
  2457. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2458. * and release the software descriptors after processing is complete
  2459. *
  2460. * Return: none
  2461. */
  2462. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2463. struct dp_tx_desc_s *comp_head)
  2464. {
  2465. struct dp_tx_desc_s *desc;
  2466. struct dp_tx_desc_s *next;
  2467. struct hal_tx_completion_status ts = {0};
  2468. uint32_t length;
  2469. struct dp_peer *peer;
  2470. DP_HIST_INIT();
  2471. desc = comp_head;
  2472. while (desc) {
  2473. hal_tx_comp_get_status(&desc->comp, &ts);
  2474. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2475. length = qdf_nbuf_len(desc->nbuf);
  2476. /* check tx completion notification */
  2477. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(desc->nbuf))
  2478. dp_tx_notify_completion(soc, desc, desc->nbuf);
  2479. dp_tx_comp_process_tx_status(desc, length);
  2480. DPTRACE(qdf_dp_trace_ptr
  2481. (desc->nbuf,
  2482. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  2483. QDF_TRACE_DEFAULT_PDEV_ID,
  2484. qdf_nbuf_data_addr(desc->nbuf),
  2485. sizeof(qdf_nbuf_data(desc->nbuf)),
  2486. desc->id, ts.status)
  2487. );
  2488. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2489. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2490. desc->pdev, ts.peer_id, ts.ppdu_id,
  2491. ts.first_msdu, ts.last_msdu,
  2492. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2493. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2494. QDF_DMA_TO_DEVICE);
  2495. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2496. ts.ppdu_id, desc->nbuf);
  2497. } else {
  2498. dp_tx_comp_free_buf(soc, desc);
  2499. }
  2500. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2501. next = desc->next;
  2502. dp_tx_desc_release(desc, desc->pool_id);
  2503. desc = next;
  2504. }
  2505. DP_TX_HIST_STATS_PER_PDEV();
  2506. }
  2507. /**
  2508. * dp_tx_comp_handler() - Tx completion handler
  2509. * @soc: core txrx main context
  2510. * @ring_id: completion ring id
  2511. * @quota: No. of packets/descriptors that can be serviced in one loop
  2512. *
  2513. * This function will collect hardware release ring element contents and
  2514. * handle descriptor contents. Based on contents, free packet or handle error
  2515. * conditions
  2516. *
  2517. * Return: none
  2518. */
  2519. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2520. {
  2521. void *tx_comp_hal_desc;
  2522. uint8_t buffer_src;
  2523. uint8_t pool_id;
  2524. uint32_t tx_desc_id;
  2525. struct dp_tx_desc_s *tx_desc = NULL;
  2526. struct dp_tx_desc_s *head_desc = NULL;
  2527. struct dp_tx_desc_s *tail_desc = NULL;
  2528. uint32_t num_processed;
  2529. uint32_t count;
  2530. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2531. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2532. "%s %d : HAL RING Access Failed -- %pK\n",
  2533. __func__, __LINE__, hal_srng);
  2534. return 0;
  2535. }
  2536. num_processed = 0;
  2537. count = 0;
  2538. /* Find head descriptor from completion ring */
  2539. while (qdf_likely(tx_comp_hal_desc =
  2540. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2541. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2542. /* If this buffer was not released by TQM or FW, then it is not
  2543. * Tx completion indication, assert */
  2544. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2545. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2546. QDF_TRACE(QDF_MODULE_ID_DP,
  2547. QDF_TRACE_LEVEL_FATAL,
  2548. "Tx comp release_src != TQM | FW");
  2549. qdf_assert_always(0);
  2550. }
  2551. /* Get descriptor id */
  2552. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2553. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2554. DP_TX_DESC_ID_POOL_OS;
  2555. if (!dp_tx_is_desc_id_valid(soc, tx_desc_id))
  2556. continue;
  2557. /* Find Tx descriptor */
  2558. tx_desc = dp_tx_desc_find(soc, pool_id,
  2559. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2560. DP_TX_DESC_ID_PAGE_OS,
  2561. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2562. DP_TX_DESC_ID_OFFSET_OS);
  2563. /*
  2564. * If the release source is FW, process the HTT status
  2565. */
  2566. if (qdf_unlikely(buffer_src ==
  2567. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2568. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2569. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2570. htt_tx_status);
  2571. dp_tx_process_htt_completion(tx_desc,
  2572. htt_tx_status);
  2573. } else {
  2574. /* Pool id is not matching. Error */
  2575. if (tx_desc->pool_id != pool_id) {
  2576. QDF_TRACE(QDF_MODULE_ID_DP,
  2577. QDF_TRACE_LEVEL_FATAL,
  2578. "Tx Comp pool id %d not matched %d",
  2579. pool_id, tx_desc->pool_id);
  2580. qdf_assert_always(0);
  2581. }
  2582. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2583. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2584. QDF_TRACE(QDF_MODULE_ID_DP,
  2585. QDF_TRACE_LEVEL_FATAL,
  2586. "Txdesc invalid, flgs = %x,id = %d",
  2587. tx_desc->flags, tx_desc_id);
  2588. qdf_assert_always(0);
  2589. }
  2590. /* First ring descriptor on the cycle */
  2591. if (!head_desc) {
  2592. head_desc = tx_desc;
  2593. tail_desc = tx_desc;
  2594. }
  2595. tail_desc->next = tx_desc;
  2596. tx_desc->next = NULL;
  2597. tail_desc = tx_desc;
  2598. /* Collect hw completion contents */
  2599. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2600. &tx_desc->comp, 1);
  2601. }
  2602. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2603. /* Decrement PM usage count if the packet has been sent.*/
  2604. hif_pm_runtime_put(soc->hif_handle);
  2605. /*
  2606. * Processed packet count is more than given quota
  2607. * stop to processing
  2608. */
  2609. if ((num_processed >= quota))
  2610. break;
  2611. count++;
  2612. }
  2613. hal_srng_access_end(soc->hal_soc, hal_srng);
  2614. /* Process the reaped descriptors */
  2615. if (head_desc)
  2616. dp_tx_comp_process_desc(soc, head_desc);
  2617. return num_processed;
  2618. }
  2619. #ifdef CONVERGED_TDLS_ENABLE
  2620. /**
  2621. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2622. *
  2623. * @data_vdev - which vdev should transmit the tx data frames
  2624. * @tx_spec - what non-standard handling to apply to the tx data frames
  2625. * @msdu_list - NULL-terminated list of tx MSDUs
  2626. *
  2627. * Return: NULL on success,
  2628. * nbuf when it fails to send
  2629. */
  2630. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2631. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2632. {
  2633. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2634. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2635. vdev->is_tdls_frame = true;
  2636. return dp_tx_send(vdev_handle, msdu_list);
  2637. }
  2638. #endif
  2639. /**
  2640. * dp_tx_vdev_attach() - attach vdev to dp tx
  2641. * @vdev: virtual device instance
  2642. *
  2643. * Return: QDF_STATUS_SUCCESS: success
  2644. * QDF_STATUS_E_RESOURCES: Error return
  2645. */
  2646. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2647. {
  2648. /*
  2649. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2650. */
  2651. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2652. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2653. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2654. vdev->vdev_id);
  2655. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2656. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2657. /*
  2658. * Set HTT Extension Valid bit to 0 by default
  2659. */
  2660. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2661. dp_tx_vdev_update_search_flags(vdev);
  2662. return QDF_STATUS_SUCCESS;
  2663. }
  2664. /**
  2665. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2666. * @vdev: virtual device instance
  2667. *
  2668. * Return: void
  2669. *
  2670. */
  2671. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2672. {
  2673. /*
  2674. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2675. * for TDLS link
  2676. *
  2677. * Enable AddrY (SA based search) only for non-WDS STA and
  2678. * ProxySTA VAP modes.
  2679. *
  2680. * In all other VAP modes, only DA based search should be
  2681. * enabled
  2682. */
  2683. if (vdev->opmode == wlan_op_mode_sta &&
  2684. vdev->tdls_link_connected)
  2685. vdev->hal_desc_addr_search_flags =
  2686. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2687. else if ((vdev->opmode == wlan_op_mode_sta &&
  2688. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2689. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2690. else
  2691. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2692. }
  2693. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2694. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2695. {
  2696. }
  2697. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2698. /* dp_tx_desc_flush() - release resources associated
  2699. * to tx_desc
  2700. * @vdev: virtual device instance
  2701. *
  2702. * This function will free all outstanding Tx buffers,
  2703. * including ME buffer for which either free during
  2704. * completion didn't happened or completion is not
  2705. * received.
  2706. */
  2707. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2708. {
  2709. uint8_t i, num_pool;
  2710. uint32_t j;
  2711. uint32_t num_desc;
  2712. struct dp_soc *soc = vdev->pdev->soc;
  2713. struct dp_tx_desc_s *tx_desc = NULL;
  2714. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2715. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2716. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2717. for (i = 0; i < num_pool; i++) {
  2718. for (j = 0; j < num_desc; j++) {
  2719. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2720. if (tx_desc_pool &&
  2721. tx_desc_pool->desc_pages.cacheable_pages) {
  2722. tx_desc = dp_tx_desc_find(soc, i,
  2723. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2724. DP_TX_DESC_ID_PAGE_OS,
  2725. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2726. DP_TX_DESC_ID_OFFSET_OS);
  2727. if (tx_desc && (tx_desc->vdev == vdev) &&
  2728. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2729. dp_tx_comp_free_buf(soc, tx_desc);
  2730. dp_tx_desc_release(tx_desc, i);
  2731. }
  2732. }
  2733. }
  2734. }
  2735. }
  2736. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2737. /**
  2738. * dp_tx_vdev_detach() - detach vdev from dp tx
  2739. * @vdev: virtual device instance
  2740. *
  2741. * Return: QDF_STATUS_SUCCESS: success
  2742. * QDF_STATUS_E_RESOURCES: Error return
  2743. */
  2744. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2745. {
  2746. dp_tx_desc_flush(vdev);
  2747. return QDF_STATUS_SUCCESS;
  2748. }
  2749. /**
  2750. * dp_tx_pdev_attach() - attach pdev to dp tx
  2751. * @pdev: physical device instance
  2752. *
  2753. * Return: QDF_STATUS_SUCCESS: success
  2754. * QDF_STATUS_E_RESOURCES: Error return
  2755. */
  2756. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2757. {
  2758. struct dp_soc *soc = pdev->soc;
  2759. /* Initialize Flow control counters */
  2760. qdf_atomic_init(&pdev->num_tx_exception);
  2761. qdf_atomic_init(&pdev->num_tx_outstanding);
  2762. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2763. /* Initialize descriptors in TCL Ring */
  2764. hal_tx_init_data_ring(soc->hal_soc,
  2765. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2766. }
  2767. return QDF_STATUS_SUCCESS;
  2768. }
  2769. /**
  2770. * dp_tx_pdev_detach() - detach pdev from dp tx
  2771. * @pdev: physical device instance
  2772. *
  2773. * Return: QDF_STATUS_SUCCESS: success
  2774. * QDF_STATUS_E_RESOURCES: Error return
  2775. */
  2776. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2777. {
  2778. dp_tx_me_exit(pdev);
  2779. return QDF_STATUS_SUCCESS;
  2780. }
  2781. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2782. /* Pools will be allocated dynamically */
  2783. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2784. int num_desc)
  2785. {
  2786. uint8_t i;
  2787. for (i = 0; i < num_pool; i++) {
  2788. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2789. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2790. }
  2791. return 0;
  2792. }
  2793. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2794. {
  2795. uint8_t i;
  2796. for (i = 0; i < num_pool; i++)
  2797. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2798. }
  2799. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2800. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2801. int num_desc)
  2802. {
  2803. uint8_t i;
  2804. /* Allocate software Tx descriptor pools */
  2805. for (i = 0; i < num_pool; i++) {
  2806. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2807. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2808. "%s Tx Desc Pool alloc %d failed %pK\n",
  2809. __func__, i, soc);
  2810. return ENOMEM;
  2811. }
  2812. }
  2813. return 0;
  2814. }
  2815. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2816. {
  2817. uint8_t i;
  2818. for (i = 0; i < num_pool; i++) {
  2819. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2820. if (dp_tx_desc_pool_free(soc, i)) {
  2821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2822. "%s Tx Desc Pool Free failed\n", __func__);
  2823. }
  2824. }
  2825. }
  2826. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2827. /**
  2828. * dp_tx_soc_detach() - detach soc from dp tx
  2829. * @soc: core txrx main context
  2830. *
  2831. * This function will detach dp tx into main device context
  2832. * will free dp tx resource and initialize resources
  2833. *
  2834. * Return: QDF_STATUS_SUCCESS: success
  2835. * QDF_STATUS_E_RESOURCES: Error return
  2836. */
  2837. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2838. {
  2839. uint8_t num_pool;
  2840. uint16_t num_desc;
  2841. uint16_t num_ext_desc;
  2842. uint8_t i;
  2843. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2844. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2845. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2846. dp_tx_flow_control_deinit(soc);
  2847. dp_tx_delete_static_pools(soc, num_pool);
  2848. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2849. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2850. __func__, num_pool, num_desc);
  2851. for (i = 0; i < num_pool; i++) {
  2852. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2853. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2854. "%s Tx Ext Desc Pool Free failed\n",
  2855. __func__);
  2856. return QDF_STATUS_E_RESOURCES;
  2857. }
  2858. }
  2859. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2860. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2861. __func__, num_pool, num_ext_desc);
  2862. for (i = 0; i < num_pool; i++) {
  2863. dp_tx_tso_desc_pool_free(soc, i);
  2864. }
  2865. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2866. "%s TSO Desc Pool %d Free descs = %d\n",
  2867. __func__, num_pool, num_desc);
  2868. for (i = 0; i < num_pool; i++)
  2869. dp_tx_tso_num_seg_pool_free(soc, i);
  2870. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2871. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2872. __func__, num_pool, num_desc);
  2873. return QDF_STATUS_SUCCESS;
  2874. }
  2875. /**
  2876. * dp_tx_soc_attach() - attach soc to dp tx
  2877. * @soc: core txrx main context
  2878. *
  2879. * This function will attach dp tx into main device context
  2880. * will allocate dp tx resource and initialize resources
  2881. *
  2882. * Return: QDF_STATUS_SUCCESS: success
  2883. * QDF_STATUS_E_RESOURCES: Error return
  2884. */
  2885. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2886. {
  2887. uint8_t i;
  2888. uint8_t num_pool;
  2889. uint32_t num_desc;
  2890. uint32_t num_ext_desc;
  2891. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2892. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2893. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2894. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2895. goto fail;
  2896. dp_tx_flow_control_init(soc);
  2897. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2898. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2899. __func__, num_pool, num_desc);
  2900. /* Allocate extension tx descriptor pools */
  2901. for (i = 0; i < num_pool; i++) {
  2902. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2903. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2904. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2905. i, soc);
  2906. goto fail;
  2907. }
  2908. }
  2909. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2910. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2911. __func__, num_pool, num_ext_desc);
  2912. for (i = 0; i < num_pool; i++) {
  2913. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2914. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2915. "TSO Desc Pool alloc %d failed %pK\n",
  2916. i, soc);
  2917. goto fail;
  2918. }
  2919. }
  2920. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2921. "%s TSO Desc Alloc %d, descs = %d\n",
  2922. __func__, num_pool, num_desc);
  2923. for (i = 0; i < num_pool; i++) {
  2924. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2925. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2926. "TSO Num of seg Pool alloc %d failed %pK\n",
  2927. i, soc);
  2928. goto fail;
  2929. }
  2930. }
  2931. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2932. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2933. __func__, num_pool, num_desc);
  2934. /* Initialize descriptors in TCL Rings */
  2935. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2936. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2937. hal_tx_init_data_ring(soc->hal_soc,
  2938. soc->tcl_data_ring[i].hal_srng);
  2939. }
  2940. }
  2941. /*
  2942. * todo - Add a runtime config option to enable this.
  2943. */
  2944. /*
  2945. * Due to multiple issues on NPR EMU, enable it selectively
  2946. * only for NPR EMU, should be removed, once NPR platforms
  2947. * are stable.
  2948. */
  2949. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2950. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2951. "%s HAL Tx init Success\n", __func__);
  2952. return QDF_STATUS_SUCCESS;
  2953. fail:
  2954. /* Detach will take care of freeing only allocated resources */
  2955. dp_tx_soc_detach(soc);
  2956. return QDF_STATUS_E_RESOURCES;
  2957. }
  2958. /*
  2959. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2960. * pdev: pointer to DP PDEV structure
  2961. * seg_info_head: Pointer to the head of list
  2962. *
  2963. * return: void
  2964. */
  2965. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2966. struct dp_tx_seg_info_s *seg_info_head)
  2967. {
  2968. struct dp_tx_me_buf_t *mc_uc_buf;
  2969. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2970. qdf_nbuf_t nbuf = NULL;
  2971. uint64_t phy_addr;
  2972. while (seg_info_head) {
  2973. nbuf = seg_info_head->nbuf;
  2974. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2975. seg_info_head->frags[0].vaddr;
  2976. phy_addr = seg_info_head->frags[0].paddr_hi;
  2977. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2978. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2979. phy_addr,
  2980. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2981. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2982. qdf_nbuf_free(nbuf);
  2983. seg_info_new = seg_info_head;
  2984. seg_info_head = seg_info_head->next;
  2985. qdf_mem_free(seg_info_new);
  2986. }
  2987. }
  2988. /**
  2989. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  2990. * @vdev: DP VDEV handle
  2991. * @nbuf: Multicast nbuf
  2992. * @newmac: Table of the clients to which packets have to be sent
  2993. * @new_mac_cnt: No of clients
  2994. *
  2995. * return: no of converted packets
  2996. */
  2997. uint16_t
  2998. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2999. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  3000. {
  3001. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  3002. struct dp_pdev *pdev = vdev->pdev;
  3003. struct ether_header *eh;
  3004. uint8_t *data;
  3005. uint16_t len;
  3006. /* reference to frame dst addr */
  3007. uint8_t *dstmac;
  3008. /* copy of original frame src addr */
  3009. uint8_t srcmac[DP_MAC_ADDR_LEN];
  3010. /* local index into newmac */
  3011. uint8_t new_mac_idx = 0;
  3012. struct dp_tx_me_buf_t *mc_uc_buf;
  3013. qdf_nbuf_t nbuf_clone;
  3014. struct dp_tx_msdu_info_s msdu_info;
  3015. struct dp_tx_seg_info_s *seg_info_head = NULL;
  3016. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  3017. struct dp_tx_seg_info_s *seg_info_new;
  3018. struct dp_tx_frag_info_s data_frag;
  3019. qdf_dma_addr_t paddr_data;
  3020. qdf_dma_addr_t paddr_mcbuf = 0;
  3021. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  3022. QDF_STATUS status;
  3023. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  3024. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3025. eh = (struct ether_header *) nbuf;
  3026. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  3027. len = qdf_nbuf_len(nbuf);
  3028. data = qdf_nbuf_data(nbuf);
  3029. status = qdf_nbuf_map(vdev->osdev, nbuf,
  3030. QDF_DMA_TO_DEVICE);
  3031. if (status) {
  3032. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3033. "Mapping failure Error:%d", status);
  3034. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3035. qdf_nbuf_free(nbuf);
  3036. return 1;
  3037. }
  3038. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  3039. /*preparing data fragment*/
  3040. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  3041. data_frag.paddr_lo = (uint32_t)paddr_data;
  3042. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  3043. data_frag.len = len - DP_MAC_ADDR_LEN;
  3044. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  3045. dstmac = newmac[new_mac_idx];
  3046. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3047. "added mac addr (%pM)", dstmac);
  3048. /* Check for NULL Mac Address */
  3049. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  3050. continue;
  3051. /* frame to self mac. skip */
  3052. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  3053. continue;
  3054. /*
  3055. * TODO: optimize to avoid malloc in per-packet path
  3056. * For eg. seg_pool can be made part of vdev structure
  3057. */
  3058. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  3059. if (!seg_info_new) {
  3060. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3061. "alloc failed");
  3062. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  3063. goto fail_seg_alloc;
  3064. }
  3065. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  3066. if (mc_uc_buf == NULL)
  3067. goto fail_buf_alloc;
  3068. /*
  3069. * TODO: Check if we need to clone the nbuf
  3070. * Or can we just use the reference for all cases
  3071. */
  3072. if (new_mac_idx < (new_mac_cnt - 1)) {
  3073. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  3074. if (nbuf_clone == NULL) {
  3075. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  3076. goto fail_clone;
  3077. }
  3078. } else {
  3079. /*
  3080. * Update the ref
  3081. * to account for frame sent without cloning
  3082. */
  3083. qdf_nbuf_ref(nbuf);
  3084. nbuf_clone = nbuf;
  3085. }
  3086. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  3087. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  3088. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  3089. &paddr_mcbuf);
  3090. if (status) {
  3091. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3092. "Mapping failure Error:%d", status);
  3093. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  3094. goto fail_map;
  3095. }
  3096. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  3097. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  3098. seg_info_new->frags[0].paddr_hi =
  3099. ((uint64_t) paddr_mcbuf >> 32);
  3100. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  3101. seg_info_new->frags[1] = data_frag;
  3102. seg_info_new->nbuf = nbuf_clone;
  3103. seg_info_new->frag_cnt = 2;
  3104. seg_info_new->total_len = len;
  3105. seg_info_new->next = NULL;
  3106. if (seg_info_head == NULL)
  3107. seg_info_head = seg_info_new;
  3108. else
  3109. seg_info_tail->next = seg_info_new;
  3110. seg_info_tail = seg_info_new;
  3111. }
  3112. if (!seg_info_head) {
  3113. goto free_return;
  3114. }
  3115. msdu_info.u.sg_info.curr_seg = seg_info_head;
  3116. msdu_info.num_seg = new_mac_cnt;
  3117. msdu_info.frm_type = dp_tx_frm_me;
  3118. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  3119. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3120. while (seg_info_head->next) {
  3121. seg_info_new = seg_info_head;
  3122. seg_info_head = seg_info_head->next;
  3123. qdf_mem_free(seg_info_new);
  3124. }
  3125. qdf_mem_free(seg_info_head);
  3126. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3127. qdf_nbuf_free(nbuf);
  3128. return new_mac_cnt;
  3129. fail_map:
  3130. qdf_nbuf_free(nbuf_clone);
  3131. fail_clone:
  3132. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3133. fail_buf_alloc:
  3134. qdf_mem_free(seg_info_new);
  3135. fail_seg_alloc:
  3136. dp_tx_me_mem_free(pdev, seg_info_head);
  3137. free_return:
  3138. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3139. qdf_nbuf_free(nbuf);
  3140. return 1;
  3141. }