dp_catalog.c 72 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
  6. #include <linux/delay.h>
  7. #include <linux/iopoll.h>
  8. #include <drm/drm_dp_helper.h>
  9. #include "dp_catalog.h"
  10. #include "dp_reg.h"
  11. #define DP_GET_MSB(x) (x >> 8)
  12. #define DP_GET_LSB(x) (x & 0xff)
  13. #define DP_PHY_READY BIT(1)
  14. #define dp_catalog_get_priv(x) ({ \
  15. struct dp_catalog *dp_catalog; \
  16. dp_catalog = container_of(x, struct dp_catalog, x); \
  17. container_of(dp_catalog, struct dp_catalog_private, \
  18. dp_catalog); \
  19. })
  20. #define DP_INTERRUPT_STATUS1 \
  21. (DP_INTR_AUX_I2C_DONE| \
  22. DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
  23. DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \
  24. DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \
  25. DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR)
  26. #define DP_INTR_MASK1 (DP_INTERRUPT_STATUS1 << 2)
  27. #define DP_INTERRUPT_STATUS2 \
  28. (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
  29. DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
  30. #define DP_INTR_MASK2 (DP_INTERRUPT_STATUS2 << 2)
  31. #define DP_INTERRUPT_STATUS5 \
  32. (DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
  33. #define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
  34. #define dp_catalog_fill_io(x) { \
  35. catalog->io.x = parser->get_io(parser, #x); \
  36. }
  37. #define dp_catalog_fill_io_buf(x) { \
  38. parser->get_io_buf(parser, #x); \
  39. }
  40. static u8 const vm_pre_emphasis[4][4] = {
  41. {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */
  42. {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */
  43. {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */
  44. {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
  45. };
  46. /* voltage swing, 0.2v and 1.0v are not support */
  47. static u8 const vm_voltage_swing[4][4] = {
  48. {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */
  49. {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */
  50. {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
  51. {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
  52. };
  53. enum dp_flush_bit {
  54. DP_PPS_FLUSH,
  55. DP_DHDR_FLUSH,
  56. };
  57. struct dp_catalog_io {
  58. struct dp_io_data *dp_ahb;
  59. struct dp_io_data *dp_aux;
  60. struct dp_io_data *dp_link;
  61. struct dp_io_data *dp_p0;
  62. struct dp_io_data *dp_phy;
  63. struct dp_io_data *dp_ln_tx0;
  64. struct dp_io_data *dp_ln_tx1;
  65. struct dp_io_data *dp_mmss_cc;
  66. struct dp_io_data *dp_pll;
  67. struct dp_io_data *usb3_dp_com;
  68. struct dp_io_data *hdcp_physical;
  69. struct dp_io_data *dp_p1;
  70. struct dp_io_data *dp_tcsr;
  71. };
  72. /* audio related catalog functions */
  73. struct dp_catalog_private {
  74. struct device *dev;
  75. struct dp_catalog_io io;
  76. struct dp_parser *parser;
  77. u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
  78. struct dp_catalog dp_catalog;
  79. char exe_mode[SZ_4];
  80. };
  81. /* aux related catalog functions */
  82. static u32 dp_catalog_aux_read_data(struct dp_catalog_aux *aux)
  83. {
  84. struct dp_catalog_private *catalog;
  85. struct dp_io_data *io_data;
  86. if (!aux) {
  87. pr_err("invalid input\n");
  88. goto end;
  89. }
  90. catalog = dp_catalog_get_priv(aux);
  91. io_data = catalog->io.dp_aux;
  92. return dp_read(catalog->exe_mode, io_data, DP_AUX_DATA);
  93. end:
  94. return 0;
  95. }
  96. static int dp_catalog_aux_write_data(struct dp_catalog_aux *aux)
  97. {
  98. int rc = 0;
  99. struct dp_catalog_private *catalog;
  100. struct dp_io_data *io_data;
  101. if (!aux) {
  102. pr_err("invalid input\n");
  103. rc = -EINVAL;
  104. goto end;
  105. }
  106. catalog = dp_catalog_get_priv(aux);
  107. io_data = catalog->io.dp_aux;
  108. dp_write(catalog->exe_mode, io_data, DP_AUX_DATA, aux->data);
  109. end:
  110. return rc;
  111. }
  112. static int dp_catalog_aux_write_trans(struct dp_catalog_aux *aux)
  113. {
  114. int rc = 0;
  115. struct dp_catalog_private *catalog;
  116. struct dp_io_data *io_data;
  117. if (!aux) {
  118. pr_err("invalid input\n");
  119. rc = -EINVAL;
  120. goto end;
  121. }
  122. catalog = dp_catalog_get_priv(aux);
  123. io_data = catalog->io.dp_aux;
  124. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, aux->data);
  125. end:
  126. return rc;
  127. }
  128. static int dp_catalog_aux_clear_trans(struct dp_catalog_aux *aux, bool read)
  129. {
  130. int rc = 0;
  131. u32 data = 0;
  132. struct dp_catalog_private *catalog;
  133. struct dp_io_data *io_data;
  134. if (!aux) {
  135. pr_err("invalid input\n");
  136. rc = -EINVAL;
  137. goto end;
  138. }
  139. catalog = dp_catalog_get_priv(aux);
  140. io_data = catalog->io.dp_aux;
  141. if (read) {
  142. data = dp_read(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL);
  143. data &= ~BIT(9);
  144. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, data);
  145. } else {
  146. dp_write(catalog->exe_mode, io_data, DP_AUX_TRANS_CTRL, 0);
  147. }
  148. end:
  149. return rc;
  150. }
  151. static void dp_catalog_aux_clear_hw_interrupts(struct dp_catalog_aux *aux)
  152. {
  153. struct dp_catalog_private *catalog;
  154. struct dp_io_data *io_data;
  155. u32 data = 0;
  156. if (!aux) {
  157. pr_err("invalid input\n");
  158. return;
  159. }
  160. catalog = dp_catalog_get_priv(aux);
  161. io_data = catalog->io.dp_phy;
  162. data = dp_read(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_STATUS);
  163. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f);
  164. wmb(); /* make sure 0x1f is written before next write */
  165. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f);
  166. wmb(); /* make sure 0x9f is written before next write */
  167. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_CLEAR, 0);
  168. wmb(); /* make sure register is cleared */
  169. }
  170. static void dp_catalog_aux_reset(struct dp_catalog_aux *aux)
  171. {
  172. u32 aux_ctrl;
  173. struct dp_catalog_private *catalog;
  174. struct dp_io_data *io_data;
  175. if (!aux) {
  176. pr_err("invalid input\n");
  177. return;
  178. }
  179. catalog = dp_catalog_get_priv(aux);
  180. io_data = catalog->io.dp_aux;
  181. aux_ctrl = dp_read(catalog->exe_mode, io_data, DP_AUX_CTRL);
  182. aux_ctrl |= BIT(1);
  183. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  184. usleep_range(1000, 1010); /* h/w recommended delay */
  185. aux_ctrl &= ~BIT(1);
  186. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  187. wmb(); /* make sure AUX reset is done here */
  188. }
  189. static void dp_catalog_aux_enable(struct dp_catalog_aux *aux, bool enable)
  190. {
  191. u32 aux_ctrl;
  192. struct dp_catalog_private *catalog;
  193. struct dp_io_data *io_data;
  194. if (!aux) {
  195. pr_err("invalid input\n");
  196. return;
  197. }
  198. catalog = dp_catalog_get_priv(aux);
  199. io_data = catalog->io.dp_aux;
  200. aux_ctrl = dp_read(catalog->exe_mode, io_data, DP_AUX_CTRL);
  201. if (enable) {
  202. aux_ctrl |= BIT(0);
  203. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  204. wmb(); /* make sure AUX module is enabled */
  205. dp_write(catalog->exe_mode, io_data, DP_TIMEOUT_COUNT, 0xffff);
  206. dp_write(catalog->exe_mode, io_data, DP_AUX_LIMITS, 0xffff);
  207. } else {
  208. aux_ctrl &= ~BIT(0);
  209. dp_write(catalog->exe_mode, io_data, DP_AUX_CTRL, aux_ctrl);
  210. }
  211. }
  212. static void dp_catalog_aux_update_cfg(struct dp_catalog_aux *aux,
  213. struct dp_aux_cfg *cfg, enum dp_phy_aux_config_type type)
  214. {
  215. struct dp_catalog_private *catalog;
  216. u32 new_index = 0, current_index = 0;
  217. struct dp_io_data *io_data;
  218. if (!aux || !cfg || (type >= PHY_AUX_CFG_MAX)) {
  219. pr_err("invalid input\n");
  220. return;
  221. }
  222. catalog = dp_catalog_get_priv(aux);
  223. io_data = catalog->io.dp_phy;
  224. current_index = cfg[type].current_index;
  225. new_index = (current_index + 1) % cfg[type].cfg_cnt;
  226. pr_debug("Updating %s from 0x%08x to 0x%08x\n",
  227. dp_phy_aux_config_type_to_string(type),
  228. cfg[type].lut[current_index], cfg[type].lut[new_index]);
  229. dp_write(catalog->exe_mode, io_data, cfg[type].offset,
  230. cfg[type].lut[new_index]);
  231. cfg[type].current_index = new_index;
  232. }
  233. static void dp_catalog_aux_setup(struct dp_catalog_aux *aux,
  234. struct dp_aux_cfg *cfg)
  235. {
  236. struct dp_catalog_private *catalog;
  237. struct dp_io_data *io_data;
  238. int i = 0;
  239. if (!aux || !cfg) {
  240. pr_err("invalid input\n");
  241. return;
  242. }
  243. catalog = dp_catalog_get_priv(aux);
  244. io_data = catalog->io.dp_phy;
  245. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x65);
  246. wmb(); /* make sure PD programming happened */
  247. /* Turn on BIAS current for PHY/PLL */
  248. io_data = catalog->io.dp_pll;
  249. dp_write(catalog->exe_mode, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN,
  250. 0x1b);
  251. io_data = catalog->io.dp_phy;
  252. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x02);
  253. wmb(); /* make sure PD programming happened */
  254. dp_write(catalog->exe_mode, io_data, DP_PHY_PD_CTL, 0x7d);
  255. /* Turn on BIAS current for PHY/PLL */
  256. io_data = catalog->io.dp_pll;
  257. dp_write(catalog->exe_mode, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN,
  258. 0x3f);
  259. /* DP AUX CFG register programming */
  260. io_data = catalog->io.dp_phy;
  261. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  262. dp_write(catalog->exe_mode, io_data, cfg[i].offset,
  263. cfg[i].lut[cfg[i].current_index]);
  264. dp_write(catalog->exe_mode, io_data, DP_PHY_AUX_INTERRUPT_MASK, 0x1F);
  265. wmb(); /* make sure AUX configuration is done before enabling it */
  266. }
  267. static void dp_catalog_aux_get_irq(struct dp_catalog_aux *aux, bool cmd_busy)
  268. {
  269. u32 ack;
  270. struct dp_catalog_private *catalog;
  271. struct dp_io_data *io_data;
  272. if (!aux) {
  273. pr_err("invalid input\n");
  274. return;
  275. }
  276. catalog = dp_catalog_get_priv(aux);
  277. io_data = catalog->io.dp_ahb;
  278. aux->isr = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS);
  279. aux->isr &= ~DP_INTR_MASK1;
  280. ack = aux->isr & DP_INTERRUPT_STATUS1;
  281. ack <<= 1;
  282. ack |= DP_INTR_MASK1;
  283. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS, ack);
  284. }
  285. static bool dp_catalog_ctrl_wait_for_phy_ready(
  286. struct dp_catalog_private *catalog)
  287. {
  288. u32 reg = DP_PHY_STATUS, state;
  289. void __iomem *base = catalog->io.dp_phy->io.base;
  290. bool success = true;
  291. u32 const poll_sleep_us = 500;
  292. u32 const pll_timeout_us = 10000;
  293. if (readl_poll_timeout_atomic((base + reg), state,
  294. ((state & DP_PHY_READY) > 0),
  295. poll_sleep_us, pll_timeout_us)) {
  296. pr_err("PHY status failed, status=%x\n", state);
  297. success = false;
  298. }
  299. return success;
  300. }
  301. /* controller related catalog functions */
  302. static int dp_catalog_ctrl_late_phy_init(struct dp_catalog_ctrl *ctrl,
  303. u8 lane_cnt, bool flipped)
  304. {
  305. int rc = 0;
  306. u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
  307. struct dp_catalog_private *catalog;
  308. struct dp_io_data *io_data;
  309. if (!ctrl) {
  310. pr_err("invalid input\n");
  311. return -EINVAL;
  312. }
  313. catalog = dp_catalog_get_priv(ctrl);
  314. switch (lane_cnt) {
  315. case 1:
  316. drvr0_en = flipped ? 0x13 : 0x10;
  317. bias0_en = flipped ? 0x3E : 0x15;
  318. drvr1_en = flipped ? 0x10 : 0x13;
  319. bias1_en = flipped ? 0x15 : 0x3E;
  320. break;
  321. case 2:
  322. drvr0_en = flipped ? 0x10 : 0x10;
  323. bias0_en = flipped ? 0x3F : 0x15;
  324. drvr1_en = flipped ? 0x10 : 0x10;
  325. bias1_en = flipped ? 0x15 : 0x3F;
  326. break;
  327. case 4:
  328. default:
  329. drvr0_en = 0x10;
  330. bias0_en = 0x3F;
  331. drvr1_en = 0x10;
  332. bias1_en = 0x3F;
  333. break;
  334. }
  335. io_data = catalog->io.dp_ln_tx0;
  336. dp_write(catalog->exe_mode, io_data, TXn_HIGHZ_DRVR_EN_V420, drvr0_en);
  337. dp_write(catalog->exe_mode, io_data,
  338. TXn_TRANSCEIVER_BIAS_EN_V420, bias0_en);
  339. io_data = catalog->io.dp_ln_tx1;
  340. dp_write(catalog->exe_mode, io_data, TXn_HIGHZ_DRVR_EN_V420, drvr1_en);
  341. dp_write(catalog->exe_mode, io_data,
  342. TXn_TRANSCEIVER_BIAS_EN_V420, bias1_en);
  343. io_data = catalog->io.dp_phy;
  344. dp_write(catalog->exe_mode, io_data, DP_PHY_CFG, 0x18);
  345. /* add hardware recommended delay */
  346. udelay(2000);
  347. dp_write(catalog->exe_mode, io_data, DP_PHY_CFG, 0x19);
  348. /*
  349. * Make sure all the register writes are completed before
  350. * doing any other operation
  351. */
  352. wmb();
  353. if (!dp_catalog_ctrl_wait_for_phy_ready(catalog)) {
  354. rc = -EINVAL;
  355. goto lock_err;
  356. }
  357. io_data = catalog->io.dp_ln_tx0;
  358. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, 0x0a);
  359. io_data = catalog->io.dp_ln_tx1;
  360. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV_V420, 0x0a);
  361. io_data = catalog->io.dp_ln_tx0;
  362. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL_V420, 0x27);
  363. io_data = catalog->io.dp_ln_tx1;
  364. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL_V420, 0x27);
  365. io_data = catalog->io.dp_ln_tx0;
  366. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  367. io_data = catalog->io.dp_ln_tx1;
  368. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  369. /* Make sure the PHY register writes are done */
  370. wmb();
  371. lock_err:
  372. return rc;
  373. }
  374. static u32 dp_catalog_ctrl_read_hdcp_status(struct dp_catalog_ctrl *ctrl)
  375. {
  376. struct dp_catalog_private *catalog;
  377. struct dp_io_data *io_data;
  378. if (!ctrl) {
  379. pr_err("invalid input\n");
  380. return -EINVAL;
  381. }
  382. catalog = dp_catalog_get_priv(ctrl);
  383. io_data = catalog->io.dp_ahb;
  384. return dp_read(catalog->exe_mode, io_data, DP_HDCP_STATUS);
  385. }
  386. static void dp_catalog_panel_setup_vsif_infoframe_sdp(
  387. struct dp_catalog_panel *panel)
  388. {
  389. struct dp_catalog_private *catalog;
  390. struct drm_msm_ext_hdr_metadata *hdr;
  391. struct dp_io_data *io_data;
  392. u32 header, parity, data, mst_offset = 0;
  393. u8 buf[SZ_64], off = 0;
  394. if (panel->stream_id >= DP_STREAM_MAX) {
  395. pr_err("invalid stream_id:%d\n", panel->stream_id);
  396. return;
  397. }
  398. if (panel->stream_id == DP_STREAM_1)
  399. mst_offset = MMSS_DP1_VSCEXT_0 - MMSS_DP_VSCEXT_0;
  400. catalog = dp_catalog_get_priv(panel);
  401. hdr = &panel->hdr_data.hdr_meta;
  402. io_data = catalog->io.dp_link;
  403. /* HEADER BYTE 1 */
  404. header = panel->hdr_data.vscext_header_byte1;
  405. parity = dp_header_get_parity(header);
  406. data = ((header << HEADER_BYTE_1_BIT)
  407. | (parity << PARITY_BYTE_1_BIT));
  408. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_0 + mst_offset,
  409. data);
  410. memcpy(buf + off, &data, sizeof(data));
  411. off += sizeof(data);
  412. /* HEADER BYTE 2 */
  413. header = panel->hdr_data.vscext_header_byte2;
  414. parity = dp_header_get_parity(header);
  415. data = ((header << HEADER_BYTE_2_BIT)
  416. | (parity << PARITY_BYTE_2_BIT));
  417. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_1 + mst_offset,
  418. data);
  419. /* HEADER BYTE 3 */
  420. header = panel->hdr_data.vscext_header_byte3;
  421. parity = dp_header_get_parity(header);
  422. data = ((header << HEADER_BYTE_3_BIT)
  423. | (parity << PARITY_BYTE_3_BIT));
  424. data |= dp_read(catalog->exe_mode, io_data,
  425. MMSS_DP_VSCEXT_1 + mst_offset);
  426. dp_write(catalog->exe_mode, io_data, MMSS_DP_VSCEXT_1 + mst_offset,
  427. data);
  428. memcpy(buf + off, &data, sizeof(data));
  429. off += sizeof(data);
  430. print_hex_dump(KERN_DEBUG, "[drm-dp] VSCEXT: ",
  431. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  432. }
  433. static void dp_catalog_panel_setup_hdr_infoframe_sdp(
  434. struct dp_catalog_panel *panel)
  435. {
  436. struct dp_catalog_private *catalog;
  437. struct drm_msm_ext_hdr_metadata *hdr;
  438. struct dp_io_data *io_data;
  439. u32 header, parity, data, mst_offset = 0;
  440. u8 buf[SZ_64], off = 0;
  441. if (panel->stream_id >= DP_STREAM_MAX) {
  442. pr_err("invalid stream_id:%d\n", panel->stream_id);
  443. return;
  444. }
  445. if (panel->stream_id == DP_STREAM_1)
  446. mst_offset = MMSS_DP1_GENERIC2_0 - MMSS_DP_GENERIC2_0;
  447. catalog = dp_catalog_get_priv(panel);
  448. hdr = &panel->hdr_data.hdr_meta;
  449. io_data = catalog->io.dp_link;
  450. /* HEADER BYTE 1 */
  451. header = panel->hdr_data.shdr_header_byte1;
  452. parity = dp_header_get_parity(header);
  453. data = ((header << HEADER_BYTE_1_BIT)
  454. | (parity << PARITY_BYTE_1_BIT));
  455. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_0 + mst_offset,
  456. data);
  457. memcpy(buf + off, &data, sizeof(data));
  458. off += sizeof(data);
  459. /* HEADER BYTE 2 */
  460. header = panel->hdr_data.shdr_header_byte2;
  461. parity = dp_header_get_parity(header);
  462. data = ((header << HEADER_BYTE_2_BIT)
  463. | (parity << PARITY_BYTE_2_BIT));
  464. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_1 + mst_offset,
  465. data);
  466. /* HEADER BYTE 3 */
  467. header = panel->hdr_data.shdr_header_byte3;
  468. parity = dp_header_get_parity(header);
  469. data = ((header << HEADER_BYTE_3_BIT)
  470. | (parity << PARITY_BYTE_3_BIT));
  471. data |= dp_read(catalog->exe_mode, io_data,
  472. MMSS_DP_VSCEXT_1 + mst_offset);
  473. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_1 + mst_offset,
  474. data);
  475. memcpy(buf + off, &data, sizeof(data));
  476. off += sizeof(data);
  477. data = panel->hdr_data.version;
  478. data |= panel->hdr_data.length << 8;
  479. data |= hdr->eotf << 16;
  480. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_2 + mst_offset,
  481. data);
  482. memcpy(buf + off, &data, sizeof(data));
  483. off += sizeof(data);
  484. data = (DP_GET_LSB(hdr->display_primaries_x[0]) |
  485. (DP_GET_MSB(hdr->display_primaries_x[0]) << 8) |
  486. (DP_GET_LSB(hdr->display_primaries_y[0]) << 16) |
  487. (DP_GET_MSB(hdr->display_primaries_y[0]) << 24));
  488. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_3 + mst_offset,
  489. data);
  490. memcpy(buf + off, &data, sizeof(data));
  491. off += sizeof(data);
  492. data = (DP_GET_LSB(hdr->display_primaries_x[1]) |
  493. (DP_GET_MSB(hdr->display_primaries_x[1]) << 8) |
  494. (DP_GET_LSB(hdr->display_primaries_y[1]) << 16) |
  495. (DP_GET_MSB(hdr->display_primaries_y[1]) << 24));
  496. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_4 + mst_offset,
  497. data);
  498. memcpy(buf + off, &data, sizeof(data));
  499. off += sizeof(data);
  500. data = (DP_GET_LSB(hdr->display_primaries_x[2]) |
  501. (DP_GET_MSB(hdr->display_primaries_x[2]) << 8) |
  502. (DP_GET_LSB(hdr->display_primaries_y[2]) << 16) |
  503. (DP_GET_MSB(hdr->display_primaries_y[2]) << 24));
  504. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_5 + mst_offset,
  505. data);
  506. memcpy(buf + off, &data, sizeof(data));
  507. off += sizeof(data);
  508. data = (DP_GET_LSB(hdr->white_point_x) |
  509. (DP_GET_MSB(hdr->white_point_x) << 8) |
  510. (DP_GET_LSB(hdr->white_point_y) << 16) |
  511. (DP_GET_MSB(hdr->white_point_y) << 24));
  512. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_6 + mst_offset,
  513. data);
  514. memcpy(buf + off, &data, sizeof(data));
  515. off += sizeof(data);
  516. data = (DP_GET_LSB(hdr->max_luminance) |
  517. (DP_GET_MSB(hdr->max_luminance) << 8) |
  518. (DP_GET_LSB(hdr->min_luminance) << 16) |
  519. (DP_GET_MSB(hdr->min_luminance) << 24));
  520. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_7 + mst_offset,
  521. data);
  522. memcpy(buf + off, &data, sizeof(data));
  523. off += sizeof(data);
  524. data = (DP_GET_LSB(hdr->max_content_light_level) |
  525. (DP_GET_MSB(hdr->max_content_light_level) << 8) |
  526. (DP_GET_LSB(hdr->max_average_light_level) << 16) |
  527. (DP_GET_MSB(hdr->max_average_light_level) << 24));
  528. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_8 + mst_offset,
  529. data);
  530. memcpy(buf + off, &data, sizeof(data));
  531. off += sizeof(data);
  532. data = 0;
  533. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC2_9 + mst_offset,
  534. data);
  535. memcpy(buf + off, &data, sizeof(data));
  536. off += sizeof(data);
  537. print_hex_dump(KERN_DEBUG, "[drm-dp] HDR: ",
  538. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  539. }
  540. static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel)
  541. {
  542. struct dp_catalog_private *catalog;
  543. struct dp_io_data *io_data;
  544. u32 header, parity, data, mst_offset = 0;
  545. u8 bpc, off = 0;
  546. u8 buf[SZ_128];
  547. if (!panel) {
  548. pr_err("invalid input\n");
  549. return;
  550. }
  551. if (panel->stream_id >= DP_STREAM_MAX) {
  552. pr_err("invalid stream_id:%d\n", panel->stream_id);
  553. return;
  554. }
  555. if (panel->stream_id == DP_STREAM_1)
  556. mst_offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  557. catalog = dp_catalog_get_priv(panel);
  558. io_data = catalog->io.dp_link;
  559. /* HEADER BYTE 1 */
  560. header = panel->hdr_data.vsc_header_byte1;
  561. parity = dp_header_get_parity(header);
  562. data = ((header << HEADER_BYTE_1_BIT)
  563. | (parity << PARITY_BYTE_1_BIT));
  564. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_0 + mst_offset,
  565. data);
  566. memcpy(buf + off, &data, sizeof(data));
  567. off += sizeof(data);
  568. /* HEADER BYTE 2 */
  569. header = panel->hdr_data.vsc_header_byte2;
  570. parity = dp_header_get_parity(header);
  571. data = ((header << HEADER_BYTE_2_BIT)
  572. | (parity << PARITY_BYTE_2_BIT));
  573. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_1 + mst_offset,
  574. data);
  575. /* HEADER BYTE 3 */
  576. header = panel->hdr_data.vsc_header_byte3;
  577. parity = dp_header_get_parity(header);
  578. data = ((header << HEADER_BYTE_3_BIT)
  579. | (parity << PARITY_BYTE_3_BIT));
  580. data |= dp_read(catalog->exe_mode, io_data,
  581. MMSS_DP_GENERIC0_1 + mst_offset);
  582. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_1 + mst_offset,
  583. data);
  584. memcpy(buf + off, &data, sizeof(data));
  585. off += sizeof(data);
  586. data = 0;
  587. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_2 + mst_offset,
  588. data);
  589. memcpy(buf + off, &data, sizeof(data));
  590. off += sizeof(data);
  591. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_3 + mst_offset,
  592. data);
  593. memcpy(buf + off, &data, sizeof(data));
  594. off += sizeof(data);
  595. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_4 + mst_offset,
  596. data);
  597. memcpy(buf + off, &data, sizeof(data));
  598. off += sizeof(data);
  599. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_5 + mst_offset,
  600. data);
  601. memcpy(buf + off, &data, sizeof(data));
  602. off += sizeof(data);
  603. switch (panel->hdr_data.bpc) {
  604. default:
  605. case 10:
  606. bpc = BIT(1);
  607. break;
  608. case 8:
  609. bpc = BIT(0);
  610. break;
  611. case 6:
  612. bpc = 0;
  613. break;
  614. }
  615. data = (panel->hdr_data.colorimetry & 0xF) |
  616. ((panel->hdr_data.pixel_encoding & 0xF) << 4) |
  617. (bpc << 8) |
  618. ((panel->hdr_data.dynamic_range & 0x1) << 15) |
  619. ((panel->hdr_data.content_type & 0x7) << 16);
  620. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_6 + mst_offset,
  621. data);
  622. memcpy(buf + off, &data, sizeof(data));
  623. off += sizeof(data);
  624. data = 0;
  625. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_7 + mst_offset,
  626. data);
  627. memcpy(buf + off, &data, sizeof(data));
  628. off += sizeof(data);
  629. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_8 + mst_offset,
  630. data);
  631. memcpy(buf + off, &data, sizeof(data));
  632. off += sizeof(data);
  633. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC0_9 + mst_offset,
  634. data);
  635. memcpy(buf + off, &data, sizeof(data));
  636. off += sizeof(data);
  637. print_hex_dump(KERN_DEBUG, "[drm-dp] VSC: ",
  638. DUMP_PREFIX_NONE, 16, 4, buf, off, false);
  639. }
  640. static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en,
  641. u32 dhdr_max_pkts)
  642. {
  643. struct dp_catalog_private *catalog;
  644. struct dp_io_data *io_data;
  645. u32 cfg, cfg2, cfg4, misc;
  646. u32 sdp_cfg_off = 0;
  647. u32 sdp_cfg2_off = 0;
  648. u32 sdp_cfg3_off = 0;
  649. u32 sdp_cfg4_off = 0;
  650. u32 misc1_misc0_off = 0;
  651. if (!panel) {
  652. pr_err("invalid input\n");
  653. return;
  654. }
  655. if (panel->stream_id >= DP_STREAM_MAX) {
  656. pr_err("invalid stream_id:%d\n", panel->stream_id);
  657. return;
  658. }
  659. catalog = dp_catalog_get_priv(panel);
  660. io_data = catalog->io.dp_link;
  661. if (panel->stream_id == DP_STREAM_1) {
  662. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  663. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  664. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  665. sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4;
  666. misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  667. }
  668. cfg = dp_read(catalog->exe_mode, io_data,
  669. MMSS_DP_SDP_CFG + sdp_cfg_off);
  670. cfg2 = dp_read(catalog->exe_mode, io_data,
  671. MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  672. misc = dp_read(catalog->exe_mode, io_data,
  673. DP_MISC1_MISC0 + misc1_misc0_off);
  674. if (en) {
  675. if (dhdr_max_pkts) {
  676. /* VSCEXT_SDP_EN */
  677. cfg |= BIT(16);
  678. /* DHDR_EN, DHDR_PACKET_LIMIT */
  679. cfg4 = (dhdr_max_pkts << 1) | BIT(0);
  680. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4
  681. + sdp_cfg4_off, cfg4);
  682. dp_catalog_panel_setup_vsif_infoframe_sdp(panel);
  683. }
  684. /* GEN0_SDP_EN, GEN2_SDP_EN */
  685. cfg |= BIT(17) | BIT(19);
  686. dp_write(catalog->exe_mode, io_data,
  687. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  688. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  689. cfg2 |= BIT(16) | BIT(20);
  690. dp_write(catalog->exe_mode, io_data,
  691. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  692. dp_catalog_panel_setup_vsc_sdp(panel);
  693. dp_catalog_panel_setup_hdr_infoframe_sdp(panel);
  694. /* indicates presence of VSC (BIT(6) of MISC1) */
  695. misc |= BIT(14);
  696. if (panel->hdr_data.hdr_meta.eotf)
  697. pr_debug("Enabled\n");
  698. else
  699. pr_debug("Reset\n");
  700. } else {
  701. /* VSCEXT_SDP_EN, GEN0_SDP_EN */
  702. cfg &= ~BIT(16) & ~BIT(17) & ~BIT(19);
  703. dp_write(catalog->exe_mode, io_data,
  704. MMSS_DP_SDP_CFG + sdp_cfg_off, cfg);
  705. /* GENERIC0_SDPSIZE GENERIC2_SDPSIZE */
  706. cfg2 &= ~BIT(16) & ~BIT(20);
  707. dp_write(catalog->exe_mode, io_data,
  708. MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2);
  709. /* DHDR_EN, DHDR_PACKET_LIMIT */
  710. cfg4 = 0;
  711. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4
  712. + sdp_cfg4_off, cfg4);
  713. /* switch back to MSA */
  714. misc &= ~BIT(14);
  715. pr_debug("Disabled\n");
  716. }
  717. dp_write(catalog->exe_mode, io_data, DP_MISC1_MISC0 + misc1_misc0_off,
  718. misc);
  719. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  720. 0x01);
  721. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  722. 0x00);
  723. }
  724. static void dp_catalog_panel_update_transfer_unit(
  725. struct dp_catalog_panel *panel)
  726. {
  727. struct dp_catalog_private *catalog;
  728. struct dp_io_data *io_data;
  729. if (!panel || panel->stream_id >= DP_STREAM_MAX) {
  730. pr_err("invalid input\n");
  731. return;
  732. }
  733. catalog = dp_catalog_get_priv(panel);
  734. io_data = catalog->io.dp_link;
  735. dp_write(catalog->exe_mode, io_data, DP_VALID_BOUNDARY,
  736. panel->valid_boundary);
  737. dp_write(catalog->exe_mode, io_data, DP_TU, panel->dp_tu);
  738. dp_write(catalog->exe_mode, io_data, DP_VALID_BOUNDARY_2,
  739. panel->valid_boundary2);
  740. }
  741. static void dp_catalog_ctrl_state_ctrl(struct dp_catalog_ctrl *ctrl, u32 state)
  742. {
  743. struct dp_catalog_private *catalog;
  744. struct dp_io_data *io_data;
  745. if (!ctrl) {
  746. pr_err("invalid input\n");
  747. return;
  748. }
  749. catalog = dp_catalog_get_priv(ctrl);
  750. io_data = catalog->io.dp_link;
  751. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, state);
  752. /* make sure to change the hw state */
  753. wmb();
  754. }
  755. static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)
  756. {
  757. struct dp_catalog_private *catalog;
  758. struct dp_io_data *io_data;
  759. u32 cfg;
  760. if (!ctrl) {
  761. pr_err("invalid input\n");
  762. return;
  763. }
  764. catalog = dp_catalog_get_priv(ctrl);
  765. io_data = catalog->io.dp_link;
  766. cfg = dp_read(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL);
  767. cfg &= ~(BIT(4) | BIT(5));
  768. cfg |= (ln_cnt - 1) << 4;
  769. dp_write(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL, cfg);
  770. cfg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  771. cfg |= 0x02000000;
  772. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, cfg);
  773. pr_debug("DP_MAINLINK_CTRL=0x%x\n", cfg);
  774. }
  775. static void dp_catalog_panel_config_ctrl(struct dp_catalog_panel *panel,
  776. u32 cfg)
  777. {
  778. struct dp_catalog_private *catalog;
  779. struct dp_io_data *io_data;
  780. u32 strm_reg_off = 0, mainlink_ctrl;
  781. if (!panel) {
  782. pr_err("invalid input\n");
  783. return;
  784. }
  785. if (panel->stream_id >= DP_STREAM_MAX) {
  786. pr_err("invalid stream_id:%d\n", panel->stream_id);
  787. return;
  788. }
  789. catalog = dp_catalog_get_priv(panel);
  790. io_data = catalog->io.dp_link;
  791. if (panel->stream_id == DP_STREAM_1)
  792. strm_reg_off = DP1_CONFIGURATION_CTRL - DP_CONFIGURATION_CTRL;
  793. pr_debug("DP_CONFIGURATION_CTRL=0x%x\n", cfg);
  794. dp_write(catalog->exe_mode, io_data,
  795. DP_CONFIGURATION_CTRL + strm_reg_off, cfg);
  796. mainlink_ctrl = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  797. if (panel->stream_id == DP_STREAM_0)
  798. io_data = catalog->io.dp_p0;
  799. else if (panel->stream_id == DP_STREAM_1)
  800. io_data = catalog->io.dp_p1;
  801. if (mainlink_ctrl & BIT(8))
  802. dp_write(catalog->exe_mode, io_data, MMSS_DP_ASYNC_FIFO_CONFIG,
  803. 0x01);
  804. else
  805. dp_write(catalog->exe_mode, io_data, MMSS_DP_ASYNC_FIFO_CONFIG,
  806. 0x00);
  807. }
  808. static void dp_catalog_panel_config_dto(struct dp_catalog_panel *panel,
  809. bool ack)
  810. {
  811. struct dp_catalog_private *catalog;
  812. struct dp_io_data *io_data;
  813. u32 dsc_dto;
  814. if (!panel) {
  815. pr_err("invalid input\n");
  816. return;
  817. }
  818. if (panel->stream_id >= DP_STREAM_MAX) {
  819. pr_err("invalid stream_id:%d\n", panel->stream_id);
  820. return;
  821. }
  822. catalog = dp_catalog_get_priv(panel);
  823. io_data = catalog->io.dp_link;
  824. switch (panel->stream_id) {
  825. case DP_STREAM_0:
  826. io_data = catalog->io.dp_p0;
  827. break;
  828. case DP_STREAM_1:
  829. io_data = catalog->io.dp_p1;
  830. break;
  831. default:
  832. pr_err("invalid stream id\n");
  833. return;
  834. }
  835. dsc_dto = dp_read(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO);
  836. if (ack)
  837. dsc_dto = BIT(1);
  838. else
  839. dsc_dto &= ~BIT(1);
  840. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO, dsc_dto);
  841. }
  842. static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl,
  843. bool flipped, char *lane_map)
  844. {
  845. struct dp_catalog_private *catalog;
  846. struct dp_io_data *io_data;
  847. if (!ctrl) {
  848. pr_err("invalid input\n");
  849. return;
  850. }
  851. catalog = dp_catalog_get_priv(ctrl);
  852. io_data = catalog->io.dp_link;
  853. dp_write(catalog->exe_mode, io_data, DP_LOGICAL2PHYSICAL_LANE_MAPPING,
  854. 0xe4);
  855. }
  856. static void dp_catalog_ctrl_lane_pnswap(struct dp_catalog_ctrl *ctrl,
  857. u8 ln_pnswap)
  858. {
  859. struct dp_catalog_private *catalog;
  860. struct dp_io_data *io_data;
  861. u32 cfg0, cfg1;
  862. catalog = dp_catalog_get_priv(ctrl);
  863. cfg0 = 0x0a;
  864. cfg1 = 0x0a;
  865. cfg0 |= ((ln_pnswap >> 0) & 0x1) << 0;
  866. cfg0 |= ((ln_pnswap >> 1) & 0x1) << 2;
  867. cfg1 |= ((ln_pnswap >> 2) & 0x1) << 0;
  868. cfg1 |= ((ln_pnswap >> 3) & 0x1) << 2;
  869. io_data = catalog->io.dp_ln_tx0;
  870. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg0);
  871. io_data = catalog->io.dp_ln_tx1;
  872. dp_write(catalog->exe_mode, io_data, TXn_TX_POL_INV, cfg1);
  873. }
  874. static void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog_ctrl *ctrl,
  875. bool enable)
  876. {
  877. u32 mainlink_ctrl, reg;
  878. struct dp_catalog_private *catalog;
  879. struct dp_io_data *io_data;
  880. if (!ctrl) {
  881. pr_err("invalid input\n");
  882. return;
  883. }
  884. catalog = dp_catalog_get_priv(ctrl);
  885. io_data = catalog->io.dp_link;
  886. if (enable) {
  887. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  888. mainlink_ctrl = reg & ~(0x03);
  889. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  890. mainlink_ctrl);
  891. wmb(); /* make sure mainlink is turned off before reset */
  892. mainlink_ctrl = reg | 0x02;
  893. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  894. mainlink_ctrl);
  895. wmb(); /* make sure mainlink entered reset */
  896. mainlink_ctrl = reg & ~(0x03);
  897. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  898. mainlink_ctrl);
  899. wmb(); /* make sure mainlink reset done */
  900. mainlink_ctrl = reg | 0x01;
  901. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  902. mainlink_ctrl);
  903. wmb(); /* make sure mainlink turned on */
  904. } else {
  905. mainlink_ctrl = dp_read(catalog->exe_mode, io_data,
  906. DP_MAINLINK_CTRL);
  907. mainlink_ctrl &= ~BIT(0);
  908. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL,
  909. mainlink_ctrl);
  910. }
  911. }
  912. static void dp_catalog_panel_config_misc(struct dp_catalog_panel *panel)
  913. {
  914. struct dp_catalog_private *catalog;
  915. struct dp_io_data *io_data;
  916. u32 reg_offset = 0;
  917. if (!panel) {
  918. pr_err("invalid input\n");
  919. return;
  920. }
  921. if (panel->stream_id >= DP_STREAM_MAX) {
  922. pr_err("invalid stream_id:%d\n", panel->stream_id);
  923. return;
  924. }
  925. catalog = dp_catalog_get_priv(panel);
  926. io_data = catalog->io.dp_link;
  927. if (panel->stream_id == DP_STREAM_1)
  928. reg_offset = DP1_MISC1_MISC0 - DP_MISC1_MISC0;
  929. pr_debug("misc settings = 0x%x\n", panel->misc_val);
  930. dp_write(catalog->exe_mode, io_data, DP_MISC1_MISC0 + reg_offset,
  931. panel->misc_val);
  932. }
  933. static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
  934. u32 rate, u32 stream_rate_khz)
  935. {
  936. u32 pixel_m, pixel_n;
  937. u32 mvid, nvid;
  938. u32 const nvid_fixed = 0x8000;
  939. u32 const link_rate_hbr2 = 540000;
  940. u32 const link_rate_hbr3 = 810000;
  941. struct dp_catalog_private *catalog;
  942. struct dp_io_data *io_data;
  943. u32 strm_reg_off = 0;
  944. u32 mvid_reg_off = 0, nvid_reg_off = 0;
  945. if (!panel) {
  946. pr_err("invalid input\n");
  947. return;
  948. }
  949. if (panel->stream_id >= DP_STREAM_MAX) {
  950. pr_err("invalid stream_id:%d\n", panel->stream_id);
  951. return;
  952. }
  953. catalog = dp_catalog_get_priv(panel);
  954. io_data = catalog->io.dp_mmss_cc;
  955. if (panel->stream_id == DP_STREAM_1)
  956. strm_reg_off = MMSS_DP_PIXEL1_M - MMSS_DP_PIXEL_M;
  957. pixel_m = dp_read(catalog->exe_mode, io_data,
  958. MMSS_DP_PIXEL_M + strm_reg_off);
  959. pixel_n = dp_read(catalog->exe_mode, io_data,
  960. MMSS_DP_PIXEL_N + strm_reg_off);
  961. pr_debug("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n);
  962. mvid = (pixel_m & 0xFFFF) * 5;
  963. nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);
  964. if (nvid < nvid_fixed) {
  965. u32 temp;
  966. temp = (nvid_fixed / nvid) * nvid;
  967. mvid = (nvid_fixed / nvid) * mvid;
  968. nvid = temp;
  969. }
  970. pr_debug("rate = %d\n", rate);
  971. if (panel->widebus_en)
  972. mvid <<= 1;
  973. if (link_rate_hbr2 == rate)
  974. nvid *= 2;
  975. if (link_rate_hbr3 == rate)
  976. nvid *= 3;
  977. io_data = catalog->io.dp_link;
  978. if (panel->stream_id == DP_STREAM_1) {
  979. mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID;
  980. nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID;
  981. }
  982. pr_debug("mvid=0x%x, nvid=0x%x\n", mvid, nvid);
  983. dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_MVID + mvid_reg_off,
  984. mvid);
  985. dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID + nvid_reg_off,
  986. nvid);
  987. }
  988. static void dp_catalog_ctrl_set_pattern(struct dp_catalog_ctrl *ctrl,
  989. u32 pattern)
  990. {
  991. int bit, cnt = 10;
  992. u32 data;
  993. struct dp_catalog_private *catalog;
  994. struct dp_io_data *io_data;
  995. if (!ctrl) {
  996. pr_err("invalid input\n");
  997. return;
  998. }
  999. catalog = dp_catalog_get_priv(ctrl);
  1000. io_data = catalog->io.dp_link;
  1001. bit = 1;
  1002. bit <<= (pattern - 1);
  1003. pr_debug("hw: bit=%d train=%d\n", bit, pattern);
  1004. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, bit);
  1005. bit = 8;
  1006. bit <<= (pattern - 1);
  1007. while (cnt--) {
  1008. data = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1009. if (data & bit)
  1010. break;
  1011. }
  1012. if (cnt == 0)
  1013. pr_err("set link_train=%d failed\n", pattern);
  1014. }
  1015. static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip)
  1016. {
  1017. struct dp_catalog_private *catalog;
  1018. struct dp_io_data *io_data;
  1019. if (!ctrl) {
  1020. pr_err("invalid input\n");
  1021. return;
  1022. }
  1023. catalog = dp_catalog_get_priv(ctrl);
  1024. io_data = catalog->io.usb3_dp_com;
  1025. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_RESET_OVRD_CTRL, 0x0a);
  1026. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_PHY_MODE_CTRL, 0x02);
  1027. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SW_RESET, 0x01);
  1028. /* make sure usb3 com phy software reset is done */
  1029. wmb();
  1030. if (!flip) { /* CC1 */
  1031. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_TYPEC_CTRL,
  1032. 0x02);
  1033. } else { /* CC2 */
  1034. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_TYPEC_CTRL,
  1035. 0x03);
  1036. }
  1037. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SWI_CTRL, 0x00);
  1038. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_SW_RESET, 0x00);
  1039. /* make sure the software reset is done */
  1040. wmb();
  1041. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_POWER_DOWN_CTRL, 0x01);
  1042. dp_write(catalog->exe_mode, io_data, USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
  1043. /* make sure phy is brought out of reset */
  1044. wmb();
  1045. }
  1046. static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
  1047. bool enable)
  1048. {
  1049. struct dp_catalog_private *catalog;
  1050. struct dp_io_data *io_data;
  1051. if (!panel) {
  1052. pr_err("invalid input\n");
  1053. return;
  1054. }
  1055. if (panel->stream_id >= DP_STREAM_MAX) {
  1056. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1057. return;
  1058. }
  1059. catalog = dp_catalog_get_priv(panel);
  1060. if (panel->stream_id == DP_STREAM_0)
  1061. io_data = catalog->io.dp_p0;
  1062. else if (panel->stream_id == DP_STREAM_1)
  1063. io_data = catalog->io.dp_p1;
  1064. if (!enable) {
  1065. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_MAIN_CONTROL,
  1066. 0x0);
  1067. dp_write(catalog->exe_mode, io_data, MMSS_DP_BIST_ENABLE, 0x0);
  1068. dp_write(catalog->exe_mode, io_data, MMSS_DP_TIMING_ENGINE_EN,
  1069. 0x0);
  1070. wmb(); /* ensure Timing generator is turned off */
  1071. return;
  1072. }
  1073. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG, 0x0);
  1074. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_HSYNC_CTL,
  1075. panel->hsync_ctl);
  1076. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PERIOD_F0,
  1077. panel->vsync_period * panel->hsync_period);
  1078. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
  1079. panel->v_sync_width * panel->hsync_period);
  1080. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
  1081. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1,
  1082. 0);
  1083. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_HCTL,
  1084. panel->display_hctl);
  1085. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_HCTL, 0);
  1086. dp_write(catalog->exe_mode, io_data, MMSS_INTF_DISPLAY_V_START_F0,
  1087. panel->display_v_start);
  1088. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_V_END_F0,
  1089. panel->display_v_end);
  1090. dp_write(catalog->exe_mode, io_data, MMSS_INTF_DISPLAY_V_START_F1, 0);
  1091. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
  1092. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
  1093. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
  1094. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
  1095. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
  1096. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_POLARITY_CTL, 0);
  1097. wmb(); /* ensure TPG registers are programmed */
  1098. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_MAIN_CONTROL, 0x100);
  1099. dp_write(catalog->exe_mode, io_data, MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
  1100. wmb(); /* ensure TPG config is programmed */
  1101. dp_write(catalog->exe_mode, io_data, MMSS_DP_BIST_ENABLE, 0x1);
  1102. dp_write(catalog->exe_mode, io_data, MMSS_DP_TIMING_ENGINE_EN, 0x1);
  1103. wmb(); /* ensure Timing generator is turned on */
  1104. }
  1105. static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel)
  1106. {
  1107. struct dp_catalog_private *catalog;
  1108. struct dp_io_data *io_data;
  1109. u32 reg, offset;
  1110. int i;
  1111. if (!panel) {
  1112. pr_err("invalid input\n");
  1113. return;
  1114. }
  1115. if (panel->stream_id >= DP_STREAM_MAX) {
  1116. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1117. return;
  1118. }
  1119. catalog = dp_catalog_get_priv(panel);
  1120. if (panel->stream_id == DP_STREAM_0)
  1121. io_data = catalog->io.dp_p0;
  1122. else
  1123. io_data = catalog->io.dp_p1;
  1124. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO_COUNT,
  1125. panel->dsc.dto_count);
  1126. reg = dp_read(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO);
  1127. if (panel->dsc.dto_en) {
  1128. reg |= BIT(0);
  1129. reg |= (panel->dsc.dto_n << 8);
  1130. reg |= (panel->dsc.dto_d << 16);
  1131. }
  1132. dp_write(catalog->exe_mode, io_data, MMSS_DP_DSC_DTO, reg);
  1133. io_data = catalog->io.dp_link;
  1134. if (panel->stream_id == DP_STREAM_0)
  1135. offset = 0;
  1136. else
  1137. offset = DP1_COMPRESSION_MODE_CTRL - DP_COMPRESSION_MODE_CTRL;
  1138. dp_write(catalog->exe_mode, io_data, DP_PPS_HB_0_3 + offset, 0x7F1000);
  1139. dp_write(catalog->exe_mode, io_data, DP_PPS_PB_0_3 + offset, 0xA22300);
  1140. for (i = 0; i < panel->dsc.parity_word_len; i++)
  1141. dp_write(catalog->exe_mode, io_data,
  1142. DP_PPS_PB_4_7 + (i << 2) + offset,
  1143. panel->dsc.parity_word[i]);
  1144. for (i = 0; i < panel->dsc.pps_word_len; i++)
  1145. dp_write(catalog->exe_mode, io_data,
  1146. DP_PPS_PPS_0_3 + (i << 2) + offset,
  1147. panel->dsc.pps_word[i]);
  1148. reg = 0;
  1149. if (panel->dsc.dsc_en) {
  1150. reg = BIT(0);
  1151. reg |= (panel->dsc.eol_byte_num << 3);
  1152. reg |= (panel->dsc.slice_per_pkt << 5);
  1153. reg |= (panel->dsc.bytes_per_pkt << 16);
  1154. reg |= (panel->dsc.be_in_lane << 10);
  1155. }
  1156. dp_write(catalog->exe_mode, io_data,
  1157. DP_COMPRESSION_MODE_CTRL + offset, reg);
  1158. pr_debug("compression:0x%x for stream:%d\n",
  1159. reg, panel->stream_id);
  1160. }
  1161. static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel,
  1162. enum dp_flush_bit flush_bit)
  1163. {
  1164. struct dp_catalog_private *catalog;
  1165. struct dp_io_data *io_data;
  1166. u32 dp_flush, offset;
  1167. if (!panel) {
  1168. pr_err("invalid input\n");
  1169. return;
  1170. }
  1171. if (panel->stream_id >= DP_STREAM_MAX) {
  1172. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1173. return;
  1174. }
  1175. catalog = dp_catalog_get_priv(panel);
  1176. io_data = catalog->io.dp_link;
  1177. if (panel->stream_id == DP_STREAM_0)
  1178. offset = 0;
  1179. else
  1180. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1181. dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset);
  1182. dp_flush |= BIT(flush_bit);
  1183. dp_write(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset, dp_flush);
  1184. }
  1185. static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel)
  1186. {
  1187. dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH);
  1188. pr_debug("pps flush for stream:%d\n", panel->stream_id);
  1189. }
  1190. static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel)
  1191. {
  1192. dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH);
  1193. pr_debug("dhdr flush for stream:%d\n", panel->stream_id);
  1194. }
  1195. static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel)
  1196. {
  1197. struct dp_catalog_private *catalog;
  1198. struct dp_io_data *io_data;
  1199. u32 dp_flush, offset;
  1200. if (panel->stream_id >= DP_STREAM_MAX) {
  1201. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1202. return false;
  1203. }
  1204. catalog = dp_catalog_get_priv(panel);
  1205. io_data = catalog->io.dp_link;
  1206. if (panel->stream_id == DP_STREAM_0)
  1207. offset = 0;
  1208. else
  1209. offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH;
  1210. dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset);
  1211. return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false;
  1212. }
  1213. static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl)
  1214. {
  1215. u32 sw_reset;
  1216. struct dp_catalog_private *catalog;
  1217. struct dp_io_data *io_data;
  1218. if (!ctrl) {
  1219. pr_err("invalid input\n");
  1220. return;
  1221. }
  1222. catalog = dp_catalog_get_priv(ctrl);
  1223. io_data = catalog->io.dp_ahb;
  1224. sw_reset = dp_read(catalog->exe_mode, io_data, DP_SW_RESET);
  1225. sw_reset |= BIT(0);
  1226. dp_write(catalog->exe_mode, io_data, DP_SW_RESET, sw_reset);
  1227. usleep_range(1000, 1010); /* h/w recommended delay */
  1228. sw_reset &= ~BIT(0);
  1229. dp_write(catalog->exe_mode, io_data, DP_SW_RESET, sw_reset);
  1230. }
  1231. static bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog_ctrl *ctrl)
  1232. {
  1233. u32 data;
  1234. int cnt = 10;
  1235. struct dp_catalog_private *catalog;
  1236. struct dp_io_data *io_data;
  1237. if (!ctrl) {
  1238. pr_err("invalid input\n");
  1239. goto end;
  1240. }
  1241. catalog = dp_catalog_get_priv(ctrl);
  1242. io_data = catalog->io.dp_link;
  1243. while (--cnt) {
  1244. /* DP_MAINLINK_READY */
  1245. data = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1246. if (data & BIT(0))
  1247. return true;
  1248. usleep_range(1000, 1010); /* 1ms wait before next reg read */
  1249. }
  1250. pr_err("mainlink not ready\n");
  1251. end:
  1252. return false;
  1253. }
  1254. static void dp_catalog_ctrl_enable_irq(struct dp_catalog_ctrl *ctrl,
  1255. bool enable)
  1256. {
  1257. struct dp_catalog_private *catalog;
  1258. struct dp_io_data *io_data;
  1259. if (!ctrl) {
  1260. pr_err("invalid input\n");
  1261. return;
  1262. }
  1263. catalog = dp_catalog_get_priv(ctrl);
  1264. io_data = catalog->io.dp_ahb;
  1265. if (enable) {
  1266. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS,
  1267. DP_INTR_MASK1);
  1268. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2,
  1269. DP_INTR_MASK2);
  1270. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5,
  1271. DP_INTR_MASK5);
  1272. } else {
  1273. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS, 0x00);
  1274. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2, 0x00);
  1275. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5, 0x00);
  1276. }
  1277. }
  1278. static void dp_catalog_ctrl_get_interrupt(struct dp_catalog_ctrl *ctrl)
  1279. {
  1280. u32 ack = 0;
  1281. struct dp_catalog_private *catalog;
  1282. struct dp_io_data *io_data;
  1283. if (!ctrl) {
  1284. pr_err("invalid input\n");
  1285. return;
  1286. }
  1287. catalog = dp_catalog_get_priv(ctrl);
  1288. io_data = catalog->io.dp_ahb;
  1289. ctrl->isr = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS2);
  1290. ctrl->isr &= ~DP_INTR_MASK2;
  1291. ack = ctrl->isr & DP_INTERRUPT_STATUS2;
  1292. ack <<= 1;
  1293. ack |= DP_INTR_MASK2;
  1294. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS2, ack);
  1295. ctrl->isr5 = dp_read(catalog->exe_mode, io_data, DP_INTR_STATUS5);
  1296. ctrl->isr5 &= ~DP_INTR_MASK5;
  1297. ack = ctrl->isr5 & DP_INTERRUPT_STATUS5;
  1298. ack <<= 1;
  1299. ack |= DP_INTR_MASK5;
  1300. dp_write(catalog->exe_mode, io_data, DP_INTR_STATUS5, ack);
  1301. }
  1302. static void dp_catalog_ctrl_phy_reset(struct dp_catalog_ctrl *ctrl)
  1303. {
  1304. struct dp_catalog_private *catalog;
  1305. struct dp_io_data *io_data;
  1306. if (!ctrl) {
  1307. pr_err("invalid input\n");
  1308. return;
  1309. }
  1310. catalog = dp_catalog_get_priv(ctrl);
  1311. io_data = catalog->io.dp_ahb;
  1312. dp_write(catalog->exe_mode, io_data, DP_PHY_CTRL, 0x5); /* bit 0 & 2 */
  1313. usleep_range(1000, 1010); /* h/w recommended delay */
  1314. dp_write(catalog->exe_mode, io_data, DP_PHY_CTRL, 0x0);
  1315. wmb(); /* make sure PHY reset done */
  1316. }
  1317. static void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog_ctrl *ctrl,
  1318. bool flipped, u8 ln_cnt)
  1319. {
  1320. u32 info = 0x0;
  1321. struct dp_catalog_private *catalog;
  1322. struct dp_io_data *io_data;
  1323. u8 orientation = BIT(!!flipped);
  1324. if (!ctrl) {
  1325. pr_err("invalid input\n");
  1326. return;
  1327. }
  1328. catalog = dp_catalog_get_priv(ctrl);
  1329. io_data = catalog->io.dp_phy;
  1330. info |= (ln_cnt & 0x0F);
  1331. info |= ((orientation & 0x0F) << 4);
  1332. pr_debug("Shared Info = 0x%x\n", info);
  1333. dp_write(catalog->exe_mode, io_data, DP_PHY_SPARE0, info);
  1334. }
  1335. static void dp_catalog_ctrl_update_vx_px(struct dp_catalog_ctrl *ctrl,
  1336. u8 v_level, u8 p_level, bool high)
  1337. {
  1338. struct dp_catalog_private *catalog;
  1339. struct dp_io_data *io_data;
  1340. u8 value0, value1;
  1341. if (!ctrl) {
  1342. pr_err("invalid input\n");
  1343. return;
  1344. }
  1345. catalog = dp_catalog_get_priv(ctrl);
  1346. pr_debug("hw: v=%d p=%d\n", v_level, p_level);
  1347. value0 = vm_voltage_swing[v_level][p_level];
  1348. value1 = vm_pre_emphasis[v_level][p_level];
  1349. /* program default setting first */
  1350. io_data = catalog->io.dp_ln_tx0;
  1351. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A);
  1352. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  1353. io_data = catalog->io.dp_ln_tx1;
  1354. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, 0x2A);
  1355. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL, 0x20);
  1356. /* Enable MUX to use Cursor values from these registers */
  1357. value0 |= BIT(5);
  1358. value1 |= BIT(5);
  1359. /* Configure host and panel only if both values are allowed */
  1360. if (value0 != 0xFF && value1 != 0xFF) {
  1361. io_data = catalog->io.dp_ln_tx0;
  1362. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0);
  1363. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL,
  1364. value1);
  1365. io_data = catalog->io.dp_ln_tx1;
  1366. dp_write(catalog->exe_mode, io_data, TXn_TX_DRV_LVL, value0);
  1367. dp_write(catalog->exe_mode, io_data, TXn_TX_EMP_POST1_LVL,
  1368. value1);
  1369. pr_debug("hw: vx_value=0x%x px_value=0x%x\n",
  1370. value0, value1);
  1371. } else {
  1372. pr_err("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
  1373. v_level, value0, p_level, value1);
  1374. }
  1375. }
  1376. static void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog_ctrl *ctrl,
  1377. u32 pattern)
  1378. {
  1379. struct dp_catalog_private *catalog;
  1380. u32 value = 0x0;
  1381. struct dp_io_data *io_data = NULL;
  1382. if (!ctrl) {
  1383. pr_err("invalid input\n");
  1384. return;
  1385. }
  1386. catalog = dp_catalog_get_priv(ctrl);
  1387. io_data = catalog->io.dp_link;
  1388. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x0);
  1389. switch (pattern) {
  1390. case DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING:
  1391. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x1);
  1392. break;
  1393. case DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT:
  1394. value &= ~(1 << 16);
  1395. dp_write(catalog->exe_mode, io_data,
  1396. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1397. value |= 0xFC;
  1398. dp_write(catalog->exe_mode, io_data,
  1399. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1400. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS, 0x2);
  1401. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x10);
  1402. break;
  1403. case DP_TEST_PHY_PATTERN_PRBS7:
  1404. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x20);
  1405. break;
  1406. case DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN:
  1407. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x40);
  1408. /* 00111110000011111000001111100000 */
  1409. dp_write(catalog->exe_mode, io_data,
  1410. DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0);
  1411. /* 00001111100000111110000011111000 */
  1412. dp_write(catalog->exe_mode, io_data,
  1413. DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8);
  1414. /* 1111100000111110 */
  1415. dp_write(catalog->exe_mode, io_data,
  1416. DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E);
  1417. break;
  1418. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_1:
  1419. value = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1420. value &= ~BIT(4);
  1421. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, value);
  1422. value = BIT(16);
  1423. dp_write(catalog->exe_mode, io_data,
  1424. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1425. value |= 0xFC;
  1426. dp_write(catalog->exe_mode, io_data,
  1427. DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value);
  1428. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS, 0x2);
  1429. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x10);
  1430. value = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1431. value |= BIT(0);
  1432. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, value);
  1433. break;
  1434. case DP_TEST_PHY_PATTERN_CP2520_PATTERN_3:
  1435. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, 0x11);
  1436. dp_write(catalog->exe_mode, io_data, DP_STATE_CTRL, 0x8);
  1437. break;
  1438. default:
  1439. pr_debug("No valid test pattern requested: 0x%x\n", pattern);
  1440. return;
  1441. }
  1442. /* Make sure the test pattern is programmed in the hardware */
  1443. wmb();
  1444. }
  1445. static u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog_ctrl *ctrl)
  1446. {
  1447. struct dp_catalog_private *catalog;
  1448. struct dp_io_data *io_data = NULL;
  1449. if (!ctrl) {
  1450. pr_err("invalid input\n");
  1451. return 0;
  1452. }
  1453. catalog = dp_catalog_get_priv(ctrl);
  1454. io_data = catalog->io.dp_link;
  1455. return dp_read(catalog->exe_mode, io_data, DP_MAINLINK_READY);
  1456. }
  1457. static void dp_catalog_ctrl_fec_config(struct dp_catalog_ctrl *ctrl,
  1458. bool enable)
  1459. {
  1460. struct dp_catalog_private *catalog;
  1461. struct dp_io_data *io_data = NULL;
  1462. u32 reg;
  1463. if (!ctrl) {
  1464. pr_err("invalid input\n");
  1465. return;
  1466. }
  1467. catalog = dp_catalog_get_priv(ctrl);
  1468. io_data = catalog->io.dp_link;
  1469. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1470. /*
  1471. * fec_en = BIT(12)
  1472. * fec_seq_mode = BIT(22)
  1473. * sde_flush = BIT(23) | BIT(24)
  1474. * fb_boundary_sel = BIT(25)
  1475. */
  1476. if (enable)
  1477. reg |= BIT(12) | BIT(22) | BIT(23) | BIT(24) | BIT(25);
  1478. else
  1479. reg &= ~BIT(12);
  1480. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, reg);
  1481. /* make sure mainlink configuration is updated with fec sequence */
  1482. wmb();
  1483. }
  1484. static int dp_catalog_reg_dump(struct dp_catalog *dp_catalog,
  1485. char *name, u8 **out_buf, u32 *out_buf_len)
  1486. {
  1487. int ret = 0;
  1488. u8 *buf;
  1489. u32 len;
  1490. struct dp_io_data *io_data;
  1491. struct dp_catalog_private *catalog;
  1492. struct dp_parser *parser;
  1493. if (!dp_catalog) {
  1494. pr_err("invalid input\n");
  1495. return -EINVAL;
  1496. }
  1497. catalog = container_of(dp_catalog, struct dp_catalog_private,
  1498. dp_catalog);
  1499. parser = catalog->parser;
  1500. parser->get_io_buf(parser, name);
  1501. io_data = parser->get_io(parser, name);
  1502. if (!io_data) {
  1503. pr_err("IO %s not found\n", name);
  1504. ret = -EINVAL;
  1505. goto end;
  1506. }
  1507. buf = io_data->buf;
  1508. len = io_data->io.len;
  1509. if (!buf || !len) {
  1510. pr_err("no buffer available\n");
  1511. ret = -ENOMEM;
  1512. goto end;
  1513. }
  1514. if (!strcmp(catalog->exe_mode, "hw") ||
  1515. !strcmp(catalog->exe_mode, "all")) {
  1516. u32 i, data;
  1517. u32 const rowsize = 4;
  1518. void __iomem *addr = io_data->io.base;
  1519. memset(buf, 0, len);
  1520. for (i = 0; i < len / rowsize; i++) {
  1521. data = readl_relaxed(addr);
  1522. memcpy(buf + (rowsize * i), &data, sizeof(u32));
  1523. addr += rowsize;
  1524. }
  1525. }
  1526. *out_buf = buf;
  1527. *out_buf_len = len;
  1528. end:
  1529. if (ret)
  1530. parser->clear_io_buf(parser);
  1531. return ret;
  1532. }
  1533. static void dp_catalog_ctrl_mst_config(struct dp_catalog_ctrl *ctrl,
  1534. bool enable)
  1535. {
  1536. struct dp_catalog_private *catalog;
  1537. struct dp_io_data *io_data = NULL;
  1538. u32 reg;
  1539. if (!ctrl) {
  1540. pr_err("invalid input\n");
  1541. return;
  1542. }
  1543. catalog = dp_catalog_get_priv(ctrl);
  1544. io_data = catalog->io.dp_link;
  1545. reg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL);
  1546. if (enable)
  1547. reg |= (0x04000100);
  1548. else
  1549. reg &= ~(0x04000100);
  1550. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_CTRL, reg);
  1551. /* make sure mainlink MST configuration is updated */
  1552. wmb();
  1553. }
  1554. static void dp_catalog_ctrl_trigger_act(struct dp_catalog_ctrl *ctrl)
  1555. {
  1556. struct dp_catalog_private *catalog;
  1557. struct dp_io_data *io_data = NULL;
  1558. if (!ctrl) {
  1559. pr_err("invalid input\n");
  1560. return;
  1561. }
  1562. catalog = dp_catalog_get_priv(ctrl);
  1563. io_data = catalog->io.dp_link;
  1564. dp_write(catalog->exe_mode, io_data, DP_MST_ACT, 0x1);
  1565. /* make sure ACT signal is performed */
  1566. wmb();
  1567. }
  1568. static void dp_catalog_ctrl_read_act_complete_sts(struct dp_catalog_ctrl *ctrl,
  1569. bool *sts)
  1570. {
  1571. struct dp_catalog_private *catalog;
  1572. struct dp_io_data *io_data = NULL;
  1573. u32 reg;
  1574. if (!ctrl || !sts) {
  1575. pr_err("invalid input\n");
  1576. return;
  1577. }
  1578. *sts = false;
  1579. catalog = dp_catalog_get_priv(ctrl);
  1580. io_data = catalog->io.dp_link;
  1581. reg = dp_read(catalog->exe_mode, io_data, DP_MST_ACT);
  1582. if (!reg)
  1583. *sts = true;
  1584. }
  1585. static void dp_catalog_ctrl_channel_alloc(struct dp_catalog_ctrl *ctrl,
  1586. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1587. {
  1588. struct dp_catalog_private *catalog;
  1589. struct dp_io_data *io_data = NULL;
  1590. u32 i, slot_reg_1, slot_reg_2, slot;
  1591. u32 reg_off = 0;
  1592. int const num_slots_per_reg = 32;
  1593. if (!ctrl || ch >= DP_STREAM_MAX) {
  1594. pr_err("invalid input. ch %d\n", ch);
  1595. return;
  1596. }
  1597. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1598. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1599. pr_err("invalid slots start %d, tot %d\n",
  1600. ch_start_slot, tot_slot_cnt);
  1601. return;
  1602. }
  1603. catalog = dp_catalog_get_priv(ctrl);
  1604. io_data = catalog->io.dp_link;
  1605. pr_debug("ch %d, start_slot %d, tot_slot %d\n",
  1606. ch, ch_start_slot, tot_slot_cnt);
  1607. if (ch == DP_STREAM_1)
  1608. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1609. slot_reg_1 = 0;
  1610. slot_reg_2 = 0;
  1611. if (ch_start_slot && tot_slot_cnt) {
  1612. ch_start_slot--;
  1613. for (i = 0; i < tot_slot_cnt; i++) {
  1614. if (ch_start_slot < num_slots_per_reg) {
  1615. slot_reg_1 |= BIT(ch_start_slot);
  1616. } else {
  1617. slot = ch_start_slot - num_slots_per_reg;
  1618. slot_reg_2 |= BIT(slot);
  1619. }
  1620. ch_start_slot++;
  1621. }
  1622. }
  1623. pr_debug("ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1624. slot_reg_1, slot_reg_2);
  1625. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_1_32 + reg_off,
  1626. slot_reg_1);
  1627. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_33_63 + reg_off,
  1628. slot_reg_2);
  1629. }
  1630. static void dp_catalog_ctrl_channel_dealloc(struct dp_catalog_ctrl *ctrl,
  1631. u32 ch, u32 ch_start_slot, u32 tot_slot_cnt)
  1632. {
  1633. struct dp_catalog_private *catalog;
  1634. struct dp_io_data *io_data = NULL;
  1635. u32 i, slot_reg_1, slot_reg_2, slot;
  1636. u32 reg_off = 0;
  1637. if (!ctrl || ch >= DP_STREAM_MAX) {
  1638. pr_err("invalid input. ch %d\n", ch);
  1639. return;
  1640. }
  1641. if (ch_start_slot > DP_MAX_TIME_SLOTS ||
  1642. (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) {
  1643. pr_err("invalid slots start %d, tot %d\n",
  1644. ch_start_slot, tot_slot_cnt);
  1645. return;
  1646. }
  1647. catalog = dp_catalog_get_priv(ctrl);
  1648. io_data = catalog->io.dp_link;
  1649. pr_debug("dealloc ch %d, start_slot %d, tot_slot %d\n",
  1650. ch, ch_start_slot, tot_slot_cnt);
  1651. if (ch == DP_STREAM_1)
  1652. reg_off = DP_DP1_TIMESLOT_1_32 - DP_DP0_TIMESLOT_1_32;
  1653. slot_reg_1 = dp_read(catalog->exe_mode, io_data,
  1654. DP_DP0_TIMESLOT_1_32 + reg_off);
  1655. slot_reg_2 = dp_read(catalog->exe_mode, io_data,
  1656. DP_DP0_TIMESLOT_33_63 + reg_off);
  1657. ch_start_slot = ch_start_slot - 1;
  1658. for (i = 0; i < tot_slot_cnt; i++) {
  1659. if (ch_start_slot < 33) {
  1660. slot_reg_1 &= ~BIT(ch_start_slot);
  1661. } else {
  1662. slot = ch_start_slot - 33;
  1663. slot_reg_2 &= ~BIT(slot);
  1664. }
  1665. ch_start_slot++;
  1666. }
  1667. pr_debug("dealloc ch:%d slot_reg_1:%d, slot_reg_2:%d\n", ch,
  1668. slot_reg_1, slot_reg_2);
  1669. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_1_32 + reg_off,
  1670. slot_reg_1);
  1671. dp_write(catalog->exe_mode, io_data, DP_DP0_TIMESLOT_33_63 + reg_off,
  1672. slot_reg_2);
  1673. }
  1674. static void dp_catalog_ctrl_update_rg(struct dp_catalog_ctrl *ctrl, u32 ch,
  1675. u32 x_int, u32 y_frac_enum)
  1676. {
  1677. struct dp_catalog_private *catalog;
  1678. struct dp_io_data *io_data = NULL;
  1679. u32 rg, reg_off = 0;
  1680. if (!ctrl || ch >= DP_STREAM_MAX) {
  1681. pr_err("invalid input. ch %d\n", ch);
  1682. return;
  1683. }
  1684. catalog = dp_catalog_get_priv(ctrl);
  1685. io_data = catalog->io.dp_link;
  1686. rg = y_frac_enum;
  1687. rg |= (x_int << 16);
  1688. pr_debug("ch: %d x_int:%d y_frac_enum:%d rg:%d\n", ch, x_int,
  1689. y_frac_enum, rg);
  1690. if (ch == DP_STREAM_1)
  1691. reg_off = DP_DP1_RG - DP_DP0_RG;
  1692. dp_write(catalog->exe_mode, io_data, DP_DP0_RG + reg_off, rg);
  1693. }
  1694. static void dp_catalog_ctrl_mainlink_levels(struct dp_catalog_ctrl *ctrl,
  1695. u8 lane_cnt)
  1696. {
  1697. struct dp_catalog_private *catalog;
  1698. struct dp_io_data *io_data;
  1699. u32 mainlink_levels, safe_to_exit_level = 14;
  1700. catalog = dp_catalog_get_priv(ctrl);
  1701. io_data = catalog->io.dp_link;
  1702. switch (lane_cnt) {
  1703. case 1:
  1704. safe_to_exit_level = 14;
  1705. break;
  1706. case 2:
  1707. safe_to_exit_level = 8;
  1708. break;
  1709. case 4:
  1710. safe_to_exit_level = 5;
  1711. break;
  1712. default:
  1713. pr_debug("setting the default safe_to_exit_level = %u\n",
  1714. safe_to_exit_level);
  1715. break;
  1716. }
  1717. mainlink_levels = dp_read(catalog->exe_mode, io_data,
  1718. DP_MAINLINK_LEVELS);
  1719. mainlink_levels &= 0xFE0;
  1720. mainlink_levels |= safe_to_exit_level;
  1721. pr_debug("mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n",
  1722. mainlink_levels, safe_to_exit_level);
  1723. dp_write(catalog->exe_mode, io_data, DP_MAINLINK_LEVELS,
  1724. mainlink_levels);
  1725. }
  1726. /* panel related catalog functions */
  1727. static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel)
  1728. {
  1729. struct dp_catalog_private *catalog;
  1730. struct dp_io_data *io_data;
  1731. u32 offset = 0, reg;
  1732. if (!panel) {
  1733. pr_err("invalid input\n");
  1734. goto end;
  1735. }
  1736. if (panel->stream_id >= DP_STREAM_MAX) {
  1737. pr_err("invalid stream_id:%d\n", panel->stream_id);
  1738. goto end;
  1739. }
  1740. catalog = dp_catalog_get_priv(panel);
  1741. io_data = catalog->io.dp_link;
  1742. if (panel->stream_id == DP_STREAM_1)
  1743. offset = DP1_TOTAL_HOR_VER - DP_TOTAL_HOR_VER;
  1744. dp_write(catalog->exe_mode, io_data, DP_TOTAL_HOR_VER + offset,
  1745. panel->total);
  1746. dp_write(catalog->exe_mode, io_data,
  1747. DP_START_HOR_VER_FROM_SYNC + offset, panel->sync_start);
  1748. dp_write(catalog->exe_mode, io_data,
  1749. DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, panel->width_blanking);
  1750. dp_write(catalog->exe_mode, io_data, DP_ACTIVE_HOR_VER + offset,
  1751. panel->dp_active);
  1752. if (panel->stream_id == DP_STREAM_0)
  1753. io_data = catalog->io.dp_p0;
  1754. else
  1755. io_data = catalog->io.dp_p1;
  1756. reg = dp_read(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG);
  1757. if (panel->widebus_en)
  1758. reg |= BIT(4);
  1759. else
  1760. reg &= ~BIT(4);
  1761. dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG, reg);
  1762. end:
  1763. return 0;
  1764. }
  1765. static void dp_catalog_hpd_config_hpd(struct dp_catalog_hpd *hpd, bool en)
  1766. {
  1767. struct dp_catalog_private *catalog;
  1768. struct dp_io_data *io_data;
  1769. if (!hpd) {
  1770. pr_err("invalid input\n");
  1771. return;
  1772. }
  1773. catalog = dp_catalog_get_priv(hpd);
  1774. io_data = catalog->io.dp_aux;
  1775. if (en) {
  1776. u32 reftimer = dp_read(catalog->exe_mode, io_data,
  1777. DP_DP_HPD_REFTIMER);
  1778. /* Arm only the UNPLUG and HPD_IRQ interrupts */
  1779. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_ACK, 0xF);
  1780. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_MASK, 0xA);
  1781. /* Enable REFTIMER to count 1ms */
  1782. reftimer |= BIT(16);
  1783. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_REFTIMER,
  1784. reftimer);
  1785. /* Connect_time is 250us & disconnect_time is 2ms */
  1786. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_EVENT_TIME_0,
  1787. 0x3E800FA);
  1788. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_EVENT_TIME_1,
  1789. 0x1F407D0);
  1790. /* Enable HPD */
  1791. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_CTRL, 0x1);
  1792. } else {
  1793. /* Disable HPD */
  1794. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_CTRL, 0x0);
  1795. }
  1796. }
  1797. static u32 dp_catalog_hpd_get_interrupt(struct dp_catalog_hpd *hpd)
  1798. {
  1799. u32 isr = 0;
  1800. struct dp_catalog_private *catalog;
  1801. struct dp_io_data *io_data;
  1802. if (!hpd) {
  1803. pr_err("invalid input\n");
  1804. return isr;
  1805. }
  1806. catalog = dp_catalog_get_priv(hpd);
  1807. io_data = catalog->io.dp_aux;
  1808. isr = dp_read(catalog->exe_mode, io_data, DP_DP_HPD_INT_STATUS);
  1809. dp_write(catalog->exe_mode, io_data, DP_DP_HPD_INT_ACK, (isr & 0xf));
  1810. return isr;
  1811. }
  1812. static void dp_catalog_audio_init(struct dp_catalog_audio *audio)
  1813. {
  1814. struct dp_catalog_private *catalog;
  1815. static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = {
  1816. {
  1817. MMSS_DP_AUDIO_STREAM_0,
  1818. MMSS_DP_AUDIO_STREAM_1,
  1819. MMSS_DP_AUDIO_STREAM_1,
  1820. },
  1821. {
  1822. MMSS_DP_AUDIO_TIMESTAMP_0,
  1823. MMSS_DP_AUDIO_TIMESTAMP_1,
  1824. MMSS_DP_AUDIO_TIMESTAMP_1,
  1825. },
  1826. {
  1827. MMSS_DP_AUDIO_INFOFRAME_0,
  1828. MMSS_DP_AUDIO_INFOFRAME_1,
  1829. MMSS_DP_AUDIO_INFOFRAME_1,
  1830. },
  1831. {
  1832. MMSS_DP_AUDIO_COPYMANAGEMENT_0,
  1833. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1834. MMSS_DP_AUDIO_COPYMANAGEMENT_1,
  1835. },
  1836. {
  1837. MMSS_DP_AUDIO_ISRC_0,
  1838. MMSS_DP_AUDIO_ISRC_1,
  1839. MMSS_DP_AUDIO_ISRC_1,
  1840. },
  1841. };
  1842. if (!audio)
  1843. return;
  1844. catalog = dp_catalog_get_priv(audio);
  1845. catalog->audio_map = sdp_map;
  1846. }
  1847. static void dp_catalog_audio_config_sdp(struct dp_catalog_audio *audio)
  1848. {
  1849. struct dp_catalog_private *catalog;
  1850. struct dp_io_data *io_data;
  1851. u32 sdp_cfg = 0, sdp_cfg_off = 0;
  1852. u32 sdp_cfg2 = 0, sdp_cfg2_off = 0;
  1853. if (!audio)
  1854. return;
  1855. if (audio->stream_id >= DP_STREAM_MAX) {
  1856. pr_err("invalid stream id:%d\n", audio->stream_id);
  1857. return;
  1858. }
  1859. if (audio->stream_id == DP_STREAM_1) {
  1860. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  1861. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  1862. }
  1863. catalog = dp_catalog_get_priv(audio);
  1864. io_data = catalog->io.dp_link;
  1865. sdp_cfg = dp_read(catalog->exe_mode, io_data,
  1866. MMSS_DP_SDP_CFG + sdp_cfg_off);
  1867. /* AUDIO_TIMESTAMP_SDP_EN */
  1868. sdp_cfg |= BIT(1);
  1869. /* AUDIO_STREAM_SDP_EN */
  1870. sdp_cfg |= BIT(2);
  1871. /* AUDIO_COPY_MANAGEMENT_SDP_EN */
  1872. sdp_cfg |= BIT(5);
  1873. /* AUDIO_ISRC_SDP_EN */
  1874. sdp_cfg |= BIT(6);
  1875. /* AUDIO_INFOFRAME_SDP_EN */
  1876. sdp_cfg |= BIT(20);
  1877. pr_debug("sdp_cfg = 0x%x\n", sdp_cfg);
  1878. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG + sdp_cfg_off,
  1879. sdp_cfg);
  1880. sdp_cfg2 = dp_read(catalog->exe_mode, io_data,
  1881. MMSS_DP_SDP_CFG2 + sdp_cfg_off);
  1882. /* IFRM_REGSRC -> Do not use reg values */
  1883. sdp_cfg2 &= ~BIT(0);
  1884. /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */
  1885. sdp_cfg2 &= ~BIT(1);
  1886. pr_debug("sdp_cfg2 = 0x%x\n", sdp_cfg2);
  1887. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg_off,
  1888. sdp_cfg2);
  1889. }
  1890. static void dp_catalog_audio_get_header(struct dp_catalog_audio *audio)
  1891. {
  1892. struct dp_catalog_private *catalog;
  1893. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1894. struct dp_io_data *io_data;
  1895. enum dp_catalog_audio_sdp_type sdp;
  1896. enum dp_catalog_audio_header_type header;
  1897. if (!audio)
  1898. return;
  1899. catalog = dp_catalog_get_priv(audio);
  1900. io_data = catalog->io.dp_link;
  1901. sdp_map = catalog->audio_map;
  1902. sdp = audio->sdp_type;
  1903. header = audio->sdp_header;
  1904. audio->data = dp_read(catalog->exe_mode, io_data, sdp_map[sdp][header]);
  1905. }
  1906. static void dp_catalog_audio_set_header(struct dp_catalog_audio *audio)
  1907. {
  1908. struct dp_catalog_private *catalog;
  1909. u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
  1910. struct dp_io_data *io_data;
  1911. enum dp_catalog_audio_sdp_type sdp;
  1912. enum dp_catalog_audio_header_type header;
  1913. u32 data;
  1914. if (!audio)
  1915. return;
  1916. catalog = dp_catalog_get_priv(audio);
  1917. io_data = catalog->io.dp_link;
  1918. sdp_map = catalog->audio_map;
  1919. sdp = audio->sdp_type;
  1920. header = audio->sdp_header;
  1921. data = audio->data;
  1922. dp_write(catalog->exe_mode, io_data, sdp_map[sdp][header], data);
  1923. }
  1924. static void dp_catalog_audio_config_acr(struct dp_catalog_audio *audio)
  1925. {
  1926. struct dp_catalog_private *catalog;
  1927. struct dp_io_data *io_data;
  1928. u32 acr_ctrl, select;
  1929. catalog = dp_catalog_get_priv(audio);
  1930. select = audio->data;
  1931. io_data = catalog->io.dp_link;
  1932. acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
  1933. pr_debug("select = 0x%x, acr_ctrl = 0x%x\n", select, acr_ctrl);
  1934. dp_write(catalog->exe_mode, io_data, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
  1935. }
  1936. static void dp_catalog_audio_enable(struct dp_catalog_audio *audio)
  1937. {
  1938. struct dp_catalog_private *catalog;
  1939. struct dp_io_data *io_data;
  1940. bool enable;
  1941. u32 audio_ctrl;
  1942. catalog = dp_catalog_get_priv(audio);
  1943. io_data = catalog->io.dp_link;
  1944. enable = !!audio->data;
  1945. audio_ctrl = dp_read(catalog->exe_mode, io_data, MMSS_DP_AUDIO_CFG);
  1946. if (enable)
  1947. audio_ctrl |= BIT(0);
  1948. else
  1949. audio_ctrl &= ~BIT(0);
  1950. pr_debug("dp_audio_cfg = 0x%x\n", audio_ctrl);
  1951. dp_write(catalog->exe_mode, io_data, MMSS_DP_AUDIO_CFG, audio_ctrl);
  1952. /* make sure audio engine is disabled */
  1953. wmb();
  1954. }
  1955. static void dp_catalog_config_spd_header(struct dp_catalog_panel *panel)
  1956. {
  1957. struct dp_catalog_private *catalog;
  1958. struct dp_io_data *io_data;
  1959. u32 value, new_value, offset = 0;
  1960. u8 parity_byte;
  1961. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  1962. return;
  1963. catalog = dp_catalog_get_priv(panel);
  1964. io_data = catalog->io.dp_link;
  1965. if (panel->stream_id == DP_STREAM_1)
  1966. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  1967. /* Config header and parity byte 1 */
  1968. value = dp_read(catalog->exe_mode, io_data,
  1969. MMSS_DP_GENERIC1_0 + offset);
  1970. new_value = 0x83;
  1971. parity_byte = dp_header_get_parity(new_value);
  1972. value |= ((new_value << HEADER_BYTE_1_BIT)
  1973. | (parity_byte << PARITY_BYTE_1_BIT));
  1974. pr_debug("Header Byte 1: value = 0x%x, parity_byte = 0x%x\n",
  1975. value, parity_byte);
  1976. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_0 + offset,
  1977. value);
  1978. /* Config header and parity byte 2 */
  1979. value = dp_read(catalog->exe_mode, io_data,
  1980. MMSS_DP_GENERIC1_1 + offset);
  1981. new_value = 0x1b;
  1982. parity_byte = dp_header_get_parity(new_value);
  1983. value |= ((new_value << HEADER_BYTE_2_BIT)
  1984. | (parity_byte << PARITY_BYTE_2_BIT));
  1985. pr_debug("Header Byte 2: value = 0x%x, parity_byte = 0x%x\n",
  1986. value, parity_byte);
  1987. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_1 + offset,
  1988. value);
  1989. /* Config header and parity byte 3 */
  1990. value = dp_read(catalog->exe_mode, io_data,
  1991. MMSS_DP_GENERIC1_1 + offset);
  1992. new_value = (0x0 | (0x12 << 2));
  1993. parity_byte = dp_header_get_parity(new_value);
  1994. value |= ((new_value << HEADER_BYTE_3_BIT)
  1995. | (parity_byte << PARITY_BYTE_3_BIT));
  1996. pr_debug("Header Byte 3: value = 0x%x, parity_byte = 0x%x\n",
  1997. new_value, parity_byte);
  1998. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_1 + offset,
  1999. value);
  2000. }
  2001. static void dp_catalog_panel_config_spd(struct dp_catalog_panel *panel)
  2002. {
  2003. struct dp_catalog_private *catalog;
  2004. struct dp_io_data *io_data;
  2005. u32 spd_cfg = 0, spd_cfg2 = 0;
  2006. u8 *vendor = NULL, *product = NULL;
  2007. u32 offset = 0;
  2008. u32 sdp_cfg_off = 0;
  2009. u32 sdp_cfg2_off = 0;
  2010. u32 sdp_cfg3_off = 0;
  2011. /*
  2012. * Source Device Information
  2013. * 00h unknown
  2014. * 01h Digital STB
  2015. * 02h DVD
  2016. * 03h D-VHS
  2017. * 04h HDD Video
  2018. * 05h DVC
  2019. * 06h DSC
  2020. * 07h Video CD
  2021. * 08h Game
  2022. * 09h PC general
  2023. * 0ah Bluray-Disc
  2024. * 0bh Super Audio CD
  2025. * 0ch HD DVD
  2026. * 0dh PMP
  2027. * 0eh-ffh reserved
  2028. */
  2029. u32 device_type = 0;
  2030. if (!panel || panel->stream_id >= DP_STREAM_MAX)
  2031. return;
  2032. catalog = dp_catalog_get_priv(panel);
  2033. io_data = catalog->io.dp_link;
  2034. if (panel->stream_id == DP_STREAM_1)
  2035. offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
  2036. dp_catalog_config_spd_header(panel);
  2037. vendor = panel->spd_vendor_name;
  2038. product = panel->spd_product_description;
  2039. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_2 + offset,
  2040. ((vendor[0] & 0x7f) |
  2041. ((vendor[1] & 0x7f) << 8) |
  2042. ((vendor[2] & 0x7f) << 16) |
  2043. ((vendor[3] & 0x7f) << 24)));
  2044. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_3 + offset,
  2045. ((vendor[4] & 0x7f) |
  2046. ((vendor[5] & 0x7f) << 8) |
  2047. ((vendor[6] & 0x7f) << 16) |
  2048. ((vendor[7] & 0x7f) << 24)));
  2049. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_4 + offset,
  2050. ((product[0] & 0x7f) |
  2051. ((product[1] & 0x7f) << 8) |
  2052. ((product[2] & 0x7f) << 16) |
  2053. ((product[3] & 0x7f) << 24)));
  2054. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_5 + offset,
  2055. ((product[4] & 0x7f) |
  2056. ((product[5] & 0x7f) << 8) |
  2057. ((product[6] & 0x7f) << 16) |
  2058. ((product[7] & 0x7f) << 24)));
  2059. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_6 + offset,
  2060. ((product[8] & 0x7f) |
  2061. ((product[9] & 0x7f) << 8) |
  2062. ((product[10] & 0x7f) << 16) |
  2063. ((product[11] & 0x7f) << 24)));
  2064. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_7 + offset,
  2065. ((product[12] & 0x7f) |
  2066. ((product[13] & 0x7f) << 8) |
  2067. ((product[14] & 0x7f) << 16) |
  2068. ((product[15] & 0x7f) << 24)));
  2069. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_8 + offset,
  2070. device_type);
  2071. dp_write(catalog->exe_mode, io_data, MMSS_DP_GENERIC1_9 + offset, 0x00);
  2072. if (panel->stream_id == DP_STREAM_1) {
  2073. sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
  2074. sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
  2075. sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
  2076. }
  2077. spd_cfg = dp_read(catalog->exe_mode, io_data,
  2078. MMSS_DP_SDP_CFG + sdp_cfg_off);
  2079. /* GENERIC1_SDP for SPD Infoframe */
  2080. spd_cfg |= BIT(18);
  2081. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG + sdp_cfg_off,
  2082. spd_cfg);
  2083. spd_cfg2 = dp_read(catalog->exe_mode, io_data,
  2084. MMSS_DP_SDP_CFG2 + sdp_cfg2_off);
  2085. /* 28 data bytes for SPD Infoframe with GENERIC1 set */
  2086. spd_cfg2 |= BIT(17);
  2087. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg2_off,
  2088. spd_cfg2);
  2089. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  2090. 0x1);
  2091. dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG3 + sdp_cfg3_off,
  2092. 0x0);
  2093. }
  2094. static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog)
  2095. {
  2096. struct dp_parser *parser = catalog->parser;
  2097. dp_catalog_fill_io_buf(dp_ahb);
  2098. dp_catalog_fill_io_buf(dp_aux);
  2099. dp_catalog_fill_io_buf(dp_link);
  2100. dp_catalog_fill_io_buf(dp_p0);
  2101. dp_catalog_fill_io_buf(dp_phy);
  2102. dp_catalog_fill_io_buf(dp_ln_tx0);
  2103. dp_catalog_fill_io_buf(dp_ln_tx1);
  2104. dp_catalog_fill_io_buf(dp_pll);
  2105. dp_catalog_fill_io_buf(usb3_dp_com);
  2106. dp_catalog_fill_io_buf(dp_mmss_cc);
  2107. dp_catalog_fill_io_buf(hdcp_physical);
  2108. dp_catalog_fill_io_buf(dp_p1);
  2109. dp_catalog_fill_io_buf(dp_tcsr);
  2110. }
  2111. static void dp_catalog_get_io(struct dp_catalog_private *catalog)
  2112. {
  2113. struct dp_parser *parser = catalog->parser;
  2114. dp_catalog_fill_io(dp_ahb);
  2115. dp_catalog_fill_io(dp_aux);
  2116. dp_catalog_fill_io(dp_link);
  2117. dp_catalog_fill_io(dp_p0);
  2118. dp_catalog_fill_io(dp_phy);
  2119. dp_catalog_fill_io(dp_ln_tx0);
  2120. dp_catalog_fill_io(dp_ln_tx1);
  2121. dp_catalog_fill_io(dp_pll);
  2122. dp_catalog_fill_io(usb3_dp_com);
  2123. dp_catalog_fill_io(dp_mmss_cc);
  2124. dp_catalog_fill_io(hdcp_physical);
  2125. dp_catalog_fill_io(dp_p1);
  2126. dp_catalog_fill_io(dp_tcsr);
  2127. }
  2128. static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode)
  2129. {
  2130. struct dp_catalog_private *catalog;
  2131. if (!dp_catalog) {
  2132. pr_err("invalid input\n");
  2133. return;
  2134. }
  2135. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2136. dp_catalog);
  2137. strlcpy(catalog->exe_mode, mode, sizeof(catalog->exe_mode));
  2138. if (!strcmp(catalog->exe_mode, "hw"))
  2139. catalog->parser->clear_io_buf(catalog->parser);
  2140. else
  2141. dp_catalog_get_io_buf(catalog);
  2142. if (dp_catalog->priv.data && dp_catalog->priv.put)
  2143. dp_catalog->priv.set_exe_mode(dp_catalog, mode);
  2144. }
  2145. static int dp_catalog_init(struct device *dev, struct dp_catalog *catalog,
  2146. struct dp_parser *parser)
  2147. {
  2148. int rc = 0;
  2149. struct dp_catalog_private *catalog_priv;
  2150. catalog_priv = container_of(catalog, struct dp_catalog_private,
  2151. dp_catalog);
  2152. if (parser->hw_cfg.phy_version == DP_PHY_VERSION_4_2_0)
  2153. rc = dp_catalog_get_v420(dev, catalog, &catalog_priv->io);
  2154. else if (parser->hw_cfg.phy_version == DP_PHY_VERSION_2_0_0)
  2155. rc = dp_catalog_get_v200(dev, catalog, &catalog_priv->io);
  2156. return rc;
  2157. }
  2158. void dp_catalog_put(struct dp_catalog *dp_catalog)
  2159. {
  2160. struct dp_catalog_private *catalog;
  2161. if (!dp_catalog)
  2162. return;
  2163. catalog = container_of(dp_catalog, struct dp_catalog_private,
  2164. dp_catalog);
  2165. if (dp_catalog->priv.data && dp_catalog->priv.put)
  2166. dp_catalog->priv.put(dp_catalog);
  2167. catalog->parser->clear_io_buf(catalog->parser);
  2168. devm_kfree(catalog->dev, catalog);
  2169. }
  2170. struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser)
  2171. {
  2172. int rc = 0;
  2173. struct dp_catalog *dp_catalog;
  2174. struct dp_catalog_private *catalog;
  2175. struct dp_catalog_aux aux = {
  2176. .read_data = dp_catalog_aux_read_data,
  2177. .write_data = dp_catalog_aux_write_data,
  2178. .write_trans = dp_catalog_aux_write_trans,
  2179. .clear_trans = dp_catalog_aux_clear_trans,
  2180. .reset = dp_catalog_aux_reset,
  2181. .update_aux_cfg = dp_catalog_aux_update_cfg,
  2182. .enable = dp_catalog_aux_enable,
  2183. .setup = dp_catalog_aux_setup,
  2184. .get_irq = dp_catalog_aux_get_irq,
  2185. .clear_hw_interrupts = dp_catalog_aux_clear_hw_interrupts,
  2186. };
  2187. struct dp_catalog_ctrl ctrl = {
  2188. .state_ctrl = dp_catalog_ctrl_state_ctrl,
  2189. .config_ctrl = dp_catalog_ctrl_config_ctrl,
  2190. .lane_mapping = dp_catalog_ctrl_lane_mapping,
  2191. .lane_pnswap = dp_catalog_ctrl_lane_pnswap,
  2192. .mainlink_ctrl = dp_catalog_ctrl_mainlink_ctrl,
  2193. .set_pattern = dp_catalog_ctrl_set_pattern,
  2194. .reset = dp_catalog_ctrl_reset,
  2195. .usb_reset = dp_catalog_ctrl_usb_reset,
  2196. .mainlink_ready = dp_catalog_ctrl_mainlink_ready,
  2197. .enable_irq = dp_catalog_ctrl_enable_irq,
  2198. .phy_reset = dp_catalog_ctrl_phy_reset,
  2199. .phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg,
  2200. .update_vx_px = dp_catalog_ctrl_update_vx_px,
  2201. .get_interrupt = dp_catalog_ctrl_get_interrupt,
  2202. .read_hdcp_status = dp_catalog_ctrl_read_hdcp_status,
  2203. .send_phy_pattern = dp_catalog_ctrl_send_phy_pattern,
  2204. .read_phy_pattern = dp_catalog_ctrl_read_phy_pattern,
  2205. .mst_config = dp_catalog_ctrl_mst_config,
  2206. .trigger_act = dp_catalog_ctrl_trigger_act,
  2207. .read_act_complete_sts = dp_catalog_ctrl_read_act_complete_sts,
  2208. .channel_alloc = dp_catalog_ctrl_channel_alloc,
  2209. .update_rg = dp_catalog_ctrl_update_rg,
  2210. .channel_dealloc = dp_catalog_ctrl_channel_dealloc,
  2211. .fec_config = dp_catalog_ctrl_fec_config,
  2212. .mainlink_levels = dp_catalog_ctrl_mainlink_levels,
  2213. .late_phy_init = dp_catalog_ctrl_late_phy_init,
  2214. };
  2215. struct dp_catalog_hpd hpd = {
  2216. .config_hpd = dp_catalog_hpd_config_hpd,
  2217. .get_interrupt = dp_catalog_hpd_get_interrupt,
  2218. };
  2219. struct dp_catalog_audio audio = {
  2220. .init = dp_catalog_audio_init,
  2221. .config_acr = dp_catalog_audio_config_acr,
  2222. .enable = dp_catalog_audio_enable,
  2223. .config_sdp = dp_catalog_audio_config_sdp,
  2224. .set_header = dp_catalog_audio_set_header,
  2225. .get_header = dp_catalog_audio_get_header,
  2226. };
  2227. struct dp_catalog_panel panel = {
  2228. .timing_cfg = dp_catalog_panel_timing_cfg,
  2229. .config_hdr = dp_catalog_panel_config_hdr,
  2230. .tpg_config = dp_catalog_panel_tpg_cfg,
  2231. .config_spd = dp_catalog_panel_config_spd,
  2232. .config_misc = dp_catalog_panel_config_misc,
  2233. .config_msa = dp_catalog_panel_config_msa,
  2234. .update_transfer_unit = dp_catalog_panel_update_transfer_unit,
  2235. .config_ctrl = dp_catalog_panel_config_ctrl,
  2236. .config_dto = dp_catalog_panel_config_dto,
  2237. .dsc_cfg = dp_catalog_panel_dsc_cfg,
  2238. .pps_flush = dp_catalog_panel_pps_flush,
  2239. .dhdr_flush = dp_catalog_panel_dhdr_flush,
  2240. .dhdr_busy = dp_catalog_panel_dhdr_busy,
  2241. };
  2242. if (!dev || !parser) {
  2243. pr_err("invalid input\n");
  2244. rc = -EINVAL;
  2245. goto error;
  2246. }
  2247. catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL);
  2248. if (!catalog) {
  2249. rc = -ENOMEM;
  2250. goto error;
  2251. }
  2252. catalog->dev = dev;
  2253. catalog->parser = parser;
  2254. dp_catalog_get_io(catalog);
  2255. strlcpy(catalog->exe_mode, "hw", sizeof(catalog->exe_mode));
  2256. dp_catalog = &catalog->dp_catalog;
  2257. dp_catalog->aux = aux;
  2258. dp_catalog->ctrl = ctrl;
  2259. dp_catalog->hpd = hpd;
  2260. dp_catalog->audio = audio;
  2261. dp_catalog->panel = panel;
  2262. rc = dp_catalog_init(dev, dp_catalog, parser);
  2263. if (rc) {
  2264. dp_catalog_put(dp_catalog);
  2265. goto error;
  2266. }
  2267. dp_catalog->set_exe_mode = dp_catalog_set_exe_mode;
  2268. dp_catalog->get_reg_dump = dp_catalog_reg_dump;
  2269. return dp_catalog;
  2270. error:
  2271. return ERR_PTR(rc);
  2272. }