sde_crtc.c 181 KB

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  1. /*
  2. * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/sort.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/ktime.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_crtc.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_flip_work.h>
  27. #include "sde_kms.h"
  28. #include "sde_hw_lm.h"
  29. #include "sde_hw_ctl.h"
  30. #include "sde_crtc.h"
  31. #include "sde_plane.h"
  32. #include "sde_hw_util.h"
  33. #include "sde_hw_catalog.h"
  34. #include "sde_color_processing.h"
  35. #include "sde_encoder.h"
  36. #include "sde_connector.h"
  37. #include "sde_vbif.h"
  38. #include "sde_power_handle.h"
  39. #include "sde_core_perf.h"
  40. #include "sde_trace.h"
  41. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  42. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  43. struct sde_crtc_custom_events {
  44. u32 event;
  45. int (*func)(struct drm_crtc *crtc, bool en,
  46. struct sde_irq_callback *irq);
  47. };
  48. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  49. bool en, struct sde_irq_callback *ad_irq);
  50. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  51. bool en, struct sde_irq_callback *idle_irq);
  52. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  53. struct sde_irq_callback *noirq);
  54. static struct sde_crtc_custom_events custom_events[] = {
  55. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  56. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  57. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  58. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  59. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  60. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  61. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  62. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  63. };
  64. /* default input fence timeout, in ms */
  65. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  66. /*
  67. * The default input fence timeout is 2 seconds while max allowed
  68. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  69. * tolerance limit.
  70. */
  71. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  72. /* layer mixer index on sde_crtc */
  73. #define LEFT_MIXER 0
  74. #define RIGHT_MIXER 1
  75. #define MISR_BUFF_SIZE 256
  76. /*
  77. * Time period for fps calculation in micro seconds.
  78. * Default value is set to 1 sec.
  79. */
  80. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  81. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  82. #define MAX_FRAME_COUNT 1000
  83. #define MILI_TO_MICRO 1000
  84. #define SKIP_STAGING_PIPE_ZPOS 255
  85. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  86. {
  87. struct msm_drm_private *priv;
  88. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  89. SDE_ERROR("invalid crtc\n");
  90. return NULL;
  91. }
  92. priv = crtc->dev->dev_private;
  93. if (!priv || !priv->kms) {
  94. SDE_ERROR("invalid kms\n");
  95. return NULL;
  96. }
  97. return to_sde_kms(priv->kms);
  98. }
  99. /**
  100. * sde_crtc_calc_fps() - Calculates fps value.
  101. * @sde_crtc : CRTC structure
  102. *
  103. * This function is called at frame done. It counts the number
  104. * of frames done for every 1 sec. Stores the value in measured_fps.
  105. * measured_fps value is 10 times the calculated fps value.
  106. * For example, measured_fps= 594 for calculated fps of 59.4
  107. */
  108. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  109. {
  110. ktime_t current_time_us;
  111. u64 fps, diff_us;
  112. current_time_us = ktime_get();
  113. diff_us = (u64)ktime_us_delta(current_time_us,
  114. sde_crtc->fps_info.last_sampled_time_us);
  115. sde_crtc->fps_info.frame_count++;
  116. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  117. /* Multiplying with 10 to get fps in floating point */
  118. fps = ((u64)sde_crtc->fps_info.frame_count)
  119. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  120. do_div(fps, diff_us);
  121. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  122. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  123. sde_crtc->base.base.id, (unsigned int)fps/10,
  124. (unsigned int)fps%10);
  125. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  126. sde_crtc->fps_info.frame_count = 0;
  127. }
  128. if (!sde_crtc->fps_info.time_buf)
  129. return;
  130. /**
  131. * Array indexing is based on sliding window algorithm.
  132. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  133. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  134. * counter loops around and comes back to the first index to store
  135. * the next ktime.
  136. */
  137. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  138. ktime_get();
  139. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  140. }
  141. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  142. {
  143. if (!sde_crtc)
  144. return;
  145. }
  146. #ifdef CONFIG_DEBUG_FS
  147. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  148. {
  149. struct sde_crtc *sde_crtc;
  150. u64 fps_int, fps_float;
  151. ktime_t current_time_us;
  152. u64 fps, diff_us;
  153. if (!s || !s->private) {
  154. SDE_ERROR("invalid input param(s)\n");
  155. return -EAGAIN;
  156. }
  157. sde_crtc = s->private;
  158. current_time_us = ktime_get();
  159. diff_us = (u64)ktime_us_delta(current_time_us,
  160. sde_crtc->fps_info.last_sampled_time_us);
  161. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  162. /* Multiplying with 10 to get fps in floating point */
  163. fps = ((u64)sde_crtc->fps_info.frame_count)
  164. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  165. do_div(fps, diff_us);
  166. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  167. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  168. sde_crtc->fps_info.frame_count = 0;
  169. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  170. sde_crtc->base.base.id, (unsigned int)fps/10,
  171. (unsigned int)fps%10);
  172. }
  173. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  174. fps_float = do_div(fps_int, 10);
  175. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  176. return 0;
  177. }
  178. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  179. {
  180. return single_open(file, _sde_debugfs_fps_status_show,
  181. inode->i_private);
  182. }
  183. #endif
  184. static ssize_t fps_periodicity_ms_store(struct device *device,
  185. struct device_attribute *attr, const char *buf, size_t count)
  186. {
  187. struct drm_crtc *crtc;
  188. struct sde_crtc *sde_crtc;
  189. int res;
  190. /* Base of the input */
  191. int cnt = 10;
  192. if (!device || !buf) {
  193. SDE_ERROR("invalid input param(s)\n");
  194. return -EAGAIN;
  195. }
  196. crtc = dev_get_drvdata(device);
  197. if (!crtc)
  198. return -EINVAL;
  199. sde_crtc = to_sde_crtc(crtc);
  200. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  201. if (res < 0)
  202. return res;
  203. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  204. sde_crtc->fps_info.fps_periodic_duration =
  205. DEFAULT_FPS_PERIOD_1_SEC;
  206. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  207. MAX_FPS_PERIOD_5_SECONDS)
  208. sde_crtc->fps_info.fps_periodic_duration =
  209. MAX_FPS_PERIOD_5_SECONDS;
  210. else
  211. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  212. return count;
  213. }
  214. static ssize_t fps_periodicity_ms_show(struct device *device,
  215. struct device_attribute *attr, char *buf)
  216. {
  217. struct drm_crtc *crtc;
  218. struct sde_crtc *sde_crtc;
  219. if (!device || !buf) {
  220. SDE_ERROR("invalid input param(s)\n");
  221. return -EAGAIN;
  222. }
  223. crtc = dev_get_drvdata(device);
  224. if (!crtc)
  225. return -EINVAL;
  226. sde_crtc = to_sde_crtc(crtc);
  227. return scnprintf(buf, PAGE_SIZE, "%d\n",
  228. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  229. }
  230. static ssize_t measured_fps_show(struct device *device,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. struct drm_crtc *crtc;
  234. struct sde_crtc *sde_crtc;
  235. uint64_t fps_int, fps_decimal;
  236. u64 fps = 0, frame_count = 0;
  237. ktime_t current_time;
  238. int i = 0, current_time_index;
  239. u64 diff_us;
  240. if (!device || !buf) {
  241. SDE_ERROR("invalid input param(s)\n");
  242. return -EAGAIN;
  243. }
  244. crtc = dev_get_drvdata(device);
  245. if (!crtc) {
  246. scnprintf(buf, PAGE_SIZE, "fps information not available");
  247. return -EINVAL;
  248. }
  249. sde_crtc = to_sde_crtc(crtc);
  250. if (!sde_crtc->fps_info.time_buf) {
  251. scnprintf(buf, PAGE_SIZE,
  252. "timebuf null - fps information not available");
  253. return -EINVAL;
  254. }
  255. /**
  256. * Whenever the time_index counter comes to zero upon decrementing,
  257. * it is set to the last index since it is the next index that we
  258. * should check for calculating the buftime.
  259. */
  260. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  261. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  262. current_time = ktime_get();
  263. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  264. u64 ptime = (u64)ktime_to_us(current_time);
  265. u64 buftime = (u64)ktime_to_us(
  266. sde_crtc->fps_info.time_buf[current_time_index]);
  267. diff_us = (u64)ktime_us_delta(current_time,
  268. sde_crtc->fps_info.time_buf[current_time_index]);
  269. if (ptime > buftime && diff_us >= (u64)
  270. sde_crtc->fps_info.fps_periodic_duration) {
  271. /* Multiplying with 10 to get fps in floating point */
  272. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  273. do_div(fps, diff_us);
  274. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  275. SDE_DEBUG("measured fps: %d\n",
  276. sde_crtc->fps_info.measured_fps);
  277. break;
  278. }
  279. current_time_index = (current_time_index == 0) ?
  280. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  281. SDE_DEBUG("current time index: %d\n", current_time_index);
  282. frame_count++;
  283. }
  284. if (i == MAX_FRAME_COUNT) {
  285. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  286. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  287. diff_us = (u64)ktime_us_delta(current_time,
  288. sde_crtc->fps_info.time_buf[current_time_index]);
  289. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  290. /* Multiplying with 10 to get fps in floating point */
  291. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  292. do_div(fps, diff_us);
  293. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  294. }
  295. }
  296. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  297. fps_decimal = do_div(fps_int, 10);
  298. return scnprintf(buf, PAGE_SIZE,
  299. "fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  300. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  301. }
  302. static ssize_t vsync_event_show(struct device *device,
  303. struct device_attribute *attr, char *buf)
  304. {
  305. struct drm_crtc *crtc;
  306. struct sde_crtc *sde_crtc;
  307. if (!device || !buf) {
  308. SDE_ERROR("invalid input param(s)\n");
  309. return -EAGAIN;
  310. }
  311. crtc = dev_get_drvdata(device);
  312. sde_crtc = to_sde_crtc(crtc);
  313. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\n",
  314. ktime_to_ns(sde_crtc->vblank_last_cb_time));
  315. }
  316. static DEVICE_ATTR_RO(vsync_event);
  317. static DEVICE_ATTR_RO(measured_fps);
  318. static DEVICE_ATTR_RW(fps_periodicity_ms);
  319. static struct attribute *sde_crtc_dev_attrs[] = {
  320. &dev_attr_vsync_event.attr,
  321. &dev_attr_measured_fps.attr,
  322. &dev_attr_fps_periodicity_ms.attr,
  323. NULL
  324. };
  325. static const struct attribute_group sde_crtc_attr_group = {
  326. .attrs = sde_crtc_dev_attrs,
  327. };
  328. static const struct attribute_group *sde_crtc_attr_groups[] = {
  329. &sde_crtc_attr_group,
  330. NULL,
  331. };
  332. static void sde_crtc_destroy(struct drm_crtc *crtc)
  333. {
  334. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  335. SDE_DEBUG("\n");
  336. if (!crtc)
  337. return;
  338. if (sde_crtc->vsync_event_sf)
  339. sysfs_put(sde_crtc->vsync_event_sf);
  340. if (sde_crtc->sysfs_dev)
  341. device_unregister(sde_crtc->sysfs_dev);
  342. if (sde_crtc->blob_info)
  343. drm_property_blob_put(sde_crtc->blob_info);
  344. msm_property_destroy(&sde_crtc->property_info);
  345. sde_cp_crtc_destroy_properties(crtc);
  346. sde_fence_deinit(sde_crtc->output_fence);
  347. _sde_crtc_deinit_events(sde_crtc);
  348. drm_crtc_cleanup(crtc);
  349. mutex_destroy(&sde_crtc->crtc_lock);
  350. kfree(sde_crtc);
  351. }
  352. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  353. const struct drm_display_mode *mode,
  354. struct drm_display_mode *adjusted_mode)
  355. {
  356. SDE_DEBUG("\n");
  357. sde_cp_mode_switch_prop_dirty(crtc);
  358. if ((msm_is_mode_seamless(adjusted_mode) ||
  359. (msm_is_mode_seamless_vrr(adjusted_mode) ||
  360. msm_is_mode_seamless_dyn_clk(adjusted_mode))) &&
  361. (!crtc->enabled)) {
  362. SDE_ERROR("crtc state prevents seamless transition\n");
  363. return false;
  364. }
  365. return true;
  366. }
  367. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  368. struct sde_plane_state *pstate, struct sde_format *format)
  369. {
  370. uint32_t blend_op, fg_alpha, bg_alpha;
  371. uint32_t blend_type;
  372. struct sde_hw_mixer *lm = mixer->hw_lm;
  373. /* default to opaque blending */
  374. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  375. bg_alpha = 0xFF - fg_alpha;
  376. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  377. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  378. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  379. switch (blend_type) {
  380. case SDE_DRM_BLEND_OP_OPAQUE:
  381. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  382. SDE_BLEND_BG_ALPHA_BG_CONST;
  383. break;
  384. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  385. if (format->alpha_enable) {
  386. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  387. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  388. if (fg_alpha != 0xff) {
  389. bg_alpha = fg_alpha;
  390. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  391. SDE_BLEND_BG_INV_MOD_ALPHA;
  392. } else {
  393. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  394. }
  395. }
  396. break;
  397. case SDE_DRM_BLEND_OP_COVERAGE:
  398. if (format->alpha_enable) {
  399. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  400. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  401. if (fg_alpha != 0xff) {
  402. bg_alpha = fg_alpha;
  403. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  404. SDE_BLEND_BG_MOD_ALPHA |
  405. SDE_BLEND_BG_INV_MOD_ALPHA;
  406. } else {
  407. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  408. }
  409. }
  410. break;
  411. default:
  412. /* do nothing */
  413. break;
  414. }
  415. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
  416. bg_alpha, blend_op);
  417. SDE_DEBUG(
  418. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  419. (char *) &format->base.pixel_format,
  420. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  421. }
  422. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  423. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  424. struct sde_hw_dim_layer *dim_layer)
  425. {
  426. struct sde_crtc_state *cstate;
  427. struct sde_hw_mixer *lm;
  428. struct sde_hw_dim_layer split_dim_layer;
  429. int i;
  430. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  431. SDE_DEBUG("empty dim_layer\n");
  432. return;
  433. }
  434. cstate = to_sde_crtc_state(crtc->state);
  435. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  436. dim_layer->flags, dim_layer->stage);
  437. split_dim_layer.stage = dim_layer->stage;
  438. split_dim_layer.color_fill = dim_layer->color_fill;
  439. /*
  440. * traverse through the layer mixers attached to crtc and find the
  441. * intersecting dim layer rect in each LM and program accordingly.
  442. */
  443. for (i = 0; i < sde_crtc->num_mixers; i++) {
  444. split_dim_layer.flags = dim_layer->flags;
  445. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  446. &split_dim_layer.rect);
  447. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  448. /*
  449. * no extra programming required for non-intersecting
  450. * layer mixers with INCLUSIVE dim layer
  451. */
  452. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  453. continue;
  454. /*
  455. * program the other non-intersecting layer mixers with
  456. * INCLUSIVE dim layer of full size for uniformity
  457. * with EXCLUSIVE dim layer config.
  458. */
  459. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  460. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  461. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  462. sizeof(split_dim_layer.rect));
  463. } else {
  464. split_dim_layer.rect.x =
  465. split_dim_layer.rect.x -
  466. cstate->lm_roi[i].x;
  467. split_dim_layer.rect.y =
  468. split_dim_layer.rect.y -
  469. cstate->lm_roi[i].y;
  470. }
  471. SDE_EVT32(DRMID(crtc), dim_layer->stage,
  472. cstate->lm_roi[i].x,
  473. cstate->lm_roi[i].y,
  474. cstate->lm_roi[i].w,
  475. cstate->lm_roi[i].h,
  476. dim_layer->rect.x,
  477. dim_layer->rect.y,
  478. dim_layer->rect.w,
  479. dim_layer->rect.h,
  480. split_dim_layer.rect.x,
  481. split_dim_layer.rect.y,
  482. split_dim_layer.rect.w,
  483. split_dim_layer.rect.h);
  484. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  485. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  486. split_dim_layer.rect.w, split_dim_layer.rect.h);
  487. lm = mixer[i].hw_lm;
  488. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  489. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  490. }
  491. }
  492. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  493. const struct sde_rect **crtc_roi)
  494. {
  495. struct sde_crtc_state *crtc_state;
  496. if (!state || !crtc_roi)
  497. return;
  498. crtc_state = to_sde_crtc_state(state);
  499. *crtc_roi = &crtc_state->crtc_roi;
  500. }
  501. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  502. {
  503. struct sde_crtc_state *cstate;
  504. struct sde_crtc *sde_crtc;
  505. if (!state || !state->crtc)
  506. return false;
  507. sde_crtc = to_sde_crtc(state->crtc);
  508. cstate = to_sde_crtc_state(state);
  509. return msm_property_is_dirty(&sde_crtc->property_info,
  510. &cstate->property_state, CRTC_PROP_ROI_V1);
  511. }
  512. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  513. void __user *usr_ptr)
  514. {
  515. struct drm_crtc *crtc;
  516. struct sde_crtc_state *cstate;
  517. struct sde_drm_roi_v1 roi_v1;
  518. int i;
  519. if (!state) {
  520. SDE_ERROR("invalid args\n");
  521. return -EINVAL;
  522. }
  523. cstate = to_sde_crtc_state(state);
  524. crtc = cstate->base.crtc;
  525. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  526. if (!usr_ptr) {
  527. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  528. return 0;
  529. }
  530. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  531. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  532. return -EINVAL;
  533. }
  534. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  535. if (roi_v1.num_rects == 0) {
  536. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  537. return 0;
  538. }
  539. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  540. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  541. roi_v1.num_rects);
  542. return -EINVAL;
  543. }
  544. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  545. for (i = 0; i < roi_v1.num_rects; ++i) {
  546. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  547. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  548. DRMID(crtc), i,
  549. cstate->user_roi_list.roi[i].x1,
  550. cstate->user_roi_list.roi[i].y1,
  551. cstate->user_roi_list.roi[i].x2,
  552. cstate->user_roi_list.roi[i].y2);
  553. SDE_EVT32_VERBOSE(DRMID(crtc),
  554. cstate->user_roi_list.roi[i].x1,
  555. cstate->user_roi_list.roi[i].y1,
  556. cstate->user_roi_list.roi[i].x2,
  557. cstate->user_roi_list.roi[i].y2);
  558. }
  559. return 0;
  560. }
  561. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  562. struct drm_crtc_state *state)
  563. {
  564. struct drm_connector *conn;
  565. struct drm_connector_state *conn_state;
  566. struct sde_crtc *sde_crtc;
  567. struct sde_crtc_state *crtc_state;
  568. struct sde_rect *crtc_roi;
  569. struct msm_mode_info mode_info;
  570. int i = 0;
  571. int rc;
  572. bool is_crtc_roi_dirty;
  573. bool is_any_conn_roi_dirty;
  574. if (!crtc || !state)
  575. return -EINVAL;
  576. sde_crtc = to_sde_crtc(crtc);
  577. crtc_state = to_sde_crtc_state(state);
  578. crtc_roi = &crtc_state->crtc_roi;
  579. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  580. is_any_conn_roi_dirty = false;
  581. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  582. struct sde_connector *sde_conn;
  583. struct sde_connector_state *sde_conn_state;
  584. struct sde_rect conn_roi;
  585. if (!conn_state || conn_state->crtc != crtc)
  586. continue;
  587. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  588. if (rc) {
  589. SDE_ERROR("failed to get mode info\n");
  590. return -EINVAL;
  591. }
  592. sde_conn = to_sde_connector(conn_state->connector);
  593. sde_conn_state = to_sde_connector_state(conn_state);
  594. is_any_conn_roi_dirty = is_any_conn_roi_dirty ||
  595. msm_property_is_dirty(
  596. &sde_conn->property_info,
  597. &sde_conn_state->property_state,
  598. CONNECTOR_PROP_ROI_V1);
  599. if (!mode_info.roi_caps.enabled)
  600. continue;
  601. /*
  602. * current driver only supports same connector and crtc size,
  603. * but if support for different sizes is added, driver needs
  604. * to check the connector roi here to make sure is full screen
  605. * for dsc 3d-mux topology that doesn't support partial update.
  606. */
  607. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  608. sizeof(crtc_state->user_roi_list))) {
  609. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  610. sde_crtc->name);
  611. return -EINVAL;
  612. }
  613. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  614. SDE_DEBUG("conn_roi x:%u, y:%u, w:%u, h:%u\n",
  615. conn_roi.x, conn_roi.y,
  616. conn_roi.w, conn_roi.h);
  617. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  618. conn_roi.x, conn_roi.y,
  619. conn_roi.w, conn_roi.h);
  620. }
  621. /*
  622. * Check against CRTC ROI and Connector ROI not being updated together.
  623. * This restriction should be relaxed when Connector ROI scaling is
  624. * supported.
  625. */
  626. if (is_any_conn_roi_dirty != is_crtc_roi_dirty) {
  627. SDE_ERROR("connector/crtc rois not updated together\n");
  628. return -EINVAL;
  629. }
  630. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  631. /* clear the ROI to null if it matches full screen anyways */
  632. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  633. crtc_roi->w == state->adjusted_mode.hdisplay &&
  634. crtc_roi->h == state->adjusted_mode.vdisplay)
  635. memset(crtc_roi, 0, sizeof(*crtc_roi));
  636. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  637. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  638. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w,
  639. crtc_roi->h);
  640. return 0;
  641. }
  642. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  643. struct drm_crtc_state *state)
  644. {
  645. struct sde_crtc *sde_crtc;
  646. struct sde_crtc_state *crtc_state;
  647. struct drm_connector *conn;
  648. struct drm_connector_state *conn_state;
  649. int i;
  650. if (!crtc || !state)
  651. return -EINVAL;
  652. sde_crtc = to_sde_crtc(crtc);
  653. crtc_state = to_sde_crtc_state(state);
  654. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  655. return 0;
  656. /* partial update active, check if autorefresh is also requested */
  657. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  658. uint64_t autorefresh;
  659. if (!conn_state || conn_state->crtc != crtc)
  660. continue;
  661. autorefresh = sde_connector_get_property(conn_state,
  662. CONNECTOR_PROP_AUTOREFRESH);
  663. if (autorefresh) {
  664. SDE_ERROR(
  665. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  666. sde_crtc->name, autorefresh);
  667. return -EINVAL;
  668. }
  669. }
  670. return 0;
  671. }
  672. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  673. struct drm_crtc_state *state, int lm_idx)
  674. {
  675. struct sde_kms *sde_kms;
  676. struct sde_crtc *sde_crtc;
  677. struct sde_crtc_state *crtc_state;
  678. const struct sde_rect *crtc_roi;
  679. const struct sde_rect *lm_bounds;
  680. struct sde_rect *lm_roi;
  681. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  682. return -EINVAL;
  683. sde_kms = _sde_crtc_get_kms(crtc);
  684. if (!sde_kms || !sde_kms->catalog) {
  685. SDE_ERROR("invalid parameters\n");
  686. return -EINVAL;
  687. }
  688. sde_crtc = to_sde_crtc(crtc);
  689. crtc_state = to_sde_crtc_state(state);
  690. crtc_roi = &crtc_state->crtc_roi;
  691. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  692. lm_roi = &crtc_state->lm_roi[lm_idx];
  693. if (sde_kms_rect_is_null(crtc_roi))
  694. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  695. else
  696. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  697. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  698. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  699. /*
  700. * partial update is not supported with 3dmux dsc or dest scaler.
  701. * hence, crtc roi must match the mixer dimensions.
  702. */
  703. if (crtc_state->num_ds_enabled ||
  704. sde_rm_topology_is_group(&sde_kms->rm, state,
  705. SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC)) {
  706. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  707. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  708. return -EINVAL;
  709. }
  710. }
  711. /* if any dimension is zero, clear all dimensions for clarity */
  712. if (sde_kms_rect_is_null(lm_roi))
  713. memset(lm_roi, 0, sizeof(*lm_roi));
  714. return 0;
  715. }
  716. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  717. struct drm_crtc_state *state)
  718. {
  719. struct sde_crtc *sde_crtc;
  720. struct sde_crtc_state *crtc_state;
  721. u32 disp_bitmask = 0;
  722. int i;
  723. if (!crtc || !state) {
  724. pr_err("Invalid crtc or state\n");
  725. return 0;
  726. }
  727. sde_crtc = to_sde_crtc(crtc);
  728. crtc_state = to_sde_crtc_state(state);
  729. /* pingpong split: one ROI, one LM, two physical displays */
  730. if (crtc_state->is_ppsplit) {
  731. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  732. struct sde_rect *roi = &crtc_state->lm_roi[0];
  733. if (sde_kms_rect_is_null(roi))
  734. disp_bitmask = 0;
  735. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  736. disp_bitmask = BIT(0); /* left only */
  737. else if (roi->x >= lm_split_width)
  738. disp_bitmask = BIT(1); /* right only */
  739. else
  740. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  741. } else if (sde_crtc->mixers_swapped) {
  742. disp_bitmask = BIT(0);
  743. } else {
  744. for (i = 0; i < sde_crtc->num_mixers; i++) {
  745. if (!sde_kms_rect_is_null(
  746. &crtc_state->lm_roi[i]))
  747. disp_bitmask |= BIT(i);
  748. }
  749. }
  750. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  751. return disp_bitmask;
  752. }
  753. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  754. struct drm_crtc_state *state)
  755. {
  756. struct sde_crtc *sde_crtc;
  757. struct sde_crtc_state *crtc_state;
  758. const struct sde_rect *roi[MAX_MIXERS_PER_CRTC];
  759. if (!crtc || !state)
  760. return -EINVAL;
  761. sde_crtc = to_sde_crtc(crtc);
  762. crtc_state = to_sde_crtc_state(state);
  763. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  764. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  765. sde_crtc->name, sde_crtc->num_mixers);
  766. return -EINVAL;
  767. }
  768. /*
  769. * If using pingpong split: one ROI, one LM, two physical displays
  770. * then the ROI must be centered on the panel split boundary and
  771. * be of equal width across the split.
  772. */
  773. if (crtc_state->is_ppsplit) {
  774. u16 panel_split_width;
  775. u32 display_mask;
  776. roi[0] = &crtc_state->lm_roi[0];
  777. if (sde_kms_rect_is_null(roi[0]))
  778. return 0;
  779. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  780. if (display_mask != (BIT(0) | BIT(1)))
  781. return 0;
  782. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  783. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  784. SDE_ERROR("%s: roi x %d w %d split %d\n",
  785. sde_crtc->name, roi[0]->x, roi[0]->w,
  786. panel_split_width);
  787. return -EINVAL;
  788. }
  789. return 0;
  790. }
  791. /*
  792. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  793. * LMs and be of equal width.
  794. */
  795. if (sde_crtc->num_mixers < CRTC_DUAL_MIXERS_ONLY)
  796. return 0;
  797. roi[0] = &crtc_state->lm_roi[0];
  798. roi[1] = &crtc_state->lm_roi[1];
  799. /* if one of the roi is null it's a left/right-only update */
  800. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  801. return 0;
  802. /* check lm rois are equal width & first roi ends at 2nd roi */
  803. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  804. SDE_ERROR(
  805. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  806. sde_crtc->name, roi[0]->x, roi[0]->w,
  807. roi[1]->x, roi[1]->w);
  808. return -EINVAL;
  809. }
  810. return 0;
  811. }
  812. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  813. struct drm_crtc_state *state)
  814. {
  815. struct sde_crtc *sde_crtc;
  816. struct sde_crtc_state *crtc_state;
  817. const struct sde_rect *crtc_roi;
  818. const struct drm_plane_state *pstate;
  819. struct drm_plane *plane;
  820. if (!crtc || !state)
  821. return -EINVAL;
  822. /*
  823. * Reject commit if a Plane CRTC destination coordinates fall outside
  824. * the partial CRTC ROI. LM output is determined via connector ROIs,
  825. * if they are specified, not Plane CRTC ROIs.
  826. */
  827. sde_crtc = to_sde_crtc(crtc);
  828. crtc_state = to_sde_crtc_state(state);
  829. crtc_roi = &crtc_state->crtc_roi;
  830. if (sde_kms_rect_is_null(crtc_roi))
  831. return 0;
  832. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  833. struct sde_rect plane_roi, intersection;
  834. if (IS_ERR_OR_NULL(pstate)) {
  835. int rc = PTR_ERR(pstate);
  836. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  837. sde_crtc->name, plane->base.id, rc);
  838. return rc;
  839. }
  840. plane_roi.x = pstate->crtc_x;
  841. plane_roi.y = pstate->crtc_y;
  842. plane_roi.w = pstate->crtc_w;
  843. plane_roi.h = pstate->crtc_h;
  844. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  845. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  846. SDE_ERROR(
  847. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  848. sde_crtc->name, plane->base.id,
  849. plane_roi.x, plane_roi.y,
  850. plane_roi.w, plane_roi.h,
  851. crtc_roi->x, crtc_roi->y,
  852. crtc_roi->w, crtc_roi->h);
  853. return -E2BIG;
  854. }
  855. }
  856. return 0;
  857. }
  858. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  859. struct drm_crtc_state *state)
  860. {
  861. struct sde_crtc *sde_crtc;
  862. struct sde_crtc_state *sde_crtc_state;
  863. struct msm_mode_info mode_info;
  864. int rc, lm_idx, i;
  865. if (!crtc || !state)
  866. return -EINVAL;
  867. memset(&mode_info, 0, sizeof(mode_info));
  868. sde_crtc = to_sde_crtc(crtc);
  869. sde_crtc_state = to_sde_crtc_state(state);
  870. /*
  871. * check connector array cached at modeset time since incoming atomic
  872. * state may not include any connectors if they aren't modified
  873. */
  874. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  875. struct drm_connector *conn = sde_crtc_state->connectors[i];
  876. if (!conn || !conn->state)
  877. continue;
  878. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  879. if (rc) {
  880. SDE_ERROR("failed to get mode info\n");
  881. return -EINVAL;
  882. }
  883. if (!mode_info.roi_caps.enabled)
  884. continue;
  885. if (sde_crtc_state->user_roi_list.num_rects >
  886. mode_info.roi_caps.num_roi) {
  887. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  888. sde_crtc_state->user_roi_list.num_rects,
  889. mode_info.roi_caps.num_roi);
  890. return -E2BIG;
  891. }
  892. rc = _sde_crtc_set_crtc_roi(crtc, state);
  893. if (rc)
  894. return rc;
  895. rc = _sde_crtc_check_autorefresh(crtc, state);
  896. if (rc)
  897. return rc;
  898. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  899. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  900. if (rc)
  901. return rc;
  902. }
  903. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  904. if (rc)
  905. return rc;
  906. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  907. if (rc)
  908. return rc;
  909. }
  910. return 0;
  911. }
  912. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  913. {
  914. struct sde_crtc *sde_crtc;
  915. struct sde_crtc_state *crtc_state;
  916. const struct sde_rect *lm_roi;
  917. struct sde_hw_mixer *hw_lm;
  918. bool right_mixer = false;
  919. int lm_idx;
  920. if (!crtc)
  921. return;
  922. sde_crtc = to_sde_crtc(crtc);
  923. crtc_state = to_sde_crtc_state(crtc->state);
  924. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  925. struct sde_hw_mixer_cfg cfg;
  926. lm_roi = &crtc_state->lm_roi[lm_idx];
  927. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  928. if (!sde_crtc->mixers_swapped)
  929. right_mixer = lm_idx % MAX_MIXERS_PER_LAYOUT;
  930. SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx,
  931. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h,
  932. right_mixer);
  933. hw_lm->cfg.out_width = lm_roi->w;
  934. hw_lm->cfg.out_height = lm_roi->h;
  935. hw_lm->cfg.right_mixer = right_mixer;
  936. cfg.out_width = lm_roi->w;
  937. cfg.out_height = lm_roi->h;
  938. cfg.right_mixer = right_mixer;
  939. cfg.flags = 0;
  940. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  941. }
  942. }
  943. struct plane_state {
  944. struct sde_plane_state *sde_pstate;
  945. const struct drm_plane_state *drm_pstate;
  946. int stage;
  947. u32 pipe_id;
  948. };
  949. static int pstate_cmp(const void *a, const void *b)
  950. {
  951. struct plane_state *pa = (struct plane_state *)a;
  952. struct plane_state *pb = (struct plane_state *)b;
  953. int rc = 0;
  954. int pa_zpos, pb_zpos;
  955. enum sde_layout pa_layout, pb_layout;
  956. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  957. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  958. pa_layout = pa->sde_pstate->layout;
  959. pb_layout = pb->sde_pstate->layout;
  960. if (pa_zpos != pb_zpos)
  961. rc = pa_zpos - pb_zpos;
  962. else if (pa_layout != pb_layout)
  963. rc = pa_layout - pb_layout;
  964. else
  965. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  966. return rc;
  967. }
  968. /*
  969. * validate and set source split:
  970. * use pstates sorted by stage to check planes on same stage
  971. * we assume that all pipes are in source split so its valid to compare
  972. * without taking into account left/right mixer placement
  973. */
  974. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  975. struct plane_state *pstates, int cnt)
  976. {
  977. struct plane_state *prv_pstate, *cur_pstate;
  978. enum sde_layout prev_layout, cur_layout;
  979. struct sde_rect left_rect, right_rect;
  980. struct sde_kms *sde_kms;
  981. int32_t left_pid, right_pid;
  982. int32_t stage;
  983. int i, rc = 0;
  984. sde_kms = _sde_crtc_get_kms(crtc);
  985. if (!sde_kms || !sde_kms->catalog) {
  986. SDE_ERROR("invalid parameters\n");
  987. return -EINVAL;
  988. }
  989. for (i = 1; i < cnt; i++) {
  990. prv_pstate = &pstates[i - 1];
  991. cur_pstate = &pstates[i];
  992. prev_layout = prv_pstate->sde_pstate->layout;
  993. cur_layout = cur_pstate->sde_pstate->layout;
  994. if (prv_pstate->stage != cur_pstate->stage ||
  995. prev_layout != cur_layout)
  996. continue;
  997. stage = cur_pstate->stage;
  998. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  999. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1000. prv_pstate->drm_pstate->crtc_y,
  1001. prv_pstate->drm_pstate->crtc_w,
  1002. prv_pstate->drm_pstate->crtc_h, false);
  1003. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1004. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1005. cur_pstate->drm_pstate->crtc_y,
  1006. cur_pstate->drm_pstate->crtc_w,
  1007. cur_pstate->drm_pstate->crtc_h, false);
  1008. if (right_rect.x < left_rect.x) {
  1009. swap(left_pid, right_pid);
  1010. swap(left_rect, right_rect);
  1011. swap(prv_pstate, cur_pstate);
  1012. }
  1013. /*
  1014. * - planes are enumerated in pipe-priority order such that
  1015. * planes with lower drm_id must be left-most in a shared
  1016. * blend-stage when using source split.
  1017. * - planes in source split must be contiguous in width
  1018. * - planes in source split must have same dest yoff and height
  1019. */
  1020. if ((right_pid < left_pid) &&
  1021. !sde_kms->catalog->pipe_order_type) {
  1022. SDE_ERROR(
  1023. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1024. stage, left_pid, right_pid);
  1025. return -EINVAL;
  1026. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1027. SDE_ERROR(
  1028. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1029. stage, left_rect.x, left_rect.w,
  1030. right_rect.x, right_rect.w);
  1031. return -EINVAL;
  1032. } else if ((left_rect.y != right_rect.y) ||
  1033. (left_rect.h != right_rect.h)) {
  1034. SDE_ERROR(
  1035. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1036. stage, left_rect.y, left_rect.h,
  1037. right_rect.y, right_rect.h);
  1038. return -EINVAL;
  1039. }
  1040. }
  1041. return rc;
  1042. }
  1043. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1044. struct plane_state *pstates, int cnt)
  1045. {
  1046. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1047. enum sde_layout prev_layout, cur_layout;
  1048. struct sde_kms *sde_kms;
  1049. struct sde_rect left_rect, right_rect;
  1050. int32_t left_pid, right_pid;
  1051. int32_t stage;
  1052. int i;
  1053. sde_kms = _sde_crtc_get_kms(crtc);
  1054. if (!sde_kms || !sde_kms->catalog) {
  1055. SDE_ERROR("invalid parameters\n");
  1056. return;
  1057. }
  1058. if (!sde_kms->catalog->pipe_order_type)
  1059. return;
  1060. for (i = 0; i < cnt; i++) {
  1061. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1062. cur_pstate = &pstates[i];
  1063. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1064. prev_layout = prv_pstate ? prv_pstate->sde_pstate->layout :
  1065. SDE_LAYOUT_NONE;
  1066. cur_layout = cur_pstate->sde_pstate->layout;
  1067. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)
  1068. || (prev_layout != cur_layout)) {
  1069. /*
  1070. * reset if prv or nxt pipes are not in the same stage
  1071. * as the cur pipe
  1072. */
  1073. if ((!nxt_pstate)
  1074. || (nxt_pstate->stage != cur_pstate->stage)
  1075. || (nxt_pstate->sde_pstate->layout !=
  1076. cur_pstate->sde_pstate->layout))
  1077. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1078. continue;
  1079. }
  1080. stage = cur_pstate->stage;
  1081. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1082. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1083. prv_pstate->drm_pstate->crtc_y,
  1084. prv_pstate->drm_pstate->crtc_w,
  1085. prv_pstate->drm_pstate->crtc_h, false);
  1086. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1087. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1088. cur_pstate->drm_pstate->crtc_y,
  1089. cur_pstate->drm_pstate->crtc_w,
  1090. cur_pstate->drm_pstate->crtc_h, false);
  1091. if (right_rect.x < left_rect.x) {
  1092. swap(left_pid, right_pid);
  1093. swap(left_rect, right_rect);
  1094. swap(prv_pstate, cur_pstate);
  1095. }
  1096. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1097. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1098. }
  1099. for (i = 0; i < cnt; i++) {
  1100. cur_pstate = &pstates[i];
  1101. sde_plane_setup_src_split_order(
  1102. cur_pstate->drm_pstate->plane,
  1103. cur_pstate->sde_pstate->multirect_index,
  1104. cur_pstate->sde_pstate->pipe_order_flags);
  1105. }
  1106. }
  1107. static void _sde_crtc_setup_blend_cfg_by_stage(struct sde_crtc_mixer *mixer,
  1108. int num_mixers, struct plane_state *pstates, int cnt)
  1109. {
  1110. int i, lm_idx;
  1111. struct sde_format *format;
  1112. bool blend_stage[SDE_STAGE_MAX] = { false };
  1113. u32 blend_type;
  1114. for (i = cnt - 1; i >= 0; i--) {
  1115. blend_type = sde_plane_get_property(pstates[i].sde_pstate,
  1116. PLANE_PROP_BLEND_OP);
  1117. /* stage has already been programmed or BLEND_OP_SKIP type */
  1118. if (blend_stage[pstates[i].sde_pstate->stage] ||
  1119. blend_type == SDE_DRM_BLEND_OP_SKIP)
  1120. continue;
  1121. for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) {
  1122. format = to_sde_format(msm_framebuffer_format(
  1123. pstates[i].sde_pstate->base.fb));
  1124. if (!format) {
  1125. SDE_ERROR("invalid format\n");
  1126. return;
  1127. }
  1128. _sde_crtc_setup_blend_cfg(mixer + lm_idx,
  1129. pstates[i].sde_pstate, format);
  1130. blend_stage[pstates[i].sde_pstate->stage] = true;
  1131. }
  1132. }
  1133. }
  1134. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1135. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1136. struct sde_crtc_mixer *mixer)
  1137. {
  1138. struct drm_plane *plane;
  1139. struct drm_framebuffer *fb;
  1140. struct drm_plane_state *state;
  1141. struct sde_crtc_state *cstate;
  1142. struct sde_plane_state *pstate = NULL;
  1143. struct plane_state *pstates = NULL;
  1144. struct sde_format *format;
  1145. struct sde_hw_ctl *ctl;
  1146. struct sde_hw_mixer *lm;
  1147. struct sde_hw_stage_cfg *stage_cfg;
  1148. struct sde_rect plane_crtc_roi;
  1149. uint32_t stage_idx, lm_idx, layout_idx;
  1150. int zpos_cnt[MAX_LAYOUTS_PER_CRTC][SDE_STAGE_MAX + 1];
  1151. int i, mode, cnt = 0;
  1152. bool bg_alpha_enable = false, is_secure = false;
  1153. u32 blend_type;
  1154. DECLARE_BITMAP(fetch_active, SSPP_MAX);
  1155. if (!sde_crtc || !crtc->state || !mixer) {
  1156. SDE_ERROR("invalid sde_crtc or mixer\n");
  1157. return;
  1158. }
  1159. ctl = mixer->hw_ctl;
  1160. lm = mixer->hw_lm;
  1161. cstate = to_sde_crtc_state(crtc->state);
  1162. pstates = kcalloc(SDE_PSTATES_MAX,
  1163. sizeof(struct plane_state), GFP_KERNEL);
  1164. if (!pstates)
  1165. return;
  1166. memset(fetch_active, 0, sizeof(fetch_active));
  1167. memset(zpos_cnt, 0, sizeof(zpos_cnt));
  1168. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1169. state = plane->state;
  1170. if (!state)
  1171. continue;
  1172. plane_crtc_roi.x = state->crtc_x;
  1173. plane_crtc_roi.y = state->crtc_y;
  1174. plane_crtc_roi.w = state->crtc_w;
  1175. plane_crtc_roi.h = state->crtc_h;
  1176. pstate = to_sde_plane_state(state);
  1177. fb = state->fb;
  1178. mode = sde_plane_get_property(pstate,
  1179. PLANE_PROP_FB_TRANSLATION_MODE);
  1180. is_secure = ((mode == SDE_DRM_FB_SEC) ||
  1181. (mode == SDE_DRM_FB_SEC_DIR_TRANS)) ?
  1182. true : false;
  1183. set_bit(sde_plane_pipe(plane), fetch_active);
  1184. sde_plane_ctl_flush(plane, ctl, true);
  1185. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1186. crtc->base.id,
  1187. pstate->stage,
  1188. plane->base.id,
  1189. sde_plane_pipe(plane) - SSPP_VIG0,
  1190. state->fb ? state->fb->base.id : -1);
  1191. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1192. if (!format) {
  1193. SDE_ERROR("invalid format\n");
  1194. goto end;
  1195. }
  1196. blend_type = sde_plane_get_property(pstate,
  1197. PLANE_PROP_BLEND_OP);
  1198. if (blend_type != SDE_DRM_BLEND_OP_SKIP) {
  1199. if (pstate->stage == SDE_STAGE_BASE &&
  1200. format->alpha_enable)
  1201. bg_alpha_enable = true;
  1202. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1203. state->fb ? state->fb->base.id : -1,
  1204. state->src_x >> 16, state->src_y >> 16,
  1205. state->src_w >> 16, state->src_h >> 16,
  1206. state->crtc_x, state->crtc_y,
  1207. state->crtc_w, state->crtc_h,
  1208. pstate->rotation, is_secure);
  1209. /*
  1210. * none or left layout will program to layer mixer
  1211. * group 0, right layout will program to layer mixer
  1212. * group 1.
  1213. */
  1214. if (pstate->layout <= SDE_LAYOUT_LEFT)
  1215. layout_idx = 0;
  1216. else
  1217. layout_idx = 1;
  1218. stage_cfg = &sde_crtc->stage_cfg[layout_idx];
  1219. stage_idx = zpos_cnt[layout_idx][pstate->stage]++;
  1220. stage_cfg->stage[pstate->stage][stage_idx] =
  1221. sde_plane_pipe(plane);
  1222. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1223. pstate->multirect_index;
  1224. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1225. sde_plane_pipe(plane) - SSPP_VIG0,
  1226. pstate->stage,
  1227. pstate->multirect_index,
  1228. pstate->multirect_mode,
  1229. format->base.pixel_format,
  1230. fb ? fb->modifier : 0,
  1231. layout_idx);
  1232. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers;
  1233. lm_idx++) {
  1234. if (bg_alpha_enable && !format->alpha_enable)
  1235. mixer[lm_idx].mixer_op_mode = 0;
  1236. else
  1237. mixer[lm_idx].mixer_op_mode |=
  1238. 1 << pstate->stage;
  1239. }
  1240. }
  1241. if (cnt >= SDE_PSTATES_MAX)
  1242. continue;
  1243. pstates[cnt].sde_pstate = pstate;
  1244. pstates[cnt].drm_pstate = state;
  1245. if (blend_type == SDE_DRM_BLEND_OP_SKIP)
  1246. pstates[cnt].stage = SKIP_STAGING_PIPE_ZPOS;
  1247. else
  1248. pstates[cnt].stage = sde_plane_get_property(
  1249. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1250. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1251. cnt++;
  1252. }
  1253. /* blend config update */
  1254. _sde_crtc_setup_blend_cfg_by_stage(mixer, sde_crtc->num_mixers,
  1255. pstates, cnt);
  1256. if (ctl->ops.set_active_pipes)
  1257. ctl->ops.set_active_pipes(ctl, fetch_active);
  1258. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1259. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1260. if (lm && lm->ops.setup_dim_layer) {
  1261. cstate = to_sde_crtc_state(crtc->state);
  1262. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty)) {
  1263. for (i = 0; i < cstate->num_dim_layers; i++)
  1264. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1265. mixer, &cstate->dim_layer[i]);
  1266. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  1267. }
  1268. }
  1269. _sde_crtc_program_lm_output_roi(crtc);
  1270. end:
  1271. kfree(pstates);
  1272. }
  1273. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1274. struct drm_crtc *crtc)
  1275. {
  1276. struct sde_crtc *sde_crtc;
  1277. struct sde_crtc_state *cstate;
  1278. struct drm_encoder *drm_enc;
  1279. bool is_right_only;
  1280. bool encoder_in_dsc_merge = false;
  1281. if (!crtc || !crtc->state)
  1282. return;
  1283. sde_crtc = to_sde_crtc(crtc);
  1284. cstate = to_sde_crtc_state(crtc->state);
  1285. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS_ONLY)
  1286. return;
  1287. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1288. crtc->state->encoder_mask) {
  1289. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1290. encoder_in_dsc_merge = true;
  1291. break;
  1292. }
  1293. }
  1294. /**
  1295. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1296. * This is due to two reasons:
  1297. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1298. * the left DSC must be used, right DSC cannot be used alone.
  1299. * For right-only partial update, this means swap layer mixers to map
  1300. * Left LM to Right INTF. On later HW this was relaxed.
  1301. * - In DSC Merge mode, the physical encoder has already registered
  1302. * PP0 as the master, to switch to right-only we would have to
  1303. * reprogram to be driven by PP1 instead.
  1304. * To support both cases, we prefer to support the mixer swap solution.
  1305. */
  1306. if (!encoder_in_dsc_merge)
  1307. return;
  1308. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1309. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1310. if (is_right_only && !sde_crtc->mixers_swapped) {
  1311. /* right-only update swap mixers */
  1312. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1313. sde_crtc->mixers_swapped = true;
  1314. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1315. /* left-only or full update, swap back */
  1316. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1317. sde_crtc->mixers_swapped = false;
  1318. }
  1319. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1320. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1321. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1322. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1323. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1324. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1325. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1326. }
  1327. /**
  1328. * _sde_crtc_blend_setup - configure crtc mixers
  1329. * @crtc: Pointer to drm crtc structure
  1330. * @old_state: Pointer to old crtc state
  1331. * @add_planes: Whether or not to add planes to mixers
  1332. */
  1333. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1334. struct drm_crtc_state *old_state, bool add_planes)
  1335. {
  1336. struct sde_crtc *sde_crtc;
  1337. struct sde_crtc_state *sde_crtc_state;
  1338. struct sde_crtc_mixer *mixer;
  1339. struct sde_hw_ctl *ctl;
  1340. struct sde_hw_mixer *lm;
  1341. struct sde_ctl_flush_cfg cfg = {0,};
  1342. int i;
  1343. if (!crtc)
  1344. return;
  1345. sde_crtc = to_sde_crtc(crtc);
  1346. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1347. mixer = sde_crtc->mixers;
  1348. SDE_DEBUG("%s\n", sde_crtc->name);
  1349. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1350. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1351. return;
  1352. }
  1353. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1354. if (!mixer[i].hw_lm) {
  1355. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1356. return;
  1357. }
  1358. mixer[i].mixer_op_mode = 0;
  1359. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS,
  1360. sde_crtc_state->dirty)) {
  1361. /* clear dim_layer settings */
  1362. lm = mixer[i].hw_lm;
  1363. if (lm->ops.clear_dim_layer)
  1364. lm->ops.clear_dim_layer(lm);
  1365. }
  1366. }
  1367. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1368. /* initialize stage cfg */
  1369. memset(&sde_crtc->stage_cfg, 0, sizeof(sde_crtc->stage_cfg));
  1370. if (add_planes)
  1371. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1372. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1373. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1374. int lm_layout = i / MAX_MIXERS_PER_LAYOUT;
  1375. ctl = mixer[i].hw_ctl;
  1376. lm = mixer[i].hw_lm;
  1377. if (sde_kms_rect_is_null(lm_roi))
  1378. sde_crtc->mixers[i].mixer_op_mode = 0;
  1379. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1380. /* stage config flush mask */
  1381. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1382. ctl->ops.get_pending_flush(ctl, &cfg);
  1383. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1384. mixer[i].hw_lm->idx - LM_0,
  1385. mixer[i].mixer_op_mode,
  1386. ctl->idx - CTL_0,
  1387. cfg.pending_flush_mask);
  1388. if (sde_kms_rect_is_null(lm_roi)) {
  1389. SDE_DEBUG(
  1390. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1391. sde_crtc->name, lm->idx - LM_0,
  1392. ctl->idx - CTL_0);
  1393. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1394. NULL);
  1395. } else {
  1396. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1397. &sde_crtc->stage_cfg[lm_layout]);
  1398. }
  1399. }
  1400. _sde_crtc_program_lm_output_roi(crtc);
  1401. }
  1402. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1403. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1404. {
  1405. struct drm_plane *plane;
  1406. struct sde_plane_state *sde_pstate;
  1407. uint32_t mode = 0;
  1408. int rc;
  1409. if (!crtc) {
  1410. SDE_ERROR("invalid state\n");
  1411. return -EINVAL;
  1412. }
  1413. *fb_ns = 0;
  1414. *fb_sec = 0;
  1415. *fb_sec_dir = 0;
  1416. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1417. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1418. rc = PTR_ERR(plane);
  1419. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1420. DRMID(crtc), DRMID(plane), rc);
  1421. return rc;
  1422. }
  1423. sde_pstate = to_sde_plane_state(plane->state);
  1424. mode = sde_plane_get_property(sde_pstate,
  1425. PLANE_PROP_FB_TRANSLATION_MODE);
  1426. switch (mode) {
  1427. case SDE_DRM_FB_NON_SEC:
  1428. (*fb_ns)++;
  1429. break;
  1430. case SDE_DRM_FB_SEC:
  1431. (*fb_sec)++;
  1432. break;
  1433. case SDE_DRM_FB_SEC_DIR_TRANS:
  1434. (*fb_sec_dir)++;
  1435. break;
  1436. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1437. break;
  1438. default:
  1439. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1440. DRMID(plane), mode);
  1441. return -EINVAL;
  1442. }
  1443. }
  1444. return 0;
  1445. }
  1446. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1447. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1448. {
  1449. struct drm_plane *plane;
  1450. const struct drm_plane_state *pstate;
  1451. struct sde_plane_state *sde_pstate;
  1452. uint32_t mode = 0;
  1453. int rc;
  1454. if (!state) {
  1455. SDE_ERROR("invalid state\n");
  1456. return -EINVAL;
  1457. }
  1458. *fb_ns = 0;
  1459. *fb_sec = 0;
  1460. *fb_sec_dir = 0;
  1461. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1462. if (IS_ERR_OR_NULL(pstate)) {
  1463. rc = PTR_ERR(pstate);
  1464. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1465. DRMID(state->crtc), DRMID(plane), rc);
  1466. return rc;
  1467. }
  1468. sde_pstate = to_sde_plane_state(pstate);
  1469. mode = sde_plane_get_property(sde_pstate,
  1470. PLANE_PROP_FB_TRANSLATION_MODE);
  1471. switch (mode) {
  1472. case SDE_DRM_FB_NON_SEC:
  1473. (*fb_ns)++;
  1474. break;
  1475. case SDE_DRM_FB_SEC:
  1476. (*fb_sec)++;
  1477. break;
  1478. case SDE_DRM_FB_SEC_DIR_TRANS:
  1479. (*fb_sec_dir)++;
  1480. break;
  1481. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1482. break;
  1483. default:
  1484. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1485. DRMID(plane), mode);
  1486. return -EINVAL;
  1487. }
  1488. }
  1489. return 0;
  1490. }
  1491. static void _sde_drm_fb_sec_dir_trans(
  1492. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1493. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1494. {
  1495. /* secure display usecase */
  1496. if ((smmu_state->state == ATTACHED)
  1497. && (secure_level == SDE_DRM_SEC_ONLY)) {
  1498. smmu_state->state = catalog->sui_ns_allowed ?
  1499. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1500. smmu_state->secure_level = secure_level;
  1501. smmu_state->transition_type = PRE_COMMIT;
  1502. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1503. if (old_valid_fb)
  1504. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE |
  1505. SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1506. if (catalog->sui_misr_supported)
  1507. smmu_state->sui_misr_state =
  1508. SUI_MISR_ENABLE_REQ;
  1509. /* secure camera usecase */
  1510. } else if (smmu_state->state == ATTACHED) {
  1511. smmu_state->state = DETACH_SEC_REQ;
  1512. smmu_state->secure_level = secure_level;
  1513. smmu_state->transition_type = PRE_COMMIT;
  1514. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1515. }
  1516. }
  1517. static void _sde_drm_fb_transactions(
  1518. struct sde_kms_smmu_state_data *smmu_state,
  1519. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1520. int *ops)
  1521. {
  1522. if (((smmu_state->state == DETACHED)
  1523. || (smmu_state->state == DETACH_ALL_REQ))
  1524. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1525. && ((smmu_state->state == DETACHED_SEC)
  1526. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1527. smmu_state->state = catalog->sui_ns_allowed ?
  1528. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1529. smmu_state->transition_type = post_commit ?
  1530. POST_COMMIT : PRE_COMMIT;
  1531. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1532. if (old_valid_fb)
  1533. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1534. if (catalog->sui_misr_supported)
  1535. smmu_state->sui_misr_state =
  1536. SUI_MISR_DISABLE_REQ;
  1537. } else if ((smmu_state->state == DETACHED_SEC)
  1538. || (smmu_state->state == DETACH_SEC_REQ)) {
  1539. smmu_state->state = ATTACH_SEC_REQ;
  1540. smmu_state->transition_type = post_commit ?
  1541. POST_COMMIT : PRE_COMMIT;
  1542. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1543. if (old_valid_fb)
  1544. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1545. }
  1546. }
  1547. /**
  1548. * sde_crtc_get_secure_transition_ops - determines the operations that
  1549. * need to be performed before transitioning to secure state
  1550. * This function should be called after swapping the new state
  1551. * @crtc: Pointer to drm crtc structure
  1552. * Returns the bitmask of operations need to be performed, -Error in
  1553. * case of error cases
  1554. */
  1555. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1556. struct drm_crtc_state *old_crtc_state,
  1557. bool old_valid_fb)
  1558. {
  1559. struct drm_plane *plane;
  1560. struct drm_encoder *encoder;
  1561. struct sde_crtc *sde_crtc;
  1562. struct sde_kms *sde_kms;
  1563. struct sde_mdss_cfg *catalog;
  1564. struct sde_kms_smmu_state_data *smmu_state;
  1565. uint32_t translation_mode = 0, secure_level;
  1566. int ops = 0;
  1567. bool post_commit = false;
  1568. if (!crtc || !crtc->state) {
  1569. SDE_ERROR("invalid crtc\n");
  1570. return -EINVAL;
  1571. }
  1572. sde_kms = _sde_crtc_get_kms(crtc);
  1573. if (!sde_kms)
  1574. return -EINVAL;
  1575. smmu_state = &sde_kms->smmu_state;
  1576. smmu_state->prev_state = smmu_state->state;
  1577. smmu_state->prev_secure_level = smmu_state->secure_level;
  1578. sde_crtc = to_sde_crtc(crtc);
  1579. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1580. catalog = sde_kms->catalog;
  1581. /*
  1582. * SMMU operations need to be delayed in case of video mode panels
  1583. * when switching back to non_secure mode
  1584. */
  1585. drm_for_each_encoder_mask(encoder, crtc->dev,
  1586. crtc->state->encoder_mask) {
  1587. if (sde_encoder_is_dsi_display(encoder))
  1588. post_commit |= sde_encoder_check_curr_mode(encoder,
  1589. MSM_DISPLAY_VIDEO_MODE);
  1590. }
  1591. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1592. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1593. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1594. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1595. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1596. if (!plane->state)
  1597. continue;
  1598. translation_mode = sde_plane_get_property(
  1599. to_sde_plane_state(plane->state),
  1600. PLANE_PROP_FB_TRANSLATION_MODE);
  1601. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1602. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1603. DRMID(crtc), translation_mode);
  1604. return -EINVAL;
  1605. }
  1606. /* we can break if we find sec_dir plane */
  1607. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1608. break;
  1609. }
  1610. mutex_lock(&sde_kms->secure_transition_lock);
  1611. switch (translation_mode) {
  1612. case SDE_DRM_FB_SEC_DIR_TRANS:
  1613. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1614. catalog, old_valid_fb, &ops);
  1615. break;
  1616. case SDE_DRM_FB_SEC:
  1617. case SDE_DRM_FB_NON_SEC:
  1618. _sde_drm_fb_transactions(smmu_state, catalog,
  1619. old_valid_fb, post_commit, &ops);
  1620. break;
  1621. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1622. ops = 0;
  1623. break;
  1624. default:
  1625. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1626. DRMID(crtc), translation_mode);
  1627. ops = -EINVAL;
  1628. }
  1629. /* log only during actual transition times */
  1630. if (ops) {
  1631. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1632. DRMID(crtc), smmu_state->state,
  1633. secure_level, smmu_state->secure_level,
  1634. smmu_state->transition_type, ops);
  1635. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1636. smmu_state->state, smmu_state->transition_type,
  1637. smmu_state->secure_level, old_valid_fb,
  1638. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  1639. }
  1640. mutex_unlock(&sde_kms->secure_transition_lock);
  1641. return ops;
  1642. }
  1643. /**
  1644. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  1645. * LUTs are configured only once during boot
  1646. * @sde_crtc: Pointer to sde crtc
  1647. * @cstate: Pointer to sde crtc state
  1648. */
  1649. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  1650. struct sde_crtc_state *cstate, uint32_t lut_idx)
  1651. {
  1652. struct sde_hw_scaler3_lut_cfg *cfg;
  1653. struct sde_kms *sde_kms;
  1654. u32 *lut_data = NULL;
  1655. size_t len = 0;
  1656. int ret = 0;
  1657. if (!sde_crtc || !cstate) {
  1658. SDE_ERROR("invalid args\n");
  1659. return -EINVAL;
  1660. }
  1661. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  1662. if (!sde_kms)
  1663. return -EINVAL;
  1664. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  1665. return 0;
  1666. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  1667. &cstate->property_state, &len, lut_idx);
  1668. if (!lut_data || !len) {
  1669. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  1670. lut_idx, lut_data, len);
  1671. lut_data = NULL;
  1672. len = 0;
  1673. }
  1674. cfg = &cstate->scl3_lut_cfg;
  1675. switch (lut_idx) {
  1676. case CRTC_PROP_DEST_SCALER_LUT_ED:
  1677. cfg->dir_lut = lut_data;
  1678. cfg->dir_len = len;
  1679. break;
  1680. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  1681. cfg->cir_lut = lut_data;
  1682. cfg->cir_len = len;
  1683. break;
  1684. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  1685. cfg->sep_lut = lut_data;
  1686. cfg->sep_len = len;
  1687. break;
  1688. default:
  1689. ret = -EINVAL;
  1690. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  1691. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  1692. break;
  1693. }
  1694. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  1695. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  1696. cfg->is_configured);
  1697. return ret;
  1698. }
  1699. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  1700. {
  1701. struct sde_crtc *sde_crtc;
  1702. if (!crtc) {
  1703. SDE_ERROR("invalid crtc\n");
  1704. return;
  1705. }
  1706. sde_crtc = to_sde_crtc(crtc);
  1707. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  1708. }
  1709. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  1710. {
  1711. int i;
  1712. /**
  1713. * Check if sufficient hw resources are
  1714. * available as per target caps & topology
  1715. */
  1716. if (!sde_crtc) {
  1717. SDE_ERROR("invalid argument\n");
  1718. return -EINVAL;
  1719. }
  1720. if (!sde_crtc->num_mixers ||
  1721. sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1722. SDE_ERROR("%s: invalid number mixers: %d\n",
  1723. sde_crtc->name, sde_crtc->num_mixers);
  1724. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1725. SDE_EVTLOG_ERROR);
  1726. return -EINVAL;
  1727. }
  1728. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1729. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  1730. || !sde_crtc->mixers[i].hw_ds) {
  1731. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  1732. sde_crtc->name, i);
  1733. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1734. i, sde_crtc->mixers[i].hw_lm,
  1735. sde_crtc->mixers[i].hw_ctl,
  1736. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  1737. return -EINVAL;
  1738. }
  1739. }
  1740. return 0;
  1741. }
  1742. /**
  1743. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  1744. * @crtc: Pointer to drm crtc
  1745. */
  1746. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  1747. {
  1748. struct sde_crtc *sde_crtc;
  1749. struct sde_crtc_state *cstate;
  1750. struct sde_hw_mixer *hw_lm;
  1751. struct sde_hw_ctl *hw_ctl;
  1752. struct sde_hw_ds *hw_ds;
  1753. struct sde_hw_ds_cfg *cfg;
  1754. struct sde_kms *kms;
  1755. u32 op_mode = 0;
  1756. u32 lm_idx = 0, num_mixers = 0;
  1757. int i, count = 0;
  1758. if (!crtc)
  1759. return;
  1760. sde_crtc = to_sde_crtc(crtc);
  1761. cstate = to_sde_crtc_state(crtc->state);
  1762. kms = _sde_crtc_get_kms(crtc);
  1763. num_mixers = sde_crtc->num_mixers;
  1764. count = cstate->num_ds;
  1765. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1766. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->dirty[0],
  1767. cstate->num_ds_enabled);
  1768. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  1769. SDE_DEBUG("no change in settings, skip commit\n");
  1770. } else if (!kms || !kms->catalog) {
  1771. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  1772. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  1773. SDE_DEBUG("dest scaler feature not supported\n");
  1774. } else if (_sde_validate_hw_resources(sde_crtc)) {
  1775. //do nothing
  1776. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  1777. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  1778. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  1779. } else {
  1780. for (i = 0; i < count; i++) {
  1781. cfg = &cstate->ds_cfg[i];
  1782. if (!cfg->flags)
  1783. continue;
  1784. lm_idx = cfg->idx;
  1785. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1786. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  1787. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  1788. /* Setup op mode - Dual/single */
  1789. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  1790. op_mode |= BIT(hw_ds->idx - DS_0);
  1791. if ((i == count-1) && hw_ds->ops.setup_opmode) {
  1792. op_mode |= (cstate->num_ds_enabled ==
  1793. CRTC_DUAL_MIXERS_ONLY) ?
  1794. SDE_DS_OP_MODE_DUAL : 0;
  1795. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  1796. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  1797. }
  1798. /* Setup scaler */
  1799. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  1800. (cfg->flags &
  1801. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  1802. if (hw_ds->ops.setup_scaler)
  1803. hw_ds->ops.setup_scaler(hw_ds,
  1804. &cfg->scl3_cfg,
  1805. &cstate->scl3_lut_cfg);
  1806. }
  1807. /*
  1808. * Dest scaler shares the flush bit of the LM in control
  1809. */
  1810. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  1811. hw_ctl->ops.update_bitmask_mixer(
  1812. hw_ctl, hw_lm->idx, 1);
  1813. }
  1814. }
  1815. }
  1816. static void sde_crtc_frame_event_cb(void *data, u32 event)
  1817. {
  1818. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1819. struct sde_crtc *sde_crtc;
  1820. struct msm_drm_private *priv;
  1821. struct sde_crtc_frame_event *fevent;
  1822. struct sde_kms_frame_event_cb_data *cb_data;
  1823. struct drm_plane *plane;
  1824. u32 ubwc_error;
  1825. unsigned long flags;
  1826. u32 crtc_id;
  1827. cb_data = (struct sde_kms_frame_event_cb_data *)data;
  1828. if (!data) {
  1829. SDE_ERROR("invalid parameters\n");
  1830. return;
  1831. }
  1832. crtc = cb_data->crtc;
  1833. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  1834. SDE_ERROR("invalid parameters\n");
  1835. return;
  1836. }
  1837. sde_crtc = to_sde_crtc(crtc);
  1838. priv = crtc->dev->dev_private;
  1839. crtc_id = drm_crtc_index(crtc);
  1840. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1841. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  1842. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  1843. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  1844. struct sde_crtc_frame_event, list);
  1845. if (fevent)
  1846. list_del_init(&fevent->list);
  1847. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  1848. if (!fevent) {
  1849. SDE_ERROR("crtc%d event %d overflow\n",
  1850. crtc->base.id, event);
  1851. SDE_EVT32(DRMID(crtc), event);
  1852. return;
  1853. }
  1854. /* log and clear plane ubwc errors if any */
  1855. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  1856. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  1857. | SDE_ENCODER_FRAME_EVENT_DONE)) {
  1858. drm_for_each_plane_mask(plane, crtc->dev,
  1859. sde_crtc->plane_mask_old) {
  1860. ubwc_error = sde_plane_get_ubwc_error(plane);
  1861. if (ubwc_error) {
  1862. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1863. ubwc_error, SDE_EVTLOG_ERROR);
  1864. SDE_DEBUG("crtc%d plane %d ubwc_error %d\n",
  1865. DRMID(crtc), DRMID(plane),
  1866. ubwc_error);
  1867. sde_plane_clear_ubwc_error(plane);
  1868. }
  1869. }
  1870. }
  1871. fevent->event = event;
  1872. fevent->crtc = crtc;
  1873. fevent->connector = cb_data->connector;
  1874. fevent->ts = ktime_get();
  1875. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  1876. }
  1877. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  1878. struct drm_crtc_state *old_state)
  1879. {
  1880. struct drm_device *dev;
  1881. struct sde_crtc *sde_crtc;
  1882. struct sde_crtc_state *cstate;
  1883. struct drm_connector *conn;
  1884. struct drm_encoder *encoder;
  1885. struct drm_connector_list_iter conn_iter;
  1886. if (!crtc || !crtc->state) {
  1887. SDE_ERROR("invalid crtc\n");
  1888. return;
  1889. }
  1890. dev = crtc->dev;
  1891. sde_crtc = to_sde_crtc(crtc);
  1892. cstate = to_sde_crtc_state(crtc->state);
  1893. SDE_EVT32_VERBOSE(DRMID(crtc));
  1894. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  1895. /* identify connectors attached to this crtc */
  1896. cstate->num_connectors = 0;
  1897. drm_connector_list_iter_begin(dev, &conn_iter);
  1898. drm_for_each_connector_iter(conn, &conn_iter)
  1899. if (conn->state && conn->state->crtc == crtc &&
  1900. cstate->num_connectors < MAX_CONNECTORS) {
  1901. encoder = conn->state->best_encoder;
  1902. if (encoder)
  1903. sde_encoder_register_frame_event_callback(
  1904. encoder,
  1905. sde_crtc_frame_event_cb,
  1906. crtc);
  1907. cstate->connectors[cstate->num_connectors++] = conn;
  1908. sde_connector_prepare_fence(conn);
  1909. }
  1910. drm_connector_list_iter_end(&conn_iter);
  1911. /* prepare main output fence */
  1912. sde_fence_prepare(sde_crtc->output_fence);
  1913. SDE_ATRACE_END("sde_crtc_prepare_commit");
  1914. }
  1915. /**
  1916. * sde_crtc_complete_flip - signal pending page_flip events
  1917. * Any pending vblank events are added to the vblank_event_list
  1918. * so that the next vblank interrupt shall signal them.
  1919. * However PAGE_FLIP events are not handled through the vblank_event_list.
  1920. * This API signals any pending PAGE_FLIP events requested through
  1921. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  1922. * if file!=NULL, this is preclose potential cancel-flip path
  1923. * @crtc: Pointer to drm crtc structure
  1924. * @file: Pointer to drm file
  1925. */
  1926. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  1927. struct drm_file *file)
  1928. {
  1929. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1930. struct drm_device *dev = crtc->dev;
  1931. struct drm_pending_vblank_event *event;
  1932. unsigned long flags;
  1933. spin_lock_irqsave(&dev->event_lock, flags);
  1934. event = sde_crtc->event;
  1935. if (!event)
  1936. goto end;
  1937. /*
  1938. * if regular vblank case (!file) or if cancel-flip from
  1939. * preclose on file that requested flip, then send the
  1940. * event:
  1941. */
  1942. if (!file || (event->base.file_priv == file)) {
  1943. sde_crtc->event = NULL;
  1944. DRM_DEBUG_VBL("%s: send event: %pK\n",
  1945. sde_crtc->name, event);
  1946. SDE_EVT32_VERBOSE(DRMID(crtc));
  1947. drm_crtc_send_vblank_event(crtc, event);
  1948. }
  1949. end:
  1950. spin_unlock_irqrestore(&dev->event_lock, flags);
  1951. }
  1952. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  1953. struct drm_crtc_state *cstate)
  1954. {
  1955. struct drm_encoder *encoder;
  1956. if (!crtc || !crtc->dev || !cstate) {
  1957. SDE_ERROR("invalid crtc\n");
  1958. return INTF_MODE_NONE;
  1959. }
  1960. drm_for_each_encoder_mask(encoder, crtc->dev,
  1961. cstate->encoder_mask) {
  1962. /* continue if copy encoder is encountered */
  1963. if (sde_encoder_in_clone_mode(encoder))
  1964. continue;
  1965. return sde_encoder_get_intf_mode(encoder);
  1966. }
  1967. return INTF_MODE_NONE;
  1968. }
  1969. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  1970. {
  1971. struct drm_encoder *encoder;
  1972. if (!crtc || !crtc->dev) {
  1973. SDE_ERROR("invalid crtc\n");
  1974. return INTF_MODE_NONE;
  1975. }
  1976. drm_for_each_encoder(encoder, crtc->dev)
  1977. if ((encoder->crtc == crtc)
  1978. && !sde_encoder_in_cont_splash(encoder))
  1979. return sde_encoder_get_fps(encoder);
  1980. return 0;
  1981. }
  1982. static void sde_crtc_vblank_cb(void *data)
  1983. {
  1984. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1985. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1986. /* keep statistics on vblank callback - with auto reset via debugfs */
  1987. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  1988. sde_crtc->vblank_cb_time = ktime_get();
  1989. else
  1990. sde_crtc->vblank_cb_count++;
  1991. sde_crtc->vblank_last_cb_time = ktime_get();
  1992. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  1993. drm_crtc_handle_vblank(crtc);
  1994. DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
  1995. SDE_EVT32_VERBOSE(DRMID(crtc));
  1996. }
  1997. static void _sde_crtc_retire_event(struct drm_connector *connector,
  1998. ktime_t ts, enum sde_fence_event fence_event)
  1999. {
  2000. if (!connector) {
  2001. SDE_ERROR("invalid param\n");
  2002. return;
  2003. }
  2004. SDE_ATRACE_BEGIN("signal_retire_fence");
  2005. sde_connector_complete_commit(connector, ts, fence_event);
  2006. SDE_ATRACE_END("signal_retire_fence");
  2007. }
  2008. static void sde_crtc_frame_event_work(struct kthread_work *work)
  2009. {
  2010. struct msm_drm_private *priv;
  2011. struct sde_crtc_frame_event *fevent;
  2012. struct drm_crtc *crtc;
  2013. struct sde_crtc *sde_crtc;
  2014. struct sde_kms *sde_kms;
  2015. unsigned long flags;
  2016. bool in_clone_mode = false;
  2017. if (!work) {
  2018. SDE_ERROR("invalid work handle\n");
  2019. return;
  2020. }
  2021. fevent = container_of(work, struct sde_crtc_frame_event, work);
  2022. if (!fevent->crtc || !fevent->crtc->state) {
  2023. SDE_ERROR("invalid crtc\n");
  2024. return;
  2025. }
  2026. crtc = fevent->crtc;
  2027. sde_crtc = to_sde_crtc(crtc);
  2028. sde_kms = _sde_crtc_get_kms(crtc);
  2029. if (!sde_kms) {
  2030. SDE_ERROR("invalid kms handle\n");
  2031. return;
  2032. }
  2033. priv = sde_kms->dev->dev_private;
  2034. SDE_ATRACE_BEGIN("crtc_frame_event");
  2035. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  2036. ktime_to_ns(fevent->ts));
  2037. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  2038. in_clone_mode = (fevent->event & SDE_ENCODER_FRAME_EVENT_CWB_DONE) ?
  2039. true : false;
  2040. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2041. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2042. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  2043. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  2044. /* this should not happen */
  2045. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  2046. crtc->base.id,
  2047. ktime_to_ns(fevent->ts),
  2048. atomic_read(&sde_crtc->frame_pending));
  2049. SDE_EVT32(DRMID(crtc), fevent->event,
  2050. SDE_EVTLOG_FUNC_CASE1);
  2051. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  2052. /* release bandwidth and other resources */
  2053. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  2054. crtc->base.id,
  2055. ktime_to_ns(fevent->ts));
  2056. SDE_EVT32(DRMID(crtc), fevent->event,
  2057. SDE_EVTLOG_FUNC_CASE2);
  2058. sde_core_perf_crtc_release_bw(crtc);
  2059. } else {
  2060. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  2061. SDE_EVTLOG_FUNC_CASE3);
  2062. }
  2063. }
  2064. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  2065. SDE_ATRACE_BEGIN("signal_release_fence");
  2066. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  2067. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2068. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2069. SDE_ATRACE_END("signal_release_fence");
  2070. }
  2071. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2072. /* this api should be called without spin_lock */
  2073. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  2074. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2075. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2076. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  2077. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  2078. crtc->base.id, ktime_to_ns(fevent->ts));
  2079. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  2080. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  2081. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  2082. SDE_ATRACE_END("crtc_frame_event");
  2083. }
  2084. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  2085. struct drm_crtc_state *old_state)
  2086. {
  2087. struct sde_crtc *sde_crtc;
  2088. if (!crtc || !crtc->state) {
  2089. SDE_ERROR("invalid crtc\n");
  2090. return;
  2091. }
  2092. sde_crtc = to_sde_crtc(crtc);
  2093. SDE_EVT32_VERBOSE(DRMID(crtc));
  2094. sde_core_perf_crtc_update(crtc, 0, false);
  2095. }
  2096. /**
  2097. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2098. * @cstate: Pointer to sde crtc state
  2099. */
  2100. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2101. {
  2102. if (!cstate) {
  2103. SDE_ERROR("invalid cstate\n");
  2104. return;
  2105. }
  2106. cstate->input_fence_timeout_ns =
  2107. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2108. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2109. }
  2110. /**
  2111. * _sde_crtc_clear_dim_layers_v1 - clear all dim layer settings
  2112. * @cstate: Pointer to sde crtc state
  2113. */
  2114. static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
  2115. {
  2116. u32 i;
  2117. if (!cstate)
  2118. return;
  2119. for (i = 0; i < cstate->num_dim_layers; i++)
  2120. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2121. cstate->num_dim_layers = 0;
  2122. }
  2123. /**
  2124. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2125. * @cstate: Pointer to sde crtc state
  2126. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2127. */
  2128. static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
  2129. struct sde_crtc_state *cstate, void __user *usr_ptr)
  2130. {
  2131. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2132. struct sde_drm_dim_layer_cfg *user_cfg;
  2133. struct sde_hw_dim_layer *dim_layer;
  2134. u32 count, i;
  2135. struct sde_kms *kms;
  2136. if (!crtc || !cstate) {
  2137. SDE_ERROR("invalid crtc or cstate\n");
  2138. return;
  2139. }
  2140. dim_layer = cstate->dim_layer;
  2141. if (!usr_ptr) {
  2142. /* usr_ptr is null when setting the default property value */
  2143. _sde_crtc_clear_dim_layers_v1(cstate);
  2144. SDE_DEBUG("dim_layer data removed\n");
  2145. goto clear;
  2146. }
  2147. kms = _sde_crtc_get_kms(crtc);
  2148. if (!kms || !kms->catalog) {
  2149. SDE_ERROR("invalid kms\n");
  2150. return;
  2151. }
  2152. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2153. SDE_ERROR("failed to copy dim_layer data\n");
  2154. return;
  2155. }
  2156. count = dim_layer_v1.num_layers;
  2157. if (count > SDE_MAX_DIM_LAYERS) {
  2158. SDE_ERROR("invalid number of dim_layers:%d", count);
  2159. return;
  2160. }
  2161. /* populate from user space */
  2162. cstate->num_dim_layers = count;
  2163. for (i = 0; i < count; i++) {
  2164. user_cfg = &dim_layer_v1.layer_cfg[i];
  2165. dim_layer[i].flags = user_cfg->flags;
  2166. dim_layer[i].stage = (kms->catalog->has_base_layer) ?
  2167. user_cfg->stage : user_cfg->stage +
  2168. SDE_STAGE_0;
  2169. dim_layer[i].rect.x = user_cfg->rect.x1;
  2170. dim_layer[i].rect.y = user_cfg->rect.y1;
  2171. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2172. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2173. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2174. user_cfg->color_fill.color_0,
  2175. user_cfg->color_fill.color_1,
  2176. user_cfg->color_fill.color_2,
  2177. user_cfg->color_fill.color_3,
  2178. };
  2179. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2180. i, dim_layer[i].flags, dim_layer[i].stage);
  2181. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2182. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2183. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2184. dim_layer[i].color_fill.color_0,
  2185. dim_layer[i].color_fill.color_1,
  2186. dim_layer[i].color_fill.color_2,
  2187. dim_layer[i].color_fill.color_3);
  2188. }
  2189. clear:
  2190. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  2191. }
  2192. /**
  2193. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2194. * @sde_crtc : Pointer to sde crtc
  2195. * @cstate : Pointer to sde crtc state
  2196. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2197. */
  2198. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2199. struct sde_crtc_state *cstate,
  2200. void __user *usr_ptr)
  2201. {
  2202. struct sde_drm_dest_scaler_data ds_data;
  2203. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2204. struct sde_drm_scaler_v2 scaler_v2;
  2205. void __user *scaler_v2_usr;
  2206. int i, count;
  2207. if (!sde_crtc || !cstate) {
  2208. SDE_ERROR("invalid sde_crtc/state\n");
  2209. return -EINVAL;
  2210. }
  2211. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2212. if (!usr_ptr) {
  2213. SDE_DEBUG("ds data removed\n");
  2214. return 0;
  2215. }
  2216. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2217. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2218. sde_crtc->name);
  2219. return -EINVAL;
  2220. }
  2221. count = ds_data.num_dest_scaler;
  2222. if (!count) {
  2223. SDE_DEBUG("no ds data available\n");
  2224. return 0;
  2225. }
  2226. if (count > SDE_MAX_DS_COUNT) {
  2227. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2228. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2229. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2230. return -EINVAL;
  2231. }
  2232. /* Populate from user space */
  2233. for (i = 0; i < count; i++) {
  2234. ds_cfg_usr = &ds_data.ds_cfg[i];
  2235. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2236. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2237. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2238. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2239. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2240. if (ds_cfg_usr->scaler_cfg) {
  2241. scaler_v2_usr =
  2242. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2243. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2244. sizeof(scaler_v2))) {
  2245. SDE_ERROR("%s:scaler: copy from user failed\n",
  2246. sde_crtc->name);
  2247. return -EINVAL;
  2248. }
  2249. }
  2250. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2251. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2252. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2253. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2254. scaler_v2.dst_width, scaler_v2.dst_height);
  2255. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2256. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2257. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2258. scaler_v2.dst_width, scaler_v2.dst_height);
  2259. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2260. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2261. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2262. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2263. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2264. ds_cfg_usr->lm_height);
  2265. }
  2266. cstate->num_ds = count;
  2267. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2268. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count);
  2269. return 0;
  2270. }
  2271. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2272. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2273. u32 prev_lm_width, u32 prev_lm_height)
  2274. {
  2275. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2276. || !cfg->lm_width || !cfg->lm_height) {
  2277. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2278. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2279. hdisplay, mode->vdisplay);
  2280. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2281. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2282. return -E2BIG;
  2283. }
  2284. if (!prev_lm_width && !prev_lm_height) {
  2285. prev_lm_width = cfg->lm_width;
  2286. prev_lm_height = cfg->lm_height;
  2287. } else {
  2288. if (cfg->lm_width != prev_lm_width ||
  2289. cfg->lm_height != prev_lm_height) {
  2290. SDE_ERROR("crtc%d:lm left[%d,%d]right[%d %d]\n",
  2291. crtc->base.id, cfg->lm_width,
  2292. cfg->lm_height, prev_lm_width,
  2293. prev_lm_height);
  2294. SDE_EVT32(DRMID(crtc), cfg->lm_width,
  2295. cfg->lm_height, prev_lm_width,
  2296. prev_lm_height, SDE_EVTLOG_ERROR);
  2297. return -EINVAL;
  2298. }
  2299. }
  2300. return 0;
  2301. }
  2302. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2303. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2304. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2305. u32 max_in_width, u32 max_out_width)
  2306. {
  2307. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2308. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2309. /**
  2310. * Scaler src and dst width shouldn't exceed the maximum
  2311. * width limitation. Also, if there is no partial update
  2312. * dst width and height must match display resolution.
  2313. */
  2314. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2315. cfg->scl3_cfg.dst_width > max_out_width ||
  2316. !cfg->scl3_cfg.src_width[0] ||
  2317. !cfg->scl3_cfg.dst_width ||
  2318. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2319. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2320. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2321. SDE_ERROR("crtc%d: ", crtc->base.id);
  2322. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2323. cfg->scl3_cfg.src_width[0],
  2324. cfg->scl3_cfg.dst_width,
  2325. cfg->scl3_cfg.dst_height,
  2326. hdisplay, mode->vdisplay);
  2327. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2328. sde_crtc->num_mixers, cfg->flags,
  2329. hw_ds->idx - DS_0);
  2330. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2331. cfg->scl3_cfg.enable,
  2332. cfg->scl3_cfg.de.enable);
  2333. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2334. cfg->scl3_cfg.de.enable, cfg->flags,
  2335. max_in_width, max_out_width,
  2336. cfg->scl3_cfg.src_width[0],
  2337. cfg->scl3_cfg.dst_width,
  2338. cfg->scl3_cfg.dst_height, hdisplay,
  2339. mode->vdisplay, sde_crtc->num_mixers,
  2340. SDE_EVTLOG_ERROR);
  2341. cfg->flags &=
  2342. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2343. cfg->flags &=
  2344. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2345. return -EINVAL;
  2346. }
  2347. }
  2348. return 0;
  2349. }
  2350. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2351. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2352. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2353. struct sde_hw_ds_cfg *cfg, u32 hdisplay, u32 *num_ds_enable,
  2354. u32 prev_lm_width, u32 prev_lm_height, u32 max_in_width,
  2355. u32 max_out_width)
  2356. {
  2357. int i, ret;
  2358. u32 lm_idx;
  2359. for (i = 0; i < cstate->num_ds; i++) {
  2360. cfg = &cstate->ds_cfg[i];
  2361. lm_idx = cfg->idx;
  2362. /**
  2363. * Validate against topology
  2364. * No of dest scalers should match the num of mixers
  2365. * unless it is partial update left only/right only use case
  2366. */
  2367. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2368. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2369. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2370. crtc->base.id, i, lm_idx, cfg->flags);
  2371. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2372. SDE_EVTLOG_ERROR);
  2373. return -EINVAL;
  2374. }
  2375. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2376. if (!max_in_width && !max_out_width) {
  2377. max_in_width = hw_ds->scl->top->maxinputwidth;
  2378. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2379. if (cstate->num_ds == CRTC_DUAL_MIXERS_ONLY)
  2380. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2381. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2382. max_in_width, max_out_width, cstate->num_ds);
  2383. }
  2384. /* Check LM width and height */
  2385. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2386. prev_lm_width, prev_lm_height);
  2387. if (ret)
  2388. return ret;
  2389. /* Check scaler data */
  2390. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2391. hw_ds, cfg, hdisplay,
  2392. max_in_width, max_out_width);
  2393. if (ret)
  2394. return ret;
  2395. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2396. (*num_ds_enable)++;
  2397. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2398. hw_ds->idx - DS_0, cfg->flags);
  2399. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2400. }
  2401. return 0;
  2402. }
  2403. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2404. struct sde_crtc_state *cstate, struct sde_hw_ds_cfg *cfg,
  2405. u32 num_ds_enable)
  2406. {
  2407. int i;
  2408. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2409. cstate->num_ds_enabled, num_ds_enable);
  2410. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2411. cstate->num_ds, cstate->dirty[0]);
  2412. if (cstate->num_ds_enabled != num_ds_enable) {
  2413. /* Disabling destination scaler */
  2414. if (!num_ds_enable) {
  2415. for (i = 0; i < cstate->num_ds; i++) {
  2416. cfg = &cstate->ds_cfg[i];
  2417. cfg->idx = i;
  2418. /* Update scaler settings in disable case */
  2419. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2420. cfg->scl3_cfg.enable = 0;
  2421. cfg->scl3_cfg.de.enable = 0;
  2422. }
  2423. }
  2424. cstate->num_ds_enabled = num_ds_enable;
  2425. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2426. } else {
  2427. if (!cstate->num_ds_enabled)
  2428. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2429. }
  2430. }
  2431. /**
  2432. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2433. * @crtc : Pointer to drm crtc
  2434. * @state : Pointer to drm crtc state
  2435. */
  2436. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2437. struct drm_crtc_state *state)
  2438. {
  2439. struct sde_crtc *sde_crtc;
  2440. struct sde_crtc_state *cstate;
  2441. struct drm_display_mode *mode;
  2442. struct sde_kms *kms;
  2443. struct sde_hw_ds *hw_ds = NULL;
  2444. struct sde_hw_ds_cfg *cfg = NULL;
  2445. u32 ret = 0;
  2446. u32 num_ds_enable = 0, hdisplay = 0;
  2447. u32 max_in_width = 0, max_out_width = 0;
  2448. u32 prev_lm_width = 0, prev_lm_height = 0;
  2449. if (!crtc || !state)
  2450. return -EINVAL;
  2451. sde_crtc = to_sde_crtc(crtc);
  2452. cstate = to_sde_crtc_state(state);
  2453. kms = _sde_crtc_get_kms(crtc);
  2454. mode = &state->adjusted_mode;
  2455. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2456. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2457. SDE_DEBUG("dest scaler property not set, skip validation\n");
  2458. return 0;
  2459. }
  2460. if (!kms || !kms->catalog) {
  2461. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  2462. return -EINVAL;
  2463. }
  2464. if (!kms->catalog->mdp[0].has_dest_scaler) {
  2465. SDE_DEBUG("dest scaler feature not supported\n");
  2466. return 0;
  2467. }
  2468. if (!sde_crtc->num_mixers) {
  2469. SDE_DEBUG("mixers not allocated\n");
  2470. return 0;
  2471. }
  2472. ret = _sde_validate_hw_resources(sde_crtc);
  2473. if (ret)
  2474. goto err;
  2475. /**
  2476. * No of dest scalers shouldn't exceed hw ds block count and
  2477. * also, match the num of mixers unless it is partial update
  2478. * left only/right only use case - currently PU + DS is not supported
  2479. */
  2480. if (cstate->num_ds > kms->catalog->ds_count ||
  2481. ((cstate->num_ds != sde_crtc->num_mixers) &&
  2482. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2483. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  2484. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  2485. cstate->ds_cfg[0].flags);
  2486. ret = -EINVAL;
  2487. goto err;
  2488. }
  2489. /**
  2490. * Check if DS needs to be enabled or disabled
  2491. * In case of enable, validate the data
  2492. */
  2493. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  2494. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  2495. cstate->num_ds, cstate->ds_cfg[0].flags);
  2496. goto disable;
  2497. }
  2498. /* Display resolution */
  2499. hdisplay = mode->hdisplay/sde_crtc->num_mixers;
  2500. /* Validate the DS data */
  2501. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  2502. mode, hw_ds, cfg, hdisplay, &num_ds_enable,
  2503. prev_lm_width, prev_lm_height,
  2504. max_in_width, max_out_width);
  2505. if (ret)
  2506. goto err;
  2507. disable:
  2508. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, cfg,
  2509. num_ds_enable);
  2510. return 0;
  2511. err:
  2512. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2513. return ret;
  2514. }
  2515. /**
  2516. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
  2517. * @crtc: Pointer to CRTC object
  2518. */
  2519. static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  2520. {
  2521. struct drm_plane *plane = NULL;
  2522. uint32_t wait_ms = 1;
  2523. ktime_t kt_end, kt_wait;
  2524. int rc = 0;
  2525. SDE_DEBUG("\n");
  2526. if (!crtc || !crtc->state) {
  2527. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  2528. return;
  2529. }
  2530. /* use monotonic timer to limit total fence wait time */
  2531. kt_end = ktime_add_ns(ktime_get(),
  2532. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  2533. /*
  2534. * Wait for fences sequentially, as all of them need to be signalled
  2535. * before we can proceed.
  2536. *
  2537. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  2538. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  2539. * that each plane can check its fence status and react appropriately
  2540. * if its fence has timed out. Call input fence wait multiple times if
  2541. * fence wait is interrupted due to interrupt call.
  2542. */
  2543. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  2544. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2545. do {
  2546. kt_wait = ktime_sub(kt_end, ktime_get());
  2547. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  2548. wait_ms = ktime_to_ms(kt_wait);
  2549. else
  2550. wait_ms = 0;
  2551. rc = sde_plane_wait_input_fence(plane, wait_ms);
  2552. } while (wait_ms && rc == -ERESTARTSYS);
  2553. }
  2554. SDE_ATRACE_END("plane_wait_input_fence");
  2555. }
  2556. static void _sde_crtc_setup_mixer_for_encoder(
  2557. struct drm_crtc *crtc,
  2558. struct drm_encoder *enc)
  2559. {
  2560. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2561. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2562. struct sde_rm *rm = &sde_kms->rm;
  2563. struct sde_crtc_mixer *mixer;
  2564. struct sde_hw_ctl *last_valid_ctl = NULL;
  2565. int i;
  2566. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  2567. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  2568. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  2569. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  2570. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  2571. /* Set up all the mixers and ctls reserved by this encoder */
  2572. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  2573. mixer = &sde_crtc->mixers[i];
  2574. if (!sde_rm_get_hw(rm, &lm_iter))
  2575. break;
  2576. mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  2577. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  2578. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  2579. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  2580. mixer->hw_lm->idx - LM_0);
  2581. mixer->hw_ctl = last_valid_ctl;
  2582. } else {
  2583. mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
  2584. last_valid_ctl = mixer->hw_ctl;
  2585. sde_crtc->num_ctls++;
  2586. }
  2587. /* Shouldn't happen, mixers are always >= ctls */
  2588. if (!mixer->hw_ctl) {
  2589. SDE_ERROR("no valid ctls found for lm %d\n",
  2590. mixer->hw_lm->idx - LM_0);
  2591. return;
  2592. }
  2593. /* Dspp may be null */
  2594. (void) sde_rm_get_hw(rm, &dspp_iter);
  2595. mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
  2596. /* DS may be null */
  2597. (void) sde_rm_get_hw(rm, &ds_iter);
  2598. mixer->hw_ds = (struct sde_hw_ds *)ds_iter.hw;
  2599. mixer->encoder = enc;
  2600. sde_crtc->num_mixers++;
  2601. SDE_DEBUG("setup mixer %d: lm %d\n",
  2602. i, mixer->hw_lm->idx - LM_0);
  2603. SDE_DEBUG("setup mixer %d: ctl %d\n",
  2604. i, mixer->hw_ctl->idx - CTL_0);
  2605. if (mixer->hw_ds)
  2606. SDE_DEBUG("setup mixer %d: ds %d\n",
  2607. i, mixer->hw_ds->idx - DS_0);
  2608. }
  2609. }
  2610. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  2611. {
  2612. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2613. struct drm_encoder *enc;
  2614. sde_crtc->num_ctls = 0;
  2615. sde_crtc->num_mixers = 0;
  2616. sde_crtc->mixers_swapped = false;
  2617. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  2618. mutex_lock(&sde_crtc->crtc_lock);
  2619. /* Check for mixers on all encoders attached to this crtc */
  2620. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  2621. if (enc->crtc != crtc)
  2622. continue;
  2623. /* avoid overwriting mixers info from a copy encoder */
  2624. if (sde_encoder_in_clone_mode(enc))
  2625. continue;
  2626. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  2627. }
  2628. mutex_unlock(&sde_crtc->crtc_lock);
  2629. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  2630. }
  2631. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  2632. {
  2633. int i;
  2634. struct sde_crtc_state *cstate;
  2635. cstate = to_sde_crtc_state(state);
  2636. cstate->is_ppsplit = false;
  2637. for (i = 0; i < cstate->num_connectors; i++) {
  2638. struct drm_connector *conn = cstate->connectors[i];
  2639. if (sde_connector_get_topology_name(conn) ==
  2640. SDE_RM_TOPOLOGY_PPSPLIT)
  2641. cstate->is_ppsplit = true;
  2642. }
  2643. }
  2644. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc,
  2645. struct drm_crtc_state *state)
  2646. {
  2647. struct sde_crtc *sde_crtc;
  2648. struct sde_crtc_state *cstate;
  2649. struct drm_display_mode *adj_mode;
  2650. u32 crtc_split_width;
  2651. int i;
  2652. if (!crtc || !state) {
  2653. SDE_ERROR("invalid args\n");
  2654. return;
  2655. }
  2656. sde_crtc = to_sde_crtc(crtc);
  2657. cstate = to_sde_crtc_state(state);
  2658. adj_mode = &state->adjusted_mode;
  2659. crtc_split_width = sde_crtc_get_mixer_width(sde_crtc, cstate, adj_mode);
  2660. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2661. cstate->lm_bounds[i].x = crtc_split_width * i;
  2662. cstate->lm_bounds[i].y = 0;
  2663. cstate->lm_bounds[i].w = crtc_split_width;
  2664. cstate->lm_bounds[i].h =
  2665. sde_crtc_get_mixer_height(sde_crtc, cstate, adj_mode);
  2666. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i],
  2667. sizeof(cstate->lm_roi[i]));
  2668. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  2669. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  2670. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  2671. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  2672. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  2673. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  2674. }
  2675. drm_mode_debug_printmodeline(adj_mode);
  2676. }
  2677. static void _sde_crtc_clear_all_blend_stages(struct sde_crtc *sde_crtc)
  2678. {
  2679. struct sde_crtc_mixer mixer;
  2680. /*
  2681. * Use mixer[0] to get hw_ctl which will use ops to clear
  2682. * all blendstages. Clear all blendstages will iterate through
  2683. * all mixers.
  2684. */
  2685. if (sde_crtc->num_mixers) {
  2686. mixer = sde_crtc->mixers[0];
  2687. if (mixer.hw_ctl && mixer.hw_ctl->ops.clear_all_blendstages)
  2688. mixer.hw_ctl->ops.clear_all_blendstages(mixer.hw_ctl);
  2689. if (mixer.hw_ctl && mixer.hw_ctl->ops.set_active_pipes)
  2690. mixer.hw_ctl->ops.set_active_pipes(mixer.hw_ctl, NULL);
  2691. }
  2692. }
  2693. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  2694. struct drm_crtc_state *old_state)
  2695. {
  2696. struct sde_crtc *sde_crtc;
  2697. struct drm_encoder *encoder;
  2698. struct drm_device *dev;
  2699. struct sde_kms *sde_kms;
  2700. struct sde_splash_display *splash_display;
  2701. bool cont_splash_enabled = false, apply_cp_prop = false;
  2702. size_t i;
  2703. if (!crtc) {
  2704. SDE_ERROR("invalid crtc\n");
  2705. return;
  2706. }
  2707. if (!crtc->state->enable) {
  2708. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  2709. crtc->base.id, crtc->state->enable);
  2710. return;
  2711. }
  2712. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2713. SDE_ERROR("power resource is not enabled\n");
  2714. return;
  2715. }
  2716. sde_kms = _sde_crtc_get_kms(crtc);
  2717. if (!sde_kms)
  2718. return;
  2719. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  2720. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2721. sde_crtc = to_sde_crtc(crtc);
  2722. dev = crtc->dev;
  2723. if (!sde_crtc->num_mixers) {
  2724. _sde_crtc_setup_mixers(crtc);
  2725. _sde_crtc_setup_is_ppsplit(crtc->state);
  2726. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  2727. _sde_crtc_clear_all_blend_stages(sde_crtc);
  2728. }
  2729. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2730. if (encoder->crtc != crtc)
  2731. continue;
  2732. /* encoder will trigger pending mask now */
  2733. sde_encoder_trigger_kickoff_pending(encoder);
  2734. }
  2735. /* update performance setting */
  2736. sde_core_perf_crtc_update(crtc, 1, false);
  2737. /*
  2738. * If no mixers have been allocated in sde_crtc_atomic_check(),
  2739. * it means we are trying to flush a CRTC whose state is disabled:
  2740. * nothing else needs to be done.
  2741. */
  2742. if (unlikely(!sde_crtc->num_mixers))
  2743. goto end;
  2744. _sde_crtc_blend_setup(crtc, old_state, true);
  2745. _sde_crtc_dest_scaler_setup(crtc);
  2746. /*
  2747. * Since CP properties use AXI buffer to program the
  2748. * HW, check if context bank is in attached state,
  2749. * apply color processing properties only if
  2750. * smmu state is attached,
  2751. */
  2752. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2753. splash_display = &sde_kms->splash_data.splash_display[i];
  2754. if (splash_display->cont_splash_enabled &&
  2755. splash_display->encoder &&
  2756. crtc == splash_display->encoder->crtc)
  2757. cont_splash_enabled = true;
  2758. }
  2759. apply_cp_prop = sde_kms->catalog->trusted_vm_env ?
  2760. true : sde_crtc->enabled;
  2761. if (sde_kms_is_cp_operation_allowed(sde_kms) &&
  2762. (cont_splash_enabled || apply_cp_prop))
  2763. sde_cp_crtc_apply_properties(crtc);
  2764. /*
  2765. * PP_DONE irq is only used by command mode for now.
  2766. * It is better to request pending before FLUSH and START trigger
  2767. * to make sure no pp_done irq missed.
  2768. * This is safe because no pp_done will happen before SW trigger
  2769. * in command mode.
  2770. */
  2771. end:
  2772. SDE_ATRACE_END("crtc_atomic_begin");
  2773. }
  2774. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  2775. struct drm_crtc_state *old_crtc_state)
  2776. {
  2777. struct drm_encoder *encoder;
  2778. struct sde_crtc *sde_crtc;
  2779. struct drm_device *dev;
  2780. struct drm_plane *plane;
  2781. struct msm_drm_private *priv;
  2782. struct sde_crtc_state *cstate;
  2783. struct sde_kms *sde_kms;
  2784. int i;
  2785. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2786. SDE_ERROR("invalid crtc\n");
  2787. return;
  2788. }
  2789. if (!crtc->state->enable) {
  2790. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  2791. crtc->base.id, crtc->state->enable);
  2792. return;
  2793. }
  2794. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2795. SDE_ERROR("power resource is not enabled\n");
  2796. return;
  2797. }
  2798. sde_kms = _sde_crtc_get_kms(crtc);
  2799. if (!sde_kms) {
  2800. SDE_ERROR("invalid kms\n");
  2801. return;
  2802. }
  2803. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2804. sde_crtc = to_sde_crtc(crtc);
  2805. cstate = to_sde_crtc_state(crtc->state);
  2806. dev = crtc->dev;
  2807. priv = dev->dev_private;
  2808. if ((sde_crtc->cache_state == CACHE_STATE_PRE_CACHE) &&
  2809. sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE))
  2810. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_WRITE,
  2811. false);
  2812. else
  2813. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL, false);
  2814. /*
  2815. * If no mixers has been allocated in sde_crtc_atomic_check(),
  2816. * it means we are trying to flush a CRTC whose state is disabled:
  2817. * nothing else needs to be done.
  2818. */
  2819. if (unlikely(!sde_crtc->num_mixers))
  2820. return;
  2821. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  2822. /*
  2823. * For planes without commit update, drm framework will not add
  2824. * those planes to current state since hardware update is not
  2825. * required. However, if those planes were power collapsed since
  2826. * last commit cycle, driver has to restore the hardware state
  2827. * of those planes explicitly here prior to plane flush.
  2828. * Also use this iteration to see if any plane requires cache,
  2829. * so during the perf update driver can activate/deactivate
  2830. * the cache accordingly.
  2831. */
  2832. for (i = 0; i < SDE_SYS_CACHE_MAX; i++)
  2833. sde_crtc->new_perf.llcc_active[i] = false;
  2834. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2835. sde_plane_restore(plane);
  2836. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  2837. if (sde_plane_is_cache_required(plane, i))
  2838. sde_crtc->new_perf.llcc_active[i] = true;
  2839. }
  2840. }
  2841. sde_core_perf_crtc_update_llcc(crtc);
  2842. /* wait for acquire fences before anything else is done */
  2843. _sde_crtc_wait_for_fences(crtc);
  2844. if (!cstate->rsc_update) {
  2845. drm_for_each_encoder_mask(encoder, dev,
  2846. crtc->state->encoder_mask) {
  2847. cstate->rsc_client =
  2848. sde_encoder_get_rsc_client(encoder);
  2849. }
  2850. cstate->rsc_update = true;
  2851. }
  2852. /*
  2853. * Final plane updates: Give each plane a chance to complete all
  2854. * required writes/flushing before crtc's "flush
  2855. * everything" call below.
  2856. */
  2857. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2858. if (sde_kms->smmu_state.transition_error)
  2859. sde_plane_set_error(plane, true);
  2860. sde_plane_flush(plane);
  2861. }
  2862. /* Kickoff will be scheduled by outer layer */
  2863. SDE_ATRACE_END("sde_crtc_atomic_flush");
  2864. }
  2865. /**
  2866. * sde_crtc_destroy_state - state destroy hook
  2867. * @crtc: drm CRTC
  2868. * @state: CRTC state object to release
  2869. */
  2870. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  2871. struct drm_crtc_state *state)
  2872. {
  2873. struct sde_crtc *sde_crtc;
  2874. struct sde_crtc_state *cstate;
  2875. struct drm_encoder *enc;
  2876. struct sde_kms *sde_kms;
  2877. if (!crtc || !state) {
  2878. SDE_ERROR("invalid argument(s)\n");
  2879. return;
  2880. }
  2881. sde_crtc = to_sde_crtc(crtc);
  2882. cstate = to_sde_crtc_state(state);
  2883. sde_kms = _sde_crtc_get_kms(crtc);
  2884. if (!sde_kms) {
  2885. SDE_ERROR("invalid sde_kms\n");
  2886. return;
  2887. }
  2888. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2889. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  2890. sde_rm_release(&sde_kms->rm, enc, true);
  2891. __drm_atomic_helper_crtc_destroy_state(state);
  2892. /* destroy value helper */
  2893. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  2894. &cstate->property_state);
  2895. }
  2896. static int _sde_crtc_flush_event_thread(struct drm_crtc *crtc)
  2897. {
  2898. struct sde_crtc *sde_crtc;
  2899. int i;
  2900. if (!crtc) {
  2901. SDE_ERROR("invalid argument\n");
  2902. return -EINVAL;
  2903. }
  2904. sde_crtc = to_sde_crtc(crtc);
  2905. if (!atomic_read(&sde_crtc->frame_pending)) {
  2906. SDE_DEBUG("no frames pending\n");
  2907. return 0;
  2908. }
  2909. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  2910. /*
  2911. * flush all the event thread work to make sure all the
  2912. * FRAME_EVENTS from encoder are propagated to crtc
  2913. */
  2914. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  2915. if (list_empty(&sde_crtc->frame_events[i].list))
  2916. kthread_flush_work(&sde_crtc->frame_events[i].work);
  2917. }
  2918. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  2919. return 0;
  2920. }
  2921. /**
  2922. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  2923. * @crtc: Pointer to crtc structure
  2924. */
  2925. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  2926. {
  2927. struct drm_plane *plane;
  2928. struct drm_plane_state *state;
  2929. struct sde_crtc *sde_crtc;
  2930. struct sde_crtc_mixer *mixer;
  2931. struct sde_hw_ctl *ctl;
  2932. if (!crtc)
  2933. return;
  2934. sde_crtc = to_sde_crtc(crtc);
  2935. mixer = sde_crtc->mixers;
  2936. if (!mixer)
  2937. return;
  2938. ctl = mixer->hw_ctl;
  2939. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2940. state = plane->state;
  2941. if (!state)
  2942. continue;
  2943. /* clear plane flush bitmask */
  2944. sde_plane_ctl_flush(plane, ctl, false);
  2945. }
  2946. }
  2947. static void _sde_crtc_schedule_idle_notify(struct drm_crtc *crtc,
  2948. struct drm_crtc_state *old_state)
  2949. {
  2950. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2951. struct sde_crtc_state *cstate = to_sde_crtc_state(old_state);
  2952. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2953. struct msm_drm_private *priv;
  2954. struct msm_drm_thread *event_thread;
  2955. int idle_time = 0;
  2956. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  2957. return;
  2958. priv = sde_kms->dev->dev_private;
  2959. idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT);
  2960. if (!idle_time ||
  2961. !sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  2962. MSM_DISPLAY_VIDEO_MODE) ||
  2963. (crtc->index >= ARRAY_SIZE(priv->event_thread)))
  2964. return;
  2965. /* schedule the idle notify delayed work */
  2966. event_thread = &priv->event_thread[crtc->index];
  2967. kthread_mod_delayed_work(&event_thread->worker,
  2968. &sde_crtc->idle_notify_work, msecs_to_jiffies(idle_time));
  2969. SDE_DEBUG("schedule idle notify work in %dms\n", idle_time);
  2970. }
  2971. /**
  2972. * sde_crtc_reset_hw - attempt hardware reset on errors
  2973. * @crtc: Pointer to DRM crtc instance
  2974. * @old_state: Pointer to crtc state for previous commit
  2975. * @recovery_events: Whether or not recovery events are enabled
  2976. * Returns: Zero if current commit should still be attempted
  2977. */
  2978. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  2979. bool recovery_events)
  2980. {
  2981. struct drm_plane *plane_halt[MAX_PLANES];
  2982. struct drm_plane *plane;
  2983. struct drm_encoder *encoder;
  2984. struct sde_crtc *sde_crtc;
  2985. struct sde_crtc_state *cstate;
  2986. struct sde_hw_ctl *ctl;
  2987. signed int i, plane_count;
  2988. int rc;
  2989. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  2990. return -EINVAL;
  2991. sde_crtc = to_sde_crtc(crtc);
  2992. cstate = to_sde_crtc_state(crtc->state);
  2993. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  2994. /* optionally generate a panic instead of performing a h/w reset */
  2995. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  2996. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2997. ctl = sde_crtc->mixers[i].hw_ctl;
  2998. if (!ctl || !ctl->ops.reset)
  2999. continue;
  3000. rc = ctl->ops.reset(ctl);
  3001. if (rc) {
  3002. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  3003. crtc->base.id, ctl->idx - CTL_0);
  3004. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  3005. SDE_EVTLOG_ERROR);
  3006. break;
  3007. }
  3008. }
  3009. /* Early out if simple ctl reset succeeded */
  3010. if (i == sde_crtc->num_ctls)
  3011. return 0;
  3012. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  3013. /* force all components in the system into reset at the same time */
  3014. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3015. ctl = sde_crtc->mixers[i].hw_ctl;
  3016. if (!ctl || !ctl->ops.hard_reset)
  3017. continue;
  3018. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  3019. ctl->ops.hard_reset(ctl, true);
  3020. }
  3021. plane_count = 0;
  3022. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  3023. if (plane_count >= ARRAY_SIZE(plane_halt))
  3024. break;
  3025. plane_halt[plane_count++] = plane;
  3026. sde_plane_halt_requests(plane, true);
  3027. sde_plane_set_revalidate(plane, true);
  3028. }
  3029. /* provide safe "border color only" commit configuration for later */
  3030. _sde_crtc_remove_pipe_flush(crtc);
  3031. _sde_crtc_blend_setup(crtc, old_state, false);
  3032. /* take h/w components out of reset */
  3033. for (i = plane_count - 1; i >= 0; --i)
  3034. sde_plane_halt_requests(plane_halt[i], false);
  3035. /* attempt to poll for start of frame cycle before reset release */
  3036. list_for_each_entry(encoder,
  3037. &crtc->dev->mode_config.encoder_list, head) {
  3038. if (encoder->crtc != crtc)
  3039. continue;
  3040. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3041. sde_encoder_poll_line_counts(encoder);
  3042. }
  3043. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3044. ctl = sde_crtc->mixers[i].hw_ctl;
  3045. if (!ctl || !ctl->ops.hard_reset)
  3046. continue;
  3047. ctl->ops.hard_reset(ctl, false);
  3048. }
  3049. list_for_each_entry(encoder,
  3050. &crtc->dev->mode_config.encoder_list, head) {
  3051. if (encoder->crtc != crtc)
  3052. continue;
  3053. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3054. sde_encoder_kickoff(encoder, false);
  3055. }
  3056. /* panic the device if VBIF is not in good state */
  3057. return !recovery_events ? 0 : -EAGAIN;
  3058. }
  3059. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  3060. struct drm_crtc_state *old_state)
  3061. {
  3062. struct drm_encoder *encoder;
  3063. struct drm_device *dev;
  3064. struct sde_crtc *sde_crtc;
  3065. struct sde_kms *sde_kms;
  3066. struct sde_crtc_state *cstate;
  3067. bool is_error = false;
  3068. unsigned long flags;
  3069. enum sde_crtc_idle_pc_state idle_pc_state;
  3070. struct sde_encoder_kickoff_params params = { 0 };
  3071. if (!crtc) {
  3072. SDE_ERROR("invalid argument\n");
  3073. return;
  3074. }
  3075. dev = crtc->dev;
  3076. sde_crtc = to_sde_crtc(crtc);
  3077. sde_kms = _sde_crtc_get_kms(crtc);
  3078. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3079. SDE_ERROR("invalid argument\n");
  3080. return;
  3081. }
  3082. cstate = to_sde_crtc_state(crtc->state);
  3083. /*
  3084. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3085. * it means we are trying to start a CRTC whose state is disabled:
  3086. * nothing else needs to be done.
  3087. */
  3088. if (unlikely(!sde_crtc->num_mixers))
  3089. return;
  3090. SDE_ATRACE_BEGIN("crtc_commit");
  3091. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  3092. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3093. if (encoder->crtc != crtc)
  3094. continue;
  3095. /*
  3096. * Encoder will flush/start now, unless it has a tx pending.
  3097. * If so, it may delay and flush at an irq event (e.g. ppdone)
  3098. */
  3099. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  3100. crtc->state);
  3101. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  3102. sde_crtc->needs_hw_reset = true;
  3103. if (idle_pc_state != IDLE_PC_NONE)
  3104. sde_encoder_control_idle_pc(encoder,
  3105. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  3106. }
  3107. /*
  3108. * Optionally attempt h/w recovery if any errors were detected while
  3109. * preparing for the kickoff
  3110. */
  3111. if (sde_crtc->needs_hw_reset) {
  3112. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  3113. if (sde_crtc->frame_trigger_mode
  3114. != FRAME_DONE_WAIT_POSTED_START &&
  3115. sde_crtc_reset_hw(crtc, old_state,
  3116. params.recovery_events_enabled))
  3117. is_error = true;
  3118. sde_crtc->needs_hw_reset = false;
  3119. }
  3120. sde_crtc_calc_fps(sde_crtc);
  3121. SDE_ATRACE_BEGIN("flush_event_thread");
  3122. _sde_crtc_flush_event_thread(crtc);
  3123. SDE_ATRACE_END("flush_event_thread");
  3124. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  3125. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  3126. /* acquire bandwidth and other resources */
  3127. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3128. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3129. } else {
  3130. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3131. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3132. }
  3133. sde_crtc->play_count++;
  3134. sde_vbif_clear_errors(sde_kms);
  3135. if (is_error) {
  3136. _sde_crtc_remove_pipe_flush(crtc);
  3137. _sde_crtc_blend_setup(crtc, old_state, false);
  3138. }
  3139. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3140. if (encoder->crtc != crtc)
  3141. continue;
  3142. sde_encoder_kickoff(encoder, false);
  3143. }
  3144. /* store the event after frame trigger */
  3145. if (sde_crtc->event) {
  3146. WARN_ON(sde_crtc->event);
  3147. } else {
  3148. spin_lock_irqsave(&dev->event_lock, flags);
  3149. sde_crtc->event = crtc->state->event;
  3150. spin_unlock_irqrestore(&dev->event_lock, flags);
  3151. }
  3152. _sde_crtc_schedule_idle_notify(crtc, old_state);
  3153. SDE_ATRACE_END("crtc_commit");
  3154. }
  3155. /**
  3156. * _sde_crtc_vblank_enable_no_lock - update power resource and vblank request
  3157. * @sde_crtc: Pointer to sde crtc structure
  3158. * @enable: Whether to enable/disable vblanks
  3159. *
  3160. * @Return: error code
  3161. */
  3162. static int _sde_crtc_vblank_enable_no_lock(
  3163. struct sde_crtc *sde_crtc, bool enable)
  3164. {
  3165. struct drm_crtc *crtc;
  3166. struct drm_encoder *enc;
  3167. if (!sde_crtc) {
  3168. SDE_ERROR("invalid crtc\n");
  3169. return -EINVAL;
  3170. }
  3171. crtc = &sde_crtc->base;
  3172. if (enable) {
  3173. int ret;
  3174. /* drop lock since power crtc cb may try to re-acquire lock */
  3175. mutex_unlock(&sde_crtc->crtc_lock);
  3176. ret = pm_runtime_get_sync(crtc->dev->dev);
  3177. mutex_lock(&sde_crtc->crtc_lock);
  3178. if (ret < 0)
  3179. return ret;
  3180. drm_for_each_encoder_mask(enc, crtc->dev,
  3181. crtc->state->encoder_mask) {
  3182. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3183. sde_crtc->enabled);
  3184. sde_encoder_register_vblank_callback(enc,
  3185. sde_crtc_vblank_cb, (void *)crtc);
  3186. }
  3187. } else {
  3188. drm_for_each_encoder_mask(enc, crtc->dev,
  3189. crtc->state->encoder_mask) {
  3190. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3191. sde_crtc->enabled);
  3192. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3193. }
  3194. /* drop lock since power crtc cb may try to re-acquire lock */
  3195. mutex_unlock(&sde_crtc->crtc_lock);
  3196. pm_runtime_put_sync(crtc->dev->dev);
  3197. mutex_lock(&sde_crtc->crtc_lock);
  3198. }
  3199. return 0;
  3200. }
  3201. /**
  3202. * sde_crtc_duplicate_state - state duplicate hook
  3203. * @crtc: Pointer to drm crtc structure
  3204. * @Returns: Pointer to new drm_crtc_state structure
  3205. */
  3206. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3207. {
  3208. struct sde_crtc *sde_crtc;
  3209. struct sde_crtc_state *cstate, *old_cstate;
  3210. if (!crtc || !crtc->state) {
  3211. SDE_ERROR("invalid argument(s)\n");
  3212. return NULL;
  3213. }
  3214. sde_crtc = to_sde_crtc(crtc);
  3215. old_cstate = to_sde_crtc_state(crtc->state);
  3216. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3217. if (!cstate) {
  3218. SDE_ERROR("failed to allocate state\n");
  3219. return NULL;
  3220. }
  3221. /* duplicate value helper */
  3222. msm_property_duplicate_state(&sde_crtc->property_info,
  3223. old_cstate, cstate,
  3224. &cstate->property_state, cstate->property_values);
  3225. /* duplicate base helper */
  3226. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3227. return &cstate->base;
  3228. }
  3229. /**
  3230. * sde_crtc_reset - reset hook for CRTCs
  3231. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3232. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3233. * @crtc: Pointer to drm crtc structure
  3234. */
  3235. static void sde_crtc_reset(struct drm_crtc *crtc)
  3236. {
  3237. struct sde_crtc *sde_crtc;
  3238. struct sde_crtc_state *cstate;
  3239. if (!crtc) {
  3240. SDE_ERROR("invalid crtc\n");
  3241. return;
  3242. }
  3243. /* revert suspend actions, if necessary */
  3244. if (!sde_crtc_is_reset_required(crtc)) {
  3245. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  3246. return;
  3247. }
  3248. /* remove previous state, if present */
  3249. if (crtc->state) {
  3250. sde_crtc_destroy_state(crtc, crtc->state);
  3251. crtc->state = 0;
  3252. }
  3253. sde_crtc = to_sde_crtc(crtc);
  3254. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3255. if (!cstate) {
  3256. SDE_ERROR("failed to allocate state\n");
  3257. return;
  3258. }
  3259. /* reset value helper */
  3260. msm_property_reset_state(&sde_crtc->property_info, cstate,
  3261. &cstate->property_state,
  3262. cstate->property_values);
  3263. _sde_crtc_set_input_fence_timeout(cstate);
  3264. cstate->base.crtc = crtc;
  3265. crtc->state = &cstate->base;
  3266. }
  3267. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  3268. {
  3269. struct drm_crtc *crtc = arg;
  3270. struct sde_crtc *sde_crtc;
  3271. struct sde_crtc_state *cstate;
  3272. struct drm_plane *plane;
  3273. struct drm_encoder *encoder;
  3274. u32 power_on;
  3275. unsigned long flags;
  3276. struct sde_crtc_irq_info *node = NULL;
  3277. int ret = 0;
  3278. struct drm_event event;
  3279. if (!crtc) {
  3280. SDE_ERROR("invalid crtc\n");
  3281. return;
  3282. }
  3283. sde_crtc = to_sde_crtc(crtc);
  3284. cstate = to_sde_crtc_state(crtc->state);
  3285. mutex_lock(&sde_crtc->crtc_lock);
  3286. SDE_EVT32(DRMID(crtc), event_type);
  3287. switch (event_type) {
  3288. case SDE_POWER_EVENT_POST_ENABLE:
  3289. /* restore encoder; crtc will be programmed during commit */
  3290. drm_for_each_encoder_mask(encoder, crtc->dev,
  3291. crtc->state->encoder_mask) {
  3292. sde_encoder_virt_restore(encoder);
  3293. }
  3294. /* restore UIDLE */
  3295. sde_core_perf_crtc_update_uidle(crtc, true);
  3296. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3297. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3298. ret = 0;
  3299. if (node->func)
  3300. ret = node->func(crtc, true, &node->irq);
  3301. if (ret)
  3302. SDE_ERROR("%s failed to enable event %x\n",
  3303. sde_crtc->name, node->event);
  3304. }
  3305. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3306. sde_cp_crtc_post_ipc(crtc);
  3307. break;
  3308. case SDE_POWER_EVENT_PRE_DISABLE:
  3309. drm_for_each_encoder_mask(encoder, crtc->dev,
  3310. crtc->state->encoder_mask) {
  3311. /*
  3312. * disable the vsync source after updating the
  3313. * rsc state. rsc state update might have vsync wait
  3314. * and vsync source must be disabled after it.
  3315. * It will avoid generating any vsync from this point
  3316. * till mode-2 entry. It is SW workaround for HW
  3317. * limitation and should not be removed without
  3318. * checking the updated design.
  3319. */
  3320. sde_encoder_control_te(encoder, false);
  3321. }
  3322. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3323. node = NULL;
  3324. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3325. ret = 0;
  3326. if (node->func)
  3327. ret = node->func(crtc, false, &node->irq);
  3328. if (ret)
  3329. SDE_ERROR("%s failed to disable event %x\n",
  3330. sde_crtc->name, node->event);
  3331. }
  3332. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3333. sde_cp_crtc_pre_ipc(crtc);
  3334. break;
  3335. case SDE_POWER_EVENT_POST_DISABLE:
  3336. /*
  3337. * set revalidate flag in planes, so it will be re-programmed
  3338. * in the next frame update
  3339. */
  3340. drm_atomic_crtc_for_each_plane(plane, crtc)
  3341. sde_plane_set_revalidate(plane, true);
  3342. sde_cp_crtc_suspend(crtc);
  3343. /* reconfigure everything on next frame update */
  3344. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  3345. if (cstate->num_ds_enabled)
  3346. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  3347. event.type = DRM_EVENT_SDE_POWER;
  3348. event.length = sizeof(power_on);
  3349. power_on = 0;
  3350. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3351. (u8 *)&power_on);
  3352. break;
  3353. default:
  3354. SDE_DEBUG("event:%d not handled\n", event_type);
  3355. break;
  3356. }
  3357. mutex_unlock(&sde_crtc->crtc_lock);
  3358. }
  3359. static void _sde_crtc_reset(struct drm_crtc *crtc)
  3360. {
  3361. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3362. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  3363. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3364. sde_crtc->num_mixers = 0;
  3365. sde_crtc->mixers_swapped = false;
  3366. /* disable clk & bw control until clk & bw properties are set */
  3367. cstate->bw_control = false;
  3368. cstate->bw_split_vote = false;
  3369. sde_crtc_static_img_control(crtc, CACHE_STATE_DISABLED, false);
  3370. }
  3371. static void sde_crtc_disable(struct drm_crtc *crtc)
  3372. {
  3373. struct sde_kms *sde_kms;
  3374. struct sde_crtc *sde_crtc;
  3375. struct sde_crtc_state *cstate;
  3376. struct drm_encoder *encoder;
  3377. struct msm_drm_private *priv;
  3378. unsigned long flags;
  3379. struct sde_crtc_irq_info *node = NULL;
  3380. struct drm_event event;
  3381. u32 power_on;
  3382. bool in_cont_splash = false;
  3383. int ret, i;
  3384. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  3385. SDE_ERROR("invalid crtc\n");
  3386. return;
  3387. }
  3388. sde_kms = _sde_crtc_get_kms(crtc);
  3389. if (!sde_kms) {
  3390. SDE_ERROR("invalid kms\n");
  3391. return;
  3392. }
  3393. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3394. SDE_ERROR("power resource is not enabled\n");
  3395. return;
  3396. }
  3397. sde_crtc = to_sde_crtc(crtc);
  3398. cstate = to_sde_crtc_state(crtc->state);
  3399. priv = crtc->dev->dev_private;
  3400. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3401. drm_crtc_vblank_off(crtc);
  3402. mutex_lock(&sde_crtc->crtc_lock);
  3403. SDE_EVT32_VERBOSE(DRMID(crtc));
  3404. /* update color processing on suspend */
  3405. event.type = DRM_EVENT_CRTC_POWER;
  3406. event.length = sizeof(u32);
  3407. sde_cp_crtc_suspend(crtc);
  3408. power_on = 0;
  3409. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3410. (u8 *)&power_on);
  3411. _sde_crtc_flush_event_thread(crtc);
  3412. kthread_cancel_delayed_work_sync(&sde_crtc->static_cache_read_work);
  3413. kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work);
  3414. SDE_EVT32(DRMID(crtc), sde_crtc->enabled,
  3415. crtc->state->active, crtc->state->enable);
  3416. sde_crtc->enabled = false;
  3417. /* Try to disable uidle */
  3418. sde_core_perf_crtc_update_uidle(crtc, false);
  3419. if (atomic_read(&sde_crtc->frame_pending)) {
  3420. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  3421. atomic_read(&sde_crtc->frame_pending));
  3422. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  3423. SDE_EVTLOG_FUNC_CASE2);
  3424. sde_core_perf_crtc_release_bw(crtc);
  3425. atomic_set(&sde_crtc->frame_pending, 0);
  3426. }
  3427. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3428. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3429. ret = 0;
  3430. if (node->func)
  3431. ret = node->func(crtc, false, &node->irq);
  3432. if (ret)
  3433. SDE_ERROR("%s failed to disable event %x\n",
  3434. sde_crtc->name, node->event);
  3435. }
  3436. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3437. drm_for_each_encoder_mask(encoder, crtc->dev,
  3438. crtc->state->encoder_mask) {
  3439. if (sde_encoder_in_cont_splash(encoder)) {
  3440. in_cont_splash = true;
  3441. break;
  3442. }
  3443. }
  3444. /* avoid clk/bw downvote if cont-splash is enabled */
  3445. if (!in_cont_splash)
  3446. sde_core_perf_crtc_update(crtc, 0, true);
  3447. drm_for_each_encoder_mask(encoder, crtc->dev,
  3448. crtc->state->encoder_mask) {
  3449. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  3450. cstate->rsc_client = NULL;
  3451. cstate->rsc_update = false;
  3452. /*
  3453. * reset idle power-collapse to original state during suspend;
  3454. * user-mode will change the state on resume, if required
  3455. */
  3456. if (sde_kms->catalog->has_idle_pc)
  3457. sde_encoder_control_idle_pc(encoder, true);
  3458. }
  3459. if (sde_crtc->power_event) {
  3460. sde_power_handle_unregister_event(&priv->phandle,
  3461. sde_crtc->power_event);
  3462. sde_crtc->power_event = NULL;
  3463. }
  3464. /**
  3465. * All callbacks are unregistered and frame done waits are complete
  3466. * at this point. No buffers are accessed by hardware.
  3467. * reset the fence timeline if crtc will not be enabled for this commit
  3468. */
  3469. if (!crtc->state->active || !crtc->state->enable) {
  3470. sde_fence_signal(sde_crtc->output_fence,
  3471. ktime_get(), SDE_FENCE_RESET_TIMELINE);
  3472. for (i = 0; i < cstate->num_connectors; ++i)
  3473. sde_connector_commit_reset(cstate->connectors[i],
  3474. ktime_get());
  3475. }
  3476. _sde_crtc_reset(crtc);
  3477. mutex_unlock(&sde_crtc->crtc_lock);
  3478. }
  3479. static void sde_crtc_enable(struct drm_crtc *crtc,
  3480. struct drm_crtc_state *old_crtc_state)
  3481. {
  3482. struct sde_crtc *sde_crtc;
  3483. struct drm_encoder *encoder;
  3484. struct msm_drm_private *priv;
  3485. unsigned long flags;
  3486. struct sde_crtc_irq_info *node = NULL;
  3487. struct drm_event event;
  3488. u32 power_on;
  3489. int ret, i;
  3490. struct sde_crtc_state *cstate;
  3491. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3492. SDE_ERROR("invalid crtc\n");
  3493. return;
  3494. }
  3495. priv = crtc->dev->dev_private;
  3496. cstate = to_sde_crtc_state(crtc->state);
  3497. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3498. SDE_ERROR("power resource is not enabled\n");
  3499. return;
  3500. }
  3501. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3502. SDE_EVT32_VERBOSE(DRMID(crtc));
  3503. sde_crtc = to_sde_crtc(crtc);
  3504. /*
  3505. * Avoid drm_crtc_vblank_on during seamless DMS case
  3506. * when CRTC is already in enabled state
  3507. */
  3508. if (!sde_crtc->enabled)
  3509. drm_crtc_vblank_on(crtc);
  3510. mutex_lock(&sde_crtc->crtc_lock);
  3511. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  3512. /*
  3513. * Try to enable uidle (if possible), we do this before the call
  3514. * to return early during seamless dms mode, so any fps
  3515. * change is also consider to enable/disable UIDLE
  3516. */
  3517. sde_core_perf_crtc_update_uidle(crtc, true);
  3518. /* return early if crtc is already enabled, do this after UIDLE check */
  3519. if (sde_crtc->enabled) {
  3520. if (msm_is_mode_seamless_dms(&crtc->state->adjusted_mode) ||
  3521. msm_is_mode_seamless_dyn_clk(&crtc->state->adjusted_mode))
  3522. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  3523. sde_crtc->name);
  3524. else
  3525. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  3526. mutex_unlock(&sde_crtc->crtc_lock);
  3527. return;
  3528. }
  3529. drm_for_each_encoder_mask(encoder, crtc->dev,
  3530. crtc->state->encoder_mask) {
  3531. sde_encoder_register_frame_event_callback(encoder,
  3532. sde_crtc_frame_event_cb, crtc);
  3533. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL,
  3534. sde_encoder_check_curr_mode(encoder,
  3535. MSM_DISPLAY_VIDEO_MODE));
  3536. }
  3537. sde_crtc->enabled = true;
  3538. /* update color processing on resume */
  3539. event.type = DRM_EVENT_CRTC_POWER;
  3540. event.length = sizeof(u32);
  3541. sde_cp_crtc_resume(crtc);
  3542. power_on = 1;
  3543. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3544. (u8 *)&power_on);
  3545. mutex_unlock(&sde_crtc->crtc_lock);
  3546. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3547. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3548. ret = 0;
  3549. if (node->func)
  3550. ret = node->func(crtc, true, &node->irq);
  3551. if (ret)
  3552. SDE_ERROR("%s failed to enable event %x\n",
  3553. sde_crtc->name, node->event);
  3554. }
  3555. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3556. sde_crtc->power_event = sde_power_handle_register_event(
  3557. &priv->phandle,
  3558. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  3559. SDE_POWER_EVENT_PRE_DISABLE,
  3560. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  3561. /* Enable ESD thread */
  3562. for (i = 0; i < cstate->num_connectors; i++)
  3563. sde_connector_schedule_status_work(cstate->connectors[i], true);
  3564. }
  3565. /* no input validation - caller API has all the checks */
  3566. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
  3567. struct plane_state pstates[], int cnt)
  3568. {
  3569. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  3570. struct drm_display_mode *mode = &state->adjusted_mode;
  3571. const struct drm_plane_state *pstate;
  3572. struct sde_plane_state *sde_pstate;
  3573. int rc = 0, i;
  3574. /* Check dim layer rect bounds and stage */
  3575. for (i = 0; i < cstate->num_dim_layers; i++) {
  3576. if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
  3577. cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
  3578. (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
  3579. cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
  3580. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
  3581. (!cstate->dim_layer[i].rect.w) ||
  3582. (!cstate->dim_layer[i].rect.h)) {
  3583. SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  3584. cstate->dim_layer[i].rect.x,
  3585. cstate->dim_layer[i].rect.y,
  3586. cstate->dim_layer[i].rect.w,
  3587. cstate->dim_layer[i].rect.h,
  3588. cstate->dim_layer[i].stage);
  3589. SDE_ERROR("display: %dx%d\n", mode->hdisplay,
  3590. mode->vdisplay);
  3591. rc = -E2BIG;
  3592. goto end;
  3593. }
  3594. }
  3595. /* log all src and excl_rect, useful for debugging */
  3596. for (i = 0; i < cnt; i++) {
  3597. pstate = pstates[i].drm_pstate;
  3598. sde_pstate = to_sde_plane_state(pstate);
  3599. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  3600. pstate->plane->base.id, pstates[i].stage,
  3601. pstate->crtc_x, pstate->crtc_y,
  3602. pstate->crtc_w, pstate->crtc_h,
  3603. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  3604. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  3605. }
  3606. end:
  3607. return rc;
  3608. }
  3609. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  3610. struct drm_crtc_state *state, struct plane_state pstates[],
  3611. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  3612. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  3613. {
  3614. struct drm_plane *plane;
  3615. int i;
  3616. if (secure == SDE_DRM_SEC_ONLY) {
  3617. /*
  3618. * validate planes - only fb_sec_dir is allowed during sec_crtc
  3619. * - fb_sec_dir is for secure camera preview and
  3620. * secure display use case
  3621. * - fb_sec is for secure video playback
  3622. * - fb_ns is for normal non secure use cases
  3623. */
  3624. if (fb_ns || fb_sec) {
  3625. SDE_ERROR(
  3626. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  3627. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  3628. return -EINVAL;
  3629. }
  3630. /*
  3631. * - only one blending stage is allowed in sec_crtc
  3632. * - validate if pipe is allowed for sec-ui updates
  3633. */
  3634. for (i = 1; i < cnt; i++) {
  3635. if (!pstates[i].drm_pstate
  3636. || !pstates[i].drm_pstate->plane) {
  3637. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  3638. DRMID(crtc), i);
  3639. return -EINVAL;
  3640. }
  3641. plane = pstates[i].drm_pstate->plane;
  3642. if (!sde_plane_is_sec_ui_allowed(plane)) {
  3643. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  3644. DRMID(crtc), plane->base.id);
  3645. return -EINVAL;
  3646. } else if (pstates[i].stage != pstates[i-1].stage) {
  3647. SDE_ERROR(
  3648. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  3649. DRMID(crtc), i, pstates[i].stage,
  3650. i-1, pstates[i-1].stage);
  3651. return -EINVAL;
  3652. }
  3653. }
  3654. /* check if all the dim_layers are in the same stage */
  3655. for (i = 1; i < cstate->num_dim_layers; i++) {
  3656. if (cstate->dim_layer[i].stage !=
  3657. cstate->dim_layer[i-1].stage) {
  3658. SDE_ERROR(
  3659. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  3660. DRMID(crtc),
  3661. i, cstate->dim_layer[i].stage,
  3662. i-1, cstate->dim_layer[i-1].stage);
  3663. return -EINVAL;
  3664. }
  3665. }
  3666. /*
  3667. * if secure-ui supported blendstage is specified,
  3668. * - fail empty commit
  3669. * - validate dim_layer or plane is staged in the supported
  3670. * blendstage
  3671. */
  3672. if (sde_kms->catalog->sui_supported_blendstage) {
  3673. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  3674. cstate->dim_layer[0].stage;
  3675. if (!sde_kms->catalog->has_base_layer)
  3676. sec_stage -= SDE_STAGE_0;
  3677. if ((!cnt && !cstate->num_dim_layers) ||
  3678. (sde_kms->catalog->sui_supported_blendstage
  3679. != sec_stage)) {
  3680. SDE_ERROR(
  3681. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  3682. DRMID(crtc), cnt,
  3683. cstate->num_dim_layers, sec_stage);
  3684. return -EINVAL;
  3685. }
  3686. }
  3687. }
  3688. return 0;
  3689. }
  3690. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  3691. struct drm_crtc_state *state, int fb_sec_dir)
  3692. {
  3693. struct drm_encoder *encoder;
  3694. int encoder_cnt = 0;
  3695. if (fb_sec_dir) {
  3696. drm_for_each_encoder_mask(encoder, crtc->dev,
  3697. state->encoder_mask)
  3698. encoder_cnt++;
  3699. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  3700. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  3701. DRMID(crtc), encoder_cnt);
  3702. return -EINVAL;
  3703. }
  3704. }
  3705. return 0;
  3706. }
  3707. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  3708. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  3709. int fb_ns, int fb_sec, int fb_sec_dir)
  3710. {
  3711. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  3712. struct drm_encoder *encoder;
  3713. int is_video_mode = false;
  3714. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  3715. if (sde_encoder_is_dsi_display(encoder))
  3716. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  3717. MSM_DISPLAY_VIDEO_MODE);
  3718. }
  3719. /*
  3720. * Secure display to secure camera needs without direct
  3721. * transition is currently not allowed
  3722. */
  3723. if (fb_sec_dir && secure == SDE_DRM_SEC_NON_SEC &&
  3724. smmu_state->state != ATTACHED &&
  3725. smmu_state->secure_level == SDE_DRM_SEC_ONLY) {
  3726. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3727. smmu_state->state, smmu_state->secure_level,
  3728. secure);
  3729. goto sec_err;
  3730. }
  3731. /*
  3732. * In video mode check for null commit before transition
  3733. * from secure to non secure and vice versa
  3734. */
  3735. if (is_video_mode && smmu_state &&
  3736. state->plane_mask && crtc->state->plane_mask &&
  3737. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  3738. (secure == SDE_DRM_SEC_ONLY))) ||
  3739. (fb_ns && ((smmu_state->state == DETACHED) ||
  3740. (smmu_state->state == DETACH_ALL_REQ))) ||
  3741. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  3742. (smmu_state->state == DETACH_SEC_REQ)) &&
  3743. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  3744. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3745. smmu_state->state, smmu_state->secure_level,
  3746. secure, crtc->state->plane_mask, state->plane_mask);
  3747. goto sec_err;
  3748. }
  3749. return 0;
  3750. sec_err:
  3751. SDE_ERROR(
  3752. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  3753. DRMID(crtc), secure, smmu_state->state,
  3754. smmu_state->secure_level, fb_ns, fb_sec_dir);
  3755. return -EINVAL;
  3756. }
  3757. static int _sde_crtc_check_secure_conn(struct drm_crtc *crtc,
  3758. struct drm_crtc_state *state, uint32_t fb_sec)
  3759. {
  3760. bool conn_secure = false, is_wb = false;
  3761. struct drm_connector *conn;
  3762. struct drm_connector_state *conn_state;
  3763. int i;
  3764. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  3765. if (conn_state && conn_state->crtc == crtc) {
  3766. if (conn->connector_type ==
  3767. DRM_MODE_CONNECTOR_VIRTUAL)
  3768. is_wb = true;
  3769. if (sde_connector_get_property(conn_state,
  3770. CONNECTOR_PROP_FB_TRANSLATION_MODE) ==
  3771. SDE_DRM_FB_SEC)
  3772. conn_secure = true;
  3773. }
  3774. }
  3775. /*
  3776. * If any input buffers are secure for wb,
  3777. * the output buffer must also be secure.
  3778. */
  3779. if (is_wb && fb_sec && !conn_secure) {
  3780. SDE_ERROR("crtc%d: input fb sec %d, output fb secure %d\n",
  3781. DRMID(crtc), fb_sec, conn_secure);
  3782. return -EINVAL;
  3783. }
  3784. return 0;
  3785. }
  3786. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  3787. struct drm_crtc_state *state, struct plane_state pstates[],
  3788. int cnt)
  3789. {
  3790. struct sde_crtc_state *cstate;
  3791. struct sde_kms *sde_kms;
  3792. uint32_t secure;
  3793. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  3794. int rc;
  3795. if (!crtc || !state) {
  3796. SDE_ERROR("invalid arguments\n");
  3797. return -EINVAL;
  3798. }
  3799. sde_kms = _sde_crtc_get_kms(crtc);
  3800. if (!sde_kms || !sde_kms->catalog) {
  3801. SDE_ERROR("invalid kms\n");
  3802. return -EINVAL;
  3803. }
  3804. cstate = to_sde_crtc_state(state);
  3805. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  3806. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  3807. &fb_sec, &fb_sec_dir);
  3808. if (rc)
  3809. return rc;
  3810. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  3811. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  3812. if (rc)
  3813. return rc;
  3814. rc = _sde_crtc_check_secure_conn(crtc, state, fb_sec);
  3815. if (rc)
  3816. return rc;
  3817. /*
  3818. * secure_crtc is not allowed in a shared toppolgy
  3819. * across different encoders.
  3820. */
  3821. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  3822. if (rc)
  3823. return rc;
  3824. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  3825. secure, fb_ns, fb_sec, fb_sec_dir);
  3826. if (rc)
  3827. return rc;
  3828. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  3829. return 0;
  3830. }
  3831. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  3832. struct drm_crtc_state *state,
  3833. struct drm_display_mode *mode,
  3834. struct plane_state *pstates,
  3835. struct drm_plane *plane,
  3836. struct sde_multirect_plane_states *multirect_plane,
  3837. int *cnt)
  3838. {
  3839. struct sde_crtc *sde_crtc;
  3840. struct sde_crtc_state *cstate;
  3841. const struct drm_plane_state *pstate;
  3842. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  3843. int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
  3844. int inc_sde_stage = 0;
  3845. struct sde_kms *kms;
  3846. sde_crtc = to_sde_crtc(crtc);
  3847. cstate = to_sde_crtc_state(state);
  3848. kms = _sde_crtc_get_kms(crtc);
  3849. if (!kms || !kms->catalog) {
  3850. SDE_ERROR("invalid kms\n");
  3851. return -EINVAL;
  3852. }
  3853. memset(pipe_staged, 0, sizeof(pipe_staged));
  3854. mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  3855. mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  3856. if (cstate->num_ds_enabled)
  3857. mixer_width = mixer_width * cstate->num_ds_enabled;
  3858. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  3859. if (IS_ERR_OR_NULL(pstate)) {
  3860. rc = PTR_ERR(pstate);
  3861. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  3862. sde_crtc->name, plane->base.id, rc);
  3863. return rc;
  3864. }
  3865. if (*cnt >= SDE_PSTATES_MAX)
  3866. continue;
  3867. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  3868. pstates[*cnt].drm_pstate = pstate;
  3869. pstates[*cnt].stage = sde_plane_get_property(
  3870. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  3871. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  3872. if (!kms->catalog->has_base_layer)
  3873. inc_sde_stage = SDE_STAGE_0;
  3874. /* check dim layer stage with every plane */
  3875. for (i = 0; i < cstate->num_dim_layers; i++) {
  3876. if (cstate->dim_layer[i].stage ==
  3877. (pstates[*cnt].stage + inc_sde_stage)) {
  3878. SDE_ERROR(
  3879. "plane:%d/dim_layer:%i-same stage:%d\n",
  3880. plane->base.id, i,
  3881. cstate->dim_layer[i].stage);
  3882. return -EINVAL;
  3883. }
  3884. }
  3885. if (pipe_staged[pstates[*cnt].pipe_id]) {
  3886. multirect_plane[multirect_count].r0 =
  3887. pipe_staged[pstates[*cnt].pipe_id];
  3888. multirect_plane[multirect_count].r1 = pstate;
  3889. multirect_count++;
  3890. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  3891. } else {
  3892. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  3893. }
  3894. (*cnt)++;
  3895. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
  3896. mode->vdisplay) ||
  3897. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
  3898. mode->hdisplay)) {
  3899. SDE_ERROR("invalid vertical/horizontal destination\n");
  3900. SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
  3901. pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
  3902. pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
  3903. return -E2BIG;
  3904. }
  3905. if (cstate->num_ds_enabled &&
  3906. ((pstate->crtc_h > mixer_height) ||
  3907. (pstate->crtc_w > mixer_width))) {
  3908. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  3909. pstate->crtc_w, pstate->crtc_h,
  3910. mixer_width, mixer_height);
  3911. return -E2BIG;
  3912. }
  3913. }
  3914. for (i = 1; i < SSPP_MAX; i++) {
  3915. if (pipe_staged[i]) {
  3916. sde_plane_clear_multirect(pipe_staged[i]);
  3917. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  3918. struct sde_plane_state *psde_state;
  3919. SDE_DEBUG("r1 only virt plane:%d staged\n",
  3920. pipe_staged[i]->plane->base.id);
  3921. psde_state = to_sde_plane_state(
  3922. pipe_staged[i]);
  3923. psde_state->multirect_index = SDE_SSPP_RECT_1;
  3924. }
  3925. }
  3926. }
  3927. for (i = 0; i < multirect_count; i++) {
  3928. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  3929. SDE_ERROR(
  3930. "multirect validation failed for planes (%d - %d)\n",
  3931. multirect_plane[i].r0->plane->base.id,
  3932. multirect_plane[i].r1->plane->base.id);
  3933. return -EINVAL;
  3934. }
  3935. }
  3936. return rc;
  3937. }
  3938. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  3939. struct sde_crtc *sde_crtc,
  3940. struct plane_state *pstates,
  3941. struct sde_crtc_state *cstate,
  3942. struct drm_display_mode *mode,
  3943. int cnt)
  3944. {
  3945. int rc = 0, i, z_pos;
  3946. u32 zpos_cnt = 0;
  3947. struct drm_crtc *crtc;
  3948. struct sde_kms *kms;
  3949. enum sde_layout layout;
  3950. crtc = &sde_crtc->base;
  3951. kms = _sde_crtc_get_kms(crtc);
  3952. if (!kms || !kms->catalog) {
  3953. SDE_ERROR("Invalid kms\n");
  3954. return -EINVAL;
  3955. }
  3956. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  3957. rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);
  3958. if (rc)
  3959. return rc;
  3960. if (!sde_is_custom_client()) {
  3961. int stage_old = pstates[0].stage;
  3962. z_pos = 0;
  3963. for (i = 0; i < cnt; i++) {
  3964. if (stage_old != pstates[i].stage)
  3965. ++z_pos;
  3966. stage_old = pstates[i].stage;
  3967. pstates[i].stage = z_pos;
  3968. }
  3969. }
  3970. z_pos = -1;
  3971. layout = SDE_LAYOUT_NONE;
  3972. for (i = 0; i < cnt; i++) {
  3973. /* reset counts at every new blend stage */
  3974. if (pstates[i].stage != z_pos ||
  3975. pstates[i].sde_pstate->layout != layout) {
  3976. zpos_cnt = 0;
  3977. z_pos = pstates[i].stage;
  3978. layout = pstates[i].sde_pstate->layout;
  3979. }
  3980. /* verify z_pos setting before using it */
  3981. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  3982. SDE_ERROR("> %d plane stages assigned\n",
  3983. SDE_STAGE_MAX - SDE_STAGE_0);
  3984. return -EINVAL;
  3985. } else if (zpos_cnt == 2) {
  3986. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  3987. return -EINVAL;
  3988. } else {
  3989. zpos_cnt++;
  3990. }
  3991. if (!kms->catalog->has_base_layer)
  3992. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  3993. else
  3994. pstates[i].sde_pstate->stage = z_pos;
  3995. SDE_DEBUG("%s: layout %d, zpos %d", sde_crtc->name, layout,
  3996. z_pos);
  3997. }
  3998. return rc;
  3999. }
  4000. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  4001. struct drm_crtc_state *state,
  4002. struct plane_state *pstates,
  4003. struct sde_multirect_plane_states *multirect_plane)
  4004. {
  4005. struct sde_crtc *sde_crtc;
  4006. struct sde_crtc_state *cstate;
  4007. struct sde_kms *kms;
  4008. struct drm_plane *plane = NULL;
  4009. struct drm_display_mode *mode;
  4010. int rc = 0, cnt = 0;
  4011. kms = _sde_crtc_get_kms(crtc);
  4012. if (!kms || !kms->catalog) {
  4013. SDE_ERROR("invalid parameters\n");
  4014. return -EINVAL;
  4015. }
  4016. sde_crtc = to_sde_crtc(crtc);
  4017. cstate = to_sde_crtc_state(state);
  4018. mode = &state->adjusted_mode;
  4019. /* get plane state for all drm planes associated with crtc state */
  4020. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  4021. plane, multirect_plane, &cnt);
  4022. if (rc)
  4023. return rc;
  4024. /* assign mixer stages based on sorted zpos property */
  4025. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  4026. if (rc)
  4027. return rc;
  4028. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  4029. if (rc)
  4030. return rc;
  4031. /*
  4032. * validate and set source split:
  4033. * use pstates sorted by stage to check planes on same stage
  4034. * we assume that all pipes are in source split so its valid to compare
  4035. * without taking into account left/right mixer placement
  4036. */
  4037. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  4038. if (rc)
  4039. return rc;
  4040. return 0;
  4041. }
  4042. static int _sde_crtc_check_plane_layout(struct drm_crtc *crtc,
  4043. struct drm_crtc_state *crtc_state)
  4044. {
  4045. struct sde_kms *kms;
  4046. struct drm_plane *plane;
  4047. struct drm_plane_state *plane_state;
  4048. struct sde_plane_state *pstate;
  4049. int layout_split;
  4050. kms = _sde_crtc_get_kms(crtc);
  4051. if (!kms || !kms->catalog) {
  4052. SDE_ERROR("invalid parameters\n");
  4053. return -EINVAL;
  4054. }
  4055. if (!sde_rm_topology_is_group(&kms->rm, crtc_state,
  4056. SDE_RM_TOPOLOGY_GROUP_QUADPIPE))
  4057. return 0;
  4058. drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
  4059. plane_state = drm_atomic_get_existing_plane_state(
  4060. crtc_state->state, plane);
  4061. if (!plane_state)
  4062. continue;
  4063. pstate = to_sde_plane_state(plane_state);
  4064. layout_split = crtc_state->mode.hdisplay >> 1;
  4065. if (plane_state->crtc_x >= layout_split) {
  4066. plane_state->crtc_x -= layout_split;
  4067. pstate->layout_offset = layout_split;
  4068. pstate->layout = SDE_LAYOUT_RIGHT;
  4069. } else {
  4070. pstate->layout_offset = -1;
  4071. pstate->layout = SDE_LAYOUT_LEFT;
  4072. }
  4073. SDE_DEBUG("plane%d updated: crtc_x=%d layout=%d\n",
  4074. DRMID(plane), plane_state->crtc_x,
  4075. pstate->layout);
  4076. /* check layout boundary */
  4077. if (CHECK_LAYER_BOUNDS(plane_state->crtc_x,
  4078. plane_state->crtc_w, layout_split)) {
  4079. SDE_ERROR("invalid horizontal destination\n");
  4080. SDE_ERROR("x:%d w:%d hdisp:%d layout:%d\n",
  4081. plane_state->crtc_x,
  4082. plane_state->crtc_w,
  4083. layout_split, pstate->layout);
  4084. return -E2BIG;
  4085. }
  4086. }
  4087. return 0;
  4088. }
  4089. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  4090. struct drm_crtc_state *state)
  4091. {
  4092. struct drm_device *dev;
  4093. struct sde_crtc *sde_crtc;
  4094. struct plane_state *pstates = NULL;
  4095. struct sde_crtc_state *cstate;
  4096. struct drm_display_mode *mode;
  4097. int rc = 0;
  4098. struct sde_multirect_plane_states *multirect_plane = NULL;
  4099. struct drm_connector *conn;
  4100. struct drm_connector_list_iter conn_iter;
  4101. if (!crtc) {
  4102. SDE_ERROR("invalid crtc\n");
  4103. return -EINVAL;
  4104. }
  4105. dev = crtc->dev;
  4106. sde_crtc = to_sde_crtc(crtc);
  4107. cstate = to_sde_crtc_state(state);
  4108. if (!state->enable || !state->active) {
  4109. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  4110. crtc->base.id, state->enable, state->active);
  4111. goto end;
  4112. }
  4113. pstates = kcalloc(SDE_PSTATES_MAX,
  4114. sizeof(struct plane_state), GFP_KERNEL);
  4115. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  4116. sizeof(struct sde_multirect_plane_states),
  4117. GFP_KERNEL);
  4118. if (!pstates || !multirect_plane) {
  4119. rc = -ENOMEM;
  4120. goto end;
  4121. }
  4122. mode = &state->adjusted_mode;
  4123. SDE_DEBUG("%s: check", sde_crtc->name);
  4124. /* force a full mode set if active state changed */
  4125. if (state->active_changed)
  4126. state->mode_changed = true;
  4127. /* identify connectors attached to this crtc */
  4128. cstate->num_connectors = 0;
  4129. drm_connector_list_iter_begin(dev, &conn_iter);
  4130. drm_for_each_connector_iter(conn, &conn_iter)
  4131. if ((state->connector_mask & (1 << drm_connector_index(conn)))
  4132. && cstate->num_connectors < MAX_CONNECTORS) {
  4133. cstate->connectors[cstate->num_connectors++] = conn;
  4134. }
  4135. drm_connector_list_iter_end(&conn_iter);
  4136. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  4137. if (rc) {
  4138. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  4139. crtc->base.id, rc);
  4140. goto end;
  4141. }
  4142. rc = _sde_crtc_check_plane_layout(crtc, state);
  4143. if (rc) {
  4144. SDE_ERROR("crtc%d failed plane layout check %d\n",
  4145. crtc->base.id, rc);
  4146. goto end;
  4147. }
  4148. _sde_crtc_setup_is_ppsplit(state);
  4149. _sde_crtc_setup_lm_bounds(crtc, state);
  4150. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  4151. multirect_plane);
  4152. if (rc) {
  4153. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  4154. goto end;
  4155. }
  4156. rc = sde_core_perf_crtc_check(crtc, state);
  4157. if (rc) {
  4158. SDE_ERROR("crtc%d failed performance check %d\n",
  4159. crtc->base.id, rc);
  4160. goto end;
  4161. }
  4162. rc = _sde_crtc_check_rois(crtc, state);
  4163. if (rc) {
  4164. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  4165. goto end;
  4166. }
  4167. rc = sde_cp_crtc_check_properties(crtc, state);
  4168. if (rc) {
  4169. SDE_ERROR("crtc%d failed cp properties check %d\n",
  4170. crtc->base.id, rc);
  4171. goto end;
  4172. }
  4173. end:
  4174. kfree(pstates);
  4175. kfree(multirect_plane);
  4176. return rc;
  4177. }
  4178. /**
  4179. * sde_crtc_get_num_datapath - get the number of datapath active
  4180. * of primary connector
  4181. * @crtc: Pointer to DRM crtc object
  4182. * @connector: Pointer to DRM connector object of WB in CWB case
  4183. */
  4184. int sde_crtc_get_num_datapath(struct drm_crtc *crtc,
  4185. struct drm_connector *connector)
  4186. {
  4187. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4188. struct sde_connector_state *sde_conn_state = NULL;
  4189. struct drm_connector *conn;
  4190. struct drm_connector_list_iter conn_iter;
  4191. if (!sde_crtc || !connector) {
  4192. SDE_DEBUG("Invalid argument\n");
  4193. return 0;
  4194. }
  4195. if (sde_crtc->num_mixers)
  4196. return sde_crtc->num_mixers;
  4197. drm_connector_list_iter_begin(crtc->dev, &conn_iter);
  4198. drm_for_each_connector_iter(conn, &conn_iter) {
  4199. if (conn->state && conn->state->crtc == crtc &&
  4200. conn != connector)
  4201. sde_conn_state = to_sde_connector_state(conn->state);
  4202. }
  4203. drm_connector_list_iter_end(&conn_iter);
  4204. if (sde_conn_state)
  4205. return sde_conn_state->mode_info.topology.num_lm;
  4206. return 0;
  4207. }
  4208. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  4209. {
  4210. struct sde_crtc *sde_crtc;
  4211. int ret;
  4212. if (!crtc) {
  4213. SDE_ERROR("invalid crtc\n");
  4214. return -EINVAL;
  4215. }
  4216. sde_crtc = to_sde_crtc(crtc);
  4217. mutex_lock(&sde_crtc->crtc_lock);
  4218. SDE_EVT32(DRMID(&sde_crtc->base), en, sde_crtc->enabled);
  4219. ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, en);
  4220. if (ret)
  4221. SDE_ERROR("%s vblank enable failed: %d\n",
  4222. sde_crtc->name, ret);
  4223. mutex_unlock(&sde_crtc->crtc_lock);
  4224. return 0;
  4225. }
  4226. static void sde_crtc_install_dest_scale_properties(struct sde_crtc *sde_crtc,
  4227. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  4228. {
  4229. sde_kms_info_add_keyint(info, "has_dest_scaler",
  4230. catalog->mdp[0].has_dest_scaler);
  4231. sde_kms_info_add_keyint(info, "dest_scaler_count",
  4232. catalog->ds_count);
  4233. if (catalog->ds[0].top) {
  4234. sde_kms_info_add_keyint(info,
  4235. "max_dest_scaler_input_width",
  4236. catalog->ds[0].top->maxinputwidth);
  4237. sde_kms_info_add_keyint(info,
  4238. "max_dest_scaler_output_width",
  4239. catalog->ds[0].top->maxoutputwidth);
  4240. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  4241. catalog->ds[0].top->maxupscale);
  4242. }
  4243. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  4244. msm_property_install_volatile_range(
  4245. &sde_crtc->property_info, "dest_scaler",
  4246. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4247. msm_property_install_blob(&sde_crtc->property_info,
  4248. "ds_lut_ed", 0,
  4249. CRTC_PROP_DEST_SCALER_LUT_ED);
  4250. msm_property_install_blob(&sde_crtc->property_info,
  4251. "ds_lut_cir", 0,
  4252. CRTC_PROP_DEST_SCALER_LUT_CIR);
  4253. msm_property_install_blob(&sde_crtc->property_info,
  4254. "ds_lut_sep", 0,
  4255. CRTC_PROP_DEST_SCALER_LUT_SEP);
  4256. } else if (catalog->ds[0].features
  4257. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  4258. msm_property_install_volatile_range(
  4259. &sde_crtc->property_info, "dest_scaler",
  4260. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4261. }
  4262. }
  4263. static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
  4264. struct sde_kms *sde_kms, struct sde_mdss_cfg *catalog,
  4265. struct sde_kms_info *info)
  4266. {
  4267. msm_property_install_range(&sde_crtc->property_info,
  4268. "core_clk", 0x0, 0, U64_MAX,
  4269. sde_kms->perf.max_core_clk_rate,
  4270. CRTC_PROP_CORE_CLK);
  4271. msm_property_install_range(&sde_crtc->property_info,
  4272. "core_ab", 0x0, 0, U64_MAX,
  4273. catalog->perf.max_bw_high * 1000ULL,
  4274. CRTC_PROP_CORE_AB);
  4275. msm_property_install_range(&sde_crtc->property_info,
  4276. "core_ib", 0x0, 0, U64_MAX,
  4277. catalog->perf.max_bw_high * 1000ULL,
  4278. CRTC_PROP_CORE_IB);
  4279. msm_property_install_range(&sde_crtc->property_info,
  4280. "llcc_ab", 0x0, 0, U64_MAX,
  4281. catalog->perf.max_bw_high * 1000ULL,
  4282. CRTC_PROP_LLCC_AB);
  4283. msm_property_install_range(&sde_crtc->property_info,
  4284. "llcc_ib", 0x0, 0, U64_MAX,
  4285. catalog->perf.max_bw_high * 1000ULL,
  4286. CRTC_PROP_LLCC_IB);
  4287. msm_property_install_range(&sde_crtc->property_info,
  4288. "dram_ab", 0x0, 0, U64_MAX,
  4289. catalog->perf.max_bw_high * 1000ULL,
  4290. CRTC_PROP_DRAM_AB);
  4291. msm_property_install_range(&sde_crtc->property_info,
  4292. "dram_ib", 0x0, 0, U64_MAX,
  4293. catalog->perf.max_bw_high * 1000ULL,
  4294. CRTC_PROP_DRAM_IB);
  4295. msm_property_install_range(&sde_crtc->property_info,
  4296. "rot_prefill_bw", 0, 0, U64_MAX,
  4297. catalog->perf.max_bw_high * 1000ULL,
  4298. CRTC_PROP_ROT_PREFILL_BW);
  4299. msm_property_install_range(&sde_crtc->property_info,
  4300. "rot_clk", 0, 0, U64_MAX,
  4301. sde_kms->perf.max_core_clk_rate,
  4302. CRTC_PROP_ROT_CLK);
  4303. if (catalog->perf.max_bw_low)
  4304. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  4305. catalog->perf.max_bw_low * 1000LL);
  4306. if (catalog->perf.max_bw_high)
  4307. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  4308. catalog->perf.max_bw_high * 1000LL);
  4309. if (catalog->perf.min_core_ib)
  4310. sde_kms_info_add_keyint(info, "min_core_ib",
  4311. catalog->perf.min_core_ib * 1000LL);
  4312. if (catalog->perf.min_llcc_ib)
  4313. sde_kms_info_add_keyint(info, "min_llcc_ib",
  4314. catalog->perf.min_llcc_ib * 1000LL);
  4315. if (catalog->perf.min_dram_ib)
  4316. sde_kms_info_add_keyint(info, "min_dram_ib",
  4317. catalog->perf.min_dram_ib * 1000LL);
  4318. if (sde_kms->perf.max_core_clk_rate)
  4319. sde_kms_info_add_keyint(info, "max_mdp_clk",
  4320. sde_kms->perf.max_core_clk_rate);
  4321. }
  4322. static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
  4323. struct sde_mdss_cfg *catalog)
  4324. {
  4325. sde_kms_info_reset(info);
  4326. sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
  4327. sde_kms_info_add_keyint(info, "max_linewidth",
  4328. catalog->max_mixer_width);
  4329. sde_kms_info_add_keyint(info, "max_blendstages",
  4330. catalog->max_mixer_blendstages);
  4331. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2)
  4332. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  4333. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)
  4334. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  4335. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE)
  4336. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  4337. if (catalog->ubwc_version) {
  4338. sde_kms_info_add_keyint(info, "UBWC version",
  4339. catalog->ubwc_version);
  4340. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  4341. catalog->macrotile_mode);
  4342. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  4343. catalog->mdp[0].highest_bank_bit);
  4344. sde_kms_info_add_keyint(info, "UBWC swizzle",
  4345. catalog->mdp[0].ubwc_swizzle);
  4346. }
  4347. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  4348. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  4349. else
  4350. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  4351. if (sde_is_custom_client()) {
  4352. /* No support for SMART_DMA_V1 yet */
  4353. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  4354. sde_kms_info_add_keystr(info,
  4355. "smart_dma_rev", "smart_dma_v2");
  4356. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  4357. sde_kms_info_add_keystr(info,
  4358. "smart_dma_rev", "smart_dma_v2p5");
  4359. }
  4360. sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
  4361. sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
  4362. sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
  4363. if (catalog->uidle_cfg.uidle_rev)
  4364. sde_kms_info_add_keyint(info, "has_uidle",
  4365. true);
  4366. sde_kms_info_add_keystr(info, "core_ib_ff",
  4367. catalog->perf.core_ib_ff);
  4368. sde_kms_info_add_keystr(info, "core_clk_ff",
  4369. catalog->perf.core_clk_ff);
  4370. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  4371. catalog->perf.comp_ratio_rt);
  4372. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  4373. catalog->perf.comp_ratio_nrt);
  4374. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  4375. catalog->perf.dest_scale_prefill_lines);
  4376. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  4377. catalog->perf.undersized_prefill_lines);
  4378. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  4379. catalog->perf.macrotile_prefill_lines);
  4380. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  4381. catalog->perf.yuv_nv12_prefill_lines);
  4382. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  4383. catalog->perf.linear_prefill_lines);
  4384. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  4385. catalog->perf.downscaling_prefill_lines);
  4386. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  4387. catalog->perf.xtra_prefill_lines);
  4388. sde_kms_info_add_keyint(info, "amortizable_threshold",
  4389. catalog->perf.amortizable_threshold);
  4390. sde_kms_info_add_keyint(info, "min_prefill_lines",
  4391. catalog->perf.min_prefill_lines);
  4392. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  4393. catalog->perf.num_mnoc_ports);
  4394. sde_kms_info_add_keyint(info, "axi_bus_width",
  4395. catalog->perf.axi_bus_width);
  4396. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  4397. catalog->sui_supported_blendstage);
  4398. if (catalog->ubwc_bw_calc_version)
  4399. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
  4400. catalog->ubwc_bw_calc_version);
  4401. }
  4402. /**
  4403. * sde_crtc_install_properties - install all drm properties for crtc
  4404. * @crtc: Pointer to drm crtc structure
  4405. */
  4406. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  4407. struct sde_mdss_cfg *catalog)
  4408. {
  4409. struct sde_crtc *sde_crtc;
  4410. struct sde_kms_info *info;
  4411. struct sde_kms *sde_kms;
  4412. static const struct drm_prop_enum_list e_secure_level[] = {
  4413. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  4414. {SDE_DRM_SEC_ONLY, "sec_only"},
  4415. };
  4416. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  4417. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  4418. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  4419. };
  4420. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  4421. {IDLE_PC_NONE, "idle_pc_none"},
  4422. {IDLE_PC_ENABLE, "idle_pc_enable"},
  4423. {IDLE_PC_DISABLE, "idle_pc_disable"},
  4424. };
  4425. static const struct drm_prop_enum_list e_cache_state[] = {
  4426. {CACHE_STATE_DISABLED, "cache_state_disabled"},
  4427. {CACHE_STATE_ENABLED, "cache_state_enabled"},
  4428. };
  4429. static const struct drm_prop_enum_list e_vm_req_state[] = {
  4430. {VM_REQ_NONE, "vm_req_none"},
  4431. {VM_REQ_RELEASE, "vm_req_release"},
  4432. {VM_REQ_ACQUIRE, "vm_req_acquire"},
  4433. };
  4434. SDE_DEBUG("\n");
  4435. if (!crtc || !catalog) {
  4436. SDE_ERROR("invalid crtc or catalog\n");
  4437. return;
  4438. }
  4439. sde_crtc = to_sde_crtc(crtc);
  4440. sde_kms = _sde_crtc_get_kms(crtc);
  4441. if (!sde_kms) {
  4442. SDE_ERROR("invalid argument\n");
  4443. return;
  4444. }
  4445. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  4446. if (!info) {
  4447. SDE_ERROR("failed to allocate info memory\n");
  4448. return;
  4449. }
  4450. sde_crtc_setup_capabilities_blob(info, catalog);
  4451. msm_property_install_range(&sde_crtc->property_info,
  4452. "input_fence_timeout", 0x0, 0,
  4453. SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, SDE_CRTC_INPUT_FENCE_TIMEOUT,
  4454. CRTC_PROP_INPUT_FENCE_TIMEOUT);
  4455. msm_property_install_volatile_range(&sde_crtc->property_info,
  4456. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  4457. msm_property_install_range(&sde_crtc->property_info,
  4458. "output_fence_offset", 0x0, 0, 1, 0,
  4459. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4460. sde_crtc_install_perf_properties(sde_crtc, sde_kms, catalog, info);
  4461. msm_property_install_range(&sde_crtc->property_info,
  4462. "idle_time", 0, 0, U64_MAX, 0,
  4463. CRTC_PROP_IDLE_TIMEOUT);
  4464. if (catalog->has_trusted_vm_support) {
  4465. int init_idx = sde_in_trusted_vm(sde_kms) ? 1 : 0;
  4466. msm_property_install_enum(&sde_crtc->property_info,
  4467. "vm_request_state", 0x0, 0, e_vm_req_state,
  4468. ARRAY_SIZE(e_vm_req_state), init_idx,
  4469. CRTC_PROP_VM_REQ_STATE);
  4470. }
  4471. if (catalog->has_idle_pc)
  4472. msm_property_install_enum(&sde_crtc->property_info,
  4473. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  4474. ARRAY_SIZE(e_idle_pc_state), 0,
  4475. CRTC_PROP_IDLE_PC_STATE);
  4476. if (catalog->has_cwb_support)
  4477. msm_property_install_enum(&sde_crtc->property_info,
  4478. "capture_mode", 0, 0, e_cwb_data_points,
  4479. ARRAY_SIZE(e_cwb_data_points), 0,
  4480. CRTC_PROP_CAPTURE_OUTPUT);
  4481. msm_property_install_volatile_range(&sde_crtc->property_info,
  4482. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  4483. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  4484. 0x0, 0, e_secure_level,
  4485. ARRAY_SIZE(e_secure_level), 0,
  4486. CRTC_PROP_SECURITY_LEVEL);
  4487. msm_property_install_enum(&sde_crtc->property_info, "cache_state",
  4488. 0x0, 0, e_cache_state,
  4489. ARRAY_SIZE(e_cache_state), 0,
  4490. CRTC_PROP_CACHE_STATE);
  4491. if (catalog->has_dim_layer) {
  4492. msm_property_install_volatile_range(&sde_crtc->property_info,
  4493. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  4494. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  4495. SDE_MAX_DIM_LAYERS);
  4496. }
  4497. if (catalog->mdp[0].has_dest_scaler)
  4498. sde_crtc_install_dest_scale_properties(sde_crtc, catalog,
  4499. info);
  4500. if (catalog->dspp_count && catalog->rc_count)
  4501. sde_kms_info_add_keyint(info, "rc_mem_size",
  4502. catalog->dspp[0].sblk->rc.mem_total_size);
  4503. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  4504. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  4505. sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
  4506. catalog->has_base_layer);
  4507. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  4508. info->data, SDE_KMS_INFO_DATALEN(info),
  4509. CRTC_PROP_INFO);
  4510. kfree(info);
  4511. }
  4512. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  4513. const struct drm_crtc_state *state, uint64_t *val)
  4514. {
  4515. struct sde_crtc *sde_crtc;
  4516. struct sde_crtc_state *cstate;
  4517. uint32_t offset;
  4518. bool is_vid = false;
  4519. struct drm_encoder *encoder;
  4520. sde_crtc = to_sde_crtc(crtc);
  4521. cstate = to_sde_crtc_state(state);
  4522. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4523. if (sde_encoder_check_curr_mode(encoder,
  4524. MSM_DISPLAY_VIDEO_MODE))
  4525. is_vid = true;
  4526. if (is_vid)
  4527. break;
  4528. }
  4529. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4530. /*
  4531. * Increment trigger offset for vidoe mode alone as its release fence
  4532. * can be triggered only after the next frame-update. For cmd mode &
  4533. * virtual displays the release fence for the current frame can be
  4534. * triggered right after PP_DONE/WB_DONE interrupt
  4535. */
  4536. if (is_vid)
  4537. offset++;
  4538. /*
  4539. * Hwcomposer now queries the fences using the commit list in atomic
  4540. * commit ioctl. The offset should be set to next timeline
  4541. * which will be incremented during the prepare commit phase
  4542. */
  4543. offset++;
  4544. return sde_fence_create(sde_crtc->output_fence, val, offset);
  4545. }
  4546. /**
  4547. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  4548. * @crtc: Pointer to drm crtc structure
  4549. * @state: Pointer to drm crtc state structure
  4550. * @property: Pointer to targeted drm property
  4551. * @val: Updated property value
  4552. * @Returns: Zero on success
  4553. */
  4554. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  4555. struct drm_crtc_state *state,
  4556. struct drm_property *property,
  4557. uint64_t val)
  4558. {
  4559. struct sde_crtc *sde_crtc;
  4560. struct sde_crtc_state *cstate;
  4561. int idx, ret;
  4562. uint64_t fence_user_fd;
  4563. uint64_t __user prev_user_fd;
  4564. if (!crtc || !state || !property) {
  4565. SDE_ERROR("invalid argument(s)\n");
  4566. return -EINVAL;
  4567. }
  4568. sde_crtc = to_sde_crtc(crtc);
  4569. cstate = to_sde_crtc_state(state);
  4570. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  4571. /* check with cp property system first */
  4572. ret = sde_cp_crtc_set_property(crtc, property, val);
  4573. if (ret != -ENOENT)
  4574. goto exit;
  4575. /* if not handled by cp, check msm_property system */
  4576. ret = msm_property_atomic_set(&sde_crtc->property_info,
  4577. &cstate->property_state, property, val);
  4578. if (ret)
  4579. goto exit;
  4580. idx = msm_property_index(&sde_crtc->property_info, property);
  4581. switch (idx) {
  4582. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  4583. _sde_crtc_set_input_fence_timeout(cstate);
  4584. break;
  4585. case CRTC_PROP_DIM_LAYER_V1:
  4586. _sde_crtc_set_dim_layer_v1(crtc, cstate,
  4587. (void __user *)(uintptr_t)val);
  4588. break;
  4589. case CRTC_PROP_ROI_V1:
  4590. ret = _sde_crtc_set_roi_v1(state,
  4591. (void __user *)(uintptr_t)val);
  4592. break;
  4593. case CRTC_PROP_DEST_SCALER:
  4594. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  4595. (void __user *)(uintptr_t)val);
  4596. break;
  4597. case CRTC_PROP_DEST_SCALER_LUT_ED:
  4598. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  4599. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  4600. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  4601. break;
  4602. case CRTC_PROP_CORE_CLK:
  4603. case CRTC_PROP_CORE_AB:
  4604. case CRTC_PROP_CORE_IB:
  4605. cstate->bw_control = true;
  4606. break;
  4607. case CRTC_PROP_LLCC_AB:
  4608. case CRTC_PROP_LLCC_IB:
  4609. case CRTC_PROP_DRAM_AB:
  4610. case CRTC_PROP_DRAM_IB:
  4611. cstate->bw_control = true;
  4612. cstate->bw_split_vote = true;
  4613. break;
  4614. case CRTC_PROP_OUTPUT_FENCE:
  4615. if (!val)
  4616. goto exit;
  4617. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  4618. sizeof(uint64_t));
  4619. if (ret) {
  4620. SDE_ERROR("copy from user failed rc:%d\n", ret);
  4621. ret = -EFAULT;
  4622. goto exit;
  4623. }
  4624. /*
  4625. * client is expected to reset the property to -1 before
  4626. * requesting for the release fence
  4627. */
  4628. if (prev_user_fd == -1) {
  4629. ret = _sde_crtc_get_output_fence(crtc, state,
  4630. &fence_user_fd);
  4631. if (ret) {
  4632. SDE_ERROR("fence create failed rc:%d\n", ret);
  4633. goto exit;
  4634. }
  4635. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  4636. &fence_user_fd, sizeof(uint64_t));
  4637. if (ret) {
  4638. SDE_ERROR("copy to user failed rc:%d\n", ret);
  4639. put_unused_fd(fence_user_fd);
  4640. ret = -EFAULT;
  4641. goto exit;
  4642. }
  4643. }
  4644. break;
  4645. default:
  4646. /* nothing to do */
  4647. break;
  4648. }
  4649. exit:
  4650. if (ret) {
  4651. if (ret != -EPERM)
  4652. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  4653. crtc->name, DRMID(property),
  4654. property->name, ret);
  4655. else
  4656. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  4657. crtc->name, DRMID(property),
  4658. property->name, ret);
  4659. } else {
  4660. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  4661. property->base.id, val);
  4662. }
  4663. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  4664. return ret;
  4665. }
  4666. void sde_crtc_set_qos_dirty(struct drm_crtc *crtc)
  4667. {
  4668. struct drm_plane *plane;
  4669. struct drm_plane_state *state;
  4670. struct sde_plane_state *pstate;
  4671. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4672. state = plane->state;
  4673. if (!state)
  4674. continue;
  4675. pstate = to_sde_plane_state(state);
  4676. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  4677. }
  4678. }
  4679. /**
  4680. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  4681. * @crtc: Pointer to drm crtc structure
  4682. * @state: Pointer to drm crtc state structure
  4683. * @property: Pointer to targeted drm property
  4684. * @val: Pointer to variable for receiving property value
  4685. * @Returns: Zero on success
  4686. */
  4687. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  4688. const struct drm_crtc_state *state,
  4689. struct drm_property *property,
  4690. uint64_t *val)
  4691. {
  4692. struct sde_crtc *sde_crtc;
  4693. struct sde_crtc_state *cstate;
  4694. int ret = -EINVAL, i;
  4695. if (!crtc || !state) {
  4696. SDE_ERROR("invalid argument(s)\n");
  4697. goto end;
  4698. }
  4699. sde_crtc = to_sde_crtc(crtc);
  4700. cstate = to_sde_crtc_state(state);
  4701. i = msm_property_index(&sde_crtc->property_info, property);
  4702. if (i == CRTC_PROP_OUTPUT_FENCE) {
  4703. *val = ~0;
  4704. ret = 0;
  4705. } else {
  4706. ret = msm_property_atomic_get(&sde_crtc->property_info,
  4707. &cstate->property_state, property, val);
  4708. if (ret)
  4709. ret = sde_cp_crtc_get_property(crtc, property, val);
  4710. }
  4711. if (ret)
  4712. DRM_ERROR("get property failed\n");
  4713. end:
  4714. return ret;
  4715. }
  4716. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  4717. struct drm_crtc_state *crtc_state)
  4718. {
  4719. struct sde_crtc *sde_crtc;
  4720. struct sde_crtc_state *cstate;
  4721. struct drm_property *drm_prop;
  4722. enum msm_mdp_crtc_property prop_idx;
  4723. if (!crtc || !crtc_state) {
  4724. SDE_ERROR("invalid params\n");
  4725. return -EINVAL;
  4726. }
  4727. sde_crtc = to_sde_crtc(crtc);
  4728. cstate = to_sde_crtc_state(crtc_state);
  4729. sde_cp_crtc_clear(crtc);
  4730. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  4731. uint64_t val = cstate->property_values[prop_idx].value;
  4732. uint64_t def;
  4733. int ret;
  4734. drm_prop = msm_property_index_to_drm_property(
  4735. &sde_crtc->property_info, prop_idx);
  4736. if (!drm_prop) {
  4737. /* not all props will be installed, based on caps */
  4738. SDE_DEBUG("%s: invalid property index %d\n",
  4739. sde_crtc->name, prop_idx);
  4740. continue;
  4741. }
  4742. def = msm_property_get_default(&sde_crtc->property_info,
  4743. prop_idx);
  4744. if (val == def)
  4745. continue;
  4746. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  4747. sde_crtc->name, drm_prop->name, prop_idx, val,
  4748. def);
  4749. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  4750. def);
  4751. if (ret) {
  4752. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  4753. sde_crtc->name, prop_idx, ret);
  4754. continue;
  4755. }
  4756. }
  4757. /* disable clk and bw control until clk & bw properties are set */
  4758. cstate->bw_control = false;
  4759. cstate->bw_split_vote = false;
  4760. return 0;
  4761. }
  4762. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  4763. {
  4764. struct sde_crtc *sde_crtc;
  4765. struct sde_crtc_mixer *m;
  4766. int i;
  4767. if (!crtc) {
  4768. SDE_ERROR("invalid argument\n");
  4769. return;
  4770. }
  4771. sde_crtc = to_sde_crtc(crtc);
  4772. if (!sde_crtc->misr_reconfigure)
  4773. return;
  4774. sde_crtc->misr_enable_sui = enable;
  4775. sde_crtc->misr_frame_count = frame_count;
  4776. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4777. m = &sde_crtc->mixers[i];
  4778. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  4779. continue;
  4780. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  4781. }
  4782. sde_crtc->misr_reconfigure = false;
  4783. }
  4784. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  4785. struct sde_crtc_misr_info *crtc_misr_info)
  4786. {
  4787. struct sde_crtc *sde_crtc;
  4788. struct sde_kms *sde_kms;
  4789. if (!crtc_misr_info) {
  4790. SDE_ERROR("invalid misr info\n");
  4791. return;
  4792. }
  4793. crtc_misr_info->misr_enable = false;
  4794. crtc_misr_info->misr_frame_count = 0;
  4795. if (!crtc) {
  4796. SDE_ERROR("invalid crtc\n");
  4797. return;
  4798. }
  4799. sde_kms = _sde_crtc_get_kms(crtc);
  4800. if (!sde_kms) {
  4801. SDE_ERROR("invalid sde_kms\n");
  4802. return;
  4803. }
  4804. if (sde_kms_is_secure_session_inprogress(sde_kms))
  4805. return;
  4806. sde_crtc = to_sde_crtc(crtc);
  4807. crtc_misr_info->misr_enable =
  4808. sde_crtc->misr_enable_debugfs ? true : false;
  4809. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  4810. }
  4811. #ifdef CONFIG_DEBUG_FS
  4812. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  4813. {
  4814. struct sde_crtc *sde_crtc;
  4815. struct sde_plane_state *pstate = NULL;
  4816. struct sde_crtc_mixer *m;
  4817. struct drm_crtc *crtc;
  4818. struct drm_plane *plane;
  4819. struct drm_display_mode *mode;
  4820. struct drm_framebuffer *fb;
  4821. struct drm_plane_state *state;
  4822. struct sde_crtc_state *cstate;
  4823. int i, out_width, out_height;
  4824. if (!s || !s->private)
  4825. return -EINVAL;
  4826. sde_crtc = s->private;
  4827. crtc = &sde_crtc->base;
  4828. cstate = to_sde_crtc_state(crtc->state);
  4829. mutex_lock(&sde_crtc->crtc_lock);
  4830. mode = &crtc->state->adjusted_mode;
  4831. out_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  4832. out_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  4833. seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
  4834. mode->hdisplay, mode->vdisplay);
  4835. seq_puts(s, "\n");
  4836. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4837. m = &sde_crtc->mixers[i];
  4838. if (!m->hw_lm)
  4839. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  4840. else if (!m->hw_ctl)
  4841. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  4842. else
  4843. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  4844. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  4845. out_width, out_height);
  4846. }
  4847. seq_puts(s, "\n");
  4848. for (i = 0; i < cstate->num_dim_layers; i++) {
  4849. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  4850. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  4851. i, dim_layer->stage, dim_layer->flags);
  4852. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  4853. dim_layer->rect.x, dim_layer->rect.y,
  4854. dim_layer->rect.w, dim_layer->rect.h);
  4855. seq_printf(s,
  4856. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  4857. dim_layer->color_fill.color_0,
  4858. dim_layer->color_fill.color_1,
  4859. dim_layer->color_fill.color_2,
  4860. dim_layer->color_fill.color_3);
  4861. seq_puts(s, "\n");
  4862. }
  4863. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4864. pstate = to_sde_plane_state(plane->state);
  4865. state = plane->state;
  4866. if (!pstate || !state)
  4867. continue;
  4868. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  4869. plane->base.id, pstate->stage, pstate->rotation);
  4870. if (plane->state->fb) {
  4871. fb = plane->state->fb;
  4872. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  4873. fb->base.id, (char *) &fb->format->format,
  4874. fb->width, fb->height);
  4875. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  4876. seq_printf(s, "cpp[%d]:%u ",
  4877. i, fb->format->cpp[i]);
  4878. seq_puts(s, "\n\t");
  4879. seq_printf(s, "modifier:%8llu ", fb->modifier);
  4880. seq_puts(s, "\n");
  4881. seq_puts(s, "\t");
  4882. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  4883. seq_printf(s, "pitches[%d]:%8u ", i,
  4884. fb->pitches[i]);
  4885. seq_puts(s, "\n");
  4886. seq_puts(s, "\t");
  4887. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  4888. seq_printf(s, "offsets[%d]:%8u ", i,
  4889. fb->offsets[i]);
  4890. seq_puts(s, "\n");
  4891. }
  4892. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  4893. state->src_x >> 16, state->src_y >> 16,
  4894. state->src_w >> 16, state->src_h >> 16);
  4895. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  4896. state->crtc_x, state->crtc_y, state->crtc_w,
  4897. state->crtc_h);
  4898. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  4899. pstate->multirect_mode, pstate->multirect_index);
  4900. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  4901. pstate->excl_rect.x, pstate->excl_rect.y,
  4902. pstate->excl_rect.w, pstate->excl_rect.h);
  4903. seq_puts(s, "\n");
  4904. }
  4905. if (sde_crtc->vblank_cb_count) {
  4906. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  4907. u32 diff_ms = ktime_to_ms(diff);
  4908. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  4909. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  4910. seq_printf(s,
  4911. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  4912. fps, sde_crtc->vblank_cb_count,
  4913. ktime_to_ms(diff), sde_crtc->play_count);
  4914. /* reset time & count for next measurement */
  4915. sde_crtc->vblank_cb_count = 0;
  4916. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  4917. }
  4918. mutex_unlock(&sde_crtc->crtc_lock);
  4919. return 0;
  4920. }
  4921. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  4922. {
  4923. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  4924. }
  4925. static ssize_t _sde_crtc_misr_setup(struct file *file,
  4926. const char __user *user_buf, size_t count, loff_t *ppos)
  4927. {
  4928. struct drm_crtc *crtc;
  4929. struct sde_crtc *sde_crtc;
  4930. char buf[MISR_BUFF_SIZE + 1];
  4931. u32 frame_count, enable;
  4932. size_t buff_copy;
  4933. struct sde_kms *sde_kms;
  4934. if (!file || !file->private_data)
  4935. return -EINVAL;
  4936. sde_crtc = file->private_data;
  4937. crtc = &sde_crtc->base;
  4938. sde_kms = _sde_crtc_get_kms(crtc);
  4939. if (!sde_kms) {
  4940. SDE_ERROR("invalid sde_kms\n");
  4941. return -EINVAL;
  4942. }
  4943. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  4944. if (copy_from_user(buf, user_buf, buff_copy)) {
  4945. SDE_ERROR("buffer copy failed\n");
  4946. return -EINVAL;
  4947. }
  4948. buf[buff_copy] = 0; /* end of string */
  4949. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  4950. return -EINVAL;
  4951. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4952. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  4953. DRMID(crtc));
  4954. return -EINVAL;
  4955. }
  4956. sde_crtc->misr_enable_debugfs = enable;
  4957. sde_crtc->misr_frame_count = frame_count;
  4958. sde_crtc->misr_reconfigure = true;
  4959. return count;
  4960. }
  4961. static ssize_t _sde_crtc_misr_read(struct file *file,
  4962. char __user *user_buff, size_t count, loff_t *ppos)
  4963. {
  4964. struct drm_crtc *crtc;
  4965. struct sde_crtc *sde_crtc;
  4966. struct sde_kms *sde_kms;
  4967. struct sde_crtc_mixer *m;
  4968. int i = 0, rc;
  4969. ssize_t len = 0;
  4970. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  4971. if (*ppos)
  4972. return 0;
  4973. if (!file || !file->private_data)
  4974. return -EINVAL;
  4975. sde_crtc = file->private_data;
  4976. crtc = &sde_crtc->base;
  4977. sde_kms = _sde_crtc_get_kms(crtc);
  4978. if (!sde_kms)
  4979. return -EINVAL;
  4980. rc = pm_runtime_get_sync(crtc->dev->dev);
  4981. if (rc < 0)
  4982. return rc;
  4983. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4984. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  4985. goto end;
  4986. }
  4987. if (!sde_crtc->misr_enable_debugfs) {
  4988. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4989. "disabled\n");
  4990. goto buff_check;
  4991. }
  4992. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4993. u32 misr_value = 0;
  4994. m = &sde_crtc->mixers[i];
  4995. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  4996. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4997. "invalid\n");
  4998. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  4999. continue;
  5000. }
  5001. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  5002. if (rc) {
  5003. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5004. "invalid\n");
  5005. SDE_ERROR("crtc:%d failed to collect misr %d\n",
  5006. DRMID(crtc), rc);
  5007. continue;
  5008. } else {
  5009. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5010. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  5011. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5012. "0x%x\n", misr_value);
  5013. }
  5014. }
  5015. buff_check:
  5016. if (count <= len) {
  5017. len = 0;
  5018. goto end;
  5019. }
  5020. if (copy_to_user(user_buff, buf, len)) {
  5021. len = -EFAULT;
  5022. goto end;
  5023. }
  5024. *ppos += len; /* increase offset */
  5025. end:
  5026. pm_runtime_put_sync(crtc->dev->dev);
  5027. return len;
  5028. }
  5029. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  5030. static int __prefix ## _open(struct inode *inode, struct file *file) \
  5031. { \
  5032. return single_open(file, __prefix ## _show, inode->i_private); \
  5033. } \
  5034. static const struct file_operations __prefix ## _fops = { \
  5035. .owner = THIS_MODULE, \
  5036. .open = __prefix ## _open, \
  5037. .release = single_release, \
  5038. .read = seq_read, \
  5039. .llseek = seq_lseek, \
  5040. }
  5041. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  5042. {
  5043. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  5044. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  5045. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  5046. int i;
  5047. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  5048. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  5049. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  5050. crtc->state));
  5051. seq_printf(s, "core_clk_rate: %llu\n",
  5052. sde_crtc->cur_perf.core_clk_rate);
  5053. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  5054. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  5055. seq_printf(s, "bw_ctl[%s]: %llu\n",
  5056. sde_power_handle_get_dbus_name(i),
  5057. sde_crtc->cur_perf.bw_ctl[i]);
  5058. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  5059. sde_power_handle_get_dbus_name(i),
  5060. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  5061. }
  5062. return 0;
  5063. }
  5064. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  5065. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  5066. {
  5067. struct drm_crtc *crtc;
  5068. struct drm_plane *plane;
  5069. struct drm_connector *conn;
  5070. struct drm_mode_object *drm_obj;
  5071. struct sde_crtc *sde_crtc;
  5072. struct sde_crtc_state *cstate;
  5073. struct sde_fence_context *ctx;
  5074. struct drm_connector_list_iter conn_iter;
  5075. struct drm_device *dev;
  5076. if (!s || !s->private)
  5077. return -EINVAL;
  5078. sde_crtc = s->private;
  5079. crtc = &sde_crtc->base;
  5080. dev = crtc->dev;
  5081. cstate = to_sde_crtc_state(crtc->state);
  5082. /* Dump input fence info */
  5083. seq_puts(s, "===Input fence===\n");
  5084. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5085. struct sde_plane_state *pstate;
  5086. struct dma_fence *fence;
  5087. pstate = to_sde_plane_state(plane->state);
  5088. if (!pstate)
  5089. continue;
  5090. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  5091. pstate->stage);
  5092. fence = pstate->input_fence;
  5093. if (fence)
  5094. sde_fence_list_dump(fence, &s);
  5095. }
  5096. /* Dump release fence info */
  5097. seq_puts(s, "\n");
  5098. seq_puts(s, "===Release fence===\n");
  5099. ctx = sde_crtc->output_fence;
  5100. drm_obj = &crtc->base;
  5101. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  5102. seq_puts(s, "\n");
  5103. /* Dump retire fence info */
  5104. seq_puts(s, "===Retire fence===\n");
  5105. drm_connector_list_iter_begin(dev, &conn_iter);
  5106. drm_for_each_connector_iter(conn, &conn_iter)
  5107. if (conn->state && conn->state->crtc == crtc &&
  5108. cstate->num_connectors < MAX_CONNECTORS) {
  5109. struct sde_connector *c_conn;
  5110. c_conn = to_sde_connector(conn);
  5111. ctx = c_conn->retire_fence;
  5112. drm_obj = &conn->base;
  5113. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  5114. }
  5115. drm_connector_list_iter_end(&conn_iter);
  5116. seq_puts(s, "\n");
  5117. return 0;
  5118. }
  5119. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  5120. {
  5121. return single_open(file, _sde_debugfs_fence_status_show,
  5122. inode->i_private);
  5123. }
  5124. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5125. {
  5126. struct sde_crtc *sde_crtc;
  5127. struct sde_kms *sde_kms;
  5128. static const struct file_operations debugfs_status_fops = {
  5129. .open = _sde_debugfs_status_open,
  5130. .read = seq_read,
  5131. .llseek = seq_lseek,
  5132. .release = single_release,
  5133. };
  5134. static const struct file_operations debugfs_misr_fops = {
  5135. .open = simple_open,
  5136. .read = _sde_crtc_misr_read,
  5137. .write = _sde_crtc_misr_setup,
  5138. };
  5139. static const struct file_operations debugfs_fps_fops = {
  5140. .open = _sde_debugfs_fps_status,
  5141. .read = seq_read,
  5142. };
  5143. static const struct file_operations debugfs_fence_fops = {
  5144. .open = _sde_debugfs_fence_status,
  5145. .read = seq_read,
  5146. };
  5147. if (!crtc)
  5148. return -EINVAL;
  5149. sde_crtc = to_sde_crtc(crtc);
  5150. sde_kms = _sde_crtc_get_kms(crtc);
  5151. if (!sde_kms)
  5152. return -EINVAL;
  5153. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  5154. crtc->dev->primary->debugfs_root);
  5155. if (!sde_crtc->debugfs_root)
  5156. return -ENOMEM;
  5157. /* don't error check these */
  5158. debugfs_create_file("status", 0400,
  5159. sde_crtc->debugfs_root,
  5160. sde_crtc, &debugfs_status_fops);
  5161. debugfs_create_file("state", 0400,
  5162. sde_crtc->debugfs_root,
  5163. &sde_crtc->base,
  5164. &sde_crtc_debugfs_state_fops);
  5165. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  5166. sde_crtc, &debugfs_misr_fops);
  5167. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  5168. sde_crtc, &debugfs_fps_fops);
  5169. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  5170. sde_crtc, &debugfs_fence_fops);
  5171. return 0;
  5172. }
  5173. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5174. {
  5175. struct sde_crtc *sde_crtc;
  5176. if (!crtc)
  5177. return;
  5178. sde_crtc = to_sde_crtc(crtc);
  5179. debugfs_remove_recursive(sde_crtc->debugfs_root);
  5180. }
  5181. #else
  5182. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5183. {
  5184. return 0;
  5185. }
  5186. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5187. {
  5188. }
  5189. #endif /* CONFIG_DEBUG_FS */
  5190. static int sde_crtc_late_register(struct drm_crtc *crtc)
  5191. {
  5192. return _sde_crtc_init_debugfs(crtc);
  5193. }
  5194. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  5195. {
  5196. _sde_crtc_destroy_debugfs(crtc);
  5197. }
  5198. static const struct drm_crtc_funcs sde_crtc_funcs = {
  5199. .set_config = drm_atomic_helper_set_config,
  5200. .destroy = sde_crtc_destroy,
  5201. .page_flip = drm_atomic_helper_page_flip,
  5202. .atomic_set_property = sde_crtc_atomic_set_property,
  5203. .atomic_get_property = sde_crtc_atomic_get_property,
  5204. .reset = sde_crtc_reset,
  5205. .atomic_duplicate_state = sde_crtc_duplicate_state,
  5206. .atomic_destroy_state = sde_crtc_destroy_state,
  5207. .late_register = sde_crtc_late_register,
  5208. .early_unregister = sde_crtc_early_unregister,
  5209. };
  5210. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  5211. .mode_fixup = sde_crtc_mode_fixup,
  5212. .disable = sde_crtc_disable,
  5213. .atomic_enable = sde_crtc_enable,
  5214. .atomic_check = sde_crtc_atomic_check,
  5215. .atomic_begin = sde_crtc_atomic_begin,
  5216. .atomic_flush = sde_crtc_atomic_flush,
  5217. };
  5218. static void _sde_crtc_event_cb(struct kthread_work *work)
  5219. {
  5220. struct sde_crtc_event *event;
  5221. struct sde_crtc *sde_crtc;
  5222. unsigned long irq_flags;
  5223. if (!work) {
  5224. SDE_ERROR("invalid work item\n");
  5225. return;
  5226. }
  5227. event = container_of(work, struct sde_crtc_event, kt_work);
  5228. /* set sde_crtc to NULL for static work structures */
  5229. sde_crtc = event->sde_crtc;
  5230. if (!sde_crtc)
  5231. return;
  5232. if (event->cb_func)
  5233. event->cb_func(&sde_crtc->base, event->usr);
  5234. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5235. list_add_tail(&event->list, &sde_crtc->event_free_list);
  5236. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5237. }
  5238. int sde_crtc_event_queue(struct drm_crtc *crtc,
  5239. void (*func)(struct drm_crtc *crtc, void *usr),
  5240. void *usr, bool color_processing_event)
  5241. {
  5242. unsigned long irq_flags;
  5243. struct sde_crtc *sde_crtc;
  5244. struct msm_drm_private *priv;
  5245. struct sde_crtc_event *event = NULL;
  5246. u32 crtc_id;
  5247. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  5248. SDE_ERROR("invalid parameters\n");
  5249. return -EINVAL;
  5250. }
  5251. sde_crtc = to_sde_crtc(crtc);
  5252. priv = crtc->dev->dev_private;
  5253. crtc_id = drm_crtc_index(crtc);
  5254. /*
  5255. * Obtain an event struct from the private cache. This event
  5256. * queue may be called from ISR contexts, so use a private
  5257. * cache to avoid calling any memory allocation functions.
  5258. */
  5259. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5260. if (!list_empty(&sde_crtc->event_free_list)) {
  5261. event = list_first_entry(&sde_crtc->event_free_list,
  5262. struct sde_crtc_event, list);
  5263. list_del_init(&event->list);
  5264. }
  5265. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5266. if (!event)
  5267. return -ENOMEM;
  5268. /* populate event node */
  5269. event->sde_crtc = sde_crtc;
  5270. event->cb_func = func;
  5271. event->usr = usr;
  5272. /* queue new event request */
  5273. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  5274. if (color_processing_event)
  5275. kthread_queue_work(&priv->pp_event_worker,
  5276. &event->kt_work);
  5277. else
  5278. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  5279. &event->kt_work);
  5280. return 0;
  5281. }
  5282. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  5283. {
  5284. int i, rc = 0;
  5285. if (!sde_crtc) {
  5286. SDE_ERROR("invalid crtc\n");
  5287. return -EINVAL;
  5288. }
  5289. spin_lock_init(&sde_crtc->event_lock);
  5290. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  5291. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  5292. list_add_tail(&sde_crtc->event_cache[i].list,
  5293. &sde_crtc->event_free_list);
  5294. return rc;
  5295. }
  5296. void sde_crtc_static_img_control(struct drm_crtc *crtc,
  5297. enum sde_crtc_cache_state state,
  5298. bool is_vidmode)
  5299. {
  5300. struct drm_plane *plane;
  5301. struct sde_crtc *sde_crtc;
  5302. if (!crtc || !crtc->dev)
  5303. return;
  5304. sde_crtc = to_sde_crtc(crtc);
  5305. if (sde_crtc->cache_state == state)
  5306. return;
  5307. switch (state) {
  5308. case CACHE_STATE_NORMAL:
  5309. if (sde_crtc->cache_state == CACHE_STATE_DISABLED
  5310. && !is_vidmode)
  5311. return;
  5312. kthread_cancel_delayed_work_sync(
  5313. &sde_crtc->static_cache_read_work);
  5314. break;
  5315. case CACHE_STATE_PRE_CACHE:
  5316. if (sde_crtc->cache_state != CACHE_STATE_NORMAL)
  5317. return;
  5318. break;
  5319. case CACHE_STATE_FRAME_WRITE:
  5320. if (sde_crtc->cache_state != CACHE_STATE_PRE_CACHE)
  5321. return;
  5322. break;
  5323. case CACHE_STATE_FRAME_READ:
  5324. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5325. return;
  5326. break;
  5327. case CACHE_STATE_DISABLED:
  5328. break;
  5329. default:
  5330. return;
  5331. }
  5332. sde_crtc->cache_state = state;
  5333. drm_atomic_crtc_for_each_plane(plane, crtc)
  5334. sde_plane_static_img_control(plane, state);
  5335. }
  5336. /*
  5337. * __sde_crtc_static_cache_read_work - transition to cache read
  5338. */
  5339. void __sde_crtc_static_cache_read_work(struct kthread_work *work)
  5340. {
  5341. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5342. static_cache_read_work.work);
  5343. struct drm_crtc *crtc;
  5344. struct sde_crtc_mixer *mixer;
  5345. struct sde_hw_ctl *ctl;
  5346. if (!sde_crtc)
  5347. return;
  5348. crtc = &sde_crtc->base;
  5349. mixer = sde_crtc->mixers;
  5350. if (!mixer)
  5351. return;
  5352. ctl = mixer->hw_ctl;
  5353. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE ||
  5354. !ctl->ops.trigger_flush)
  5355. return;
  5356. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_READ, false);
  5357. ctl->ops.trigger_flush(ctl);
  5358. }
  5359. void sde_crtc_static_cache_read_kickoff(struct drm_crtc *crtc)
  5360. {
  5361. struct drm_device *dev;
  5362. struct msm_drm_private *priv;
  5363. struct msm_drm_thread *disp_thread;
  5364. struct sde_crtc *sde_crtc;
  5365. struct sde_crtc_state *cstate;
  5366. u32 msecs_fps = 0;
  5367. if (!crtc)
  5368. return;
  5369. dev = crtc->dev;
  5370. sde_crtc = to_sde_crtc(crtc);
  5371. cstate = to_sde_crtc_state(crtc->state);
  5372. if (!dev || !dev->dev_private || !sde_crtc)
  5373. return;
  5374. priv = dev->dev_private;
  5375. disp_thread = &priv->disp_thread[crtc->index];
  5376. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5377. return;
  5378. msecs_fps = DIV_ROUND_UP((1 * 1000), sde_crtc_get_fps_mode(crtc));
  5379. /* Kickoff transition to read state after next vblank */
  5380. kthread_queue_delayed_work(&disp_thread->worker,
  5381. &sde_crtc->static_cache_read_work,
  5382. msecs_to_jiffies(msecs_fps));
  5383. }
  5384. /*
  5385. * __sde_crtc_idle_notify_work - signal idle timeout to user space
  5386. */
  5387. static void __sde_crtc_idle_notify_work(struct kthread_work *work)
  5388. {
  5389. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5390. idle_notify_work.work);
  5391. struct drm_crtc *crtc;
  5392. struct drm_event event;
  5393. int ret = 0;
  5394. if (!sde_crtc) {
  5395. SDE_ERROR("invalid sde crtc\n");
  5396. } else {
  5397. crtc = &sde_crtc->base;
  5398. event.type = DRM_EVENT_IDLE_NOTIFY;
  5399. event.length = sizeof(u32);
  5400. msm_mode_object_event_notify(&crtc->base, crtc->dev,
  5401. &event, (u8 *)&ret);
  5402. SDE_EVT32(DRMID(crtc));
  5403. SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id);
  5404. sde_crtc_static_img_control(crtc, CACHE_STATE_PRE_CACHE, false);
  5405. }
  5406. }
  5407. /* initialize crtc */
  5408. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  5409. {
  5410. struct drm_crtc *crtc = NULL;
  5411. struct sde_crtc *sde_crtc = NULL;
  5412. struct msm_drm_private *priv = NULL;
  5413. struct sde_kms *kms = NULL;
  5414. int i, rc;
  5415. priv = dev->dev_private;
  5416. kms = to_sde_kms(priv->kms);
  5417. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  5418. if (!sde_crtc)
  5419. return ERR_PTR(-ENOMEM);
  5420. crtc = &sde_crtc->base;
  5421. crtc->dev = dev;
  5422. mutex_init(&sde_crtc->crtc_lock);
  5423. spin_lock_init(&sde_crtc->spin_lock);
  5424. atomic_set(&sde_crtc->frame_pending, 0);
  5425. sde_crtc->enabled = false;
  5426. /* Below parameters are for fps calculation for sysfs node */
  5427. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  5428. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  5429. sizeof(ktime_t), GFP_KERNEL);
  5430. if (!sde_crtc->fps_info.time_buf)
  5431. SDE_ERROR("invalid buffer\n");
  5432. else
  5433. memset(sde_crtc->fps_info.time_buf, 0,
  5434. sizeof(*(sde_crtc->fps_info.time_buf)));
  5435. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  5436. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  5437. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  5438. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  5439. list_add(&sde_crtc->frame_events[i].list,
  5440. &sde_crtc->frame_event_list);
  5441. kthread_init_work(&sde_crtc->frame_events[i].work,
  5442. sde_crtc_frame_event_work);
  5443. }
  5444. drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs,
  5445. NULL);
  5446. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  5447. /* save user friendly CRTC name for later */
  5448. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  5449. /* initialize event handling */
  5450. rc = _sde_crtc_init_events(sde_crtc);
  5451. if (rc) {
  5452. drm_crtc_cleanup(crtc);
  5453. kfree(sde_crtc);
  5454. return ERR_PTR(rc);
  5455. }
  5456. /* initialize output fence support */
  5457. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  5458. if (IS_ERR(sde_crtc->output_fence)) {
  5459. rc = PTR_ERR(sde_crtc->output_fence);
  5460. SDE_ERROR("failed to init fence, %d\n", rc);
  5461. drm_crtc_cleanup(crtc);
  5462. kfree(sde_crtc);
  5463. return ERR_PTR(rc);
  5464. }
  5465. /* create CRTC properties */
  5466. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  5467. priv->crtc_property, sde_crtc->property_data,
  5468. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  5469. sizeof(struct sde_crtc_state));
  5470. sde_crtc_install_properties(crtc, kms->catalog);
  5471. /* Install color processing properties */
  5472. sde_cp_crtc_init(crtc);
  5473. sde_cp_crtc_install_properties(crtc);
  5474. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  5475. sde_crtc->cur_perf.llcc_active[i] = false;
  5476. sde_crtc->new_perf.llcc_active[i] = false;
  5477. }
  5478. kthread_init_delayed_work(&sde_crtc->idle_notify_work,
  5479. __sde_crtc_idle_notify_work);
  5480. kthread_init_delayed_work(&sde_crtc->static_cache_read_work,
  5481. __sde_crtc_static_cache_read_work);
  5482. SDE_DEBUG("crtc=%d new_llcc=%d, old_llcc=%d\n",
  5483. crtc->base.id,
  5484. sde_crtc->new_perf.llcc_active,
  5485. sde_crtc->cur_perf.llcc_active);
  5486. SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
  5487. return crtc;
  5488. }
  5489. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  5490. {
  5491. struct sde_crtc *sde_crtc;
  5492. int rc = 0;
  5493. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  5494. SDE_ERROR("invalid input param(s)\n");
  5495. rc = -EINVAL;
  5496. goto end;
  5497. }
  5498. sde_crtc = to_sde_crtc(crtc);
  5499. sde_crtc->sysfs_dev = device_create_with_groups(
  5500. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  5501. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  5502. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  5503. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  5504. PTR_ERR(sde_crtc->sysfs_dev));
  5505. if (!sde_crtc->sysfs_dev)
  5506. rc = -EINVAL;
  5507. else
  5508. rc = PTR_ERR(sde_crtc->sysfs_dev);
  5509. goto end;
  5510. }
  5511. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  5512. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  5513. if (!sde_crtc->vsync_event_sf)
  5514. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  5515. crtc->base.id);
  5516. end:
  5517. return rc;
  5518. }
  5519. static int _sde_crtc_event_enable(struct sde_kms *kms,
  5520. struct drm_crtc *crtc_drm, u32 event)
  5521. {
  5522. struct sde_crtc *crtc = NULL;
  5523. struct sde_crtc_irq_info *node;
  5524. unsigned long flags;
  5525. bool found = false;
  5526. int ret, i = 0;
  5527. bool add_event = false;
  5528. crtc = to_sde_crtc(crtc_drm);
  5529. spin_lock_irqsave(&crtc->spin_lock, flags);
  5530. list_for_each_entry(node, &crtc->user_event_list, list) {
  5531. if (node->event == event) {
  5532. found = true;
  5533. break;
  5534. }
  5535. }
  5536. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5537. /* event already enabled */
  5538. if (found)
  5539. return 0;
  5540. node = NULL;
  5541. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  5542. if (custom_events[i].event == event &&
  5543. custom_events[i].func) {
  5544. node = kzalloc(sizeof(*node), GFP_KERNEL);
  5545. if (!node)
  5546. return -ENOMEM;
  5547. INIT_LIST_HEAD(&node->list);
  5548. INIT_LIST_HEAD(&node->irq.list);
  5549. node->func = custom_events[i].func;
  5550. node->event = event;
  5551. node->state = IRQ_NOINIT;
  5552. spin_lock_init(&node->state_lock);
  5553. break;
  5554. }
  5555. }
  5556. if (!node) {
  5557. SDE_ERROR("unsupported event %x\n", event);
  5558. return -EINVAL;
  5559. }
  5560. ret = 0;
  5561. if (crtc_drm->enabled) {
  5562. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5563. if (ret < 0) {
  5564. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5565. kfree(node);
  5566. return ret;
  5567. }
  5568. INIT_LIST_HEAD(&node->irq.list);
  5569. mutex_lock(&crtc->crtc_lock);
  5570. ret = node->func(crtc_drm, true, &node->irq);
  5571. if (!ret) {
  5572. spin_lock_irqsave(&crtc->spin_lock, flags);
  5573. list_add_tail(&node->list, &crtc->user_event_list);
  5574. add_event = true;
  5575. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5576. }
  5577. mutex_unlock(&crtc->crtc_lock);
  5578. pm_runtime_put_sync(crtc_drm->dev->dev);
  5579. }
  5580. if (add_event)
  5581. return 0;
  5582. if (!ret) {
  5583. spin_lock_irqsave(&crtc->spin_lock, flags);
  5584. list_add_tail(&node->list, &crtc->user_event_list);
  5585. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5586. } else {
  5587. kfree(node);
  5588. }
  5589. return ret;
  5590. }
  5591. static int _sde_crtc_event_disable(struct sde_kms *kms,
  5592. struct drm_crtc *crtc_drm, u32 event)
  5593. {
  5594. struct sde_crtc *crtc = NULL;
  5595. struct sde_crtc_irq_info *node = NULL;
  5596. unsigned long flags;
  5597. bool found = false;
  5598. int ret;
  5599. crtc = to_sde_crtc(crtc_drm);
  5600. spin_lock_irqsave(&crtc->spin_lock, flags);
  5601. list_for_each_entry(node, &crtc->user_event_list, list) {
  5602. if (node->event == event) {
  5603. list_del_init(&node->list);
  5604. found = true;
  5605. break;
  5606. }
  5607. }
  5608. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5609. /* event already disabled */
  5610. if (!found)
  5611. return 0;
  5612. /**
  5613. * crtc is disabled interrupts are cleared remove from the list,
  5614. * no need to disable/de-register.
  5615. */
  5616. if (!crtc_drm->enabled) {
  5617. kfree(node);
  5618. return 0;
  5619. }
  5620. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5621. if (ret < 0) {
  5622. SDE_ERROR("failed to enable power resource %d\n", ret);
  5623. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5624. kfree(node);
  5625. return ret;
  5626. }
  5627. ret = node->func(crtc_drm, false, &node->irq);
  5628. if (ret) {
  5629. spin_lock_irqsave(&crtc->spin_lock, flags);
  5630. list_add_tail(&node->list, &crtc->user_event_list);
  5631. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5632. } else {
  5633. kfree(node);
  5634. }
  5635. pm_runtime_put_sync(crtc_drm->dev->dev);
  5636. return ret;
  5637. }
  5638. int sde_crtc_register_custom_event(struct sde_kms *kms,
  5639. struct drm_crtc *crtc_drm, u32 event, bool en)
  5640. {
  5641. struct sde_crtc *crtc = NULL;
  5642. int ret;
  5643. crtc = to_sde_crtc(crtc_drm);
  5644. if (!crtc || !kms || !kms->dev) {
  5645. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  5646. kms, ((kms) ? (kms->dev) : NULL));
  5647. return -EINVAL;
  5648. }
  5649. if (en)
  5650. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  5651. else
  5652. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  5653. return ret;
  5654. }
  5655. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  5656. bool en, struct sde_irq_callback *irq)
  5657. {
  5658. return 0;
  5659. }
  5660. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  5661. struct sde_irq_callback *noirq)
  5662. {
  5663. /*
  5664. * IRQ object noirq is not being used here since there is
  5665. * no crtc irq from pm event.
  5666. */
  5667. return 0;
  5668. }
  5669. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  5670. bool en, struct sde_irq_callback *irq)
  5671. {
  5672. return 0;
  5673. }
  5674. /**
  5675. * sde_crtc_update_cont_splash_settings - update mixer settings
  5676. * and initial clk during device bootup for cont_splash use case
  5677. * @crtc: Pointer to drm crtc structure
  5678. */
  5679. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  5680. {
  5681. struct sde_kms *kms = NULL;
  5682. struct msm_drm_private *priv;
  5683. struct sde_crtc *sde_crtc;
  5684. u64 rate;
  5685. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  5686. SDE_ERROR("invalid crtc\n");
  5687. return;
  5688. }
  5689. priv = crtc->dev->dev_private;
  5690. kms = to_sde_kms(priv->kms);
  5691. if (!kms || !kms->catalog) {
  5692. SDE_ERROR("invalid parameters\n");
  5693. return;
  5694. }
  5695. _sde_crtc_setup_mixers(crtc);
  5696. crtc->enabled = true;
  5697. /* update core clk value for initial state with cont-splash */
  5698. sde_crtc = to_sde_crtc(crtc);
  5699. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  5700. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  5701. rate : kms->perf.max_core_clk_rate;
  5702. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  5703. }