This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
424 rader
10 KiB
C
424 rader
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/regulator/consumer.h>
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#include <linux/delay.h>
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#include "sde_rotator_io_util.h"
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void sde_reg_w(struct sde_io_data *io, u32 offset, u32 value, u32 debug)
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{
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u32 in_val;
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if (!io || !io->base) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return;
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}
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if (offset > io->len) {
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DEV_ERR("%pS->%s: offset out of range\n",
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__builtin_return_address(0), __func__);
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return;
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}
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DEV_DBG("sdeio:%6.6x:%8.8x\n", offset, value);
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writel_relaxed(value, io->base + offset);
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if (debug) {
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/* ensure register read is ordered after register write */
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mb();
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in_val = readl_relaxed(io->base + offset);
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DEV_DBG("[%08x] => %08x [%08x]\n",
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(u32)(unsigned long)(io->base + offset),
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value, in_val);
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}
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} /* sde_reg_w */
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u32 sde_reg_r(struct sde_io_data *io, u32 offset, u32 debug)
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{
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u32 value;
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if (!io || !io->base) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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if (offset > io->len) {
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DEV_ERR("%pS->%s: offset out of range\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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value = readl_relaxed(io->base + offset);
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if (debug)
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DEV_DBG("[%08x] <= %08x\n",
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(u32)(unsigned long)(io->base + offset), value);
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DEV_DBG("sdeio:%6.6x:%8.8x\n", offset, value);
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return value;
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} /* sde_reg_r */
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void sde_reg_dump(void __iomem *base, u32 length, const char *prefix,
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u32 debug)
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{
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if (debug)
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print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
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(void *)base, length, false);
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} /* sde_reg_dump */
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static struct resource *sde_rot_get_res_byname(struct platform_device *pdev,
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unsigned int type, const char *name)
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{
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struct resource *res = NULL;
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res = platform_get_resource_byname(pdev, type, name);
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if (!res)
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DEV_ERR("%s: '%s' resource not found\n", __func__, name);
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return res;
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} /* sde_rot_get_res_byname */
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int sde_rot_ioremap_byname(struct platform_device *pdev,
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struct sde_io_data *io_data, const char *name)
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{
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struct resource *res = NULL;
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if (!pdev || !io_data) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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res = sde_rot_get_res_byname(pdev, IORESOURCE_MEM, name);
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if (!res) {
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DEV_ERR("%pS->%s: '%s' sde_rot_get_res_byname failed\n",
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__builtin_return_address(0), __func__, name);
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return -ENODEV;
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}
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io_data->len = (u32)resource_size(res);
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io_data->base = ioremap(res->start, io_data->len);
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if (!io_data->base) {
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DEV_ERR("%pS->%s: '%s' ioremap failed\n",
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__builtin_return_address(0), __func__, name);
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return -EIO;
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}
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return 0;
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} /* sde_rot_ioremap_byname */
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void sde_rot_iounmap(struct sde_io_data *io_data)
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{
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if (!io_data) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return;
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}
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if (io_data->base) {
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iounmap(io_data->base);
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io_data->base = NULL;
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}
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io_data->len = 0;
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} /* sde_rot_iounmap */
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int sde_rot_config_vreg(struct device *dev, struct sde_vreg *in_vreg,
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int num_vreg, int config)
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{
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int i = 0, rc = 0;
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struct sde_vreg *curr_vreg = NULL;
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enum sde_vreg_type type;
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if (!dev || !in_vreg || !num_vreg) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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if (config) {
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for (i = 0; i < num_vreg; i++) {
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curr_vreg = &in_vreg[i];
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curr_vreg->vreg = regulator_get(dev,
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curr_vreg->vreg_name);
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rc = PTR_RET(curr_vreg->vreg);
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if (rc) {
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DEV_ERR("%pS->%s: %s get failed. rc=%d\n",
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__builtin_return_address(0), __func__,
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curr_vreg->vreg_name, rc);
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curr_vreg->vreg = NULL;
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goto vreg_get_fail;
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}
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type = (regulator_count_voltages(curr_vreg->vreg) > 0)
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? SDE_REG_LDO : SDE_REG_VS;
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if (type == SDE_REG_LDO) {
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rc = regulator_set_voltage(
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curr_vreg->vreg,
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curr_vreg->min_voltage,
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curr_vreg->max_voltage);
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if (rc < 0) {
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DEV_ERR("%pS->%s: %s set vltg fail\n",
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__builtin_return_address(0),
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__func__,
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curr_vreg->vreg_name);
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goto vreg_set_voltage_fail;
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}
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}
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}
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} else {
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for (i = num_vreg-1; i >= 0; i--) {
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curr_vreg = &in_vreg[i];
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if (curr_vreg->vreg) {
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type = (regulator_count_voltages(
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curr_vreg->vreg) > 0)
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? SDE_REG_LDO : SDE_REG_VS;
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if (type == SDE_REG_LDO) {
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regulator_set_voltage(curr_vreg->vreg,
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0, curr_vreg->max_voltage);
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}
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regulator_put(curr_vreg->vreg);
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curr_vreg->vreg = NULL;
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}
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}
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}
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return 0;
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vreg_unconfig:
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if (type == SDE_REG_LDO)
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regulator_set_load(curr_vreg->vreg, 0);
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vreg_set_voltage_fail:
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regulator_put(curr_vreg->vreg);
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curr_vreg->vreg = NULL;
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vreg_get_fail:
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for (i--; i >= 0; i--) {
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curr_vreg = &in_vreg[i];
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type = (regulator_count_voltages(curr_vreg->vreg) > 0)
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? SDE_REG_LDO : SDE_REG_VS;
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goto vreg_unconfig;
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}
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return rc;
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} /* sde_rot_config_vreg */
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int sde_rot_enable_vreg(struct sde_vreg *in_vreg, int num_vreg, int enable)
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{
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int i = 0, rc = 0;
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bool need_sleep;
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if (!in_vreg) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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if (enable) {
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for (i = 0; i < num_vreg; i++) {
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rc = PTR_RET(in_vreg[i].vreg);
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if (rc) {
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DEV_ERR("%pS->%s: %s regulator error. rc=%d\n",
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__builtin_return_address(0), __func__,
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in_vreg[i].vreg_name, rc);
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goto vreg_set_opt_mode_fail;
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}
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need_sleep = !regulator_is_enabled(in_vreg[i].vreg);
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if (in_vreg[i].pre_on_sleep && need_sleep)
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usleep_range(in_vreg[i].pre_on_sleep * 1000,
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in_vreg[i].pre_on_sleep * 1000);
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rc = regulator_set_load(in_vreg[i].vreg,
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in_vreg[i].enable_load);
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if (rc < 0) {
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DEV_ERR("%pS->%s: %s set opt m fail\n",
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__builtin_return_address(0), __func__,
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in_vreg[i].vreg_name);
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goto vreg_set_opt_mode_fail;
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}
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rc = regulator_enable(in_vreg[i].vreg);
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if (in_vreg[i].post_on_sleep && need_sleep)
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usleep_range(in_vreg[i].post_on_sleep * 1000,
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in_vreg[i].post_on_sleep * 1000);
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if (rc < 0) {
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DEV_ERR("%pS->%s: %s enable failed\n",
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__builtin_return_address(0), __func__,
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in_vreg[i].vreg_name);
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goto disable_vreg;
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}
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}
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} else {
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for (i = num_vreg-1; i >= 0; i--) {
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if (in_vreg[i].pre_off_sleep)
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usleep_range(in_vreg[i].pre_off_sleep * 1000,
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in_vreg[i].pre_off_sleep * 1000);
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regulator_set_load(in_vreg[i].vreg,
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in_vreg[i].disable_load);
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regulator_disable(in_vreg[i].vreg);
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if (in_vreg[i].post_off_sleep)
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usleep_range(in_vreg[i].post_off_sleep * 1000,
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in_vreg[i].post_off_sleep * 1000);
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}
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}
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return rc;
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disable_vreg:
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regulator_set_load(in_vreg[i].vreg, in_vreg[i].disable_load);
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vreg_set_opt_mode_fail:
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for (i--; i >= 0; i--) {
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if (in_vreg[i].pre_off_sleep)
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usleep_range(in_vreg[i].pre_off_sleep * 1000,
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in_vreg[i].pre_off_sleep * 1000);
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regulator_set_load(in_vreg[i].vreg,
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in_vreg[i].disable_load);
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regulator_disable(in_vreg[i].vreg);
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if (in_vreg[i].post_off_sleep)
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usleep_range(in_vreg[i].post_off_sleep * 1000,
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in_vreg[i].post_off_sleep * 1000);
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}
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return rc;
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} /* sde_rot_enable_vreg */
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void sde_rot_put_clk(struct sde_clk *clk_arry, int num_clk)
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{
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int i;
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if (!clk_arry) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return;
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}
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for (i = num_clk - 1; i >= 0; i--) {
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if (clk_arry[i].clk)
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clk_put(clk_arry[i].clk);
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clk_arry[i].clk = NULL;
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}
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} /* sde_rot_put_clk */
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int sde_rot_get_clk(struct device *dev, struct sde_clk *clk_arry, int num_clk)
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{
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int i, rc = 0;
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if (!dev || !clk_arry) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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for (i = 0; i < num_clk; i++) {
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clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name);
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rc = PTR_RET(clk_arry[i].clk);
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if (rc) {
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DEV_ERR("%pS->%s: '%s' get failed. rc=%d\n",
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__builtin_return_address(0), __func__,
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clk_arry[i].clk_name, rc);
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goto error;
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}
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}
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return rc;
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error:
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sde_rot_put_clk(clk_arry, num_clk);
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return rc;
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} /* sde_rot_get_clk */
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int sde_rot_clk_set_rate(struct sde_clk *clk_arry, int num_clk)
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{
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int i, rc = 0;
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if (!clk_arry) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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for (i = 0; i < num_clk; i++) {
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if (clk_arry[i].clk) {
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if (clk_arry[i].type != SDE_CLK_AHB) {
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DEV_DBG("%pS->%s: '%s' rate %ld\n",
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__builtin_return_address(0), __func__,
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clk_arry[i].clk_name,
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clk_arry[i].rate);
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rc = clk_set_rate(clk_arry[i].clk,
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clk_arry[i].rate);
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if (rc) {
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DEV_ERR("%pS->%s: %s failed. rc=%d\n",
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__builtin_return_address(0),
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__func__,
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clk_arry[i].clk_name, rc);
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break;
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}
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}
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} else {
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DEV_ERR("%pS->%s: '%s' is not available\n",
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__builtin_return_address(0), __func__,
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clk_arry[i].clk_name);
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rc = -EPERM;
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break;
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}
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}
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return rc;
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} /* sde_rot_clk_set_rate */
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int sde_rot_enable_clk(struct sde_clk *clk_arry, int num_clk, int enable)
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{
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int i, rc = 0;
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if (!clk_arry) {
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DEV_ERR("%pS->%s: invalid input\n",
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__builtin_return_address(0), __func__);
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return -EINVAL;
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}
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if (enable) {
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for (i = 0; i < num_clk; i++) {
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DEV_DBG("%pS->%s: enable '%s'\n",
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__builtin_return_address(0), __func__,
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clk_arry[i].clk_name);
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if (clk_arry[i].clk) {
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rc = clk_prepare_enable(clk_arry[i].clk);
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if (rc)
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DEV_ERR("%pS->%s: %s en fail. rc=%d\n",
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__builtin_return_address(0),
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__func__,
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clk_arry[i].clk_name, rc);
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} else {
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DEV_ERR("%pS->%s: '%s' is not available\n",
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__builtin_return_address(0), __func__,
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clk_arry[i].clk_name);
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rc = -EPERM;
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}
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if (rc) {
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sde_rot_enable_clk(&clk_arry[i],
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i, false);
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break;
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}
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}
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} else {
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for (i = num_clk - 1; i >= 0; i--) {
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DEV_DBG("%pS->%s: disable '%s'\n",
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__builtin_return_address(0), __func__,
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clk_arry[i].clk_name);
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if (clk_arry[i].clk)
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clk_disable_unprepare(clk_arry[i].clk);
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else
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DEV_ERR("%pS->%s: '%s' is not available\n",
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__builtin_return_address(0), __func__,
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clk_arry[i].clk_name);
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}
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}
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return rc;
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} /* sde_rot_enable_clk */
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