wsa884x.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x-registers.h"
  31. #include "wsa884x.h"
  32. #include "internal.h"
  33. #include "asoc/bolero-slave-internal.h"
  34. #include <linux/qti-regmap-debugfs.h>
  35. #define T1_TEMP -10
  36. #define T2_TEMP 150
  37. #define LOW_TEMP_THRESHOLD 5
  38. #define HIGH_TEMP_THRESHOLD 45
  39. #define TEMP_INVALID 0xFFFF
  40. #define WSA884X_TEMP_RETRY 3
  41. #define WSA884X_IRQ_RETRY 2
  42. #define PBR_MAX_VOLTAGE 20
  43. #define PBR_MAX_CODE 255
  44. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  45. #define MAX_NAME_LEN 40
  46. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  47. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  48. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  49. SNDRV_PCM_RATE_384000)
  50. /* Fractional Rates */
  51. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  52. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  53. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  54. SNDRV_PCM_FMTBIT_S24_LE |\
  55. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  56. #define REG_FIELD_VALUE(register_name, field_name, value) \
  57. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  58. value << FIELD_SHIFT(register_name, field_name)
  59. enum {
  60. IDLE_DETECT,
  61. NG1,
  62. NG2,
  63. NG3,
  64. };
  65. struct wsa_temp_register {
  66. u8 d1_msb;
  67. u8 d1_lsb;
  68. u8 d2_msb;
  69. u8 d2_lsb;
  70. u8 dmeas_msb;
  71. u8 dmeas_lsb;
  72. };
  73. enum {
  74. COMP_OFFSET0,
  75. COMP_OFFSET1,
  76. COMP_OFFSET2,
  77. COMP_OFFSET3,
  78. COMP_OFFSET4,
  79. };
  80. #define WSA884X_VTH_TO_REG(vth) \
  81. ((vth) != 0 ? (((vth) - 150) * PBR_MAX_CODE / (PBR_MAX_VOLTAGE * 100) + 1) : 0)
  82. struct wsa_reg_mask_val {
  83. u16 reg;
  84. u8 mask;
  85. u8 val;
  86. };
  87. static const struct wsa_reg_mask_val reg_init[] = {
  88. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  106. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  107. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  108. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  109. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  110. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  111. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  112. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  113. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  114. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  115. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  116. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  117. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  118. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  119. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  120. {REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
  121. {REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
  122. {REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
  123. };
  124. static const struct wsa_reg_mask_val reg_init_2S[] = {
  125. {REG_FIELD_VALUE(CLSH_CTL_1, SLR_MAX, 0x02)},
  126. {REG_FIELD_VALUE(CLSH_V_HD_PA, V_HD_PA, 0x13)},
  127. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_VTH, 0x03)},
  128. {REG_FIELD_VALUE(UVLO_PROG, UVLO1_HYST, 0x03)},
  129. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG2, DAC_VCM_SHIFT, 0x06)},
  130. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG3, DAC_VCM_SHIFT, 0x14)},
  131. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG4, DAC_VCM_SHIFT, 0x19)},
  132. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG5, DAC_VCM_SHIFT, 0x1B)},
  133. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG6, DAC_VCM_SHIFT, 0x1C)},
  134. {REG_FIELD_VALUE(DAC_VCM_CTRL_REG7, DAC_VCM_SHIFT_FINAL_OVERRIDE, 0x01)},
  135. };
  136. static const struct wsa_reg_mask_val reg_init_uvlo[] = {
  137. {WSA884X_UVLO_PROG, 0xFF, 0x77},
  138. {WSA884X_UVLO_DEGLITCH_CTL, 0xFF, 0x1B},
  139. {WSA884X_UVLO_PROG1, 0xFF, 0x40},
  140. };
  141. static int wsa884x_handle_post_irq(void *data);
  142. static int wsa884x_get_temperature(struct snd_soc_component *component,
  143. int *temp);
  144. enum {
  145. WSA8840 = 0,
  146. WSA8845 = 5,
  147. WSA8845H = 0xC,
  148. };
  149. enum {
  150. SPKR_STATUS = 0,
  151. WSA_SUPPLIES_LPM_MODE,
  152. SPKR_ADIE_LB,
  153. };
  154. enum {
  155. COMP_PORT_EN_STATUS_BIT = 0,
  156. VI_PORT_EN_STATUS_BIT,
  157. PBR_PORT_EN_STATUS_BIT,
  158. CPS_PORT_EN_STATUS_BIT,
  159. };
  160. enum {
  161. WSA884X_IRQ_INT_SAF2WAR = 0,
  162. WSA884X_IRQ_INT_WAR2SAF,
  163. WSA884X_IRQ_INT_DISABLE,
  164. WSA884X_IRQ_INT_OCP,
  165. WSA884X_IRQ_INT_CLIP,
  166. WSA884X_IRQ_INT_PDM_WD,
  167. WSA884X_IRQ_INT_CLK_WD,
  168. WSA884X_IRQ_INT_INTR_PIN,
  169. WSA884X_IRQ_INT_UVLO,
  170. WSA884X_IRQ_INT_PA_ON_ERR,
  171. WSA884X_NUM_IRQS,
  172. };
  173. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  174. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  175. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  176. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  177. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  178. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  179. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  180. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  181. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  182. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  183. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  184. };
  185. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  186. .name = "wsa884x",
  187. .irqs = wsa884x_irqs,
  188. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  189. .num_regs = 2,
  190. .status_base = WSA884X_INTR_STATUS0,
  191. .mask_base = WSA884X_INTR_MASK0,
  192. .type_base = WSA884X_INTR_LEVEL0,
  193. .ack_base = WSA884X_INTR_CLEAR0,
  194. .use_ack = 1,
  195. .runtime_pm = false,
  196. .handle_post_irq = wsa884x_handle_post_irq,
  197. .irq_drv_data = NULL,
  198. };
  199. static int wsa884x_handle_post_irq(void *data)
  200. {
  201. struct wsa884x_priv *wsa884x = data;
  202. u32 sts1 = 0, sts2 = 0;
  203. int retry = WSA884X_IRQ_RETRY;
  204. if (!wsa884x)
  205. return IRQ_NONE;
  206. if (!wsa884x->pa_mute) {
  207. do {
  208. wsa884x->pa_mute = 0;
  209. regmap_update_bits(wsa884x->regmap,
  210. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  211. usleep_range(1000, 1100);
  212. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  213. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  214. wsa884x->swr_slave->slave_irq_pending =
  215. ((sts1 || sts2) ? true : false);
  216. pr_debug("%s: IRQs Sts0: %x, Sts1: %x\n", __func__,
  217. sts1, sts2);
  218. if (wsa884x->swr_slave->slave_irq_pending) {
  219. pr_debug("%s: IRQ retries left: %0d\n",
  220. __func__, retry);
  221. regmap_update_bits(wsa884x->regmap,
  222. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  223. wsa884x->pa_mute = 1;
  224. if (retry--)
  225. usleep_range(1000, 1100);
  226. } else {
  227. break;
  228. }
  229. } while (retry);
  230. }
  231. return IRQ_HANDLED;
  232. }
  233. #ifdef CONFIG_DEBUG_FS
  234. static int codec_debug_open(struct inode *inode, struct file *file)
  235. {
  236. file->private_data = inode->i_private;
  237. return 0;
  238. }
  239. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  240. {
  241. char *token;
  242. int base, cnt;
  243. token = strsep(&buf, " ");
  244. for (cnt = 0; cnt < num_of_par; cnt++) {
  245. if (token) {
  246. if ((token[1] == 'x') || (token[1] == 'X'))
  247. base = 16;
  248. else
  249. base = 10;
  250. if (kstrtou32(token, base, &param1[cnt]) != 0)
  251. return -EINVAL;
  252. token = strsep(&buf, " ");
  253. } else {
  254. return -EINVAL;
  255. }
  256. }
  257. return 0;
  258. }
  259. static bool is_swr_slave_reg_readable(int reg)
  260. {
  261. int ret = true;
  262. if (((reg > 0x46) && (reg < 0x4A)) ||
  263. ((reg > 0x4A) && (reg < 0x50)) ||
  264. ((reg > 0x55) && (reg < 0x60)) ||
  265. ((reg > 0x60) && (reg < 0x70)) ||
  266. ((reg > 0x70) && (reg < 0xC0)) ||
  267. ((reg > 0xC1) && (reg < 0xC8)) ||
  268. ((reg > 0xC8) && (reg < 0xD0)) ||
  269. ((reg > 0xD0) && (reg < 0xE0)) ||
  270. ((reg > 0xE0) && (reg < 0xF0)) ||
  271. ((reg > 0xF0) && (reg < 0x100)) ||
  272. ((reg > 0x105) && (reg < 0x120)) ||
  273. ((reg > 0x205) && (reg < 0x220)) ||
  274. ((reg > 0x305) && (reg < 0x320)) ||
  275. ((reg > 0x405) && (reg < 0x420)) ||
  276. ((reg > 0x505) && (reg < 0x520)) ||
  277. ((reg > 0x605) && (reg < 0x620)) ||
  278. ((reg > 0x127) && (reg < 0x130)) ||
  279. ((reg > 0x227) && (reg < 0x230)) ||
  280. ((reg > 0x327) && (reg < 0x330)) ||
  281. ((reg > 0x427) && (reg < 0x430)) ||
  282. ((reg > 0x527) && (reg < 0x530)) ||
  283. ((reg > 0x627) && (reg < 0x630)) ||
  284. ((reg > 0x137) && (reg < 0x200)) ||
  285. ((reg > 0x237) && (reg < 0x300)) ||
  286. ((reg > 0x337) && (reg < 0x400)) ||
  287. ((reg > 0x437) && (reg < 0x500)) ||
  288. ((reg > 0x537) && (reg < 0x600)) ||
  289. ((reg > 0x637) && (reg < 0xF00)) ||
  290. ((reg > 0xF05) && (reg < 0xF20)) ||
  291. ((reg > 0xF25) && (reg < 0xF30)) ||
  292. ((reg > 0xF35) && (reg < 0x2000)))
  293. ret = false;
  294. return ret;
  295. }
  296. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  297. size_t count, loff_t *ppos)
  298. {
  299. int i, reg_val, len;
  300. ssize_t total = 0;
  301. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  302. if (!ubuf || !ppos)
  303. return 0;
  304. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  305. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  306. if (!is_swr_slave_reg_readable(i))
  307. continue;
  308. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  309. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  310. (reg_val & 0xFF));
  311. if (len < 0) {
  312. pr_err_ratelimited("%s: fail to fill the buffer\n", __func__);
  313. total = -EFAULT;
  314. goto copy_err;
  315. }
  316. if ((total + len) >= count - 1)
  317. break;
  318. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  319. pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
  320. total = -EFAULT;
  321. goto copy_err;
  322. }
  323. total += len;
  324. *ppos += len;
  325. }
  326. copy_err:
  327. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  328. return total;
  329. }
  330. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  331. size_t count, loff_t *ppos)
  332. {
  333. struct swr_device *pdev;
  334. if (!count || !file || !ppos || !ubuf)
  335. return -EINVAL;
  336. pdev = file->private_data;
  337. if (!pdev)
  338. return -EINVAL;
  339. if (*ppos < 0)
  340. return -EINVAL;
  341. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  342. }
  343. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  344. size_t count, loff_t *ppos)
  345. {
  346. char lbuf[SWR_SLV_RD_BUF_LEN];
  347. struct swr_device *pdev = NULL;
  348. struct wsa884x_priv *wsa884x = NULL;
  349. if (!count || !file || !ppos || !ubuf)
  350. return -EINVAL;
  351. pdev = file->private_data;
  352. if (!pdev)
  353. return -EINVAL;
  354. wsa884x = swr_get_dev_data(pdev);
  355. if (!wsa884x)
  356. return -EINVAL;
  357. if (*ppos < 0)
  358. return -EINVAL;
  359. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  360. (wsa884x->read_data & 0xFF));
  361. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  362. strnlen(lbuf, 7));
  363. }
  364. static ssize_t codec_debug_peek_write(struct file *file,
  365. const char __user *ubuf, size_t cnt, loff_t *ppos)
  366. {
  367. char lbuf[SWR_SLV_WR_BUF_LEN];
  368. int rc = 0;
  369. u32 param[5];
  370. struct swr_device *pdev = NULL;
  371. struct wsa884x_priv *wsa884x = NULL;
  372. if (!cnt || !file || !ppos || !ubuf)
  373. return -EINVAL;
  374. pdev = file->private_data;
  375. if (!pdev)
  376. return -EINVAL;
  377. wsa884x = swr_get_dev_data(pdev);
  378. if (!wsa884x)
  379. return -EINVAL;
  380. if (*ppos < 0)
  381. return -EINVAL;
  382. if (cnt > sizeof(lbuf) - 1)
  383. return -EINVAL;
  384. rc = copy_from_user(lbuf, ubuf, cnt);
  385. if (rc)
  386. return -EFAULT;
  387. lbuf[cnt] = '\0';
  388. rc = get_parameters(lbuf, param, 1);
  389. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  390. return -EINVAL;
  391. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  392. if (rc == 0)
  393. rc = cnt;
  394. else
  395. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  396. return rc;
  397. }
  398. static ssize_t codec_debug_write(struct file *file,
  399. const char __user *ubuf, size_t cnt, loff_t *ppos)
  400. {
  401. char lbuf[SWR_SLV_WR_BUF_LEN];
  402. int rc = 0;
  403. u32 param[5];
  404. struct swr_device *pdev;
  405. if (!file || !ppos || !ubuf)
  406. return -EINVAL;
  407. pdev = file->private_data;
  408. if (!pdev)
  409. return -EINVAL;
  410. if (cnt > sizeof(lbuf) - 1)
  411. return -EINVAL;
  412. rc = copy_from_user(lbuf, ubuf, cnt);
  413. if (rc)
  414. return -EFAULT;
  415. lbuf[cnt] = '\0';
  416. rc = get_parameters(lbuf, param, 2);
  417. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  418. (param[1] <= 0xFF) && (rc == 0)))
  419. return -EINVAL;
  420. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  421. if (rc == 0)
  422. rc = cnt;
  423. else
  424. pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
  425. return rc;
  426. }
  427. static const struct file_operations codec_debug_write_ops = {
  428. .open = codec_debug_open,
  429. .write = codec_debug_write,
  430. };
  431. static const struct file_operations codec_debug_read_ops = {
  432. .open = codec_debug_open,
  433. .read = codec_debug_read,
  434. .write = codec_debug_peek_write,
  435. };
  436. static const struct file_operations codec_debug_dump_ops = {
  437. .open = codec_debug_open,
  438. .read = codec_debug_dump,
  439. };
  440. #endif
  441. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  442. {
  443. mutex_lock(&wsa884x->res_lock);
  444. regcache_mark_dirty(wsa884x->regmap);
  445. regcache_sync(wsa884x->regmap);
  446. mutex_unlock(&wsa884x->res_lock);
  447. }
  448. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  449. {
  450. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  451. __func__, irq);
  452. return IRQ_HANDLED;
  453. }
  454. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  455. {
  456. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  457. __func__, irq);
  458. return IRQ_HANDLED;
  459. }
  460. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  461. {
  462. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  463. __func__, irq);
  464. return IRQ_HANDLED;
  465. }
  466. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  467. {
  468. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  469. __func__, irq);
  470. return IRQ_HANDLED;
  471. }
  472. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  473. {
  474. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  475. __func__, irq);
  476. return IRQ_HANDLED;
  477. }
  478. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  479. {
  480. struct wsa884x_priv *wsa884x = data;
  481. struct snd_soc_component *component = NULL;
  482. if (!wsa884x)
  483. return IRQ_NONE;
  484. component = wsa884x->component;
  485. snd_soc_component_update_bits(component,
  486. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  487. snd_soc_component_update_bits(component,
  488. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  489. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  490. __func__, irq);
  491. return IRQ_HANDLED;
  492. }
  493. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  494. {
  495. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  496. __func__, irq);
  497. return IRQ_HANDLED;
  498. }
  499. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  500. {
  501. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  502. __func__, irq);
  503. return IRQ_HANDLED;
  504. }
  505. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  506. {
  507. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  508. __func__, irq);
  509. return IRQ_HANDLED;
  510. }
  511. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  512. {
  513. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  514. struct wsa884x_priv *wsa884x = data;
  515. struct snd_soc_component *component = NULL;
  516. if (!wsa884x)
  517. return IRQ_NONE;
  518. component = wsa884x->component;
  519. if (!component)
  520. return IRQ_NONE;
  521. snd_soc_component_update_bits(component,
  522. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  523. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  524. & 0x1F);
  525. if (pa_fsm_sta)
  526. pa_fsm_err = snd_soc_component_read(component,
  527. WSA884X_PA_FSM_ERR_COND0);
  528. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  529. __func__, irq);
  530. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  531. 0x10, 0x00);
  532. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  533. 0x10, 0x10);
  534. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  535. 0x10, 0x00);
  536. return IRQ_HANDLED;
  537. }
  538. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  539. {
  540. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  541. u8 igain;
  542. u8 vgain;
  543. switch (wsa884x->bat_cfg) {
  544. case CONFIG_1S:
  545. case EXT_1S:
  546. switch (wsa884x->system_gain) {
  547. case G_21_DB:
  548. wsa884x->comp_offset = COMP_OFFSET0;
  549. wsa884x->min_gain = G_0_DB;
  550. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  551. break;
  552. case G_19P5_DB:
  553. wsa884x->comp_offset = COMP_OFFSET1;
  554. wsa884x->min_gain = G_M1P5_DB;
  555. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  556. break;
  557. case G_18_DB:
  558. wsa884x->comp_offset = COMP_OFFSET2;
  559. wsa884x->min_gain = G_M3_DB;
  560. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  561. break;
  562. case G_16P5_DB:
  563. wsa884x->comp_offset = COMP_OFFSET3;
  564. wsa884x->min_gain = G_M4P5_DB;
  565. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  566. break;
  567. default:
  568. wsa884x->comp_offset = COMP_OFFSET4;
  569. wsa884x->min_gain = G_M6_DB;
  570. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  571. break;
  572. }
  573. break;
  574. case CONFIG_3S:
  575. case EXT_3S:
  576. wsa884x->comp_offset = COMP_OFFSET0;
  577. wsa884x->min_gain = G_7P5_DB;
  578. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  579. break;
  580. case EXT_ABOVE_3S:
  581. wsa884x->comp_offset = COMP_OFFSET0;
  582. wsa884x->min_gain = G_12_DB;
  583. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  584. break;
  585. default:
  586. wsa884x->comp_offset = COMP_OFFSET0;
  587. wsa884x->min_gain = G_0_DB;
  588. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  589. break;
  590. }
  591. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  592. vgain = vsense_gain_data[wsa884x->system_gain];
  593. snd_soc_component_update_bits(component,
  594. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  595. snd_soc_component_update_bits(component,
  596. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  597. snd_soc_component_update_bits(component,
  598. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  599. if (wsa884x->comp_enable) {
  600. snd_soc_component_update_bits(component,
  601. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  602. wsa884x->comp_offset));
  603. snd_soc_component_update_bits(component,
  604. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  605. } else {
  606. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
  607. snd_soc_component_update_bits(component,
  608. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  609. snd_soc_component_update_bits(component,
  610. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  611. }
  612. return 0;
  613. }
  614. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  615. {
  616. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  617. int vth1_reg_val;
  618. int vth2_reg_val;
  619. int vth3_reg_val;
  620. int vth4_reg_val;
  621. int vth5_reg_val;
  622. int vth6_reg_val;
  623. int vth7_reg_val;
  624. int vth8_reg_val;
  625. int vth9_reg_val;
  626. int vth10_reg_val;
  627. int vth11_reg_val;
  628. int vth12_reg_val;
  629. int vth13_reg_val;
  630. int vth14_reg_val;
  631. int vth15_reg_val;
  632. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  633. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  634. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  635. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  636. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  637. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  638. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  639. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  640. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  641. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  642. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  643. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  644. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  645. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  646. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  647. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  648. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  649. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  650. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  651. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  652. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  653. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  654. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  655. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  656. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  657. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  658. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  659. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  660. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  661. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  662. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  663. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  664. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  665. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  666. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  667. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  668. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  669. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  670. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  671. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  672. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  673. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  674. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  675. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  676. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  677. return 0;
  678. }
  679. static void wsa_noise_gate_write(struct snd_soc_component *component,
  680. int imode)
  681. {
  682. switch (imode) {
  683. case NG1:
  684. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  685. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  686. break;
  687. case NG2:
  688. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  689. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x20);
  690. break;
  691. case NG3:
  692. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  693. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x10);
  694. break;
  695. default:
  696. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  697. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  698. break;
  699. }
  700. }
  701. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  702. struct snd_ctl_elem_value *ucontrol)
  703. {
  704. struct snd_soc_component *component =
  705. snd_soc_kcontrol_component(kcontrol);
  706. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  707. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  708. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  709. wsa884x->dev_mode);
  710. return 0;
  711. }
  712. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  713. struct snd_ctl_elem_value *ucontrol)
  714. {
  715. struct snd_soc_component *component =
  716. snd_soc_kcontrol_component(kcontrol);
  717. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  718. int dev_mode;
  719. int wsa_dev_index;
  720. if ((ucontrol->value.integer.value[0] >= SPEAKER) &&
  721. (ucontrol->value.integer.value[0] < MAX_DEV_MODE))
  722. dev_mode = ucontrol->value.integer.value[0];
  723. else
  724. return -EINVAL;
  725. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d\n",
  726. __func__, wsa884x->dev_mode, dev_mode);
  727. /* Check if input parameter is in range */
  728. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  729. if ((dev_mode + wsa_dev_index * 2) < (MAX_DEV_MODE * 2)) {
  730. wsa884x->dev_mode = dev_mode;
  731. wsa884x->system_gain = wsa884x->sys_gains[dev_mode + wsa_dev_index * 2];
  732. } else {
  733. return -EINVAL;
  734. }
  735. return 0;
  736. }
  737. static const char * const wsa_pa_gain_text[] = {
  738. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  739. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  740. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  741. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  742. };
  743. static const struct soc_enum wsa_pa_gain_enum =
  744. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  745. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  746. struct snd_ctl_elem_value *ucontrol)
  747. {
  748. struct snd_soc_component *component =
  749. snd_soc_kcontrol_component(kcontrol);
  750. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  751. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  752. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  753. wsa884x->pa_gain);
  754. return 0;
  755. }
  756. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  757. struct snd_ctl_elem_value *ucontrol)
  758. {
  759. struct snd_soc_component *component =
  760. snd_soc_kcontrol_component(kcontrol);
  761. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  762. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  763. __func__, ucontrol->value.integer.value[0]);
  764. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  765. return 0;
  766. }
  767. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  768. struct snd_ctl_elem_value *ucontrol)
  769. {
  770. struct snd_soc_component *component =
  771. snd_soc_kcontrol_component(kcontrol);
  772. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  773. int temp = 0;
  774. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  775. temp = wsa884x->curr_temp;
  776. else
  777. wsa884x_get_temperature(component, &temp);
  778. ucontrol->value.integer.value[0] = temp;
  779. return 0;
  780. }
  781. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  782. void *file_private_data, struct file *file,
  783. char __user *buf, size_t count, loff_t pos)
  784. {
  785. struct wsa884x_priv *wsa884x;
  786. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  787. int len = 0;
  788. wsa884x = (struct wsa884x_priv *) entry->private_data;
  789. if (!wsa884x) {
  790. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  791. return -EINVAL;
  792. }
  793. switch (wsa884x->version) {
  794. case WSA884X_VERSION_1_0:
  795. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  796. break;
  797. default:
  798. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  799. break;
  800. }
  801. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  802. }
  803. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  804. .read = wsa884x_codec_version_read,
  805. };
  806. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  807. void *file_private_data,
  808. struct file *file,
  809. char __user *buf, size_t count,
  810. loff_t pos)
  811. {
  812. struct wsa884x_priv *wsa884x;
  813. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  814. int len = 0;
  815. wsa884x = (struct wsa884x_priv *) entry->private_data;
  816. if (!wsa884x) {
  817. pr_err_ratelimited("%s: wsa884x priv is null\n", __func__);
  818. return -EINVAL;
  819. }
  820. switch (wsa884x->variant) {
  821. case WSA8840:
  822. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  823. break;
  824. case WSA8845:
  825. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  826. break;
  827. case WSA8845H:
  828. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  829. break;
  830. default:
  831. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  832. break;
  833. }
  834. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  835. }
  836. static struct snd_info_entry_ops wsa884x_variant_ops = {
  837. .read = wsa884x_variant_read,
  838. };
  839. /*
  840. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  841. * @codec_root: The parent directory
  842. * @component: Codec instance
  843. *
  844. * Creates wsa884x module and version entry under the given
  845. * parent directory.
  846. *
  847. * Return: 0 on success or negative error code on failure.
  848. */
  849. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  850. struct snd_soc_component *component)
  851. {
  852. struct snd_info_entry *version_entry;
  853. struct snd_info_entry *variant_entry;
  854. struct wsa884x_priv *wsa884x;
  855. struct snd_soc_card *card;
  856. char name[80];
  857. if (!codec_root || !component)
  858. return -EINVAL;
  859. wsa884x = snd_soc_component_get_drvdata(component);
  860. if (wsa884x->entry) {
  861. dev_dbg(wsa884x->dev,
  862. "%s:wsa884x module already created\n", __func__);
  863. return 0;
  864. }
  865. card = component->card;
  866. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  867. wsa884x->swr_slave->addr);
  868. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  869. (const char *)name,
  870. codec_root);
  871. if (!wsa884x->entry) {
  872. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  873. __func__);
  874. return -ENOMEM;
  875. }
  876. wsa884x->entry->mode = S_IFDIR | 0555;
  877. if (snd_info_register(wsa884x->entry) < 0) {
  878. snd_info_free_entry(wsa884x->entry);
  879. return -ENOMEM;
  880. }
  881. version_entry = snd_info_create_card_entry(card->snd_card,
  882. "version",
  883. wsa884x->entry);
  884. if (!version_entry) {
  885. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  886. __func__);
  887. snd_info_free_entry(wsa884x->entry);
  888. return -ENOMEM;
  889. }
  890. version_entry->private_data = wsa884x;
  891. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  892. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  893. version_entry->c.ops = &wsa884x_codec_info_ops;
  894. if (snd_info_register(version_entry) < 0) {
  895. snd_info_free_entry(version_entry);
  896. snd_info_free_entry(wsa884x->entry);
  897. return -ENOMEM;
  898. }
  899. wsa884x->version_entry = version_entry;
  900. variant_entry = snd_info_create_card_entry(card->snd_card,
  901. "variant",
  902. wsa884x->entry);
  903. if (!variant_entry) {
  904. dev_dbg(component->dev,
  905. "%s: failed to create wsa884x variant entry\n",
  906. __func__);
  907. snd_info_free_entry(version_entry);
  908. snd_info_free_entry(wsa884x->entry);
  909. return -ENOMEM;
  910. }
  911. variant_entry->private_data = wsa884x;
  912. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  913. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  914. variant_entry->c.ops = &wsa884x_variant_ops;
  915. if (snd_info_register(variant_entry) < 0) {
  916. snd_info_free_entry(variant_entry);
  917. snd_info_free_entry(version_entry);
  918. snd_info_free_entry(wsa884x->entry);
  919. return -ENOMEM;
  920. }
  921. wsa884x->variant_entry = variant_entry;
  922. return 0;
  923. }
  924. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  925. /*
  926. * wsa884x_codec_get_dev_num - returns swr device number
  927. * @component: Codec instance
  928. *
  929. * Return: swr device number on success or negative error
  930. * code on failure.
  931. */
  932. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  933. {
  934. struct wsa884x_priv *wsa884x;
  935. if (!component)
  936. return -EINVAL;
  937. wsa884x = snd_soc_component_get_drvdata(component);
  938. if (!wsa884x) {
  939. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  940. return -EINVAL;
  941. }
  942. return wsa884x->swr_slave->dev_num;
  943. }
  944. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  945. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  946. struct snd_ctl_elem_value *ucontrol)
  947. {
  948. struct snd_soc_component *component =
  949. snd_soc_kcontrol_component(kcontrol);
  950. struct wsa884x_priv *wsa884x;
  951. if (!component)
  952. return -EINVAL;
  953. wsa884x = snd_soc_component_get_drvdata(component);
  954. if (!wsa884x) {
  955. pr_err_ratelimited("%s: wsa884x component is NULL\n", __func__);
  956. return -EINVAL;
  957. }
  958. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  959. return 0;
  960. }
  961. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  962. struct snd_ctl_elem_value *ucontrol)
  963. {
  964. struct snd_soc_component *component =
  965. snd_soc_kcontrol_component(kcontrol);
  966. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  967. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  968. return 0;
  969. }
  970. /*
  971. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  972. * Return: 0 Valid configuration, 1 Invalid configuration
  973. */
  974. static bool wsa884x_validate_dt_configuration_params(struct snd_soc_component *component,
  975. u8 irload, u8 ibat_cfg_dts, u8 isystem_gain)
  976. {
  977. u8 bat_cfg_reg;
  978. bool is_invalid_flag = true;
  979. bat_cfg_reg = snd_soc_component_read(component, WSA884X_VPHX_SYS_EN_STATUS);
  980. dev_info(component->dev, "VPHX EN Status: %d", bat_cfg_reg);
  981. if ((ibat_cfg_dts == EXT_1S) || (ibat_cfg_dts == EXT_2S) || (ibat_cfg_dts == EXT_3S))
  982. ibat_cfg_dts = EXT_ABOVE_3S;
  983. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  984. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  985. (EXT_ABOVE_3S <= ibat_cfg_dts && ibat_cfg_dts < CONFIG_MAX) &&
  986. (ibat_cfg_dts == bat_cfg_reg))
  987. is_invalid_flag = false;
  988. return is_invalid_flag;
  989. }
  990. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  991. struct snd_ctl_elem_value *ucontrol)
  992. {
  993. struct snd_soc_component *component =
  994. snd_soc_kcontrol_component(kcontrol);
  995. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  996. int value = ucontrol->value.integer.value[0];
  997. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  998. __func__, wsa884x->comp_enable, value);
  999. wsa884x->comp_enable = value;
  1000. return 0;
  1001. }
  1002. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  1003. struct snd_ctl_elem_value *ucontrol)
  1004. {
  1005. struct snd_soc_component *component =
  1006. snd_soc_kcontrol_component(kcontrol);
  1007. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1008. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  1009. return 0;
  1010. }
  1011. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  1012. struct snd_ctl_elem_value *ucontrol)
  1013. {
  1014. struct snd_soc_component *component =
  1015. snd_soc_kcontrol_component(kcontrol);
  1016. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1017. int value = ucontrol->value.integer.value[0];
  1018. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  1019. __func__, wsa884x->visense_enable, value);
  1020. wsa884x->visense_enable = value;
  1021. return 0;
  1022. }
  1023. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  1024. struct snd_ctl_elem_value *ucontrol)
  1025. {
  1026. struct snd_soc_component *component =
  1027. snd_soc_kcontrol_component(kcontrol);
  1028. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1029. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  1030. return 0;
  1031. }
  1032. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  1033. struct snd_ctl_elem_value *ucontrol)
  1034. {
  1035. struct snd_soc_component *component =
  1036. snd_soc_kcontrol_component(kcontrol);
  1037. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1038. int value = ucontrol->value.integer.value[0];
  1039. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  1040. __func__, wsa884x->pbr_enable, value);
  1041. wsa884x->pbr_enable = value;
  1042. return 0;
  1043. }
  1044. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  1045. struct snd_ctl_elem_value *ucontrol)
  1046. {
  1047. struct snd_soc_component *component =
  1048. snd_soc_kcontrol_component(kcontrol);
  1049. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1050. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  1051. return 0;
  1052. }
  1053. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  1054. struct snd_ctl_elem_value *ucontrol)
  1055. {
  1056. struct snd_soc_component *component =
  1057. snd_soc_kcontrol_component(kcontrol);
  1058. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1059. int value = ucontrol->value.integer.value[0];
  1060. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  1061. __func__, wsa884x->cps_enable, value);
  1062. wsa884x->cps_enable = value;
  1063. return 0;
  1064. }
  1065. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  1066. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  1067. wsa_pa_gain_get, wsa_pa_gain_put),
  1068. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1069. wsa_get_temp, NULL),
  1070. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1071. wsa884x_get_dev_num, NULL),
  1072. SOC_SINGLE_EXT("WSA MODE", SND_SOC_NOPM, 0, 1, 0,
  1073. wsa_dev_mode_get, wsa_dev_mode_put),
  1074. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1075. wsa884x_get_compander, wsa884x_set_compander),
  1076. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1077. wsa884x_get_visense, wsa884x_set_visense),
  1078. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1079. wsa884x_get_pbr, wsa884x_set_pbr),
  1080. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1081. wsa884x_get_cps, wsa884x_set_cps),
  1082. };
  1083. static const struct snd_kcontrol_new swr_dac_port[] = {
  1084. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1085. };
  1086. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1087. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1088. u8 *port_type)
  1089. {
  1090. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1091. *port_id = wsa884x->port[port_idx].port_id;
  1092. *num_ch = wsa884x->port[port_idx].num_ch;
  1093. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1094. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1095. *port_type = wsa884x->port[port_idx].port_type;
  1096. return 0;
  1097. }
  1098. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1099. struct snd_kcontrol *kcontrol, int event)
  1100. {
  1101. struct snd_soc_component *component =
  1102. snd_soc_dapm_to_component(w->dapm);
  1103. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1104. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1105. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1106. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1107. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1108. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1109. u8 num_port = 0;
  1110. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1111. event, w->name);
  1112. if (wsa884x == NULL)
  1113. return -EINVAL;
  1114. switch (event) {
  1115. case SND_SOC_DAPM_PRE_PMU:
  1116. wsa884x_set_port(component, SWR_DAC_PORT,
  1117. &port_id[num_port], &num_ch[num_port],
  1118. &ch_mask[num_port], &ch_rate[num_port],
  1119. &port_type[num_port]);
  1120. if (wsa884x->dev_mode == RECEIVER)
  1121. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1122. ++num_port;
  1123. if (wsa884x->comp_enable) {
  1124. wsa884x_set_port(component, SWR_COMP_PORT,
  1125. &port_id[num_port], &num_ch[num_port],
  1126. &ch_mask[num_port], &ch_rate[num_port],
  1127. &port_type[num_port]);
  1128. ++num_port;
  1129. set_bit(COMP_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1130. }
  1131. if (wsa884x->pbr_enable) {
  1132. wsa884x_set_port(component, SWR_PBR_PORT,
  1133. &port_id[num_port], &num_ch[num_port],
  1134. &ch_mask[num_port], &ch_rate[num_port],
  1135. &port_type[num_port]);
  1136. ++num_port;
  1137. set_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1138. }
  1139. if (wsa884x->visense_enable) {
  1140. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1141. &port_id[num_port], &num_ch[num_port],
  1142. &ch_mask[num_port], &ch_rate[num_port],
  1143. &port_type[num_port]);
  1144. ++num_port;
  1145. set_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1146. }
  1147. if (wsa884x->cps_enable) {
  1148. wsa884x_set_port(component, SWR_CPS_PORT,
  1149. &port_id[num_port], &num_ch[num_port],
  1150. &ch_mask[num_port], &ch_rate[num_port],
  1151. &port_type[num_port]);
  1152. ++num_port;
  1153. set_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1154. }
  1155. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1156. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1157. &port_type[0]);
  1158. break;
  1159. case SND_SOC_DAPM_POST_PMU:
  1160. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1161. break;
  1162. case SND_SOC_DAPM_PRE_PMD:
  1163. wsa884x_set_port(component, SWR_DAC_PORT,
  1164. &port_id[num_port], &num_ch[num_port],
  1165. &ch_mask[num_port], &ch_rate[num_port],
  1166. &port_type[num_port]);
  1167. ++num_port;
  1168. if (wsa884x->comp_enable &&
  1169. test_bit(COMP_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1170. wsa884x_set_port(component, SWR_COMP_PORT,
  1171. &port_id[num_port], &num_ch[num_port],
  1172. &ch_mask[num_port], &ch_rate[num_port],
  1173. &port_type[num_port]);
  1174. ++num_port;
  1175. clear_bit(COMP_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1176. }
  1177. if (wsa884x->pbr_enable &&
  1178. test_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1179. wsa884x_set_port(component, SWR_PBR_PORT,
  1180. &port_id[num_port], &num_ch[num_port],
  1181. &ch_mask[num_port], &ch_rate[num_port],
  1182. &port_type[num_port]);
  1183. ++num_port;
  1184. clear_bit(PBR_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1185. }
  1186. if (wsa884x->visense_enable &&
  1187. test_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1188. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1189. &port_id[num_port], &num_ch[num_port],
  1190. &ch_mask[num_port], &ch_rate[num_port],
  1191. &port_type[num_port]);
  1192. ++num_port;
  1193. clear_bit(VI_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1194. }
  1195. if (wsa884x->cps_enable &&
  1196. test_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask)) {
  1197. wsa884x_set_port(component, SWR_CPS_PORT,
  1198. &port_id[num_port], &num_ch[num_port],
  1199. &ch_mask[num_port], &ch_rate[num_port],
  1200. &port_type[num_port]);
  1201. ++num_port;
  1202. clear_bit(CPS_PORT_EN_STATUS_BIT, &wsa884x->port_status_mask);
  1203. }
  1204. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1205. &ch_mask[0], &port_type[0]);
  1206. break;
  1207. case SND_SOC_DAPM_POST_PMD:
  1208. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1209. dev_err_ratelimited(component->dev,
  1210. "%s: set num ch failed\n", __func__);
  1211. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1212. wsa884x->swr_slave->dev_num,
  1213. false);
  1214. break;
  1215. default:
  1216. break;
  1217. }
  1218. return 0;
  1219. }
  1220. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1221. struct snd_kcontrol *kcontrol, int event)
  1222. {
  1223. struct snd_soc_component *component =
  1224. snd_soc_dapm_to_component(w->dapm);
  1225. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1226. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1227. switch (event) {
  1228. case SND_SOC_DAPM_POST_PMU:
  1229. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1230. wsa884x->swr_slave->dev_num,
  1231. true);
  1232. wsa884x_set_gain_parameters(component);
  1233. if (wsa884x->dev_mode == SPEAKER) {
  1234. snd_soc_component_update_bits(component,
  1235. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1236. } else {
  1237. snd_soc_component_update_bits(component,
  1238. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1239. snd_soc_component_update_bits(component,
  1240. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1241. snd_soc_component_update_bits(component,
  1242. REG_FIELD_VALUE(PWM_CLK_CTL,
  1243. PWM_CLK_FREQ_SEL, 0x01));
  1244. }
  1245. if (wsa884x->pbr_enable) {
  1246. snd_soc_component_update_bits(component,
  1247. REG_FIELD_VALUE(CURRENT_LIMIT,
  1248. CURRENT_LIMIT_OVRD_EN, 0x00));
  1249. switch (wsa884x->bat_cfg) {
  1250. case CONFIG_1S:
  1251. snd_soc_component_update_bits(component,
  1252. REG_FIELD_VALUE(CURRENT_LIMIT,
  1253. CURRENT_LIMIT, 0x15));
  1254. break;
  1255. case CONFIG_2S:
  1256. snd_soc_component_update_bits(component,
  1257. REG_FIELD_VALUE(CURRENT_LIMIT,
  1258. CURRENT_LIMIT, 0x11));
  1259. break;
  1260. case CONFIG_3S:
  1261. snd_soc_component_update_bits(component,
  1262. REG_FIELD_VALUE(CURRENT_LIMIT,
  1263. CURRENT_LIMIT, 0x0D));
  1264. break;
  1265. }
  1266. } else {
  1267. snd_soc_component_update_bits(component,
  1268. REG_FIELD_VALUE(CURRENT_LIMIT,
  1269. CURRENT_LIMIT_OVRD_EN, 0x01));
  1270. if (wsa884x->system_gain >= G_12_DB)
  1271. snd_soc_component_update_bits(component,
  1272. REG_FIELD_VALUE(CURRENT_LIMIT,
  1273. CURRENT_LIMIT, 0x15));
  1274. else
  1275. snd_soc_component_update_bits(component,
  1276. REG_FIELD_VALUE(CURRENT_LIMIT,
  1277. CURRENT_LIMIT, 0x09));
  1278. }
  1279. /* Force remove group */
  1280. swr_remove_from_group(wsa884x->swr_slave,
  1281. wsa884x->swr_slave->dev_num);
  1282. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask) &&
  1283. !wsa884x->pa_mute)
  1284. snd_soc_component_update_bits(component,
  1285. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1286. break;
  1287. case SND_SOC_DAPM_PRE_PMD:
  1288. snd_soc_component_update_bits(component,
  1289. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1290. snd_soc_component_update_bits(component,
  1291. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1292. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1293. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1294. wsa884x->pa_mute = 0;
  1295. break;
  1296. }
  1297. return 0;
  1298. }
  1299. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1300. SND_SOC_DAPM_INPUT("IN"),
  1301. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1302. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1303. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1304. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1305. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1306. };
  1307. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1308. {"SWR DAC_Port", "Switch", "IN"},
  1309. {"SPKR", NULL, "SWR DAC_Port"},
  1310. };
  1311. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1312. u8 num_port, unsigned int *ch_mask,
  1313. unsigned int *ch_rate, u8 *port_type)
  1314. {
  1315. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1316. int i;
  1317. if (!port || !ch_mask || !ch_rate ||
  1318. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1319. dev_err_ratelimited(component->dev,
  1320. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1321. __func__, port, ch_mask, ch_rate);
  1322. return -EINVAL;
  1323. }
  1324. for (i = 0; i < num_port; i++) {
  1325. wsa884x->port[i].port_id = port[i];
  1326. wsa884x->port[i].ch_mask = ch_mask[i];
  1327. wsa884x->port[i].ch_rate = ch_rate[i];
  1328. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1329. if (port_type)
  1330. wsa884x->port[i].port_type = port_type[i];
  1331. }
  1332. return 0;
  1333. }
  1334. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1335. static void wsa884x_codec_init(struct snd_soc_component *component)
  1336. {
  1337. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1338. int i;
  1339. if (!wsa884x)
  1340. return;
  1341. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1342. snd_soc_component_update_bits(component, reg_init[i].reg,
  1343. reg_init[i].mask, reg_init[i].val);
  1344. /* Register updates for 2S battery configuration */
  1345. if (wsa884x->bat_cfg == CONFIG_2S) {
  1346. for (i = 0; i < ARRAY_SIZE(reg_init_2S); i++)
  1347. snd_soc_component_update_bits(component, reg_init_2S[i].reg,
  1348. reg_init_2S[i].mask, reg_init_2S[i].val);
  1349. }
  1350. for (i = 0; i < ARRAY_SIZE(reg_init_uvlo); i++)
  1351. snd_soc_component_update_bits(component, reg_init_uvlo[i].reg,
  1352. reg_init_uvlo[i].mask, reg_init_uvlo[i].val);
  1353. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1354. }
  1355. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1356. struct wsa_temp_register *wsa_temp_reg)
  1357. {
  1358. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1359. if (!wsa884x) {
  1360. dev_err_ratelimited(component->dev, "%s: wsa884x is NULL\n", __func__);
  1361. return -EINVAL;
  1362. }
  1363. mutex_lock(&wsa884x->res_lock);
  1364. snd_soc_component_update_bits(component,
  1365. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1366. snd_soc_component_update_bits(component,
  1367. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1368. snd_soc_component_update_bits(component,
  1369. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1370. snd_soc_component_update_bits(component,
  1371. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1372. snd_soc_component_update_bits(component,
  1373. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1374. snd_soc_component_update_bits(component,
  1375. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1376. snd_soc_component_update_bits(component,
  1377. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1378. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1379. WSA884X_TEMP_DIN_MSB);
  1380. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1381. WSA884X_TEMP_DIN_LSB);
  1382. snd_soc_component_update_bits(component,
  1383. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1384. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1385. WSA884X_OTP_REG_1);
  1386. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1387. WSA884X_OTP_REG_2);
  1388. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1389. WSA884X_OTP_REG_3);
  1390. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1391. WSA884X_OTP_REG_4);
  1392. snd_soc_component_update_bits(component,
  1393. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1394. mutex_unlock(&wsa884x->res_lock);
  1395. return 0;
  1396. }
  1397. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1398. int *temp)
  1399. {
  1400. struct wsa_temp_register reg;
  1401. int dmeas, d1, d2;
  1402. int ret = 0;
  1403. int temp_val = 0;
  1404. int t1 = T1_TEMP;
  1405. int t2 = T2_TEMP;
  1406. u8 retry = WSA884X_TEMP_RETRY;
  1407. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1408. if (!wsa884x)
  1409. return -EINVAL;
  1410. do {
  1411. ret = wsa884x_temp_reg_read(component, &reg);
  1412. if (ret) {
  1413. pr_err_ratelimited("%s: temp read failed: %d, current temp: %d\n",
  1414. __func__, ret, wsa884x->curr_temp);
  1415. if (temp)
  1416. *temp = wsa884x->curr_temp;
  1417. return 0;
  1418. }
  1419. /*
  1420. * Temperature register values are expected to be in the
  1421. * following range.
  1422. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1423. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1424. */
  1425. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1426. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1427. reg.d1_lsb == 192)) ||
  1428. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1429. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1430. reg.d2_lsb == 192))) {
  1431. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1432. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1433. reg.d2_lsb);
  1434. }
  1435. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1436. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1437. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1438. if (d1 == d2)
  1439. temp_val = TEMP_INVALID;
  1440. else
  1441. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1442. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1443. temp_val >= HIGH_TEMP_THRESHOLD) {
  1444. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1445. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1446. if (retry--)
  1447. msleep(10);
  1448. } else {
  1449. break;
  1450. }
  1451. } while (retry);
  1452. wsa884x->curr_temp = temp_val;
  1453. if (temp)
  1454. *temp = temp_val;
  1455. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1456. __func__, temp_val, dmeas, d1, d2);
  1457. return ret;
  1458. }
  1459. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1460. {
  1461. char w_name[MAX_NAME_LEN];
  1462. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1463. struct swr_device *dev;
  1464. int variant = 0, version = 0;
  1465. struct snd_soc_dapm_context *dapm =
  1466. snd_soc_component_get_dapm(component);
  1467. if (!wsa884x)
  1468. return -EINVAL;
  1469. if (!component->name_prefix)
  1470. return -EINVAL;
  1471. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1472. dev = wsa884x->swr_slave;
  1473. wsa884x->component = component;
  1474. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1475. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1476. wsa884x->variant = variant;
  1477. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1478. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1479. wsa884x->version = version;
  1480. wsa884x->comp_offset = COMP_OFFSET2;
  1481. wsa884x_codec_init(component);
  1482. wsa884x->global_pa_cnt = 0;
  1483. memset(w_name, 0, sizeof(w_name));
  1484. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1485. sizeof(w_name));
  1486. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1487. memset(w_name, 0, sizeof(w_name));
  1488. strlcpy(w_name, "IN", sizeof(w_name));
  1489. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1490. memset(w_name, 0, sizeof(w_name));
  1491. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1492. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1493. memset(w_name, 0, sizeof(w_name));
  1494. strlcpy(w_name, "SPKR", sizeof(w_name));
  1495. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1496. snd_soc_dapm_sync(dapm);
  1497. return 0;
  1498. }
  1499. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1500. {
  1501. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1502. if (!wsa884x)
  1503. return;
  1504. snd_soc_component_exit_regmap(component);
  1505. return;
  1506. }
  1507. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1508. {
  1509. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1510. if (!wsa884x)
  1511. return 0;
  1512. wsa884x->dapm_bias_off = true;
  1513. return 0;
  1514. }
  1515. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1516. {
  1517. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1518. if (!wsa884x)
  1519. return 0;
  1520. wsa884x->dapm_bias_off = false;
  1521. return 0;
  1522. }
  1523. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1524. .name = "",
  1525. .probe = wsa884x_codec_probe,
  1526. .remove = wsa884x_codec_remove,
  1527. .controls = wsa884x_snd_controls,
  1528. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1529. .dapm_widgets = wsa884x_dapm_widgets,
  1530. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1531. .dapm_routes = wsa884x_audio_map,
  1532. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1533. .suspend = wsa884x_soc_codec_suspend,
  1534. .resume = wsa884x_soc_codec_resume,
  1535. };
  1536. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1537. {
  1538. int ret = 0;
  1539. if (enable)
  1540. ret = msm_cdc_pinctrl_select_active_state(
  1541. wsa884x->wsa_rst_np);
  1542. else
  1543. ret = msm_cdc_pinctrl_select_sleep_state(
  1544. wsa884x->wsa_rst_np);
  1545. if (ret != 0)
  1546. dev_err_ratelimited(wsa884x->dev,
  1547. "%s: Failed to turn state %d; ret=%d\n",
  1548. __func__, enable, ret);
  1549. return ret;
  1550. }
  1551. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1552. {
  1553. int ret;
  1554. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1555. if (ret)
  1556. dev_err_ratelimited(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1557. return ret;
  1558. }
  1559. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1560. {
  1561. int ret;
  1562. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1563. if (ret)
  1564. dev_err_ratelimited(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1565. return ret;
  1566. }
  1567. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1568. {
  1569. u8 retry = WSA884X_NUM_RETRY;
  1570. u8 devnum = 0;
  1571. struct swr_device *pdev;
  1572. pdev = wsa884x->swr_slave;
  1573. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1574. /* Retry after 1 msec delay */
  1575. usleep_range(1000, 1100);
  1576. }
  1577. pdev->dev_num = devnum;
  1578. wsa884x_regcache_sync(wsa884x);
  1579. return 0;
  1580. }
  1581. static int wsa884x_event_notify(struct notifier_block *nb,
  1582. unsigned long val, void *ptr)
  1583. {
  1584. u16 event = (val & 0xffff);
  1585. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1586. parent_nblock);
  1587. if (!wsa884x)
  1588. return -EINVAL;
  1589. switch (event) {
  1590. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1591. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1592. snd_soc_component_update_bits(wsa884x->component,
  1593. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1594. wsa884x_swr_down(wsa884x);
  1595. break;
  1596. case BOLERO_SLV_EVT_SSR_UP:
  1597. wsa884x_swr_up(wsa884x);
  1598. /* Add delay to allow enumerate */
  1599. usleep_range(20000, 20010);
  1600. wsa884x_swr_reset(wsa884x);
  1601. dev_err(wsa884x->dev, "%s: BOLERO_SLV_EVT_SSR_UP Called", __func__);
  1602. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1603. wsa884x->swr_wsa_port_params);
  1604. break;
  1605. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1606. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1607. snd_soc_component_update_bits(wsa884x->component,
  1608. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1609. snd_soc_component_update_bits(wsa884x->component,
  1610. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1611. }
  1612. break;
  1613. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1614. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1615. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1616. break;
  1617. default:
  1618. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1619. __func__, event);
  1620. break;
  1621. }
  1622. return 0;
  1623. }
  1624. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1625. {
  1626. u32 *dt_array, map_size, max_uc;
  1627. int ret = 0;
  1628. u32 cnt = 0;
  1629. u32 i, j;
  1630. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1631. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1632. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1633. map = &wsa884x->wsa_port_params;
  1634. map_uc = &wsa884x->swr_wsa_port_params;
  1635. if (!of_find_property(dev->of_node, prop,
  1636. &map_size)) {
  1637. dev_err(dev, "missing port mapping prop %s\n", prop);
  1638. ret = -EINVAL;
  1639. goto err_port_map;
  1640. }
  1641. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1642. if (max_uc != SWR_UC_MAX) {
  1643. dev_err(dev, "%s: port params not provided for all usecases\n",
  1644. __func__);
  1645. ret = -EINVAL;
  1646. goto err_port_map;
  1647. }
  1648. dt_array = kzalloc(map_size, GFP_KERNEL);
  1649. if (!dt_array) {
  1650. ret = -ENOMEM;
  1651. goto err_port_map;
  1652. }
  1653. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1654. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1655. if (ret) {
  1656. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1657. __func__, prop);
  1658. goto err_pdata_fail;
  1659. }
  1660. for (i = 0; i < max_uc; i++) {
  1661. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1662. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1663. (*map)[i][j].offset1 = dt_array[cnt];
  1664. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1665. }
  1666. (*map_uc)[i].pp = &(*map)[i][0];
  1667. }
  1668. kfree(dt_array);
  1669. return 0;
  1670. err_pdata_fail:
  1671. kfree(dt_array);
  1672. err_port_map:
  1673. return ret;
  1674. }
  1675. static int wsa884x_enable_supplies(struct device *dev,
  1676. struct wsa884x_priv *priv)
  1677. {
  1678. int ret = 0;
  1679. /* Parse power supplies */
  1680. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1681. &priv->num_supplies);
  1682. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1683. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1684. return -EINVAL;
  1685. }
  1686. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1687. priv->regulator, priv->num_supplies);
  1688. if (!priv->supplies) {
  1689. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1690. __func__);
  1691. return ret;
  1692. }
  1693. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1694. priv->regulator,
  1695. priv->num_supplies);
  1696. if (ret)
  1697. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1698. __func__);
  1699. return ret;
  1700. }
  1701. static struct snd_soc_dai_driver wsa_dai[] = {
  1702. {
  1703. .name = "",
  1704. .playback = {
  1705. .stream_name = "",
  1706. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1707. .formats = WSA884X_FORMATS,
  1708. .rate_max = 192000,
  1709. .rate_min = 8000,
  1710. .channels_min = 1,
  1711. .channels_max = 2,
  1712. },
  1713. },
  1714. };
  1715. static int wsa884x_swr_probe(struct swr_device *pdev)
  1716. {
  1717. int ret = 0;
  1718. struct wsa884x_priv *wsa884x;
  1719. u8 devnum = 0;
  1720. bool pin_state_current = false;
  1721. struct wsa_ctrl_platform_data *plat_data = NULL;
  1722. struct snd_soc_component *component;
  1723. u32 noise_gate_mode;
  1724. char buffer[MAX_NAME_LEN];
  1725. int dev_index = 0;
  1726. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1727. u8 wo0_val;
  1728. int sys_gain_size, sys_gain_length;
  1729. int wsa_dev_index;
  1730. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1731. GFP_KERNEL);
  1732. if (!wsa884x)
  1733. return -ENOMEM;
  1734. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1735. GFP_KERNEL);
  1736. if (!wsa884x_sub_regmap_irq_chip)
  1737. return -ENOMEM;
  1738. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1739. sizeof(struct regmap_irq_chip));
  1740. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1741. if (ret) {
  1742. ret = -EPROBE_DEFER;
  1743. goto err;
  1744. }
  1745. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1746. "qcom,spkr-sd-n-node", 0);
  1747. if (!wsa884x->wsa_rst_np) {
  1748. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1749. goto err_supply;
  1750. }
  1751. swr_set_dev_data(pdev, wsa884x);
  1752. wsa884x->swr_slave = pdev;
  1753. wsa884x->dev = &pdev->dev;
  1754. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1755. wsa884x_gpio_ctrl(wsa884x, true);
  1756. /*
  1757. * Add 5msec delay to provide sufficient time for
  1758. * soundwire auto enumeration of slave devices as
  1759. * per HW requirement.
  1760. */
  1761. usleep_range(5000, 5010);
  1762. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1763. if (ret) {
  1764. dev_dbg(&pdev->dev,
  1765. "%s get devnum %d for dev addr %lx failed\n",
  1766. __func__, devnum, pdev->addr);
  1767. ret = -EPROBE_DEFER;
  1768. goto err_supply;
  1769. }
  1770. pdev->dev_num = devnum;
  1771. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1772. &wsa884x_regmap_config);
  1773. if (IS_ERR(wsa884x->regmap)) {
  1774. ret = PTR_ERR(wsa884x->regmap);
  1775. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1776. __func__, ret);
  1777. goto dev_err;
  1778. }
  1779. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1780. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1781. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1782. wsa884x->irq_info.codec_name = "WSA884X";
  1783. wsa884x->irq_info.regmap = wsa884x->regmap;
  1784. wsa884x->irq_info.dev = &pdev->dev;
  1785. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1786. if (ret) {
  1787. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1788. __func__, ret);
  1789. goto dev_err;
  1790. }
  1791. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1792. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1793. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1794. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1795. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1796. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1797. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1798. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1799. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1800. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1801. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1802. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1803. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1804. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1805. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1806. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1807. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1808. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1809. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1810. /* Under Voltage Lock out (UVLO) interrupt handle */
  1811. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1812. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1813. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1814. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1815. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1816. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1817. if (!wsa884x->driver) {
  1818. ret = -ENOMEM;
  1819. goto err_irq;
  1820. }
  1821. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1822. sizeof(struct snd_soc_component_driver));
  1823. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1824. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1825. if (!wsa884x->dai_driver) {
  1826. ret = -ENOMEM;
  1827. goto err_mem;
  1828. }
  1829. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1830. /* Get last digit from HEX format */
  1831. dev_index = (int)((char)(pdev->addr & 0xF));
  1832. dev_index += 1;
  1833. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1834. dev_index += 2;
  1835. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1836. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1837. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1838. wsa884x->dai_driver->name =
  1839. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1840. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1841. wsa884x->dai_driver->playback.stream_name =
  1842. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1843. /* Number of DAI's used is 1 */
  1844. ret = snd_soc_register_component(&pdev->dev,
  1845. wsa884x->driver, wsa884x->dai_driver, 1);
  1846. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1847. if (!component) {
  1848. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1849. ret = -EINVAL;
  1850. goto err_mem;
  1851. }
  1852. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1853. "qcom,bolero-handle", 0);
  1854. if (!wsa884x->parent_np)
  1855. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1856. "qcom,lpass-cdc-handle", 0);
  1857. if (wsa884x->parent_np) {
  1858. wsa884x->parent_dev =
  1859. of_find_device_by_node(wsa884x->parent_np);
  1860. if (wsa884x->parent_dev) {
  1861. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1862. if (plat_data) {
  1863. wsa884x->parent_nblock.notifier_call =
  1864. wsa884x_event_notify;
  1865. if (plat_data->register_notifier)
  1866. plat_data->register_notifier(
  1867. plat_data->handle,
  1868. &wsa884x->parent_nblock,
  1869. true);
  1870. wsa884x->register_notifier =
  1871. plat_data->register_notifier;
  1872. wsa884x->handle = plat_data->handle;
  1873. } else {
  1874. dev_err(&pdev->dev, "%s: plat data not found\n",
  1875. __func__);
  1876. }
  1877. } else {
  1878. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1879. __func__);
  1880. }
  1881. } else {
  1882. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1883. }
  1884. /* Start in speaker mode by default */
  1885. wsa884x->dev_mode = SPEAKER;
  1886. wsa884x->dev_index = dev_index;
  1887. /* wsa_dev_index is macro_agnostic index */
  1888. wsa_dev_index = (wsa884x->dev_index - 1) % 2;
  1889. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1890. "qcom,wsa-macro-handle", 0);
  1891. if (wsa884x->macro_np) {
  1892. wsa884x->macro_dev =
  1893. of_find_device_by_node(wsa884x->macro_np);
  1894. if (wsa884x->macro_dev) {
  1895. ret = of_property_read_u32_index(
  1896. wsa884x->macro_dev->dev.of_node,
  1897. "qcom,wsa-rloads",
  1898. wsa_dev_index,
  1899. &wsa884x->rload);
  1900. if (ret) {
  1901. dev_err(&pdev->dev,
  1902. "%s: Failed to read wsa rloads\n",
  1903. __func__);
  1904. goto err_mem;
  1905. }
  1906. ret = of_property_read_u32_index(
  1907. wsa884x->macro_dev->dev.of_node,
  1908. "qcom,wsa-bat-cfgs",
  1909. wsa_dev_index,
  1910. &wsa884x->bat_cfg);
  1911. if (ret) {
  1912. dev_err(&pdev->dev,
  1913. "%s: Failed to read wsa bat cfgs\n",
  1914. __func__);
  1915. goto err_mem;
  1916. }
  1917. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1918. "qcom,noise-gate-mode", &noise_gate_mode);
  1919. if (ret) {
  1920. dev_info(&pdev->dev,
  1921. "%s: Failed to read wsa noise gate mode\n",
  1922. __func__);
  1923. wsa884x->noise_gate_mode = IDLE_DETECT;
  1924. } else {
  1925. if (IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1926. wsa884x->noise_gate_mode = noise_gate_mode;
  1927. else
  1928. wsa884x->noise_gate_mode = IDLE_DETECT;
  1929. }
  1930. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1931. "qcom,wsa-system-gains", &sys_gain_size)) {
  1932. dev_err(&pdev->dev,
  1933. "%s: missing wsa-system-gains\n",
  1934. __func__);
  1935. goto err_mem;
  1936. }
  1937. sys_gain_length = sys_gain_size / (2 * sizeof(u32));
  1938. ret = of_property_read_u32_array(
  1939. wsa884x->macro_dev->dev.of_node,
  1940. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1941. sys_gain_length);
  1942. if (ret) {
  1943. dev_err(&pdev->dev,
  1944. "%s: Failed to read wsa system gains\n",
  1945. __func__);
  1946. goto err_mem;
  1947. }
  1948. wsa884x->system_gain = wsa884x->sys_gains[
  1949. wsa884x->dev_mode + wsa_dev_index * 2];
  1950. } else {
  1951. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1952. __func__);
  1953. goto err_mem;
  1954. }
  1955. } else {
  1956. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1957. goto err_mem;
  1958. }
  1959. dev_dbg(component->dev,
  1960. "%s: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n", __func__,
  1961. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1962. ret = wsa884x_validate_dt_configuration_params(component, wsa884x->rload,
  1963. wsa884x->bat_cfg, wsa884x->system_gain);
  1964. if (ret) {
  1965. dev_err(&pdev->dev,
  1966. "%s: invalid dt parameter: Bat_cfg: 0x%x rload: 0x%x, sys_gain: 0x%x\n",
  1967. __func__, wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1968. ret = -EINVAL;
  1969. goto err_mem;
  1970. }
  1971. /* Assume that compander is enabled by default unless it is haptics sku */
  1972. if (wsa884x->variant == WSA8845H)
  1973. wsa884x->comp_enable = false;
  1974. else
  1975. wsa884x->comp_enable = true;
  1976. wsa884x_set_gain_parameters(component);
  1977. wsa884x_set_pbr_parameters(component);
  1978. /* Must write WO registers in a single write */
  1979. wo0_val = (0xC0 | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1980. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1981. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1982. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1983. snd_soc_component_update_bits(component,
  1984. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1985. if (wsa884x->dev_mode == SPEAKER) {
  1986. snd_soc_component_update_bits(component,
  1987. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1988. } else {
  1989. snd_soc_component_update_bits(component,
  1990. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1991. snd_soc_component_update_bits(component,
  1992. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1993. snd_soc_component_update_bits(component,
  1994. REG_FIELD_VALUE(PWM_CLK_CTL,
  1995. PWM_CLK_FREQ_SEL, 0x01));
  1996. }
  1997. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1998. snd_soc_component_update_bits(component,
  1999. REG_FIELD_VALUE(TOP_CTRL1,
  2000. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  2001. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  2002. if (ret) {
  2003. dev_err(&pdev->dev, "Failed to read port params\n");
  2004. goto err;
  2005. }
  2006. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  2007. wsa884x->swr_wsa_port_params);
  2008. mutex_init(&wsa884x->res_lock);
  2009. #ifdef CONFIG_DEBUG_FS
  2010. if (!wsa884x->debugfs_dent) {
  2011. wsa884x->debugfs_dent = debugfs_create_dir(
  2012. dev_name(&pdev->dev), 0);
  2013. if (!IS_ERR(wsa884x->debugfs_dent)) {
  2014. wsa884x->debugfs_peek =
  2015. debugfs_create_file("swrslave_peek",
  2016. S_IFREG | 0444,
  2017. wsa884x->debugfs_dent,
  2018. (void *) pdev,
  2019. &codec_debug_read_ops);
  2020. wsa884x->debugfs_poke =
  2021. debugfs_create_file("swrslave_poke",
  2022. S_IFREG | 0444,
  2023. wsa884x->debugfs_dent,
  2024. (void *) pdev,
  2025. &codec_debug_write_ops);
  2026. wsa884x->debugfs_reg_dump =
  2027. debugfs_create_file(
  2028. "swrslave_reg_dump",
  2029. S_IFREG | 0444,
  2030. wsa884x->debugfs_dent,
  2031. (void *) pdev,
  2032. &codec_debug_dump_ops);
  2033. }
  2034. }
  2035. #endif
  2036. return 0;
  2037. err_mem:
  2038. snd_soc_unregister_component(&pdev->dev);
  2039. if (wsa884x->dai_driver) {
  2040. kfree(wsa884x->dai_driver->name);
  2041. kfree(wsa884x->dai_driver->playback.stream_name);
  2042. devm_kfree(&pdev->dev, wsa884x->dai_driver);
  2043. wsa884x->dai_driver = NULL;
  2044. }
  2045. if (wsa884x->driver) {
  2046. kfree(wsa884x->driver->name);
  2047. devm_kfree(&pdev->dev, wsa884x->driver);
  2048. wsa884x->driver = NULL;
  2049. }
  2050. err_irq:
  2051. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  2052. dev_err:
  2053. if (pin_state_current == false)
  2054. wsa884x_gpio_ctrl(wsa884x, false);
  2055. swr_remove_device(pdev);
  2056. err_supply:
  2057. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2058. wsa884x->regulator,
  2059. wsa884x->num_supplies);
  2060. err:
  2061. swr_set_dev_data(pdev, NULL);
  2062. return ret;
  2063. }
  2064. static int wsa884x_swr_remove(struct swr_device *pdev)
  2065. {
  2066. struct wsa884x_priv *wsa884x;
  2067. wsa884x = swr_get_dev_data(pdev);
  2068. if (!wsa884x) {
  2069. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  2070. return -EINVAL;
  2071. }
  2072. if (wsa884x->register_notifier)
  2073. wsa884x->register_notifier(wsa884x->handle,
  2074. &wsa884x->parent_nblock, false);
  2075. #ifdef CONFIG_DEBUG_FS
  2076. debugfs_remove_recursive(wsa884x->debugfs_dent);
  2077. wsa884x->debugfs_dent = NULL;
  2078. #endif
  2079. mutex_destroy(&wsa884x->res_lock);
  2080. snd_soc_unregister_component(&pdev->dev);
  2081. if (wsa884x->dai_driver) {
  2082. kfree(wsa884x->dai_driver->name);
  2083. kfree(wsa884x->dai_driver->playback.stream_name);
  2084. kfree(wsa884x->dai_driver);
  2085. }
  2086. if (wsa884x->driver) {
  2087. kfree(wsa884x->driver->name);
  2088. kfree(wsa884x->driver);
  2089. }
  2090. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  2091. wsa884x->regulator,
  2092. wsa884x->num_supplies);
  2093. swr_set_dev_data(pdev, NULL);
  2094. return 0;
  2095. }
  2096. #ifdef CONFIG_PM_SLEEP
  2097. static int wsa884x_swr_suspend(struct device *dev)
  2098. {
  2099. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2100. if (!wsa884x) {
  2101. dev_err_ratelimited(dev, "%s: wsa884x private data is NULL\n", __func__);
  2102. return -EINVAL;
  2103. }
  2104. dev_dbg(dev, "%s: system suspend\n", __func__);
  2105. if (wsa884x->dapm_bias_off ||
  2106. (wsa884x->component &&
  2107. (snd_soc_component_get_bias_level(wsa884x->component) ==
  2108. SND_SOC_BIAS_OFF))) {
  2109. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2110. wsa884x->regulator,
  2111. wsa884x->num_supplies,
  2112. true);
  2113. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2114. }
  2115. return 0;
  2116. }
  2117. static int wsa884x_swr_resume(struct device *dev)
  2118. {
  2119. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2120. if (!wsa884x) {
  2121. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2122. return -EINVAL;
  2123. }
  2124. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2125. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2126. wsa884x->regulator,
  2127. wsa884x->num_supplies,
  2128. false);
  2129. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2130. }
  2131. dev_dbg(dev, "%s: system resume\n", __func__);
  2132. return 0;
  2133. }
  2134. #endif /* CONFIG_PM_SLEEP */
  2135. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2136. .suspend_late = wsa884x_swr_suspend,
  2137. .resume_early = wsa884x_swr_resume,
  2138. };
  2139. static const struct swr_device_id wsa884x_swr_id[] = {
  2140. {"wsa884x", 0},
  2141. {"wsa884x_2", 0},
  2142. {}
  2143. };
  2144. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2145. {
  2146. .compatible = "qcom,wsa884x",
  2147. },
  2148. {
  2149. .compatible = "qcom,wsa884x_2",
  2150. },
  2151. {}
  2152. };
  2153. static struct swr_driver wsa884x_swr_driver = {
  2154. .driver = {
  2155. .name = "wsa884x",
  2156. .owner = THIS_MODULE,
  2157. .pm = &wsa884x_swr_pm_ops,
  2158. .of_match_table = wsa884x_swr_dt_match,
  2159. },
  2160. .probe = wsa884x_swr_probe,
  2161. .remove = wsa884x_swr_remove,
  2162. .id_table = wsa884x_swr_id,
  2163. };
  2164. static int __init wsa884x_swr_init(void)
  2165. {
  2166. return swr_driver_register(&wsa884x_swr_driver);
  2167. }
  2168. static void __exit wsa884x_swr_exit(void)
  2169. {
  2170. swr_driver_unregister(&wsa884x_swr_driver);
  2171. }
  2172. module_init(wsa884x_swr_init);
  2173. module_exit(wsa884x_swr_exit);
  2174. MODULE_DESCRIPTION("WSA884x codec driver");
  2175. MODULE_LICENSE("GPL v2");