cam_mem_mgr.c 34 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #include "cam_compat.h"
  13. #include "cam_req_mgr_util.h"
  14. #include "cam_mem_mgr.h"
  15. #include "cam_smmu_api.h"
  16. #include "cam_debug_util.h"
  17. #include "cam_trace.h"
  18. #include "cam_common_util.h"
  19. static struct cam_mem_table tbl;
  20. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  21. static void cam_mem_mgr_print_tbl(void)
  22. {
  23. int i;
  24. uint64_t ms, tmp, hrs, min, sec;
  25. struct timespec64 *ts = NULL;
  26. struct timespec64 current_ts;
  27. ktime_get_real_ts64(&(current_ts));
  28. tmp = current_ts.tv_sec;
  29. ms = (current_ts.tv_nsec) / 1000000;
  30. sec = do_div(tmp, 60);
  31. min = do_div(tmp, 60);
  32. hrs = do_div(tmp, 24);
  33. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  34. hrs, min, sec, ms);
  35. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  36. if (tbl.bufq[i].active) {
  37. ts = &tbl.bufq[i].timestamp;
  38. tmp = ts->tv_sec;
  39. ms = (ts->tv_nsec) / 1000000;
  40. sec = do_div(tmp, 60);
  41. min = do_div(tmp, 60);
  42. hrs = do_div(tmp, 24);
  43. CAM_INFO(CAM_MEM,
  44. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  45. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  46. tbl.bufq[i].len);
  47. }
  48. }
  49. }
  50. static int cam_mem_util_get_dma_dir(uint32_t flags)
  51. {
  52. int rc = -EINVAL;
  53. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  54. rc = DMA_TO_DEVICE;
  55. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  56. rc = DMA_FROM_DEVICE;
  57. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  58. rc = DMA_BIDIRECTIONAL;
  59. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  60. rc = DMA_BIDIRECTIONAL;
  61. return rc;
  62. }
  63. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  64. uintptr_t *vaddr,
  65. size_t *len)
  66. {
  67. int rc = 0;
  68. void *addr;
  69. /*
  70. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  71. * need to be called in pair to avoid stability issue.
  72. */
  73. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  74. if (rc) {
  75. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  76. return rc;
  77. }
  78. addr = dma_buf_vmap(dmabuf);
  79. if (!addr) {
  80. CAM_ERR(CAM_MEM, "kernel map fail");
  81. *vaddr = 0;
  82. *len = 0;
  83. rc = -ENOSPC;
  84. goto fail;
  85. }
  86. *vaddr = (uint64_t)addr;
  87. *len = dmabuf->size;
  88. return 0;
  89. fail:
  90. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  91. return rc;
  92. }
  93. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  94. uint64_t vaddr)
  95. {
  96. int rc = 0;
  97. if (!dmabuf || !vaddr) {
  98. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  99. return -EINVAL;
  100. }
  101. dma_buf_vunmap(dmabuf, (void *)vaddr);
  102. /*
  103. * dma_buf_begin_cpu_access() and
  104. * dma_buf_end_cpu_access() need to be called in pair
  105. * to avoid stability issue.
  106. */
  107. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  108. if (rc) {
  109. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  110. dmabuf);
  111. return rc;
  112. }
  113. return rc;
  114. }
  115. static int cam_mem_mgr_create_debug_fs(void)
  116. {
  117. int rc = 0;
  118. struct dentry *dbgfileptr = NULL;
  119. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  120. if (!dbgfileptr) {
  121. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  122. rc = -ENOENT;
  123. goto end;
  124. }
  125. /* Store parent inode for cleanup in caller */
  126. tbl.dentry = dbgfileptr;
  127. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  128. tbl.dentry, &tbl.alloc_profile_enable);
  129. if (IS_ERR(dbgfileptr)) {
  130. if (PTR_ERR(dbgfileptr) == -ENODEV)
  131. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  132. else
  133. rc = PTR_ERR(dbgfileptr);
  134. }
  135. end:
  136. return rc;
  137. }
  138. int cam_mem_mgr_init(void)
  139. {
  140. int i;
  141. int bitmap_size;
  142. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  143. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  144. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  145. if (!tbl.bitmap)
  146. return -ENOMEM;
  147. tbl.bits = bitmap_size * BITS_PER_BYTE;
  148. bitmap_zero(tbl.bitmap, tbl.bits);
  149. /* We need to reserve slot 0 because 0 is invalid */
  150. set_bit(0, tbl.bitmap);
  151. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  152. tbl.bufq[i].fd = -1;
  153. tbl.bufq[i].buf_handle = -1;
  154. }
  155. mutex_init(&tbl.m_lock);
  156. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  157. cam_mem_mgr_create_debug_fs();
  158. return 0;
  159. }
  160. static int32_t cam_mem_get_slot(void)
  161. {
  162. int32_t idx;
  163. mutex_lock(&tbl.m_lock);
  164. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  165. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  166. mutex_unlock(&tbl.m_lock);
  167. return -ENOMEM;
  168. }
  169. set_bit(idx, tbl.bitmap);
  170. tbl.bufq[idx].active = true;
  171. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  172. mutex_init(&tbl.bufq[idx].q_lock);
  173. mutex_unlock(&tbl.m_lock);
  174. return idx;
  175. }
  176. static void cam_mem_put_slot(int32_t idx)
  177. {
  178. mutex_lock(&tbl.m_lock);
  179. mutex_lock(&tbl.bufq[idx].q_lock);
  180. tbl.bufq[idx].active = false;
  181. tbl.bufq[idx].is_internal = false;
  182. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  183. mutex_unlock(&tbl.bufq[idx].q_lock);
  184. mutex_destroy(&tbl.bufq[idx].q_lock);
  185. clear_bit(idx, tbl.bitmap);
  186. mutex_unlock(&tbl.m_lock);
  187. }
  188. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  189. dma_addr_t *iova_ptr, size_t *len_ptr)
  190. {
  191. int rc = 0, idx;
  192. *len_ptr = 0;
  193. if (!atomic_read(&cam_mem_mgr_state)) {
  194. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  195. return -EINVAL;
  196. }
  197. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  198. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  199. return -ENOENT;
  200. if (!tbl.bufq[idx].active)
  201. return -EAGAIN;
  202. mutex_lock(&tbl.bufq[idx].q_lock);
  203. if (buf_handle != tbl.bufq[idx].buf_handle) {
  204. rc = -EINVAL;
  205. goto handle_mismatch;
  206. }
  207. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  208. rc = cam_smmu_get_stage2_iova(mmu_handle,
  209. tbl.bufq[idx].fd,
  210. iova_ptr,
  211. len_ptr);
  212. else
  213. rc = cam_smmu_get_iova(mmu_handle,
  214. tbl.bufq[idx].fd,
  215. iova_ptr,
  216. len_ptr);
  217. if (rc) {
  218. CAM_ERR(CAM_MEM,
  219. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  220. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  221. goto handle_mismatch;
  222. }
  223. CAM_DBG(CAM_MEM,
  224. "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu",
  225. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  226. handle_mismatch:
  227. mutex_unlock(&tbl.bufq[idx].q_lock);
  228. return rc;
  229. }
  230. EXPORT_SYMBOL(cam_mem_get_io_buf);
  231. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  232. {
  233. int idx;
  234. if (!atomic_read(&cam_mem_mgr_state)) {
  235. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  236. return -EINVAL;
  237. }
  238. if (!atomic_read(&cam_mem_mgr_state)) {
  239. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  240. return -EINVAL;
  241. }
  242. if (!buf_handle || !vaddr_ptr || !len)
  243. return -EINVAL;
  244. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  245. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  246. return -EINVAL;
  247. if (!tbl.bufq[idx].active)
  248. return -EPERM;
  249. if (buf_handle != tbl.bufq[idx].buf_handle)
  250. return -EINVAL;
  251. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  252. return -EINVAL;
  253. if (tbl.bufq[idx].kmdvaddr) {
  254. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  255. *len = tbl.bufq[idx].len;
  256. } else {
  257. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  258. buf_handle);
  259. return -EINVAL;
  260. }
  261. return 0;
  262. }
  263. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  264. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  265. {
  266. int rc = 0, idx;
  267. uint32_t cache_dir;
  268. unsigned long dmabuf_flag = 0;
  269. if (!atomic_read(&cam_mem_mgr_state)) {
  270. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  271. return -EINVAL;
  272. }
  273. if (!cmd)
  274. return -EINVAL;
  275. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  276. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  277. return -EINVAL;
  278. mutex_lock(&tbl.bufq[idx].q_lock);
  279. if (!tbl.bufq[idx].active) {
  280. rc = -EINVAL;
  281. goto end;
  282. }
  283. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  284. rc = -EINVAL;
  285. goto end;
  286. }
  287. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  288. if (rc) {
  289. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  290. goto end;
  291. }
  292. if (dmabuf_flag & ION_FLAG_CACHED) {
  293. switch (cmd->mem_cache_ops) {
  294. case CAM_MEM_CLEAN_CACHE:
  295. cache_dir = DMA_TO_DEVICE;
  296. break;
  297. case CAM_MEM_INV_CACHE:
  298. cache_dir = DMA_FROM_DEVICE;
  299. break;
  300. case CAM_MEM_CLEAN_INV_CACHE:
  301. cache_dir = DMA_BIDIRECTIONAL;
  302. break;
  303. default:
  304. CAM_ERR(CAM_MEM,
  305. "invalid cache ops :%d", cmd->mem_cache_ops);
  306. rc = -EINVAL;
  307. goto end;
  308. }
  309. } else {
  310. CAM_DBG(CAM_MEM, "BUF is not cached");
  311. goto end;
  312. }
  313. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  314. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  315. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  316. if (rc) {
  317. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  318. goto end;
  319. }
  320. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  321. cache_dir);
  322. if (rc) {
  323. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  324. goto end;
  325. }
  326. end:
  327. mutex_unlock(&tbl.bufq[idx].q_lock);
  328. return rc;
  329. }
  330. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  331. static int cam_mem_util_get_dma_buf(size_t len,
  332. unsigned int heap_id_mask,
  333. unsigned int flags,
  334. struct dma_buf **buf)
  335. {
  336. int rc = 0;
  337. if (!buf) {
  338. CAM_ERR(CAM_MEM, "Invalid params");
  339. return -EINVAL;
  340. }
  341. *buf = ion_alloc(len, heap_id_mask, flags);
  342. if (IS_ERR_OR_NULL(*buf))
  343. return -ENOMEM;
  344. return rc;
  345. }
  346. static int cam_mem_util_get_dma_buf_fd(size_t len,
  347. size_t align,
  348. unsigned int heap_id_mask,
  349. unsigned int flags,
  350. struct dma_buf **buf,
  351. int *fd)
  352. {
  353. struct dma_buf *dmabuf = NULL;
  354. int rc = 0;
  355. struct timespec64 ts1, ts2;
  356. long microsec = 0;
  357. if (!buf || !fd) {
  358. CAM_ERR(CAM_MEM, "Invalid params, buf=%pK, fd=%pK", buf, fd);
  359. return -EINVAL;
  360. }
  361. if (tbl.alloc_profile_enable)
  362. CAM_GET_TIMESTAMP(ts1);
  363. *buf = ion_alloc(len, heap_id_mask, flags);
  364. if (IS_ERR_OR_NULL(*buf))
  365. return -ENOMEM;
  366. *fd = dma_buf_fd(*buf, O_CLOEXEC);
  367. if (*fd < 0) {
  368. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  369. rc = -EINVAL;
  370. goto get_fd_fail;
  371. }
  372. /*
  373. * increment the ref count so that ref count becomes 2 here
  374. * when we close fd, refcount becomes 1 and when we do
  375. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  376. */
  377. dmabuf = dma_buf_get(*fd);
  378. if (IS_ERR_OR_NULL(dmabuf)) {
  379. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  380. rc = -EINVAL;
  381. }
  382. if (tbl.alloc_profile_enable) {
  383. CAM_GET_TIMESTAMP(ts2);
  384. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  385. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  386. len, microsec);
  387. }
  388. return rc;
  389. get_fd_fail:
  390. dma_buf_put(*buf);
  391. return rc;
  392. }
  393. static int cam_mem_util_ion_alloc(struct cam_mem_mgr_alloc_cmd *cmd,
  394. struct dma_buf **dmabuf,
  395. int *fd)
  396. {
  397. uint32_t heap_id;
  398. uint32_t ion_flag = 0;
  399. int rc;
  400. if ((cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  401. (cmd->flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  402. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  403. ion_flag |=
  404. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  405. } else if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  406. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  407. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  408. } else {
  409. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  410. ION_HEAP(ION_CAMERA_HEAP_ID);
  411. }
  412. if (cmd->flags & CAM_MEM_FLAG_CACHE)
  413. ion_flag |= ION_FLAG_CACHED;
  414. else
  415. ion_flag &= ~ION_FLAG_CACHED;
  416. rc = cam_mem_util_get_dma_buf_fd(cmd->len,
  417. cmd->align,
  418. heap_id,
  419. ion_flag,
  420. dmabuf,
  421. fd);
  422. return rc;
  423. }
  424. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  425. {
  426. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  427. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  428. CAM_MEM_MMU_MAX_HANDLE);
  429. return -EINVAL;
  430. }
  431. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  432. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  433. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  434. return -EINVAL;
  435. }
  436. return 0;
  437. }
  438. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  439. {
  440. if (!cmd->flags) {
  441. CAM_ERR(CAM_MEM, "Invalid flags");
  442. return -EINVAL;
  443. }
  444. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  445. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  446. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  447. return -EINVAL;
  448. }
  449. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  450. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  451. CAM_ERR(CAM_MEM,
  452. "Kernel mapping in secure mode not allowed, flags=0x%x",
  453. cmd->flags);
  454. return -EINVAL;
  455. }
  456. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  457. CAM_ERR(CAM_MEM,
  458. "Shared memory buffers are not allowed to be mapped");
  459. return -EINVAL;
  460. }
  461. return 0;
  462. }
  463. static int cam_mem_util_map_hw_va(uint32_t flags,
  464. int32_t *mmu_hdls,
  465. int32_t num_hdls,
  466. int fd,
  467. dma_addr_t *hw_vaddr,
  468. size_t *len,
  469. enum cam_smmu_region_id region,
  470. bool is_internal)
  471. {
  472. int i;
  473. int rc = -1;
  474. int dir = cam_mem_util_get_dma_dir(flags);
  475. bool dis_delayed_unmap = false;
  476. if (dir < 0) {
  477. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  478. return dir;
  479. }
  480. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  481. dis_delayed_unmap = true;
  482. CAM_DBG(CAM_MEM,
  483. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  484. fd, flags, dir, num_hdls);
  485. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  486. for (i = 0; i < num_hdls; i++) {
  487. rc = cam_smmu_map_stage2_iova(mmu_hdls[i],
  488. fd,
  489. dir,
  490. hw_vaddr,
  491. len);
  492. if (rc < 0) {
  493. CAM_ERR(CAM_MEM,
  494. "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  495. i, fd, dir, mmu_hdls[i], rc);
  496. goto multi_map_fail;
  497. }
  498. }
  499. } else {
  500. for (i = 0; i < num_hdls; i++) {
  501. rc = cam_smmu_map_user_iova(mmu_hdls[i],
  502. fd,
  503. dis_delayed_unmap,
  504. dir,
  505. (dma_addr_t *)hw_vaddr,
  506. len,
  507. region,
  508. is_internal);
  509. if (rc < 0) {
  510. CAM_ERR(CAM_MEM,
  511. "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d",
  512. i, fd, dir, mmu_hdls[i], region, rc);
  513. goto multi_map_fail;
  514. }
  515. }
  516. }
  517. return rc;
  518. multi_map_fail:
  519. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  520. for (--i; i > 0; i--)
  521. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  522. else
  523. for (--i; i > 0; i--)
  524. cam_smmu_unmap_user_iova(mmu_hdls[i],
  525. fd,
  526. CAM_SMMU_REGION_IO);
  527. return rc;
  528. }
  529. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  530. {
  531. int rc;
  532. int32_t idx;
  533. struct dma_buf *dmabuf = NULL;
  534. int fd = -1;
  535. dma_addr_t hw_vaddr = 0;
  536. size_t len;
  537. uintptr_t kvaddr = 0;
  538. size_t klen;
  539. if (!atomic_read(&cam_mem_mgr_state)) {
  540. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  541. return -EINVAL;
  542. }
  543. if (!cmd) {
  544. CAM_ERR(CAM_MEM, " Invalid argument");
  545. return -EINVAL;
  546. }
  547. len = cmd->len;
  548. rc = cam_mem_util_check_alloc_flags(cmd);
  549. if (rc) {
  550. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  551. cmd->flags, rc);
  552. return rc;
  553. }
  554. rc = cam_mem_util_ion_alloc(cmd,
  555. &dmabuf,
  556. &fd);
  557. if (rc) {
  558. CAM_ERR(CAM_MEM,
  559. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  560. cmd->len, cmd->align, cmd->flags, cmd->num_hdl);
  561. cam_mem_mgr_print_tbl();
  562. return rc;
  563. }
  564. idx = cam_mem_get_slot();
  565. if (idx < 0) {
  566. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  567. rc = -ENOMEM;
  568. goto slot_fail;
  569. }
  570. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  571. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  572. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  573. enum cam_smmu_region_id region;
  574. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  575. region = CAM_SMMU_REGION_IO;
  576. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  577. region = CAM_SMMU_REGION_SHARED;
  578. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  579. region = CAM_SMMU_REGION_SECHEAP;
  580. rc = cam_mem_util_map_hw_va(cmd->flags,
  581. cmd->mmu_hdls,
  582. cmd->num_hdl,
  583. fd,
  584. &hw_vaddr,
  585. &len,
  586. region,
  587. true);
  588. if (rc) {
  589. CAM_ERR(CAM_MEM,
  590. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  591. len, cmd->flags,
  592. fd, region, cmd->num_hdl, rc);
  593. if (rc == -EALREADY) {
  594. if ((size_t)dmabuf->size != len)
  595. rc = -EBADR;
  596. cam_mem_mgr_print_tbl();
  597. }
  598. goto map_hw_fail;
  599. }
  600. }
  601. mutex_lock(&tbl.bufq[idx].q_lock);
  602. tbl.bufq[idx].fd = fd;
  603. tbl.bufq[idx].dma_buf = NULL;
  604. tbl.bufq[idx].flags = cmd->flags;
  605. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  606. tbl.bufq[idx].is_internal = true;
  607. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  608. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  609. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  610. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  611. if (rc) {
  612. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  613. dmabuf, rc);
  614. goto map_kernel_fail;
  615. }
  616. }
  617. tbl.bufq[idx].kmdvaddr = kvaddr;
  618. tbl.bufq[idx].vaddr = hw_vaddr;
  619. tbl.bufq[idx].dma_buf = dmabuf;
  620. tbl.bufq[idx].len = cmd->len;
  621. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  622. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  623. sizeof(int32_t) * cmd->num_hdl);
  624. tbl.bufq[idx].is_imported = false;
  625. mutex_unlock(&tbl.bufq[idx].q_lock);
  626. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  627. cmd->out.fd = tbl.bufq[idx].fd;
  628. cmd->out.vaddr = 0;
  629. CAM_DBG(CAM_MEM,
  630. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  631. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  632. tbl.bufq[idx].len);
  633. return rc;
  634. map_kernel_fail:
  635. mutex_unlock(&tbl.bufq[idx].q_lock);
  636. map_hw_fail:
  637. cam_mem_put_slot(idx);
  638. slot_fail:
  639. dma_buf_put(dmabuf);
  640. return rc;
  641. }
  642. static bool cam_mem_util_is_map_internal(int32_t fd)
  643. {
  644. uint32_t i;
  645. bool is_internal = false;
  646. mutex_lock(&tbl.m_lock);
  647. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  648. if (tbl.bufq[i].fd == fd) {
  649. is_internal = tbl.bufq[i].is_internal;
  650. break;
  651. }
  652. }
  653. mutex_unlock(&tbl.m_lock);
  654. return is_internal;
  655. }
  656. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  657. {
  658. int32_t idx;
  659. int rc;
  660. struct dma_buf *dmabuf;
  661. dma_addr_t hw_vaddr = 0;
  662. size_t len = 0;
  663. bool is_internal = false;
  664. if (!atomic_read(&cam_mem_mgr_state)) {
  665. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  666. return -EINVAL;
  667. }
  668. if (!cmd || (cmd->fd < 0)) {
  669. CAM_ERR(CAM_MEM, "Invalid argument");
  670. return -EINVAL;
  671. }
  672. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  673. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  674. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  675. return -EINVAL;
  676. }
  677. rc = cam_mem_util_check_map_flags(cmd);
  678. if (rc) {
  679. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  680. return rc;
  681. }
  682. dmabuf = dma_buf_get(cmd->fd);
  683. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  684. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  685. return -EINVAL;
  686. }
  687. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  688. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  689. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  690. rc = cam_mem_util_map_hw_va(cmd->flags,
  691. cmd->mmu_hdls,
  692. cmd->num_hdl,
  693. cmd->fd,
  694. &hw_vaddr,
  695. &len,
  696. CAM_SMMU_REGION_IO,
  697. is_internal);
  698. if (rc) {
  699. CAM_ERR(CAM_MEM,
  700. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  701. cmd->flags, cmd->fd, len,
  702. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  703. if (rc == -EALREADY) {
  704. if ((size_t)dmabuf->size != len) {
  705. rc = -EBADR;
  706. cam_mem_mgr_print_tbl();
  707. }
  708. }
  709. goto map_fail;
  710. }
  711. }
  712. idx = cam_mem_get_slot();
  713. if (idx < 0) {
  714. rc = -ENOMEM;
  715. goto map_fail;
  716. }
  717. mutex_lock(&tbl.bufq[idx].q_lock);
  718. tbl.bufq[idx].fd = cmd->fd;
  719. tbl.bufq[idx].dma_buf = NULL;
  720. tbl.bufq[idx].flags = cmd->flags;
  721. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  722. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  723. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  724. tbl.bufq[idx].kmdvaddr = 0;
  725. if (cmd->num_hdl > 0)
  726. tbl.bufq[idx].vaddr = hw_vaddr;
  727. else
  728. tbl.bufq[idx].vaddr = 0;
  729. tbl.bufq[idx].dma_buf = dmabuf;
  730. tbl.bufq[idx].len = len;
  731. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  732. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  733. sizeof(int32_t) * cmd->num_hdl);
  734. tbl.bufq[idx].is_imported = true;
  735. tbl.bufq[idx].is_internal = is_internal;
  736. mutex_unlock(&tbl.bufq[idx].q_lock);
  737. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  738. cmd->out.vaddr = 0;
  739. cmd->out.size = (uint32_t)len;
  740. CAM_DBG(CAM_MEM,
  741. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  742. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  743. tbl.bufq[idx].len);
  744. return rc;
  745. map_fail:
  746. dma_buf_put(dmabuf);
  747. return rc;
  748. }
  749. static int cam_mem_util_unmap_hw_va(int32_t idx,
  750. enum cam_smmu_region_id region,
  751. enum cam_smmu_mapping_client client)
  752. {
  753. int i;
  754. uint32_t flags;
  755. int32_t *mmu_hdls;
  756. int num_hdls;
  757. int fd;
  758. int rc = 0;
  759. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  760. CAM_ERR(CAM_MEM, "Incorrect index");
  761. return -EINVAL;
  762. }
  763. flags = tbl.bufq[idx].flags;
  764. mmu_hdls = tbl.bufq[idx].hdls;
  765. num_hdls = tbl.bufq[idx].num_hdl;
  766. fd = tbl.bufq[idx].fd;
  767. CAM_DBG(CAM_MEM,
  768. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  769. idx, fd, flags, num_hdls, client);
  770. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  771. for (i = 0; i < num_hdls; i++) {
  772. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  773. if (rc < 0) {
  774. CAM_ERR(CAM_MEM,
  775. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  776. i, fd, mmu_hdls[i], rc);
  777. goto unmap_end;
  778. }
  779. }
  780. } else {
  781. for (i = 0; i < num_hdls; i++) {
  782. if (client == CAM_SMMU_MAPPING_USER) {
  783. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  784. fd, region);
  785. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  786. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  787. tbl.bufq[idx].dma_buf, region);
  788. } else {
  789. CAM_ERR(CAM_MEM,
  790. "invalid caller for unmapping : %d",
  791. client);
  792. rc = -EINVAL;
  793. }
  794. if (rc < 0) {
  795. CAM_ERR(CAM_MEM,
  796. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  797. i, fd, mmu_hdls[i], region, rc);
  798. goto unmap_end;
  799. }
  800. }
  801. }
  802. return rc;
  803. unmap_end:
  804. CAM_ERR(CAM_MEM, "unmapping failed");
  805. return rc;
  806. }
  807. static void cam_mem_mgr_unmap_active_buf(int idx)
  808. {
  809. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  810. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  811. region = CAM_SMMU_REGION_SHARED;
  812. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  813. region = CAM_SMMU_REGION_IO;
  814. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  815. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  816. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  817. tbl.bufq[idx].kmdvaddr);
  818. }
  819. static int cam_mem_mgr_cleanup_table(void)
  820. {
  821. int i;
  822. mutex_lock(&tbl.m_lock);
  823. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  824. if (!tbl.bufq[i].active) {
  825. CAM_DBG(CAM_MEM,
  826. "Buffer inactive at idx=%d, continuing", i);
  827. continue;
  828. } else {
  829. CAM_DBG(CAM_MEM,
  830. "Active buffer at idx=%d, possible leak needs unmapping",
  831. i);
  832. cam_mem_mgr_unmap_active_buf(i);
  833. }
  834. mutex_lock(&tbl.bufq[i].q_lock);
  835. if (tbl.bufq[i].dma_buf) {
  836. dma_buf_put(tbl.bufq[i].dma_buf);
  837. tbl.bufq[i].dma_buf = NULL;
  838. }
  839. tbl.bufq[i].fd = -1;
  840. tbl.bufq[i].flags = 0;
  841. tbl.bufq[i].buf_handle = -1;
  842. tbl.bufq[i].vaddr = 0;
  843. tbl.bufq[i].len = 0;
  844. memset(tbl.bufq[i].hdls, 0,
  845. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  846. tbl.bufq[i].num_hdl = 0;
  847. tbl.bufq[i].dma_buf = NULL;
  848. tbl.bufq[i].active = false;
  849. tbl.bufq[i].is_internal = false;
  850. mutex_unlock(&tbl.bufq[i].q_lock);
  851. mutex_destroy(&tbl.bufq[i].q_lock);
  852. }
  853. bitmap_zero(tbl.bitmap, tbl.bits);
  854. /* We need to reserve slot 0 because 0 is invalid */
  855. set_bit(0, tbl.bitmap);
  856. mutex_unlock(&tbl.m_lock);
  857. return 0;
  858. }
  859. void cam_mem_mgr_deinit(void)
  860. {
  861. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  862. cam_mem_mgr_cleanup_table();
  863. debugfs_remove_recursive(tbl.dentry);
  864. mutex_lock(&tbl.m_lock);
  865. bitmap_zero(tbl.bitmap, tbl.bits);
  866. kfree(tbl.bitmap);
  867. tbl.bitmap = NULL;
  868. mutex_unlock(&tbl.m_lock);
  869. mutex_destroy(&tbl.m_lock);
  870. }
  871. static int cam_mem_util_unmap(int32_t idx,
  872. enum cam_smmu_mapping_client client)
  873. {
  874. int rc = 0;
  875. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  876. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  877. CAM_ERR(CAM_MEM, "Incorrect index");
  878. return -EINVAL;
  879. }
  880. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  881. mutex_lock(&tbl.m_lock);
  882. if ((!tbl.bufq[idx].active) &&
  883. (tbl.bufq[idx].vaddr) == 0) {
  884. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  885. idx);
  886. mutex_unlock(&tbl.m_lock);
  887. return 0;
  888. }
  889. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  890. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  891. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  892. tbl.bufq[idx].kmdvaddr);
  893. if (rc)
  894. CAM_ERR(CAM_MEM,
  895. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  896. tbl.bufq[idx].dma_buf,
  897. (void *) tbl.bufq[idx].kmdvaddr);
  898. }
  899. }
  900. /* SHARED flag gets precedence, all other flags after it */
  901. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  902. region = CAM_SMMU_REGION_SHARED;
  903. } else {
  904. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  905. region = CAM_SMMU_REGION_IO;
  906. }
  907. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  908. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  909. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  910. if (cam_mem_util_unmap_hw_va(idx, region, client))
  911. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  912. tbl.bufq[idx].dma_buf);
  913. if (client == CAM_SMMU_MAPPING_KERNEL)
  914. tbl.bufq[idx].dma_buf = NULL;
  915. }
  916. mutex_lock(&tbl.bufq[idx].q_lock);
  917. tbl.bufq[idx].flags = 0;
  918. tbl.bufq[idx].buf_handle = -1;
  919. tbl.bufq[idx].vaddr = 0;
  920. memset(tbl.bufq[idx].hdls, 0,
  921. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  922. CAM_DBG(CAM_MEM,
  923. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  924. idx, tbl.bufq[idx].fd,
  925. tbl.bufq[idx].is_imported,
  926. tbl.bufq[idx].dma_buf);
  927. if (tbl.bufq[idx].dma_buf)
  928. dma_buf_put(tbl.bufq[idx].dma_buf);
  929. tbl.bufq[idx].fd = -1;
  930. tbl.bufq[idx].dma_buf = NULL;
  931. tbl.bufq[idx].is_imported = false;
  932. tbl.bufq[idx].is_internal = false;
  933. tbl.bufq[idx].len = 0;
  934. tbl.bufq[idx].num_hdl = 0;
  935. tbl.bufq[idx].active = false;
  936. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  937. mutex_unlock(&tbl.bufq[idx].q_lock);
  938. mutex_destroy(&tbl.bufq[idx].q_lock);
  939. clear_bit(idx, tbl.bitmap);
  940. mutex_unlock(&tbl.m_lock);
  941. return rc;
  942. }
  943. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  944. {
  945. int idx;
  946. int rc;
  947. if (!atomic_read(&cam_mem_mgr_state)) {
  948. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  949. return -EINVAL;
  950. }
  951. if (!cmd) {
  952. CAM_ERR(CAM_MEM, "Invalid argument");
  953. return -EINVAL;
  954. }
  955. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  956. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  957. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  958. idx);
  959. return -EINVAL;
  960. }
  961. if (!tbl.bufq[idx].active) {
  962. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  963. return -EINVAL;
  964. }
  965. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  966. CAM_ERR(CAM_MEM,
  967. "Released buf handle %d not matching within table %d, idx=%d",
  968. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  969. return -EINVAL;
  970. }
  971. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  972. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  973. return rc;
  974. }
  975. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  976. struct cam_mem_mgr_memory_desc *out)
  977. {
  978. struct dma_buf *buf = NULL;
  979. int ion_fd = -1;
  980. int rc = 0;
  981. uint32_t heap_id;
  982. int32_t ion_flag = 0;
  983. uintptr_t kvaddr;
  984. dma_addr_t iova = 0;
  985. size_t request_len = 0;
  986. uint32_t mem_handle;
  987. int32_t idx;
  988. int32_t smmu_hdl = 0;
  989. int32_t num_hdl = 0;
  990. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  991. if (!atomic_read(&cam_mem_mgr_state)) {
  992. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  993. return -EINVAL;
  994. }
  995. if (!inp || !out) {
  996. CAM_ERR(CAM_MEM, "Invalid params");
  997. return -EINVAL;
  998. }
  999. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1000. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1001. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1002. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1003. return -EINVAL;
  1004. }
  1005. if (inp->flags & CAM_MEM_FLAG_CACHE)
  1006. ion_flag |= ION_FLAG_CACHED;
  1007. else
  1008. ion_flag &= ~ION_FLAG_CACHED;
  1009. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  1010. ION_HEAP(ION_CAMERA_HEAP_ID);
  1011. rc = cam_mem_util_get_dma_buf(inp->size,
  1012. heap_id,
  1013. ion_flag,
  1014. &buf);
  1015. if (rc) {
  1016. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1017. goto ion_fail;
  1018. } else {
  1019. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1020. }
  1021. /*
  1022. * we are mapping kva always here,
  1023. * update flags so that we do unmap properly
  1024. */
  1025. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1026. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1027. if (rc) {
  1028. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1029. goto map_fail;
  1030. }
  1031. if (!inp->smmu_hdl) {
  1032. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1033. rc = -EINVAL;
  1034. goto smmu_fail;
  1035. }
  1036. /* SHARED flag gets precedence, all other flags after it */
  1037. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1038. region = CAM_SMMU_REGION_SHARED;
  1039. } else {
  1040. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1041. region = CAM_SMMU_REGION_IO;
  1042. }
  1043. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1044. buf,
  1045. CAM_SMMU_MAP_RW,
  1046. &iova,
  1047. &request_len,
  1048. region);
  1049. if (rc < 0) {
  1050. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1051. goto smmu_fail;
  1052. }
  1053. smmu_hdl = inp->smmu_hdl;
  1054. num_hdl = 1;
  1055. idx = cam_mem_get_slot();
  1056. if (idx < 0) {
  1057. rc = -ENOMEM;
  1058. goto slot_fail;
  1059. }
  1060. mutex_lock(&tbl.bufq[idx].q_lock);
  1061. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1062. tbl.bufq[idx].dma_buf = buf;
  1063. tbl.bufq[idx].fd = -1;
  1064. tbl.bufq[idx].flags = inp->flags;
  1065. tbl.bufq[idx].buf_handle = mem_handle;
  1066. tbl.bufq[idx].kmdvaddr = kvaddr;
  1067. tbl.bufq[idx].vaddr = iova;
  1068. tbl.bufq[idx].len = inp->size;
  1069. tbl.bufq[idx].num_hdl = num_hdl;
  1070. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1071. sizeof(int32_t));
  1072. tbl.bufq[idx].is_imported = false;
  1073. mutex_unlock(&tbl.bufq[idx].q_lock);
  1074. out->kva = kvaddr;
  1075. out->iova = (uint32_t)iova;
  1076. out->smmu_hdl = smmu_hdl;
  1077. out->mem_handle = mem_handle;
  1078. out->len = inp->size;
  1079. out->region = region;
  1080. return rc;
  1081. slot_fail:
  1082. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1083. buf, region);
  1084. smmu_fail:
  1085. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1086. map_fail:
  1087. dma_buf_put(buf);
  1088. ion_fail:
  1089. return rc;
  1090. }
  1091. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1092. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1093. {
  1094. int32_t idx;
  1095. int rc;
  1096. if (!atomic_read(&cam_mem_mgr_state)) {
  1097. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1098. return -EINVAL;
  1099. }
  1100. if (!inp) {
  1101. CAM_ERR(CAM_MEM, "Invalid argument");
  1102. return -EINVAL;
  1103. }
  1104. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1105. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1106. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1107. return -EINVAL;
  1108. }
  1109. if (!tbl.bufq[idx].active) {
  1110. if (tbl.bufq[idx].vaddr == 0) {
  1111. CAM_ERR(CAM_MEM, "buffer is released already");
  1112. return 0;
  1113. }
  1114. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1115. return -EINVAL;
  1116. }
  1117. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1118. CAM_ERR(CAM_MEM,
  1119. "Released buf handle not matching within table");
  1120. return -EINVAL;
  1121. }
  1122. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1123. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1124. return rc;
  1125. }
  1126. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1127. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1128. enum cam_smmu_region_id region,
  1129. struct cam_mem_mgr_memory_desc *out)
  1130. {
  1131. struct dma_buf *buf = NULL;
  1132. int rc = 0;
  1133. int ion_fd = -1;
  1134. uint32_t heap_id;
  1135. dma_addr_t iova = 0;
  1136. size_t request_len = 0;
  1137. uint32_t mem_handle;
  1138. int32_t idx;
  1139. int32_t smmu_hdl = 0;
  1140. int32_t num_hdl = 0;
  1141. if (!atomic_read(&cam_mem_mgr_state)) {
  1142. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1143. return -EINVAL;
  1144. }
  1145. if (!inp || !out) {
  1146. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1147. return -EINVAL;
  1148. }
  1149. if (!inp->smmu_hdl) {
  1150. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1151. return -EINVAL;
  1152. }
  1153. if (region != CAM_SMMU_REGION_SECHEAP) {
  1154. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1155. return -EINVAL;
  1156. }
  1157. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  1158. ION_HEAP(ION_CAMERA_HEAP_ID);
  1159. rc = cam_mem_util_get_dma_buf(inp->size,
  1160. heap_id,
  1161. 0,
  1162. &buf);
  1163. if (rc) {
  1164. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1165. goto ion_fail;
  1166. } else {
  1167. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1168. }
  1169. rc = cam_smmu_reserve_sec_heap(inp->smmu_hdl,
  1170. buf,
  1171. &iova,
  1172. &request_len);
  1173. if (rc) {
  1174. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1175. goto smmu_fail;
  1176. }
  1177. smmu_hdl = inp->smmu_hdl;
  1178. num_hdl = 1;
  1179. idx = cam_mem_get_slot();
  1180. if (idx < 0) {
  1181. rc = -ENOMEM;
  1182. goto slot_fail;
  1183. }
  1184. mutex_lock(&tbl.bufq[idx].q_lock);
  1185. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1186. tbl.bufq[idx].fd = -1;
  1187. tbl.bufq[idx].dma_buf = buf;
  1188. tbl.bufq[idx].flags = inp->flags;
  1189. tbl.bufq[idx].buf_handle = mem_handle;
  1190. tbl.bufq[idx].kmdvaddr = 0;
  1191. tbl.bufq[idx].vaddr = iova;
  1192. tbl.bufq[idx].len = request_len;
  1193. tbl.bufq[idx].num_hdl = num_hdl;
  1194. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1195. sizeof(int32_t));
  1196. tbl.bufq[idx].is_imported = false;
  1197. mutex_unlock(&tbl.bufq[idx].q_lock);
  1198. out->kva = 0;
  1199. out->iova = (uint32_t)iova;
  1200. out->smmu_hdl = smmu_hdl;
  1201. out->mem_handle = mem_handle;
  1202. out->len = request_len;
  1203. out->region = region;
  1204. return rc;
  1205. slot_fail:
  1206. cam_smmu_release_sec_heap(smmu_hdl);
  1207. smmu_fail:
  1208. dma_buf_put(buf);
  1209. ion_fail:
  1210. return rc;
  1211. }
  1212. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1213. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1214. {
  1215. int32_t idx;
  1216. int rc;
  1217. int32_t smmu_hdl;
  1218. if (!atomic_read(&cam_mem_mgr_state)) {
  1219. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1220. return -EINVAL;
  1221. }
  1222. if (!inp) {
  1223. CAM_ERR(CAM_MEM, "Invalid argument");
  1224. return -EINVAL;
  1225. }
  1226. if (inp->region != CAM_SMMU_REGION_SECHEAP) {
  1227. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1228. return -EINVAL;
  1229. }
  1230. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1231. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1232. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1233. return -EINVAL;
  1234. }
  1235. if (!tbl.bufq[idx].active) {
  1236. if (tbl.bufq[idx].vaddr == 0) {
  1237. CAM_ERR(CAM_MEM, "buffer is released already");
  1238. return 0;
  1239. }
  1240. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1241. return -EINVAL;
  1242. }
  1243. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1244. CAM_ERR(CAM_MEM,
  1245. "Released buf handle not matching within table");
  1246. return -EINVAL;
  1247. }
  1248. if (tbl.bufq[idx].num_hdl != 1) {
  1249. CAM_ERR(CAM_MEM,
  1250. "Sec heap region should have only one smmu hdl");
  1251. return -ENODEV;
  1252. }
  1253. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1254. sizeof(int32_t));
  1255. if (inp->smmu_hdl != smmu_hdl) {
  1256. CAM_ERR(CAM_MEM,
  1257. "Passed SMMU handle doesn't match with internal hdl");
  1258. return -ENODEV;
  1259. }
  1260. rc = cam_smmu_release_sec_heap(inp->smmu_hdl);
  1261. if (rc) {
  1262. CAM_ERR(CAM_MEM,
  1263. "Sec heap region release failed");
  1264. return -ENODEV;
  1265. }
  1266. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1267. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1268. if (rc)
  1269. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1270. return rc;
  1271. }
  1272. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);