hfi.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/slab.h>
  8. #include <linux/random.h>
  9. #include <asm/errno.h>
  10. #include <linux/timer.h>
  11. #include <media/cam_icp.h>
  12. #include <linux/iopoll.h>
  13. #include "cam_io_util.h"
  14. #include "hfi_reg.h"
  15. #include "hfi_sys_defs.h"
  16. #include "hfi_session_defs.h"
  17. #include "hfi_intf.h"
  18. #include "cam_icp_hw_mgr_intf.h"
  19. #include "cam_debug_util.h"
  20. #define HFI_VERSION_INFO_MAJOR_VAL 1
  21. #define HFI_VERSION_INFO_MINOR_VAL 1
  22. #define HFI_VERSION_INFO_STEP_VAL 0
  23. #define HFI_VERSION_INFO_STEP_VAL 0
  24. #define HFI_VERSION_INFO_MAJOR_BMSK 0xFF000000
  25. #define HFI_VERSION_INFO_MAJOR_SHFT 24
  26. #define HFI_VERSION_INFO_MINOR_BMSK 0xFFFF00
  27. #define HFI_VERSION_INFO_MINOR_SHFT 8
  28. #define HFI_VERSION_INFO_STEP_BMSK 0xFF
  29. #define HFI_VERSION_INFO_STEP_SHFT 0
  30. #define HFI_POLL_DELAY_US 100
  31. #define HFI_POLL_TIMEOUT_US 10000
  32. #define HFI_MAX_PC_POLL_TRY 150
  33. #define HFI_POLL_TRY_SLEEP 1
  34. static struct hfi_info *g_hfi;
  35. unsigned int g_icp_mmu_hdl;
  36. static DEFINE_MUTEX(hfi_cmd_q_mutex);
  37. static DEFINE_MUTEX(hfi_msg_q_mutex);
  38. void cam_hfi_queue_dump(void)
  39. {
  40. struct hfi_qtbl *qtbl;
  41. struct hfi_qtbl_hdr *qtbl_hdr;
  42. struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr;
  43. struct hfi_mem_info *hfi_mem = NULL;
  44. uint32_t *read_q, *read_ptr;
  45. int i;
  46. hfi_mem = &g_hfi->map;
  47. if (!hfi_mem) {
  48. CAM_ERR(CAM_HFI, "Unable to dump queues hfi memory is NULL");
  49. return;
  50. }
  51. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  52. qtbl_hdr = &qtbl->q_tbl_hdr;
  53. CAM_DBG(CAM_HFI,
  54. "qtbl: version = %x size = %u num q = %u qhdr_size = %u",
  55. qtbl_hdr->qtbl_version, qtbl_hdr->qtbl_size,
  56. qtbl_hdr->qtbl_num_q, qtbl_hdr->qtbl_qhdr_size);
  57. cmd_q_hdr = &qtbl->q_hdr[Q_CMD];
  58. CAM_DBG(CAM_HFI, "cmd: size = %u r_idx = %u w_idx = %u addr = %x",
  59. cmd_q_hdr->qhdr_q_size, cmd_q_hdr->qhdr_read_idx,
  60. cmd_q_hdr->qhdr_write_idx, hfi_mem->cmd_q.iova);
  61. read_q = (uint32_t *)g_hfi->map.cmd_q.kva;
  62. read_ptr = (uint32_t *)(read_q + 0);
  63. CAM_DBG(CAM_HFI, "CMD Q START");
  64. for (i = 0; i < ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT; i++)
  65. CAM_DBG(CAM_HFI, "Word: %d Data: 0x%08x ", i, read_ptr[i]);
  66. msg_q_hdr = &qtbl->q_hdr[Q_MSG];
  67. CAM_DBG(CAM_HFI, "msg: size = %u r_idx = %u w_idx = %u addr = %x",
  68. msg_q_hdr->qhdr_q_size, msg_q_hdr->qhdr_read_idx,
  69. msg_q_hdr->qhdr_write_idx, hfi_mem->msg_q.iova);
  70. read_q = (uint32_t *)g_hfi->map.msg_q.kva;
  71. read_ptr = (uint32_t *)(read_q + 0);
  72. CAM_DBG(CAM_HFI, "MSG Q START");
  73. for (i = 0; i < ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT; i++)
  74. CAM_DBG(CAM_HFI, "Word: %d Data: 0x%08x ", i, read_ptr[i]);
  75. }
  76. int hfi_write_cmd(void *cmd_ptr)
  77. {
  78. uint32_t size_in_words, empty_space, new_write_idx, read_idx, temp;
  79. uint32_t *write_q, *write_ptr;
  80. struct hfi_qtbl *q_tbl;
  81. struct hfi_q_hdr *q;
  82. int rc = 0;
  83. if (!cmd_ptr) {
  84. CAM_ERR(CAM_HFI, "command is null");
  85. return -EINVAL;
  86. }
  87. mutex_lock(&hfi_cmd_q_mutex);
  88. if (!g_hfi) {
  89. CAM_ERR(CAM_HFI, "HFI interface not setup");
  90. rc = -ENODEV;
  91. goto err;
  92. }
  93. if (g_hfi->hfi_state != HFI_READY ||
  94. !g_hfi->cmd_q_state) {
  95. CAM_ERR(CAM_HFI, "HFI state: %u, cmd q state: %u",
  96. g_hfi->hfi_state, g_hfi->cmd_q_state);
  97. rc = -ENODEV;
  98. goto err;
  99. }
  100. q_tbl = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  101. q = &q_tbl->q_hdr[Q_CMD];
  102. write_q = (uint32_t *)g_hfi->map.cmd_q.kva;
  103. size_in_words = (*(uint32_t *)cmd_ptr) >> BYTE_WORD_SHIFT;
  104. if (!size_in_words) {
  105. CAM_DBG(CAM_HFI, "failed");
  106. rc = -EINVAL;
  107. goto err;
  108. }
  109. read_idx = q->qhdr_read_idx;
  110. empty_space = (q->qhdr_write_idx >= read_idx) ?
  111. (q->qhdr_q_size - (q->qhdr_write_idx - read_idx)) :
  112. (read_idx - q->qhdr_write_idx);
  113. if (empty_space <= size_in_words) {
  114. CAM_ERR(CAM_HFI, "failed: empty space %u, size_in_words %u",
  115. empty_space, size_in_words);
  116. rc = -EIO;
  117. goto err;
  118. }
  119. new_write_idx = q->qhdr_write_idx + size_in_words;
  120. write_ptr = (uint32_t *)(write_q + q->qhdr_write_idx);
  121. if (new_write_idx < q->qhdr_q_size) {
  122. memcpy(write_ptr, (uint8_t *)cmd_ptr,
  123. size_in_words << BYTE_WORD_SHIFT);
  124. } else {
  125. new_write_idx -= q->qhdr_q_size;
  126. temp = (size_in_words - new_write_idx) << BYTE_WORD_SHIFT;
  127. memcpy(write_ptr, (uint8_t *)cmd_ptr, temp);
  128. memcpy(write_q, (uint8_t *)cmd_ptr + temp,
  129. new_write_idx << BYTE_WORD_SHIFT);
  130. }
  131. /*
  132. * To make sure command data in a command queue before
  133. * updating write index
  134. */
  135. wmb();
  136. q->qhdr_write_idx = new_write_idx;
  137. /*
  138. * Before raising interrupt make sure command data is ready for
  139. * firmware to process
  140. */
  141. wmb();
  142. cam_io_w_mb((uint32_t)INTR_ENABLE,
  143. g_hfi->csr_base + HFI_REG_A5_CSR_HOST2ICPINT);
  144. err:
  145. mutex_unlock(&hfi_cmd_q_mutex);
  146. return rc;
  147. }
  148. int hfi_read_message(uint32_t *pmsg, uint8_t q_id,
  149. uint32_t *words_read)
  150. {
  151. struct hfi_qtbl *q_tbl_ptr;
  152. struct hfi_q_hdr *q;
  153. uint32_t new_read_idx, size_in_words, word_diff, temp;
  154. uint32_t *read_q, *read_ptr, *write_ptr;
  155. uint32_t size_upper_bound = 0;
  156. int rc = 0;
  157. if (!pmsg) {
  158. CAM_ERR(CAM_HFI, "Invalid msg");
  159. return -EINVAL;
  160. }
  161. if (q_id > Q_DBG) {
  162. CAM_ERR(CAM_HFI, "Invalid q :%u", q_id);
  163. return -EINVAL;
  164. }
  165. mutex_lock(&hfi_msg_q_mutex);
  166. if (!g_hfi) {
  167. CAM_ERR(CAM_HFI, "hfi not set up yet");
  168. rc = -ENODEV;
  169. goto err;
  170. }
  171. if ((g_hfi->hfi_state != HFI_READY) ||
  172. !g_hfi->msg_q_state) {
  173. CAM_ERR(CAM_HFI, "hfi state: %u, msg q state: %u",
  174. g_hfi->hfi_state, g_hfi->msg_q_state);
  175. rc = -ENODEV;
  176. goto err;
  177. }
  178. q_tbl_ptr = (struct hfi_qtbl *)g_hfi->map.qtbl.kva;
  179. q = &q_tbl_ptr->q_hdr[q_id];
  180. if (q->qhdr_read_idx == q->qhdr_write_idx) {
  181. CAM_DBG(CAM_HFI, "Q not ready, state:%u, r idx:%u, w idx:%u",
  182. g_hfi->hfi_state, q->qhdr_read_idx, q->qhdr_write_idx);
  183. rc = -EIO;
  184. goto err;
  185. }
  186. if (q_id == Q_MSG) {
  187. read_q = (uint32_t *)g_hfi->map.msg_q.kva;
  188. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS;
  189. } else {
  190. read_q = (uint32_t *)g_hfi->map.dbg_q.kva;
  191. size_upper_bound = ICP_HFI_MAX_PKT_SIZE_IN_WORDS;
  192. }
  193. read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx);
  194. write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx);
  195. if (write_ptr > read_ptr)
  196. size_in_words = write_ptr - read_ptr;
  197. else {
  198. word_diff = read_ptr - write_ptr;
  199. if (q_id == Q_MSG)
  200. size_in_words = (ICP_MSG_Q_SIZE_IN_BYTES >>
  201. BYTE_WORD_SHIFT) - word_diff;
  202. else
  203. size_in_words = (ICP_DBG_Q_SIZE_IN_BYTES >>
  204. BYTE_WORD_SHIFT) - word_diff;
  205. }
  206. if ((size_in_words == 0) ||
  207. (size_in_words > size_upper_bound)) {
  208. CAM_ERR(CAM_HFI, "invalid HFI message packet size - 0x%08x",
  209. size_in_words << BYTE_WORD_SHIFT);
  210. q->qhdr_read_idx = q->qhdr_write_idx;
  211. rc = -EIO;
  212. goto err;
  213. }
  214. new_read_idx = q->qhdr_read_idx + size_in_words;
  215. if (new_read_idx < q->qhdr_q_size) {
  216. memcpy(pmsg, read_ptr, size_in_words << BYTE_WORD_SHIFT);
  217. } else {
  218. new_read_idx -= q->qhdr_q_size;
  219. temp = (size_in_words - new_read_idx) << BYTE_WORD_SHIFT;
  220. memcpy(pmsg, read_ptr, temp);
  221. memcpy((uint8_t *)pmsg + temp, read_q,
  222. new_read_idx << BYTE_WORD_SHIFT);
  223. }
  224. q->qhdr_read_idx = new_read_idx;
  225. *words_read = size_in_words;
  226. /* Memory Barrier to make sure message
  227. * queue parameters are updated after read
  228. */
  229. wmb();
  230. err:
  231. mutex_unlock(&hfi_msg_q_mutex);
  232. return rc;
  233. }
  234. int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg)
  235. {
  236. uint8_t *prop;
  237. struct hfi_cmd_prop *dbg_prop;
  238. uint32_t size = 0;
  239. size = sizeof(struct hfi_cmd_prop) +
  240. sizeof(struct hfi_cmd_ubwc_cfg);
  241. CAM_DBG(CAM_HFI,
  242. "size of ubwc %u, ubwc_cfg [rd-0x%x,wr-0x%x]",
  243. size, ubwc_cfg[0], ubwc_cfg[1]);
  244. prop = kzalloc(size, GFP_KERNEL);
  245. if (!prop)
  246. return -ENOMEM;
  247. dbg_prop = (struct hfi_cmd_prop *)prop;
  248. dbg_prop->size = size;
  249. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  250. dbg_prop->num_prop = 1;
  251. dbg_prop->prop_data[0] = HFI_PROP_SYS_UBWC_CFG;
  252. dbg_prop->prop_data[1] = ubwc_cfg[0];
  253. dbg_prop->prop_data[2] = ubwc_cfg[1];
  254. hfi_write_cmd(prop);
  255. kfree(prop);
  256. return 0;
  257. }
  258. int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg,
  259. uint32_t *ubwc_bps_cfg)
  260. {
  261. uint8_t *prop;
  262. struct hfi_cmd_prop *dbg_prop;
  263. uint32_t size = 0;
  264. size = sizeof(struct hfi_cmd_prop) +
  265. sizeof(struct hfi_cmd_ubwc_cfg_ext);
  266. CAM_DBG(CAM_HFI,
  267. "size of ubwc %u, ubwc_ipe_cfg[rd-0x%x,wr-0x%x] ubwc_bps_cfg[rd-0x%x,wr-0x%x]",
  268. size, ubwc_ipe_cfg[0], ubwc_ipe_cfg[1],
  269. ubwc_bps_cfg[0], ubwc_bps_cfg[1]);
  270. prop = kzalloc(size, GFP_KERNEL);
  271. if (!prop)
  272. return -ENOMEM;
  273. dbg_prop = (struct hfi_cmd_prop *)prop;
  274. dbg_prop->size = size;
  275. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  276. dbg_prop->num_prop = 1;
  277. dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG_EX;
  278. dbg_prop->prop_data[1] = ubwc_bps_cfg[0];
  279. dbg_prop->prop_data[2] = ubwc_bps_cfg[1];
  280. dbg_prop->prop_data[3] = ubwc_ipe_cfg[0];
  281. dbg_prop->prop_data[4] = ubwc_ipe_cfg[1];
  282. hfi_write_cmd(prop);
  283. kfree(prop);
  284. return 0;
  285. }
  286. int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info)
  287. {
  288. uint8_t *prop;
  289. struct hfi_cmd_prop *dbg_prop;
  290. uint32_t size = 0;
  291. size = sizeof(struct hfi_cmd_prop) +
  292. sizeof(struct hfi_ipe_bps_pc);
  293. prop = kzalloc(size, GFP_KERNEL);
  294. if (!prop)
  295. return -ENOMEM;
  296. dbg_prop = (struct hfi_cmd_prop *)prop;
  297. dbg_prop->size = size;
  298. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  299. dbg_prop->num_prop = 1;
  300. dbg_prop->prop_data[0] = HFI_PROP_SYS_IPEBPS_PC;
  301. dbg_prop->prop_data[1] = enable;
  302. dbg_prop->prop_data[2] = core_info;
  303. hfi_write_cmd(prop);
  304. kfree(prop);
  305. return 0;
  306. }
  307. int hfi_set_debug_level(u64 a5_dbg_type, uint32_t lvl)
  308. {
  309. uint8_t *prop;
  310. struct hfi_cmd_prop *dbg_prop;
  311. uint32_t size = 0, val;
  312. val = HFI_DEBUG_MSG_LOW |
  313. HFI_DEBUG_MSG_MEDIUM |
  314. HFI_DEBUG_MSG_HIGH |
  315. HFI_DEBUG_MSG_ERROR |
  316. HFI_DEBUG_MSG_FATAL |
  317. HFI_DEBUG_MSG_PERF |
  318. HFI_DEBUG_CFG_WFI |
  319. HFI_DEBUG_CFG_ARM9WD;
  320. if (lvl > val)
  321. return -EINVAL;
  322. size = sizeof(struct hfi_cmd_prop) +
  323. sizeof(struct hfi_debug);
  324. prop = kzalloc(size, GFP_KERNEL);
  325. if (!prop)
  326. return -ENOMEM;
  327. dbg_prop = (struct hfi_cmd_prop *)prop;
  328. dbg_prop->size = size;
  329. dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  330. dbg_prop->num_prop = 1;
  331. dbg_prop->prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  332. dbg_prop->prop_data[1] = lvl;
  333. dbg_prop->prop_data[2] = a5_dbg_type;
  334. hfi_write_cmd(prop);
  335. kfree(prop);
  336. return 0;
  337. }
  338. int hfi_set_fw_dump_level(uint32_t lvl)
  339. {
  340. uint8_t *prop = NULL;
  341. struct hfi_cmd_prop *fw_dump_level_switch_prop = NULL;
  342. uint32_t size = 0;
  343. CAM_DBG(CAM_HFI, "fw dump ENTER");
  344. size = sizeof(struct hfi_cmd_prop) + sizeof(lvl);
  345. prop = kzalloc(size, GFP_KERNEL);
  346. if (!prop)
  347. return -ENOMEM;
  348. fw_dump_level_switch_prop = (struct hfi_cmd_prop *)prop;
  349. fw_dump_level_switch_prop->size = size;
  350. fw_dump_level_switch_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY;
  351. fw_dump_level_switch_prop->num_prop = 1;
  352. fw_dump_level_switch_prop->prop_data[0] = HFI_PROP_SYS_FW_DUMP_CFG;
  353. fw_dump_level_switch_prop->prop_data[1] = lvl;
  354. CAM_DBG(CAM_HFI, "prop->size = %d\n"
  355. "prop->pkt_type = %d\n"
  356. "prop->num_prop = %d\n"
  357. "prop->prop_data[0] = %d\n"
  358. "prop->prop_data[1] = %d\n",
  359. fw_dump_level_switch_prop->size,
  360. fw_dump_level_switch_prop->pkt_type,
  361. fw_dump_level_switch_prop->num_prop,
  362. fw_dump_level_switch_prop->prop_data[0],
  363. fw_dump_level_switch_prop->prop_data[1]);
  364. hfi_write_cmd(prop);
  365. kfree(prop);
  366. return 0;
  367. }
  368. void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size)
  369. {
  370. switch (type) {
  371. case HFI_CMD_SYS_INIT: {
  372. struct hfi_cmd_sys_init init;
  373. memset(&init, 0, sizeof(init));
  374. init.size = sizeof(struct hfi_cmd_sys_init);
  375. init.pkt_type = type;
  376. hfi_write_cmd(&init);
  377. }
  378. break;
  379. case HFI_CMD_SYS_PC_PREP: {
  380. struct hfi_cmd_pc_prep prep;
  381. prep.size = sizeof(struct hfi_cmd_pc_prep);
  382. prep.pkt_type = type;
  383. hfi_write_cmd(&prep);
  384. }
  385. break;
  386. case HFI_CMD_SYS_SET_PROPERTY: {
  387. struct hfi_cmd_prop prop;
  388. if ((uint32_t)data == (uint32_t)HFI_PROP_SYS_DEBUG_CFG) {
  389. prop.size = sizeof(struct hfi_cmd_prop);
  390. prop.pkt_type = type;
  391. prop.num_prop = 1;
  392. prop.prop_data[0] = HFI_PROP_SYS_DEBUG_CFG;
  393. hfi_write_cmd(&prop);
  394. }
  395. }
  396. break;
  397. case HFI_CMD_SYS_GET_PROPERTY:
  398. break;
  399. case HFI_CMD_SYS_PING: {
  400. struct hfi_cmd_ping_pkt ping;
  401. ping.size = sizeof(struct hfi_cmd_ping_pkt);
  402. ping.pkt_type = type;
  403. ping.user_data = (uint64_t)data;
  404. hfi_write_cmd(&ping);
  405. }
  406. break;
  407. case HFI_CMD_SYS_RESET: {
  408. struct hfi_cmd_sys_reset_pkt reset;
  409. reset.size = sizeof(struct hfi_cmd_sys_reset_pkt);
  410. reset.pkt_type = type;
  411. reset.user_data = (uint64_t)data;
  412. hfi_write_cmd(&reset);
  413. }
  414. break;
  415. case HFI_CMD_IPEBPS_CREATE_HANDLE: {
  416. struct hfi_cmd_create_handle handle;
  417. handle.size = sizeof(struct hfi_cmd_create_handle);
  418. handle.pkt_type = type;
  419. handle.handle_type = (uint32_t)data;
  420. handle.user_data1 = 0;
  421. hfi_write_cmd(&handle);
  422. }
  423. break;
  424. case HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT:
  425. break;
  426. default:
  427. CAM_ERR(CAM_HFI, "command not supported :%d", type);
  428. break;
  429. }
  430. }
  431. int hfi_get_hw_caps(void *query_buf)
  432. {
  433. int i = 0;
  434. struct cam_icp_query_cap_cmd *query_cmd = NULL;
  435. if (!query_buf) {
  436. CAM_ERR(CAM_HFI, "query buf is NULL");
  437. return -EINVAL;
  438. }
  439. query_cmd = (struct cam_icp_query_cap_cmd *)query_buf;
  440. query_cmd->fw_version.major = 0x12;
  441. query_cmd->fw_version.minor = 0x12;
  442. query_cmd->fw_version.revision = 0x12;
  443. query_cmd->api_version.major = 0x13;
  444. query_cmd->api_version.minor = 0x13;
  445. query_cmd->api_version.revision = 0x13;
  446. query_cmd->num_ipe = 2;
  447. query_cmd->num_bps = 1;
  448. for (i = 0; i < CAM_ICP_DEV_TYPE_MAX; i++) {
  449. query_cmd->dev_ver[i].dev_type = i;
  450. query_cmd->dev_ver[i].hw_ver.major = 0x34 + i;
  451. query_cmd->dev_ver[i].hw_ver.minor = 0x34 + i;
  452. query_cmd->dev_ver[i].hw_ver.incr = 0x34 + i;
  453. }
  454. return 0;
  455. }
  456. void cam_hfi_disable_cpu(void __iomem *icp_base)
  457. {
  458. uint32_t data;
  459. uint32_t val;
  460. uint32_t try = 0;
  461. while (try < HFI_MAX_PC_POLL_TRY) {
  462. data = cam_io_r_mb(icp_base + HFI_REG_A5_CSR_A5_STATUS);
  463. CAM_DBG(CAM_HFI, "wfi status = %x\n", (int)data);
  464. if (data & ICP_CSR_A5_STATUS_WFI)
  465. break;
  466. /* Need to poll here to confirm that FW is going trigger wfi
  467. * and Host can the proceed. No interrupt is expected from FW
  468. * at this time.
  469. */
  470. usleep_range(HFI_POLL_TRY_SLEEP * 1000,
  471. (HFI_POLL_TRY_SLEEP * 1000) + 1000);
  472. try++;
  473. }
  474. val = cam_io_r(icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  475. val &= ~(ICP_FLAG_CSR_A5_EN | ICP_FLAG_CSR_WAKE_UP_EN);
  476. cam_io_w_mb(val, icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  477. val = cam_io_r(icp_base + HFI_REG_A5_CSR_NSEC_RESET);
  478. cam_io_w_mb(val, icp_base + HFI_REG_A5_CSR_NSEC_RESET);
  479. cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_RESET,
  480. icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
  481. cam_io_w_mb((uint32_t)INTR_DISABLE,
  482. icp_base + HFI_REG_A5_CSR_A2HOSTINTEN);
  483. }
  484. void cam_hfi_enable_cpu(void __iomem *icp_base)
  485. {
  486. cam_io_w_mb((uint32_t)ICP_FLAG_CSR_A5_EN,
  487. icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  488. cam_io_w_mb((uint32_t)0x10, icp_base + HFI_REG_A5_CSR_NSEC_RESET);
  489. }
  490. int cam_hfi_resume(struct hfi_mem_info *hfi_mem,
  491. void __iomem *icp_base, bool debug)
  492. {
  493. int rc = 0;
  494. uint32_t data;
  495. uint32_t fw_version, status = 0;
  496. cam_hfi_enable_cpu(icp_base);
  497. g_hfi->csr_base = icp_base;
  498. if (debug) {
  499. cam_io_w_mb(ICP_FLAG_A5_CTRL_DBG_EN,
  500. (icp_base + HFI_REG_A5_CSR_A5_CONTROL));
  501. /* Barrier needed as next write should be done after
  502. * sucessful previous write. Next write enable clock
  503. * gating
  504. */
  505. wmb();
  506. cam_io_w_mb((uint32_t)ICP_FLAG_A5_CTRL_EN,
  507. icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  508. } else {
  509. cam_io_w_mb((uint32_t)ICP_FLAG_A5_CTRL_EN,
  510. icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  511. }
  512. if (readl_poll_timeout(icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE,
  513. status, status == ICP_INIT_RESP_SUCCESS,
  514. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US)) {
  515. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  516. status);
  517. return -ETIMEDOUT;
  518. }
  519. cam_io_w_mb((uint32_t)(INTR_ENABLE|INTR_ENABLE_WD0),
  520. icp_base + HFI_REG_A5_CSR_A2HOSTINTEN);
  521. fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION);
  522. CAM_DBG(CAM_HFI, "fw version : [%x]", fw_version);
  523. data = cam_io_r(icp_base + HFI_REG_A5_CSR_A5_STATUS);
  524. CAM_DBG(CAM_HFI, "wfi status = %x", (int)data);
  525. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, icp_base + HFI_REG_QTBL_PTR);
  526. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  527. icp_base + HFI_REG_SFR_PTR);
  528. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  529. icp_base + HFI_REG_SHARED_MEM_PTR);
  530. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  531. icp_base + HFI_REG_SHARED_MEM_SIZE);
  532. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  533. icp_base + HFI_REG_UNCACHED_HEAP_PTR);
  534. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  535. icp_base + HFI_REG_UNCACHED_HEAP_SIZE);
  536. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  537. icp_base + HFI_REG_QDSS_IOVA);
  538. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  539. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  540. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  541. icp_base + HFI_REG_IO_REGION_IOVA);
  542. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  543. icp_base + HFI_REG_IO_REGION_SIZE);
  544. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  545. icp_base + HFI_REG_IO2_REGION_IOVA);
  546. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  547. icp_base + HFI_REG_IO2_REGION_SIZE);
  548. CAM_INFO(CAM_HFI, "Resume IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  549. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  550. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  551. return rc;
  552. }
  553. int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem,
  554. void __iomem *icp_base, bool debug)
  555. {
  556. int rc = 0;
  557. struct hfi_qtbl *qtbl;
  558. struct hfi_qtbl_hdr *qtbl_hdr;
  559. struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr;
  560. uint32_t hw_version, fw_version, status = 0;
  561. struct sfr_buf *sfr_buffer;
  562. mutex_lock(&hfi_cmd_q_mutex);
  563. mutex_lock(&hfi_msg_q_mutex);
  564. if (!g_hfi) {
  565. g_hfi = kzalloc(sizeof(struct hfi_info), GFP_KERNEL);
  566. if (!g_hfi) {
  567. rc = -ENOMEM;
  568. goto alloc_fail;
  569. }
  570. }
  571. if (g_hfi->hfi_state != HFI_DEINIT) {
  572. CAM_ERR(CAM_HFI, "hfi_init: invalid state");
  573. return -EINVAL;
  574. }
  575. memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map));
  576. g_hfi->hfi_state = HFI_DEINIT;
  577. if (debug) {
  578. cam_io_w_mb(
  579. (uint32_t)(ICP_FLAG_CSR_A5_EN | ICP_FLAG_CSR_WAKE_UP_EN |
  580. ICP_CSR_EDBGRQ | ICP_CSR_DBGSWENABLE),
  581. icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  582. msleep(100);
  583. cam_io_w_mb((uint32_t)(ICP_FLAG_CSR_A5_EN |
  584. ICP_FLAG_CSR_WAKE_UP_EN | ICP_CSR_EN_CLKGATE_WFI),
  585. icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  586. } else {
  587. /* Due to hardware bug in V1 ICP clock gating has to be
  588. * disabled, this is supposed to be fixed in V-2. But enabling
  589. * the clock gating is causing the firmware hang, hence
  590. * disabling the clock gating on both V1 and V2 until the
  591. * hardware team root causes this
  592. */
  593. cam_io_w_mb((uint32_t)ICP_FLAG_CSR_A5_EN |
  594. ICP_FLAG_CSR_WAKE_UP_EN |
  595. ICP_CSR_EN_CLKGATE_WFI,
  596. icp_base + HFI_REG_A5_CSR_A5_CONTROL);
  597. }
  598. qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva;
  599. qtbl_hdr = &qtbl->q_tbl_hdr;
  600. qtbl_hdr->qtbl_version = 0xFFFFFFFF;
  601. qtbl_hdr->qtbl_size = sizeof(struct hfi_qtbl);
  602. qtbl_hdr->qtbl_qhdr0_offset = sizeof(struct hfi_qtbl_hdr);
  603. qtbl_hdr->qtbl_qhdr_size = sizeof(struct hfi_q_hdr);
  604. qtbl_hdr->qtbl_num_q = ICP_HFI_NUMBER_OF_QS;
  605. qtbl_hdr->qtbl_num_active_q = ICP_HFI_NUMBER_OF_QS;
  606. /* setup host-to-firmware command queue */
  607. cmd_q_hdr = &qtbl->q_hdr[Q_CMD];
  608. cmd_q_hdr->qhdr_status = QHDR_ACTIVE;
  609. cmd_q_hdr->qhdr_start_addr = hfi_mem->cmd_q.iova;
  610. cmd_q_hdr->qhdr_q_size = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  611. cmd_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  612. cmd_q_hdr->qhdr_pkt_drop_cnt = RESET;
  613. cmd_q_hdr->qhdr_read_idx = RESET;
  614. cmd_q_hdr->qhdr_write_idx = RESET;
  615. /* setup firmware-to-Host message queue */
  616. msg_q_hdr = &qtbl->q_hdr[Q_MSG];
  617. msg_q_hdr->qhdr_status = QHDR_ACTIVE;
  618. msg_q_hdr->qhdr_start_addr = hfi_mem->msg_q.iova;
  619. msg_q_hdr->qhdr_q_size = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  620. msg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  621. msg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  622. msg_q_hdr->qhdr_read_idx = RESET;
  623. msg_q_hdr->qhdr_write_idx = RESET;
  624. /* setup firmware-to-Host message queue */
  625. dbg_q_hdr = &qtbl->q_hdr[Q_DBG];
  626. dbg_q_hdr->qhdr_status = QHDR_ACTIVE;
  627. dbg_q_hdr->qhdr_start_addr = hfi_mem->dbg_q.iova;
  628. dbg_q_hdr->qhdr_q_size = ICP_DBG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT;
  629. dbg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT;
  630. dbg_q_hdr->qhdr_pkt_drop_cnt = RESET;
  631. dbg_q_hdr->qhdr_read_idx = RESET;
  632. dbg_q_hdr->qhdr_write_idx = RESET;
  633. sfr_buffer = (struct sfr_buf *)hfi_mem->sfr_buf.kva;
  634. sfr_buffer->size = ICP_MSG_SFR_SIZE_IN_BYTES;
  635. switch (event_driven_mode) {
  636. case INTR_MODE:
  637. cmd_q_hdr->qhdr_type = Q_CMD;
  638. cmd_q_hdr->qhdr_rx_wm = SET;
  639. cmd_q_hdr->qhdr_tx_wm = SET;
  640. cmd_q_hdr->qhdr_rx_req = SET;
  641. cmd_q_hdr->qhdr_tx_req = RESET;
  642. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  643. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  644. msg_q_hdr->qhdr_type = Q_MSG;
  645. msg_q_hdr->qhdr_rx_wm = SET;
  646. msg_q_hdr->qhdr_tx_wm = SET;
  647. msg_q_hdr->qhdr_rx_req = SET;
  648. msg_q_hdr->qhdr_tx_req = RESET;
  649. msg_q_hdr->qhdr_rx_irq_status = RESET;
  650. msg_q_hdr->qhdr_tx_irq_status = RESET;
  651. dbg_q_hdr->qhdr_type = Q_DBG;
  652. dbg_q_hdr->qhdr_rx_wm = SET;
  653. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  654. dbg_q_hdr->qhdr_rx_req = RESET;
  655. dbg_q_hdr->qhdr_tx_req = RESET;
  656. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  657. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  658. break;
  659. case POLL_MODE:
  660. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_POLL_MODE_2 |
  661. RX_EVENT_POLL_MODE_2;
  662. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_POLL_MODE_2 |
  663. RX_EVENT_POLL_MODE_2;
  664. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_POLL_MODE_2 |
  665. RX_EVENT_POLL_MODE_2;
  666. break;
  667. case WM_MODE:
  668. cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_DRIVEN_MODE_2 |
  669. RX_EVENT_DRIVEN_MODE_2;
  670. cmd_q_hdr->qhdr_rx_wm = SET;
  671. cmd_q_hdr->qhdr_tx_wm = SET;
  672. cmd_q_hdr->qhdr_rx_req = RESET;
  673. cmd_q_hdr->qhdr_tx_req = SET;
  674. cmd_q_hdr->qhdr_rx_irq_status = RESET;
  675. cmd_q_hdr->qhdr_tx_irq_status = RESET;
  676. msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_DRIVEN_MODE_2 |
  677. RX_EVENT_DRIVEN_MODE_2;
  678. msg_q_hdr->qhdr_rx_wm = SET;
  679. msg_q_hdr->qhdr_tx_wm = SET;
  680. msg_q_hdr->qhdr_rx_req = SET;
  681. msg_q_hdr->qhdr_tx_req = RESET;
  682. msg_q_hdr->qhdr_rx_irq_status = RESET;
  683. msg_q_hdr->qhdr_tx_irq_status = RESET;
  684. dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_DRIVEN_MODE_2 |
  685. RX_EVENT_DRIVEN_MODE_2;
  686. dbg_q_hdr->qhdr_rx_wm = SET;
  687. dbg_q_hdr->qhdr_tx_wm = SET_WM;
  688. dbg_q_hdr->qhdr_rx_req = RESET;
  689. dbg_q_hdr->qhdr_tx_req = RESET;
  690. dbg_q_hdr->qhdr_rx_irq_status = RESET;
  691. dbg_q_hdr->qhdr_tx_irq_status = RESET;
  692. break;
  693. default:
  694. CAM_ERR(CAM_HFI, "Invalid event driven mode :%u",
  695. event_driven_mode);
  696. break;
  697. }
  698. cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova,
  699. icp_base + HFI_REG_QTBL_PTR);
  700. cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova,
  701. icp_base + HFI_REG_SFR_PTR);
  702. cam_io_w_mb((uint32_t)hfi_mem->shmem.iova,
  703. icp_base + HFI_REG_SHARED_MEM_PTR);
  704. cam_io_w_mb((uint32_t)hfi_mem->shmem.len,
  705. icp_base + HFI_REG_SHARED_MEM_SIZE);
  706. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova,
  707. icp_base + HFI_REG_UNCACHED_HEAP_PTR);
  708. cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len,
  709. icp_base + HFI_REG_UNCACHED_HEAP_SIZE);
  710. cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET,
  711. icp_base + HFI_REG_HOST_ICP_INIT_REQUEST);
  712. cam_io_w_mb((uint32_t)hfi_mem->qdss.iova,
  713. icp_base + HFI_REG_QDSS_IOVA);
  714. cam_io_w_mb((uint32_t)hfi_mem->qdss.len,
  715. icp_base + HFI_REG_QDSS_IOVA_SIZE);
  716. cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova,
  717. icp_base + HFI_REG_IO_REGION_IOVA);
  718. cam_io_w_mb((uint32_t)hfi_mem->io_mem.len,
  719. icp_base + HFI_REG_IO_REGION_SIZE);
  720. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova,
  721. icp_base + HFI_REG_IO2_REGION_IOVA);
  722. cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len,
  723. icp_base + HFI_REG_IO2_REGION_SIZE);
  724. CAM_INFO(CAM_HFI, "Init IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]",
  725. hfi_mem->io_mem.iova, hfi_mem->io_mem.len,
  726. hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len);
  727. if (readl_poll_timeout(icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE,
  728. status, status == ICP_INIT_RESP_SUCCESS,
  729. HFI_POLL_DELAY_US, HFI_POLL_TIMEOUT_US)) {
  730. CAM_ERR(CAM_HFI, "response poll timed out: status=0x%08x",
  731. status);
  732. rc = -ETIMEDOUT;
  733. goto regions_fail;
  734. }
  735. hw_version = cam_io_r(icp_base + HFI_REG_A5_HW_VERSION);
  736. fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION);
  737. CAM_DBG(CAM_HFI, "hw version : : [%x], fw version : [%x]",
  738. hw_version, fw_version);
  739. g_hfi->csr_base = icp_base;
  740. g_hfi->hfi_state = HFI_READY;
  741. g_hfi->cmd_q_state = true;
  742. g_hfi->msg_q_state = true;
  743. cam_io_w_mb((uint32_t)(INTR_ENABLE|INTR_ENABLE_WD0),
  744. icp_base + HFI_REG_A5_CSR_A2HOSTINTEN);
  745. mutex_unlock(&hfi_cmd_q_mutex);
  746. mutex_unlock(&hfi_msg_q_mutex);
  747. return rc;
  748. regions_fail:
  749. kfree(g_hfi);
  750. g_hfi = NULL;
  751. alloc_fail:
  752. mutex_unlock(&hfi_cmd_q_mutex);
  753. mutex_unlock(&hfi_msg_q_mutex);
  754. return rc;
  755. }
  756. void cam_hfi_deinit(void __iomem *icp_base)
  757. {
  758. mutex_lock(&hfi_cmd_q_mutex);
  759. mutex_lock(&hfi_msg_q_mutex);
  760. if (!g_hfi) {
  761. CAM_ERR(CAM_HFI, "hfi path not established yet");
  762. goto err;
  763. }
  764. g_hfi->cmd_q_state = false;
  765. g_hfi->msg_q_state = false;
  766. kzfree(g_hfi);
  767. g_hfi = NULL;
  768. err:
  769. mutex_unlock(&hfi_cmd_q_mutex);
  770. mutex_unlock(&hfi_msg_q_mutex);
  771. }