hfi_reg.h 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _CAM_HFI_REG_H_
  6. #define _CAM_HFI_REG_H_
  7. #include <linux/types.h>
  8. #include "hfi_intf.h"
  9. /* start of ICP CSR registers */
  10. #define HFI_REG_A5_HW_VERSION 0x0
  11. #define HFI_REG_A5_CSR_NSEC_RESET 0x4
  12. #define HFI_REG_A5_CSR_A5_CONTROL 0x8
  13. #define HFI_REG_A5_CSR_ETM 0xC
  14. #define HFI_REG_A5_CSR_A2HOSTINTEN 0x10
  15. #define HFI_REG_A5_CSR_A2HOSTINT 0x14
  16. #define HFI_REG_A5_CSR_A2HOSTINTCLR 0x18
  17. #define HFI_REG_A5_CSR_A2HOSTINTSTATUS 0x1C
  18. #define HFI_REG_A5_CSR_A2HOSTINTSET 0x20
  19. #define HFI_REG_A5_CSR_HOST2ICPINT 0x30
  20. #define HFI_REG_A5_CSR_A5_STATUS 0x200
  21. #define HFI_REG_A5_QGIC2_LM_ID 0x204
  22. #define HFI_REG_A5_SPARE 0x400
  23. /* general purpose registers from */
  24. #define HFI_REG_FW_VERSION 0x44
  25. #define HFI_REG_HOST_ICP_INIT_REQUEST 0x48
  26. #define HFI_REG_ICP_HOST_INIT_RESPONSE 0x4C
  27. #define HFI_REG_SHARED_MEM_PTR 0x50
  28. #define HFI_REG_SHARED_MEM_SIZE 0x54
  29. #define HFI_REG_QTBL_PTR 0x58
  30. #define HFI_REG_UNCACHED_HEAP_PTR 0x5C
  31. #define HFI_REG_UNCACHED_HEAP_SIZE 0x60
  32. #define HFI_REG_QDSS_IOVA 0x6C
  33. #define HFI_REG_SFR_PTR 0x68
  34. #define HFI_REG_QDSS_IOVA_SIZE 0x70
  35. #define HFI_REG_IO_REGION_IOVA 0x74
  36. #define HFI_REG_IO_REGION_SIZE 0x78
  37. #define HFI_REG_IO2_REGION_IOVA 0x7C
  38. #define HFI_REG_IO2_REGION_SIZE 0x80
  39. /* end of ICP CSR registers */
  40. /* flags for ICP CSR registers */
  41. #define ICP_FLAG_CSR_WAKE_UP_EN (1 << 4)
  42. #define ICP_FLAG_CSR_A5_EN (1 << 9)
  43. #define ICP_CSR_EN_CLKGATE_WFI (1 << 12)
  44. #define ICP_CSR_EDBGRQ (1 << 14)
  45. #define ICP_CSR_DBGSWENABLE (1 << 22)
  46. #define ICP_CSR_A5_STATUS_WFI (1 << 7)
  47. #define ICP_FLAG_A5_CTRL_DBG_EN (ICP_FLAG_CSR_WAKE_UP_EN|\
  48. ICP_FLAG_CSR_A5_EN|\
  49. ICP_CSR_EDBGRQ|\
  50. ICP_CSR_DBGSWENABLE)
  51. #define ICP_FLAG_A5_CTRL_EN (ICP_FLAG_CSR_WAKE_UP_EN|\
  52. ICP_FLAG_CSR_A5_EN|\
  53. ICP_CSR_EN_CLKGATE_WFI)
  54. /* start of Queue table and queues */
  55. #define MAX_ICP_HFI_QUEUES 4
  56. #define ICP_QHDR_TX_TYPE_MASK 0xFF000000
  57. #define ICP_QHDR_RX_TYPE_MASK 0x00FF0000
  58. #define ICP_QHDR_PRI_TYPE_MASK 0x0000FF00
  59. #define ICP_QHDR_Q_ID_MASK 0x000000FF
  60. #define ICP_CMD_Q_SIZE_IN_BYTES 4096
  61. #define ICP_MSG_Q_SIZE_IN_BYTES 4096
  62. #define ICP_DBG_Q_SIZE_IN_BYTES 102400
  63. #define ICP_MSG_SFR_SIZE_IN_BYTES 4096
  64. #define ICP_SHARED_MEM_IN_BYTES (1024 * 1024)
  65. #define ICP_UNCACHED_HEAP_SIZE_IN_BYTES (2 * 1024 * 1024)
  66. #define ICP_HFI_MAX_PKT_SIZE_IN_WORDS 25600
  67. #define ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS 1024
  68. #define ICP_HFI_QTBL_HOSTID1 0x01000000
  69. #define ICP_HFI_QTBL_STATUS_ENABLED 0x00000001
  70. #define ICP_HFI_NUMBER_OF_QS 3
  71. #define ICP_HFI_NUMBER_OF_ACTIVE_QS 3
  72. #define ICP_HFI_QTBL_OFFSET 0
  73. #define ICP_HFI_VAR_SIZE_PKT 0
  74. #define ICP_HFI_MAX_MSG_SIZE_IN_WORDS 128
  75. /* Queue Header type masks. Use these to access bitfields in qhdr_type */
  76. #define HFI_MASK_QHDR_TX_TYPE 0xFF000000
  77. #define HFI_MASK_QHDR_RX_TYPE 0x00FF0000
  78. #define HFI_MASK_QHDR_PRI_TYPE 0x0000FF00
  79. #define HFI_MASK_QHDR_Q_ID_TYPE 0x000000FF
  80. #define TX_EVENT_DRIVEN_MODE_1 0
  81. #define RX_EVENT_DRIVEN_MODE_1 0
  82. #define TX_EVENT_DRIVEN_MODE_2 0x01000000
  83. #define RX_EVENT_DRIVEN_MODE_2 0x00010000
  84. #define TX_EVENT_POLL_MODE_2 0x02000000
  85. #define RX_EVENT_POLL_MODE_2 0x00020000
  86. #define U32_OFFSET 0x1
  87. #define BYTE_WORD_SHIFT 2
  88. /**
  89. * @INVALID: Invalid state
  90. * @HFI_DEINIT: HFI is not initialized yet
  91. * @HFI_INIT: HFI is initialized
  92. * @HFI_READY: HFI is ready to send/receive commands/messages
  93. */
  94. enum hfi_state {
  95. HFI_DEINIT,
  96. HFI_INIT,
  97. HFI_READY
  98. };
  99. /**
  100. * @RESET: init success
  101. * @SET: init failed
  102. */
  103. enum reg_settings {
  104. RESET,
  105. SET,
  106. SET_WM = 1024
  107. };
  108. /**
  109. * @INTR_DISABLE: Disable interrupt
  110. * @INTR_ENABLE: Enable interrupt
  111. * @INTR_ENABLE_WD0: Enable WD0
  112. * @INTR_ENABLE_WD1: Enable WD1
  113. */
  114. enum intr_status {
  115. INTR_DISABLE,
  116. INTR_ENABLE,
  117. INTR_ENABLE_WD0,
  118. INTR_ENABLE_WD1 = 0x4
  119. };
  120. /**
  121. * @ICP_INIT_RESP_RESET: reset init state
  122. * @ICP_INIT_RESP_SUCCESS: init success
  123. * @ICP_INIT_RESP_FAILED: init failed
  124. */
  125. enum host_init_resp {
  126. ICP_INIT_RESP_RESET,
  127. ICP_INIT_RESP_SUCCESS,
  128. ICP_INIT_RESP_FAILED
  129. };
  130. /**
  131. * @ICP_INIT_REQUEST_RESET: reset init request
  132. * @ICP_INIT_REQUEST_SET: set init request
  133. */
  134. enum host_init_request {
  135. ICP_INIT_REQUEST_RESET,
  136. ICP_INIT_REQUEST_SET
  137. };
  138. /**
  139. * @QHDR_INACTIVE: Queue is inactive
  140. * @QHDR_ACTIVE: Queue is active
  141. */
  142. enum qhdr_status {
  143. QHDR_INACTIVE,
  144. QHDR_ACTIVE
  145. };
  146. /**
  147. * @INTR_MODE: event driven mode 1, each send and receive generates interrupt
  148. * @WM_MODE: event driven mode 2, interrupts based on watermark mechanism
  149. * @POLL_MODE: poll method
  150. */
  151. enum qhdr_event_drv_type {
  152. INTR_MODE,
  153. WM_MODE,
  154. POLL_MODE
  155. };
  156. /**
  157. * @TX_INT: event driven mode 1, each send and receive generates interrupt
  158. * @TX_INT_WM: event driven mode 2, interrupts based on watermark mechanism
  159. * @TX_POLL: poll method
  160. * @ICP_QHDR_TX_TYPE_MASK defines position in qhdr_type
  161. */
  162. enum qhdr_tx_type {
  163. TX_INT,
  164. TX_INT_WM,
  165. TX_POLL
  166. };
  167. /**
  168. * @RX_INT: event driven mode 1, each send and receive generates interrupt
  169. * @RX_INT_WM: event driven mode 2, interrupts based on watermark mechanism
  170. * @RX_POLL: poll method
  171. * @ICP_QHDR_RX_TYPE_MASK defines position in qhdr_type
  172. */
  173. enum qhdr_rx_type {
  174. RX_INT,
  175. RX_INT_WM,
  176. RX_POLL
  177. };
  178. /**
  179. * @Q_CMD: Host to FW command queue
  180. * @Q_MSG: FW to Host message queue
  181. * @Q_DEBUG: FW to Host debug queue
  182. * @ICP_QHDR_Q_ID_MASK defines position in qhdr_type
  183. */
  184. enum qhdr_q_id {
  185. Q_CMD,
  186. Q_MSG,
  187. Q_DBG
  188. };
  189. /**
  190. * struct hfi_qtbl_hdr
  191. * @qtbl_version: Queue table version number
  192. * Higher 16 bits: Major version
  193. * Lower 16 bits: Minor version
  194. * @qtbl_size: Queue table size from version to last parametr in qhdr entry
  195. * @qtbl_qhdr0_offset: Offset to the start of first qhdr
  196. * @qtbl_qhdr_size: Queue header size in bytes
  197. * @qtbl_num_q: Total number of queues in Queue table
  198. * @qtbl_num_active_q: Total number of active queues
  199. */
  200. struct hfi_qtbl_hdr {
  201. uint32_t qtbl_version;
  202. uint32_t qtbl_size;
  203. uint32_t qtbl_qhdr0_offset;
  204. uint32_t qtbl_qhdr_size;
  205. uint32_t qtbl_num_q;
  206. uint32_t qtbl_num_active_q;
  207. } __packed;
  208. /**
  209. * struct hfi_q_hdr
  210. * @qhdr_status: Queue status, qhdr_state define possible status
  211. * @qhdr_start_addr: Queue start address in non cached memory
  212. * @qhdr_type: qhdr_tx, qhdr_rx, qhdr_q_id and priority defines qhdr type
  213. * @qhdr_q_size: Queue size
  214. * Number of queue packets if qhdr_pkt_size is non-zero
  215. * Queue size in bytes if qhdr_pkt_size is zero
  216. * @qhdr_pkt_size: Size of queue packet entries
  217. * 0x0: variable queue packet size
  218. * non zero: size of queue packet entry, fixed
  219. * @qhdr_pkt_drop_cnt: Number of packets dropped by sender
  220. * @qhdr_rx_wm: Receiver watermark, applicable in event driven mode
  221. * @qhdr_tx_wm: Sender watermark, applicable in event driven mode
  222. * @qhdr_rx_req: Receiver sets this bit if queue is empty
  223. * @qhdr_tx_req: Sender sets this bit if queue is full
  224. * @qhdr_rx_irq_status: Receiver sets this bit and triggers an interrupt to
  225. * the sender after packets are dequeued. Sender clears this bit
  226. * @qhdr_tx_irq_status: Sender sets this bit and triggers an interrupt to
  227. * the receiver after packets are queued. Receiver clears this bit
  228. * @qhdr_read_idx: Read index
  229. * @qhdr_write_idx: Write index
  230. */
  231. struct hfi_q_hdr {
  232. uint32_t dummy[15];
  233. uint32_t qhdr_status;
  234. uint32_t dummy1[15];
  235. uint32_t qhdr_start_addr;
  236. uint32_t dummy2[15];
  237. uint32_t qhdr_type;
  238. uint32_t dummy3[15];
  239. uint32_t qhdr_q_size;
  240. uint32_t dummy4[15];
  241. uint32_t qhdr_pkt_size;
  242. uint32_t dummy5[15];
  243. uint32_t qhdr_pkt_drop_cnt;
  244. uint32_t dummy6[15];
  245. uint32_t qhdr_rx_wm;
  246. uint32_t dummy7[15];
  247. uint32_t qhdr_tx_wm;
  248. uint32_t dummy8[15];
  249. uint32_t qhdr_rx_req;
  250. uint32_t dummy9[15];
  251. uint32_t qhdr_tx_req;
  252. uint32_t dummy10[15];
  253. uint32_t qhdr_rx_irq_status;
  254. uint32_t dummy11[15];
  255. uint32_t qhdr_tx_irq_status;
  256. uint32_t dummy12[15];
  257. uint32_t qhdr_read_idx;
  258. uint32_t dummy13[15];
  259. uint32_t qhdr_write_idx;
  260. uint32_t dummy14[15];
  261. };
  262. /**
  263. * struct sfr_buf
  264. * @size: Number of characters
  265. * @msg : Subsystem failure reason
  266. */
  267. struct sfr_buf {
  268. uint32_t size;
  269. char msg[ICP_MSG_SFR_SIZE_IN_BYTES];
  270. };
  271. /**
  272. * struct hfi_q_tbl
  273. * @q_tbl_hdr: Queue table header
  274. * @q_hdr: Queue header info, it holds info of cmd, msg and debug queues
  275. */
  276. struct hfi_qtbl {
  277. struct hfi_qtbl_hdr q_tbl_hdr;
  278. struct hfi_q_hdr q_hdr[MAX_ICP_HFI_QUEUES];
  279. };
  280. /**
  281. * struct hfi_info
  282. * @map: Hfi shared memory info
  283. * @smem_size: Shared memory size
  284. * @uncachedheap_size: uncached heap size
  285. * @msgpacket_buf: message buffer
  286. * @hfi_state: State machine for hfi
  287. * @cmd_q_lock: Lock for command queue
  288. * @cmd_q_state: State of command queue
  289. * @mutex msg_q_lock: Lock for message queue
  290. * @msg_q_state: State of message queue
  291. * @csr_base: CSR base address
  292. */
  293. struct hfi_info {
  294. struct hfi_mem_info map;
  295. uint32_t smem_size;
  296. uint32_t uncachedheap_size;
  297. uint32_t msgpacket_buf[ICP_HFI_MAX_MSG_SIZE_IN_WORDS];
  298. uint8_t hfi_state;
  299. struct mutex cmd_q_lock;
  300. bool cmd_q_state;
  301. struct mutex msg_q_lock;
  302. bool msg_q_state;
  303. void __iomem *csr_base;
  304. };
  305. #endif /* _CAM_HFI_REG_H_ */