sde_kms.c 103 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <linux/debugfs.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/dma-buf.h>
  25. #include <drm/drm_atomic_uapi.h>
  26. #include <drm/drm_probe_helper.h>
  27. #include "msm_drv.h"
  28. #include "msm_mmu.h"
  29. #include "msm_gem.h"
  30. #include "dsi_display.h"
  31. #include "dsi_drm.h"
  32. #include "sde_wb.h"
  33. #include "dp_display.h"
  34. #include "dp_drm.h"
  35. #include "dp_mst_drm.h"
  36. #include "sde_kms.h"
  37. #include "sde_core_irq.h"
  38. #include "sde_formats.h"
  39. #include "sde_hw_vbif.h"
  40. #include "sde_vbif.h"
  41. #include "sde_encoder.h"
  42. #include "sde_plane.h"
  43. #include "sde_crtc.h"
  44. #include "sde_reg_dma.h"
  45. #include "sde_connector.h"
  46. #include "sde_vm.h"
  47. #include <linux/qcom_scm.h>
  48. #include "soc/qcom/secure_buffer.h"
  49. #include <linux/qtee_shmbridge.h>
  50. #include <linux/haven/hh_irq_lend.h>
  51. #define CREATE_TRACE_POINTS
  52. #include "sde_trace.h"
  53. /* defines for secure channel call */
  54. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  55. #define MDP_DEVICE_ID 0x1A
  56. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  57. static const char * const iommu_ports[] = {
  58. "mdp_0",
  59. };
  60. /**
  61. * Controls size of event log buffer. Specified as a power of 2.
  62. */
  63. #define SDE_EVTLOG_SIZE 1024
  64. /*
  65. * To enable overall DRM driver logging
  66. * # echo 0x2 > /sys/module/drm/parameters/debug
  67. *
  68. * To enable DRM driver h/w logging
  69. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  70. *
  71. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  72. */
  73. #define SDE_DEBUGFS_DIR "msm_sde"
  74. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  75. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  76. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  77. /**
  78. * sdecustom - enable certain driver customizations for sde clients
  79. * Enabling this modifies the standard DRM behavior slightly and assumes
  80. * that the clients have specific knowledge about the modifications that
  81. * are involved, so don't enable this unless you know what you're doing.
  82. *
  83. * Parts of the driver that are affected by this setting may be located by
  84. * searching for invocations of the 'sde_is_custom_client()' function.
  85. *
  86. * This is disabled by default.
  87. */
  88. static bool sdecustom = true;
  89. module_param(sdecustom, bool, 0400);
  90. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  91. static int sde_kms_hw_init(struct msm_kms *kms);
  92. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  93. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  94. static int _sde_kms_register_events(struct msm_kms *kms,
  95. struct drm_mode_object *obj, u32 event, bool en);
  96. bool sde_is_custom_client(void)
  97. {
  98. return sdecustom;
  99. }
  100. #ifdef CONFIG_DEBUG_FS
  101. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  102. {
  103. struct msm_drm_private *priv;
  104. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  105. return NULL;
  106. priv = sde_kms->dev->dev_private;
  107. return priv->debug_root;
  108. }
  109. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  110. {
  111. void *p;
  112. int rc;
  113. void *debugfs_root;
  114. p = sde_hw_util_get_log_mask_ptr();
  115. if (!sde_kms || !p)
  116. return -EINVAL;
  117. debugfs_root = sde_debugfs_get_root(sde_kms);
  118. if (!debugfs_root)
  119. return -EINVAL;
  120. /* allow debugfs_root to be NULL */
  121. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  122. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  123. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  124. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  125. if (rc) {
  126. SDE_ERROR("failed to init perf %d\n", rc);
  127. return rc;
  128. }
  129. if (sde_kms->catalog->qdss_count)
  130. debugfs_create_u32("qdss", 0600, debugfs_root,
  131. (u32 *)&sde_kms->qdss_enabled);
  132. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  133. (u32 *)&sde_kms->pm_suspend_clk_dump);
  134. return 0;
  135. }
  136. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  137. {
  138. /* don't need to NULL check debugfs_root */
  139. if (sde_kms) {
  140. sde_debugfs_vbif_destroy(sde_kms);
  141. sde_debugfs_core_irq_destroy(sde_kms);
  142. }
  143. }
  144. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  145. {
  146. int i;
  147. struct device *dev = sde_kms->dev->dev;
  148. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  149. for (i = 0; i < sde_kms->dsi_display_count; i++)
  150. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  151. return 0;
  152. }
  153. #else
  154. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  155. {
  156. return 0;
  157. }
  158. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  159. {
  160. }
  161. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  162. {
  163. return 0;
  164. }
  165. #endif
  166. static bool _sde_kms_skip_vblank_op(struct sde_kms *sde_kms)
  167. {
  168. struct sde_vm_ops *vm_ops = NULL;
  169. if (!sde_kms->vm)
  170. return false;
  171. vm_ops = &sde_kms->vm->vm_ops;
  172. if (!vm_ops->vm_owns_hw(sde_kms))
  173. return true;
  174. return false;
  175. }
  176. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  177. {
  178. int ret = 0;
  179. struct sde_kms *sde_kms;
  180. if (!kms)
  181. return -EINVAL;
  182. sde_kms = to_sde_kms(kms);
  183. if (sde_kms->vm)
  184. mutex_lock(&sde_kms->vm->vm_res_lock);
  185. if (_sde_kms_skip_vblank_op(sde_kms)) {
  186. SDE_DEBUG("skipping vblank enable due to HW unavailablity\n");
  187. mutex_unlock(&sde_kms->vm->vm_res_lock);
  188. return 0;
  189. }
  190. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  191. ret = sde_crtc_vblank(crtc, true);
  192. SDE_ATRACE_END("sde_kms_enable_vblank");
  193. if (sde_kms->vm)
  194. mutex_unlock(&sde_kms->vm->vm_res_lock);
  195. return ret;
  196. }
  197. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  198. {
  199. struct sde_kms *sde_kms;
  200. if (!kms)
  201. return;
  202. sde_kms = to_sde_kms(kms);
  203. if (sde_kms->vm)
  204. mutex_lock(&sde_kms->vm->vm_res_lock);
  205. if (_sde_kms_skip_vblank_op(sde_kms)) {
  206. SDE_DEBUG("skipping vblank disable due to HW unavailablity\n");
  207. mutex_unlock(&sde_kms->vm->vm_res_lock);
  208. return;
  209. }
  210. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  211. sde_crtc_vblank(crtc, false);
  212. SDE_ATRACE_END("sde_kms_disable_vblank");
  213. if (sde_kms->vm)
  214. mutex_unlock(&sde_kms->vm->vm_res_lock);
  215. }
  216. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  217. struct drm_crtc *crtc)
  218. {
  219. struct drm_encoder *encoder;
  220. struct drm_device *dev;
  221. int ret;
  222. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  223. SDE_ERROR("invalid params\n");
  224. return;
  225. }
  226. if (!crtc->state->enable) {
  227. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  228. return;
  229. }
  230. if (!crtc->state->active) {
  231. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  232. return;
  233. }
  234. dev = crtc->dev;
  235. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  236. if (encoder->crtc != crtc)
  237. continue;
  238. /*
  239. * Video Mode - Wait for VSYNC
  240. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  241. * complete
  242. */
  243. SDE_EVT32_VERBOSE(DRMID(crtc));
  244. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  245. if (ret && ret != -EWOULDBLOCK) {
  246. SDE_ERROR(
  247. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  248. crtc->base.id, encoder->base.id, ret);
  249. break;
  250. }
  251. }
  252. }
  253. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  254. struct drm_crtc *crtc, bool enable)
  255. {
  256. struct drm_device *dev;
  257. struct msm_drm_private *priv;
  258. struct sde_mdss_cfg *sde_cfg;
  259. struct drm_plane *plane;
  260. int i, ret;
  261. dev = sde_kms->dev;
  262. priv = dev->dev_private;
  263. sde_cfg = sde_kms->catalog;
  264. ret = sde_vbif_halt_xin_mask(sde_kms,
  265. sde_cfg->sui_block_xin_mask, enable);
  266. if (ret) {
  267. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  268. return ret;
  269. }
  270. if (enable) {
  271. for (i = 0; i < priv->num_planes; i++) {
  272. plane = priv->planes[i];
  273. sde_plane_secure_ctrl_xin_client(plane, crtc);
  274. }
  275. }
  276. return 0;
  277. }
  278. /**
  279. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  280. * @sde_kms: Pointer to sde_kms struct
  281. * @vimd: switch the stage 2 translation to this VMID
  282. */
  283. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  284. {
  285. struct device dummy = {};
  286. dma_addr_t dma_handle;
  287. uint32_t num_sids;
  288. uint32_t *sec_sid;
  289. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  290. int ret = 0, i;
  291. struct qtee_shm shm;
  292. bool qtee_en = qtee_shmbridge_is_enabled();
  293. phys_addr_t mem_addr;
  294. u64 mem_size;
  295. num_sids = sde_cfg->sec_sid_mask_count;
  296. if (!num_sids) {
  297. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  298. return -EINVAL;
  299. }
  300. if (qtee_en) {
  301. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  302. &shm);
  303. if (ret)
  304. return -ENOMEM;
  305. sec_sid = (uint32_t *) shm.vaddr;
  306. mem_addr = shm.paddr;
  307. /**
  308. * SMMUSecureModeSwitch requires the size to be number of SID's
  309. * but shm allocates size in pages. Modify the args as per
  310. * client requirement.
  311. */
  312. mem_size = sizeof(uint32_t) * num_sids;
  313. } else {
  314. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  315. if (!sec_sid)
  316. return -ENOMEM;
  317. mem_addr = virt_to_phys(sec_sid);
  318. mem_size = sizeof(uint32_t) * num_sids;
  319. }
  320. for (i = 0; i < num_sids; i++) {
  321. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  322. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  323. }
  324. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  325. if (ret) {
  326. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  327. goto map_error;
  328. }
  329. set_dma_ops(&dummy, NULL);
  330. dma_handle = dma_map_single(&dummy, sec_sid,
  331. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  332. if (dma_mapping_error(&dummy, dma_handle)) {
  333. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  334. vmid);
  335. goto map_error;
  336. }
  337. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  338. vmid, num_sids, qtee_en);
  339. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  340. mem_size, vmid);
  341. if (ret)
  342. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  343. vmid, ret);
  344. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  345. vmid, qtee_en, num_sids, ret);
  346. dma_unmap_single(&dummy, dma_handle,
  347. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  348. map_error:
  349. if (qtee_en)
  350. qtee_shmbridge_free_shm(&shm);
  351. else
  352. kfree(sec_sid);
  353. return ret;
  354. }
  355. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  356. {
  357. u32 ret;
  358. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  359. return 0;
  360. /* detach_all_contexts */
  361. ret = sde_kms_mmu_detach(sde_kms, false);
  362. if (ret) {
  363. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  364. goto mmu_error;
  365. }
  366. ret = _sde_kms_scm_call(sde_kms, vmid);
  367. if (ret) {
  368. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  369. goto scm_error;
  370. }
  371. return 0;
  372. scm_error:
  373. sde_kms_mmu_attach(sde_kms, false);
  374. mmu_error:
  375. atomic_dec(&sde_kms->detach_all_cb);
  376. return ret;
  377. }
  378. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  379. u32 old_vmid)
  380. {
  381. u32 ret;
  382. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  383. return 0;
  384. ret = _sde_kms_scm_call(sde_kms, vmid);
  385. if (ret) {
  386. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  387. goto scm_error;
  388. }
  389. /* attach_all_contexts */
  390. ret = sde_kms_mmu_attach(sde_kms, false);
  391. if (ret) {
  392. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  393. goto mmu_error;
  394. }
  395. return 0;
  396. mmu_error:
  397. _sde_kms_scm_call(sde_kms, old_vmid);
  398. scm_error:
  399. atomic_inc(&sde_kms->detach_all_cb);
  400. return ret;
  401. }
  402. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  403. {
  404. u32 ret;
  405. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  406. return 0;
  407. /* detach secure_context */
  408. ret = sde_kms_mmu_detach(sde_kms, true);
  409. if (ret) {
  410. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  411. goto mmu_error;
  412. }
  413. ret = _sde_kms_scm_call(sde_kms, vmid);
  414. if (ret) {
  415. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  416. goto scm_error;
  417. }
  418. return 0;
  419. scm_error:
  420. sde_kms_mmu_attach(sde_kms, true);
  421. mmu_error:
  422. atomic_dec(&sde_kms->detach_sec_cb);
  423. return ret;
  424. }
  425. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  426. u32 old_vmid)
  427. {
  428. u32 ret;
  429. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  430. return 0;
  431. ret = _sde_kms_scm_call(sde_kms, vmid);
  432. if (ret) {
  433. goto scm_error;
  434. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  435. }
  436. ret = sde_kms_mmu_attach(sde_kms, true);
  437. if (ret) {
  438. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  439. goto mmu_error;
  440. }
  441. return 0;
  442. mmu_error:
  443. _sde_kms_scm_call(sde_kms, old_vmid);
  444. scm_error:
  445. atomic_inc(&sde_kms->detach_sec_cb);
  446. return ret;
  447. }
  448. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  449. struct drm_crtc *crtc, bool enable)
  450. {
  451. int ret;
  452. if (enable) {
  453. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  454. if (ret < 0) {
  455. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  456. return ret;
  457. }
  458. sde_crtc_misr_setup(crtc, true, 1);
  459. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  460. if (ret) {
  461. sde_crtc_misr_setup(crtc, false, 0);
  462. pm_runtime_put_sync(sde_kms->dev->dev);
  463. return ret;
  464. }
  465. } else {
  466. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  467. sde_crtc_misr_setup(crtc, false, 0);
  468. pm_runtime_put_sync(sde_kms->dev->dev);
  469. }
  470. return 0;
  471. }
  472. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  473. bool post_commit)
  474. {
  475. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  476. int old_smmu_state = smmu_state->state;
  477. int ret = 0;
  478. u32 vmid;
  479. if (!sde_kms || !crtc) {
  480. SDE_ERROR("invalid argument(s)\n");
  481. return -EINVAL;
  482. }
  483. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  484. post_commit, smmu_state->sui_misr_state,
  485. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  486. if ((!smmu_state->transition_type) ||
  487. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  488. /* Bail out */
  489. return 0;
  490. /* enable sui misr if requested, before the transition */
  491. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  492. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  493. if (ret) {
  494. smmu_state->sui_misr_state = NONE;
  495. goto end;
  496. }
  497. }
  498. mutex_lock(&sde_kms->secure_transition_lock);
  499. switch (smmu_state->state) {
  500. case DETACH_ALL_REQ:
  501. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  502. if (!ret)
  503. smmu_state->state = DETACHED;
  504. break;
  505. case ATTACH_ALL_REQ:
  506. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  507. VMID_CP_SEC_DISPLAY);
  508. if (!ret) {
  509. smmu_state->state = ATTACHED;
  510. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  511. }
  512. break;
  513. case DETACH_SEC_REQ:
  514. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  515. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  516. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  517. if (!ret)
  518. smmu_state->state = DETACHED_SEC;
  519. break;
  520. case ATTACH_SEC_REQ:
  521. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  522. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  523. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  524. if (!ret) {
  525. smmu_state->state = ATTACHED;
  526. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  527. }
  528. break;
  529. default:
  530. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  531. DRMID(crtc), smmu_state->state,
  532. smmu_state->transition_type);
  533. ret = -EINVAL;
  534. break;
  535. }
  536. mutex_unlock(&sde_kms->secure_transition_lock);
  537. /* disable sui misr if requested, after the transition */
  538. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  539. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  540. if (ret)
  541. goto end;
  542. }
  543. end:
  544. smmu_state->transition_error = false;
  545. if (ret) {
  546. smmu_state->transition_error = true;
  547. SDE_ERROR(
  548. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  549. DRMID(crtc), old_smmu_state, smmu_state->state,
  550. smmu_state->secure_level, ret);
  551. smmu_state->state = smmu_state->prev_state;
  552. smmu_state->secure_level = smmu_state->prev_secure_level;
  553. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  554. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  555. }
  556. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  557. DRMID(crtc), old_smmu_state, smmu_state->state,
  558. smmu_state->secure_level, ret);
  559. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  560. smmu_state->transition_type,
  561. smmu_state->transition_error,
  562. smmu_state->secure_level, smmu_state->prev_secure_level,
  563. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  564. smmu_state->sui_misr_state = NONE;
  565. smmu_state->transition_type = NONE;
  566. return ret;
  567. }
  568. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  569. struct drm_atomic_state *state)
  570. {
  571. struct drm_crtc *crtc;
  572. struct drm_crtc_state *old_crtc_state;
  573. struct drm_plane_state *old_plane_state, *new_plane_state;
  574. struct drm_plane *plane;
  575. struct drm_plane_state *plane_state;
  576. struct sde_kms *sde_kms = to_sde_kms(kms);
  577. struct drm_device *dev = sde_kms->dev;
  578. int i, ops = 0, ret = 0;
  579. bool old_valid_fb = false;
  580. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  581. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  582. if (!crtc->state || !crtc->state->active)
  583. continue;
  584. /*
  585. * It is safe to assume only one active crtc,
  586. * and compatible translation modes on the
  587. * planes staged on this crtc.
  588. * otherwise validation would have failed.
  589. * For this CRTC,
  590. */
  591. /*
  592. * 1. Check if old state on the CRTC has planes
  593. * staged with valid fbs
  594. */
  595. for_each_old_plane_in_state(state, plane, plane_state, i) {
  596. if (!plane_state->crtc)
  597. continue;
  598. if (plane_state->fb) {
  599. old_valid_fb = true;
  600. break;
  601. }
  602. }
  603. /*
  604. * 2.Get the operations needed to be performed before
  605. * secure transition can be initiated.
  606. */
  607. ops = sde_crtc_get_secure_transition_ops(crtc,
  608. old_crtc_state, old_valid_fb);
  609. if (ops < 0) {
  610. SDE_ERROR("invalid secure operations %x\n", ops);
  611. return ops;
  612. }
  613. if (!ops) {
  614. smmu_state->transition_error = false;
  615. goto no_ops;
  616. }
  617. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  618. crtc->base.id, ops, crtc->state);
  619. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  620. /* 3. Perform operations needed for secure transition */
  621. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  622. SDE_DEBUG("wait_for_transfer_done\n");
  623. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  624. }
  625. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  626. SDE_DEBUG("cleanup planes\n");
  627. drm_atomic_helper_cleanup_planes(dev, state);
  628. for_each_oldnew_plane_in_state(state, plane,
  629. old_plane_state, new_plane_state, i)
  630. sde_plane_destroy_fb(old_plane_state);
  631. }
  632. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  633. SDE_DEBUG("secure ctrl\n");
  634. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  635. }
  636. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  637. SDE_DEBUG("prepare planes %d",
  638. crtc->state->plane_mask);
  639. drm_atomic_crtc_for_each_plane(plane,
  640. crtc) {
  641. const struct drm_plane_helper_funcs *funcs;
  642. plane_state = plane->state;
  643. funcs = plane->helper_private;
  644. SDE_DEBUG("psde:%d FB[%u]\n",
  645. plane->base.id,
  646. plane->fb->base.id);
  647. if (!funcs)
  648. continue;
  649. if (funcs->prepare_fb(plane, plane_state)) {
  650. ret = funcs->prepare_fb(plane,
  651. plane_state);
  652. if (ret)
  653. return ret;
  654. }
  655. }
  656. }
  657. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  658. SDE_DEBUG("secure operations completed\n");
  659. }
  660. no_ops:
  661. return 0;
  662. }
  663. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  664. unsigned int splash_buffer_size,
  665. unsigned int ramdump_base,
  666. unsigned int ramdump_buffer_size)
  667. {
  668. unsigned long pfn_start, pfn_end, pfn_idx;
  669. int ret = 0;
  670. if (!mem_addr || !splash_buffer_size) {
  671. SDE_ERROR("invalid params\n");
  672. return -EINVAL;
  673. }
  674. /* leave ramdump memory only if base address matches */
  675. if (ramdump_base == mem_addr &&
  676. ramdump_buffer_size <= splash_buffer_size) {
  677. mem_addr += ramdump_buffer_size;
  678. splash_buffer_size -= ramdump_buffer_size;
  679. }
  680. pfn_start = mem_addr >> PAGE_SHIFT;
  681. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  682. if (ret) {
  683. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  684. return ret;
  685. }
  686. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  687. free_reserved_page(pfn_to_page(pfn_idx));
  688. return ret;
  689. }
  690. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  691. struct sde_splash_mem *splash)
  692. {
  693. struct msm_mmu *mmu = NULL;
  694. int ret = 0;
  695. if (!sde_kms->aspace[0]) {
  696. SDE_ERROR("aspace not found for sde kms node\n");
  697. return -EINVAL;
  698. }
  699. mmu = sde_kms->aspace[0]->mmu;
  700. if (!mmu) {
  701. SDE_ERROR("mmu not found for aspace\n");
  702. return -EINVAL;
  703. }
  704. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  705. SDE_ERROR("invalid input params for map\n");
  706. return -EINVAL;
  707. }
  708. if (!splash->ref_cnt) {
  709. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  710. splash->splash_buf_base,
  711. splash->splash_buf_size,
  712. IOMMU_READ | IOMMU_NOEXEC);
  713. if (ret)
  714. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  715. }
  716. splash->ref_cnt++;
  717. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  718. splash->splash_buf_base,
  719. splash->splash_buf_size,
  720. splash->ref_cnt);
  721. return ret;
  722. }
  723. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  724. {
  725. int i = 0;
  726. int ret = 0;
  727. if (!sde_kms)
  728. return -EINVAL;
  729. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  730. ret = _sde_kms_splash_mem_get(sde_kms,
  731. sde_kms->splash_data.splash_display[i].splash);
  732. if (ret)
  733. return ret;
  734. }
  735. return ret;
  736. }
  737. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  738. struct sde_splash_mem *splash)
  739. {
  740. struct msm_mmu *mmu = NULL;
  741. int rc = 0;
  742. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  743. SDE_ERROR("invalid params\n");
  744. return -EINVAL;
  745. }
  746. mmu = sde_kms->aspace[0]->mmu;
  747. if (!splash || !splash->ref_cnt ||
  748. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  749. return -EINVAL;
  750. splash->ref_cnt--;
  751. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  752. splash->splash_buf_base, splash->ref_cnt);
  753. if (!splash->ref_cnt) {
  754. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  755. splash->splash_buf_size);
  756. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  757. splash->splash_buf_size, splash->ramdump_base,
  758. splash->ramdump_size);
  759. splash->splash_buf_base = 0;
  760. splash->splash_buf_size = 0;
  761. }
  762. return rc;
  763. }
  764. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  765. {
  766. int i = 0;
  767. int ret = 0;
  768. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  769. return -EINVAL;
  770. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  771. ret = _sde_kms_splash_mem_put(sde_kms,
  772. sde_kms->splash_data.splash_display[i].splash);
  773. if (ret)
  774. return ret;
  775. }
  776. return ret;
  777. }
  778. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  779. struct drm_atomic_state *state)
  780. {
  781. struct drm_device *ddev;
  782. struct drm_crtc *crtc;
  783. struct drm_encoder *encoder;
  784. struct drm_connector *connector;
  785. struct sde_vm_ops *vm_ops;
  786. struct sde_crtc_state *cstate;
  787. enum sde_crtc_vm_req vm_req;
  788. int rc = 0;
  789. ddev = sde_kms->dev;
  790. if (!sde_kms->vm)
  791. return -EINVAL;
  792. vm_ops = &sde_kms->vm->vm_ops;
  793. crtc = state->crtcs[0].ptr;
  794. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  795. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  796. if (vm_req != VM_REQ_ACQUIRE)
  797. return 0;
  798. /* enable MDSS irq line */
  799. sde_irq_update(&sde_kms->base, true);
  800. /* clear the stale IRQ status bits */
  801. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  802. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  803. /* enable the display path IRQ's */
  804. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  805. sde_encoder_irq_control(encoder, true);
  806. /* Schedule ESD work */
  807. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  808. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  809. sde_connector_schedule_status_work(connector, true);
  810. /* handle non-SDE pre_acquire */
  811. if (vm_ops->vm_client_post_acquire)
  812. rc = vm_ops->vm_client_post_acquire(sde_kms);
  813. return rc;
  814. }
  815. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  816. struct drm_atomic_state *state)
  817. {
  818. struct drm_device *ddev;
  819. struct drm_plane *plane;
  820. struct sde_crtc_state *cstate;
  821. enum sde_crtc_vm_req vm_req;
  822. ddev = sde_kms->dev;
  823. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  824. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  825. if (vm_req != VM_REQ_ACQUIRE)
  826. return 0;
  827. /* Clear the stale IRQ status bits */
  828. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  829. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  830. /* Program the SID's for the trusted VM */
  831. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  832. sde_plane_set_sid(plane, 1);
  833. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  834. return 0;
  835. }
  836. static void sde_kms_prepare_commit(struct msm_kms *kms,
  837. struct drm_atomic_state *state)
  838. {
  839. struct sde_kms *sde_kms;
  840. struct msm_drm_private *priv;
  841. struct drm_device *dev;
  842. struct drm_encoder *encoder;
  843. struct drm_crtc *crtc;
  844. struct drm_crtc_state *crtc_state;
  845. struct sde_vm_ops *vm_ops;
  846. int i, rc;
  847. if (!kms)
  848. return;
  849. sde_kms = to_sde_kms(kms);
  850. dev = sde_kms->dev;
  851. if (!dev || !dev->dev_private)
  852. return;
  853. priv = dev->dev_private;
  854. SDE_ATRACE_BEGIN("prepare_commit");
  855. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  856. if (rc < 0) {
  857. SDE_ERROR("failed to enable power resources %d\n", rc);
  858. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  859. goto end;
  860. }
  861. if (sde_kms->first_kickoff) {
  862. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  863. sde_kms->first_kickoff = false;
  864. }
  865. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  866. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  867. head) {
  868. if (encoder->crtc != crtc)
  869. continue;
  870. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  871. SDE_ERROR("crtc:%d, initiating hw reset\n",
  872. DRMID(crtc));
  873. sde_encoder_needs_hw_reset(encoder);
  874. sde_crtc_set_needs_hw_reset(crtc);
  875. }
  876. }
  877. }
  878. /*
  879. * NOTE: for secure use cases we want to apply the new HW
  880. * configuration only after completing preparation for secure
  881. * transitions prepare below if any transtions is required.
  882. */
  883. sde_kms_prepare_secure_transition(kms, state);
  884. if (!sde_kms->vm)
  885. goto end;
  886. vm_ops = &sde_kms->vm->vm_ops;
  887. if (vm_ops->vm_prepare_commit)
  888. vm_ops->vm_prepare_commit(sde_kms, state);
  889. end:
  890. SDE_ATRACE_END("prepare_commit");
  891. }
  892. static void sde_kms_commit(struct msm_kms *kms,
  893. struct drm_atomic_state *old_state)
  894. {
  895. struct sde_kms *sde_kms;
  896. struct drm_crtc *crtc;
  897. struct drm_crtc_state *old_crtc_state;
  898. int i;
  899. if (!kms || !old_state)
  900. return;
  901. sde_kms = to_sde_kms(kms);
  902. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  903. SDE_ERROR("power resource is not enabled\n");
  904. return;
  905. }
  906. SDE_ATRACE_BEGIN("sde_kms_commit");
  907. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  908. if (crtc->state->active) {
  909. SDE_EVT32(DRMID(crtc));
  910. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  911. }
  912. }
  913. SDE_ATRACE_END("sde_kms_commit");
  914. }
  915. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  916. struct sde_splash_display *splash_display)
  917. {
  918. if (!sde_kms || !splash_display ||
  919. !sde_kms->splash_data.num_splash_displays)
  920. return;
  921. if (sde_kms->splash_data.num_splash_regions)
  922. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  923. sde_kms->splash_data.num_splash_displays--;
  924. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  925. sde_kms->splash_data.num_splash_displays);
  926. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  927. }
  928. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  929. struct drm_crtc *crtc)
  930. {
  931. struct msm_drm_private *priv;
  932. struct sde_splash_display *splash_display;
  933. int i;
  934. if (!sde_kms || !crtc)
  935. return;
  936. priv = sde_kms->dev->dev_private;
  937. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  938. return;
  939. SDE_EVT32(DRMID(crtc), crtc->state->active,
  940. sde_kms->splash_data.num_splash_displays);
  941. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  942. splash_display = &sde_kms->splash_data.splash_display[i];
  943. if (splash_display->encoder &&
  944. crtc == splash_display->encoder->crtc)
  945. break;
  946. }
  947. if (i >= MAX_DSI_DISPLAYS)
  948. return;
  949. if (splash_display->cont_splash_enabled) {
  950. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  951. splash_display, false);
  952. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  953. }
  954. /* remove the votes if all displays are done with splash */
  955. if (!sde_kms->splash_data.num_splash_displays) {
  956. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  957. sde_power_data_bus_set_quota(&priv->phandle, i,
  958. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  959. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  960. pm_runtime_put_sync(sde_kms->dev->dev);
  961. }
  962. }
  963. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  964. struct drm_atomic_state *state)
  965. {
  966. struct sde_vm_ops *vm_ops;
  967. struct drm_device *ddev;
  968. struct drm_crtc *crtc;
  969. struct drm_plane *plane;
  970. struct drm_encoder *encoder;
  971. struct sde_crtc_state *cstate;
  972. struct drm_crtc_state *new_cstate;
  973. enum sde_crtc_vm_req vm_req;
  974. int rc = 0;
  975. if (!sde_kms || !sde_kms->vm)
  976. return -EINVAL;
  977. vm_ops = &sde_kms->vm->vm_ops;
  978. ddev = sde_kms->dev;
  979. crtc = state->crtcs[0].ptr;
  980. new_cstate = state->crtcs[0].new_state;
  981. cstate = to_sde_crtc_state(new_cstate);
  982. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  983. if (vm_req != VM_REQ_RELEASE)
  984. return rc;
  985. if (!new_cstate->active && !new_cstate->active_changed)
  986. return rc;
  987. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  988. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  989. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  990. sde_encoder_irq_control(encoder, false);
  991. sde_irq_update(&sde_kms->base, false);
  992. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  993. sde_plane_set_sid(plane, 0);
  994. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  995. if (vm_ops->vm_release)
  996. rc = vm_ops->vm_release(sde_kms);
  997. return rc;
  998. }
  999. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1000. struct drm_atomic_state *state)
  1001. {
  1002. struct drm_device *ddev;
  1003. struct drm_crtc *crtc;
  1004. struct drm_encoder *encoder;
  1005. struct drm_connector *connector;
  1006. int rc = 0;
  1007. ddev = sde_kms->dev;
  1008. crtc = state->crtcs[0].ptr;
  1009. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1010. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1011. /* disable ESD work */
  1012. list_for_each_entry(connector,
  1013. &ddev->mode_config.connector_list, head) {
  1014. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1015. sde_connector_schedule_status_work(connector, false);
  1016. }
  1017. /* disable SDE irq's */
  1018. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1019. sde_encoder_irq_control(encoder, false);
  1020. /* disable IRQ line */
  1021. sde_irq_update(&sde_kms->base, false);
  1022. return rc;
  1023. }
  1024. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1025. struct drm_atomic_state *state)
  1026. {
  1027. struct sde_vm_ops *vm_ops;
  1028. struct sde_crtc_state *cstate;
  1029. enum sde_crtc_vm_req vm_req;
  1030. int rc = 0;
  1031. if (!sde_kms || !sde_kms->vm)
  1032. return -EINVAL;
  1033. vm_ops = &sde_kms->vm->vm_ops;
  1034. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  1035. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1036. if (vm_req != VM_REQ_RELEASE)
  1037. goto exit;
  1038. /* handle SDE pre-release */
  1039. sde_kms_vm_pre_release(sde_kms, state);
  1040. /* handle non-SDE clients pre-release */
  1041. if (vm_ops->vm_client_pre_release) {
  1042. rc = vm_ops->vm_client_pre_release(sde_kms);
  1043. if (rc) {
  1044. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1045. goto exit;
  1046. }
  1047. }
  1048. /* release HW */
  1049. if (vm_ops->vm_release) {
  1050. rc = vm_ops->vm_release(sde_kms);
  1051. if (rc)
  1052. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1053. }
  1054. exit:
  1055. return rc;
  1056. }
  1057. static void sde_kms_complete_commit(struct msm_kms *kms,
  1058. struct drm_atomic_state *old_state)
  1059. {
  1060. struct sde_kms *sde_kms;
  1061. struct msm_drm_private *priv;
  1062. struct drm_crtc *crtc;
  1063. struct drm_crtc_state *old_crtc_state;
  1064. struct drm_connector *connector;
  1065. struct drm_connector_state *old_conn_state;
  1066. struct msm_display_conn_params params;
  1067. struct sde_vm_ops *vm_ops;
  1068. int i, rc = 0;
  1069. if (!kms || !old_state)
  1070. return;
  1071. sde_kms = to_sde_kms(kms);
  1072. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1073. return;
  1074. priv = sde_kms->dev->dev_private;
  1075. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1076. SDE_ERROR("power resource is not enabled\n");
  1077. return;
  1078. }
  1079. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1080. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1081. sde_crtc_complete_commit(crtc, old_crtc_state);
  1082. /* complete secure transitions if any */
  1083. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1084. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1085. }
  1086. for_each_old_connector_in_state(old_state, connector,
  1087. old_conn_state, i) {
  1088. struct sde_connector *c_conn;
  1089. c_conn = to_sde_connector(connector);
  1090. if (!c_conn->ops.post_kickoff)
  1091. continue;
  1092. memset(&params, 0, sizeof(params));
  1093. sde_connector_complete_qsync_commit(connector, &params);
  1094. rc = c_conn->ops.post_kickoff(connector, &params);
  1095. if (rc) {
  1096. pr_err("Connector Post kickoff failed rc=%d\n",
  1097. rc);
  1098. }
  1099. }
  1100. if (sde_kms->vm) {
  1101. vm_ops = &sde_kms->vm->vm_ops;
  1102. if (vm_ops->vm_post_commit) {
  1103. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1104. if (rc)
  1105. SDE_ERROR("vm post commit failed, rc = %d\n",
  1106. rc);
  1107. }
  1108. }
  1109. pm_runtime_put_sync(sde_kms->dev->dev);
  1110. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1111. _sde_kms_release_splash_resource(sde_kms, crtc);
  1112. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1113. SDE_ATRACE_END("sde_kms_complete_commit");
  1114. }
  1115. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1116. struct drm_crtc *crtc)
  1117. {
  1118. struct drm_encoder *encoder;
  1119. struct drm_device *dev;
  1120. int ret;
  1121. if (!kms || !crtc || !crtc->state) {
  1122. SDE_ERROR("invalid params\n");
  1123. return;
  1124. }
  1125. dev = crtc->dev;
  1126. if (!crtc->state->enable) {
  1127. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1128. return;
  1129. }
  1130. if (!crtc->state->active) {
  1131. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1132. return;
  1133. }
  1134. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1135. SDE_ERROR("power resource is not enabled\n");
  1136. return;
  1137. }
  1138. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1139. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1140. if (encoder->crtc != crtc)
  1141. continue;
  1142. /*
  1143. * Wait for post-flush if necessary to delay before
  1144. * plane_cleanup. For example, wait for vsync in case of video
  1145. * mode panels. This may be a no-op for command mode panels.
  1146. */
  1147. SDE_EVT32_VERBOSE(DRMID(crtc));
  1148. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1149. if (ret && ret != -EWOULDBLOCK) {
  1150. SDE_ERROR("wait for commit done returned %d\n", ret);
  1151. sde_crtc_request_frame_reset(crtc);
  1152. break;
  1153. }
  1154. sde_crtc_complete_flip(crtc, NULL);
  1155. }
  1156. sde_crtc_static_cache_read_kickoff(crtc);
  1157. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1158. }
  1159. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1160. struct drm_atomic_state *old_state)
  1161. {
  1162. struct drm_crtc *crtc;
  1163. struct drm_crtc_state *old_crtc_state;
  1164. int i, rc;
  1165. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1166. SDE_ERROR("invalid argument(s)\n");
  1167. return;
  1168. }
  1169. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1170. retry:
  1171. /* attempt to acquire ww mutex for connection */
  1172. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1173. old_state->acquire_ctx);
  1174. if (rc == -EDEADLK) {
  1175. drm_modeset_backoff(old_state->acquire_ctx);
  1176. goto retry;
  1177. }
  1178. /* old_state actually contains updated crtc pointers */
  1179. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1180. if (crtc->state->active || crtc->state->active_changed)
  1181. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1182. }
  1183. SDE_ATRACE_END("sde_kms_prepare_fence");
  1184. }
  1185. /**
  1186. * _sde_kms_get_displays - query for underlying display handles and cache them
  1187. * @sde_kms: Pointer to sde kms structure
  1188. * Returns: Zero on success
  1189. */
  1190. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1191. {
  1192. int rc = -ENOMEM;
  1193. if (!sde_kms) {
  1194. SDE_ERROR("invalid sde kms\n");
  1195. return -EINVAL;
  1196. }
  1197. /* dsi */
  1198. sde_kms->dsi_displays = NULL;
  1199. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1200. if (sde_kms->dsi_display_count) {
  1201. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1202. sizeof(void *),
  1203. GFP_KERNEL);
  1204. if (!sde_kms->dsi_displays) {
  1205. SDE_ERROR("failed to allocate dsi displays\n");
  1206. goto exit_deinit_dsi;
  1207. }
  1208. sde_kms->dsi_display_count =
  1209. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1210. sde_kms->dsi_display_count);
  1211. }
  1212. /* wb */
  1213. sde_kms->wb_displays = NULL;
  1214. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1215. if (sde_kms->wb_display_count) {
  1216. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1217. sizeof(void *),
  1218. GFP_KERNEL);
  1219. if (!sde_kms->wb_displays) {
  1220. SDE_ERROR("failed to allocate wb displays\n");
  1221. goto exit_deinit_wb;
  1222. }
  1223. sde_kms->wb_display_count =
  1224. wb_display_get_displays(sde_kms->wb_displays,
  1225. sde_kms->wb_display_count);
  1226. }
  1227. /* dp */
  1228. sde_kms->dp_displays = NULL;
  1229. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1230. if (sde_kms->dp_display_count) {
  1231. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1232. sizeof(void *), GFP_KERNEL);
  1233. if (!sde_kms->dp_displays) {
  1234. SDE_ERROR("failed to allocate dp displays\n");
  1235. goto exit_deinit_dp;
  1236. }
  1237. sde_kms->dp_display_count =
  1238. dp_display_get_displays(sde_kms->dp_displays,
  1239. sde_kms->dp_display_count);
  1240. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1241. }
  1242. return 0;
  1243. exit_deinit_dp:
  1244. kfree(sde_kms->dp_displays);
  1245. sde_kms->dp_stream_count = 0;
  1246. sde_kms->dp_display_count = 0;
  1247. sde_kms->dp_displays = NULL;
  1248. exit_deinit_wb:
  1249. kfree(sde_kms->wb_displays);
  1250. sde_kms->wb_display_count = 0;
  1251. sde_kms->wb_displays = NULL;
  1252. exit_deinit_dsi:
  1253. kfree(sde_kms->dsi_displays);
  1254. sde_kms->dsi_display_count = 0;
  1255. sde_kms->dsi_displays = NULL;
  1256. return rc;
  1257. }
  1258. /**
  1259. * _sde_kms_release_displays - release cache of underlying display handles
  1260. * @sde_kms: Pointer to sde kms structure
  1261. */
  1262. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1263. {
  1264. if (!sde_kms) {
  1265. SDE_ERROR("invalid sde kms\n");
  1266. return;
  1267. }
  1268. kfree(sde_kms->wb_displays);
  1269. sde_kms->wb_displays = NULL;
  1270. sde_kms->wb_display_count = 0;
  1271. kfree(sde_kms->dsi_displays);
  1272. sde_kms->dsi_displays = NULL;
  1273. sde_kms->dsi_display_count = 0;
  1274. }
  1275. /**
  1276. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1277. * for underlying displays
  1278. * @dev: Pointer to drm device structure
  1279. * @priv: Pointer to private drm device data
  1280. * @sde_kms: Pointer to sde kms structure
  1281. * Returns: Zero on success
  1282. */
  1283. static int _sde_kms_setup_displays(struct drm_device *dev,
  1284. struct msm_drm_private *priv,
  1285. struct sde_kms *sde_kms)
  1286. {
  1287. static const struct sde_connector_ops dsi_ops = {
  1288. .set_info_blob = dsi_conn_set_info_blob,
  1289. .detect = dsi_conn_detect,
  1290. .get_modes = dsi_connector_get_modes,
  1291. .pre_destroy = dsi_connector_put_modes,
  1292. .mode_valid = dsi_conn_mode_valid,
  1293. .get_info = dsi_display_get_info,
  1294. .set_backlight = dsi_display_set_backlight,
  1295. .soft_reset = dsi_display_soft_reset,
  1296. .pre_kickoff = dsi_conn_pre_kickoff,
  1297. .clk_ctrl = dsi_display_clk_ctrl,
  1298. .set_power = dsi_display_set_power,
  1299. .get_mode_info = dsi_conn_get_mode_info,
  1300. .get_dst_format = dsi_display_get_dst_format,
  1301. .post_kickoff = dsi_conn_post_kickoff,
  1302. .check_status = dsi_display_check_status,
  1303. .enable_event = dsi_conn_enable_event,
  1304. .cmd_transfer = dsi_display_cmd_transfer,
  1305. .cont_splash_config = dsi_display_cont_splash_config,
  1306. .get_panel_vfp = dsi_display_get_panel_vfp,
  1307. .get_default_lms = dsi_display_get_default_lms,
  1308. .cmd_receive = dsi_display_cmd_receive,
  1309. };
  1310. static const struct sde_connector_ops wb_ops = {
  1311. .post_init = sde_wb_connector_post_init,
  1312. .set_info_blob = sde_wb_connector_set_info_blob,
  1313. .detect = sde_wb_connector_detect,
  1314. .get_modes = sde_wb_connector_get_modes,
  1315. .set_property = sde_wb_connector_set_property,
  1316. .get_info = sde_wb_get_info,
  1317. .soft_reset = NULL,
  1318. .get_mode_info = sde_wb_get_mode_info,
  1319. .get_dst_format = NULL,
  1320. .check_status = NULL,
  1321. .cmd_transfer = NULL,
  1322. .cont_splash_config = NULL,
  1323. .get_panel_vfp = NULL,
  1324. .cmd_receive = NULL,
  1325. };
  1326. static const struct sde_connector_ops dp_ops = {
  1327. .post_init = dp_connector_post_init,
  1328. .detect = dp_connector_detect,
  1329. .get_modes = dp_connector_get_modes,
  1330. .atomic_check = dp_connector_atomic_check,
  1331. .mode_valid = dp_connector_mode_valid,
  1332. .get_info = dp_connector_get_info,
  1333. .get_mode_info = dp_connector_get_mode_info,
  1334. .post_open = dp_connector_post_open,
  1335. .check_status = NULL,
  1336. .set_colorspace = dp_connector_set_colorspace,
  1337. .config_hdr = dp_connector_config_hdr,
  1338. .cmd_transfer = NULL,
  1339. .cont_splash_config = NULL,
  1340. .get_panel_vfp = NULL,
  1341. .update_pps = dp_connector_update_pps,
  1342. .cmd_receive = NULL,
  1343. };
  1344. struct msm_display_info info;
  1345. struct drm_encoder *encoder;
  1346. void *display, *connector;
  1347. int i, max_encoders;
  1348. int rc = 0;
  1349. u32 dsc_count = 0, mixer_count = 0;
  1350. u32 max_dp_dsc_count, max_dp_mixer_count;
  1351. if (!dev || !priv || !sde_kms) {
  1352. SDE_ERROR("invalid argument(s)\n");
  1353. return -EINVAL;
  1354. }
  1355. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1356. sde_kms->dp_display_count +
  1357. sde_kms->dp_stream_count;
  1358. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1359. max_encoders = ARRAY_SIZE(priv->encoders);
  1360. SDE_ERROR("capping number of displays to %d", max_encoders);
  1361. }
  1362. /* wb */
  1363. for (i = 0; i < sde_kms->wb_display_count &&
  1364. priv->num_encoders < max_encoders; ++i) {
  1365. display = sde_kms->wb_displays[i];
  1366. encoder = NULL;
  1367. memset(&info, 0x0, sizeof(info));
  1368. rc = sde_wb_get_info(NULL, &info, display);
  1369. if (rc) {
  1370. SDE_ERROR("wb get_info %d failed\n", i);
  1371. continue;
  1372. }
  1373. encoder = sde_encoder_init(dev, &info);
  1374. if (IS_ERR_OR_NULL(encoder)) {
  1375. SDE_ERROR("encoder init failed for wb %d\n", i);
  1376. continue;
  1377. }
  1378. rc = sde_wb_drm_init(display, encoder);
  1379. if (rc) {
  1380. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1381. sde_encoder_destroy(encoder);
  1382. continue;
  1383. }
  1384. connector = sde_connector_init(dev,
  1385. encoder,
  1386. 0,
  1387. display,
  1388. &wb_ops,
  1389. DRM_CONNECTOR_POLL_HPD,
  1390. DRM_MODE_CONNECTOR_VIRTUAL);
  1391. if (connector) {
  1392. priv->encoders[priv->num_encoders++] = encoder;
  1393. priv->connectors[priv->num_connectors++] = connector;
  1394. } else {
  1395. SDE_ERROR("wb %d connector init failed\n", i);
  1396. sde_wb_drm_deinit(display);
  1397. sde_encoder_destroy(encoder);
  1398. }
  1399. }
  1400. /* dsi */
  1401. for (i = 0; i < sde_kms->dsi_display_count &&
  1402. priv->num_encoders < max_encoders; ++i) {
  1403. display = sde_kms->dsi_displays[i];
  1404. encoder = NULL;
  1405. memset(&info, 0x0, sizeof(info));
  1406. rc = dsi_display_get_info(NULL, &info, display);
  1407. if (rc) {
  1408. SDE_ERROR("dsi get_info %d failed\n", i);
  1409. continue;
  1410. }
  1411. encoder = sde_encoder_init(dev, &info);
  1412. if (IS_ERR_OR_NULL(encoder)) {
  1413. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1414. continue;
  1415. }
  1416. rc = dsi_display_drm_bridge_init(display, encoder);
  1417. if (rc) {
  1418. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1419. sde_encoder_destroy(encoder);
  1420. continue;
  1421. }
  1422. connector = sde_connector_init(dev,
  1423. encoder,
  1424. dsi_display_get_drm_panel(display),
  1425. display,
  1426. &dsi_ops,
  1427. DRM_CONNECTOR_POLL_HPD,
  1428. DRM_MODE_CONNECTOR_DSI);
  1429. if (connector) {
  1430. priv->encoders[priv->num_encoders++] = encoder;
  1431. priv->connectors[priv->num_connectors++] = connector;
  1432. } else {
  1433. SDE_ERROR("dsi %d connector init failed\n", i);
  1434. dsi_display_drm_bridge_deinit(display);
  1435. sde_encoder_destroy(encoder);
  1436. continue;
  1437. }
  1438. rc = dsi_display_drm_ext_bridge_init(display,
  1439. encoder, connector);
  1440. if (rc) {
  1441. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1442. dsi_display_drm_bridge_deinit(display);
  1443. sde_connector_destroy(connector);
  1444. sde_encoder_destroy(encoder);
  1445. }
  1446. dsc_count += info.dsc_count;
  1447. mixer_count += info.lm_count;
  1448. }
  1449. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1450. sde_kms->catalog->mixer_count - mixer_count : 0;
  1451. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1452. sde_kms->catalog->dsc_count - dsc_count : 0;
  1453. /* dp */
  1454. for (i = 0; i < sde_kms->dp_display_count &&
  1455. priv->num_encoders < max_encoders; ++i) {
  1456. int idx;
  1457. display = sde_kms->dp_displays[i];
  1458. encoder = NULL;
  1459. memset(&info, 0x0, sizeof(info));
  1460. rc = dp_connector_get_info(NULL, &info, display);
  1461. if (rc) {
  1462. SDE_ERROR("dp get_info %d failed\n", i);
  1463. continue;
  1464. }
  1465. encoder = sde_encoder_init(dev, &info);
  1466. if (IS_ERR_OR_NULL(encoder)) {
  1467. SDE_ERROR("dp encoder init failed %d\n", i);
  1468. continue;
  1469. }
  1470. rc = dp_drm_bridge_init(display, encoder,
  1471. max_dp_mixer_count, max_dp_dsc_count);
  1472. if (rc) {
  1473. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1474. sde_encoder_destroy(encoder);
  1475. continue;
  1476. }
  1477. connector = sde_connector_init(dev,
  1478. encoder,
  1479. NULL,
  1480. display,
  1481. &dp_ops,
  1482. DRM_CONNECTOR_POLL_HPD,
  1483. DRM_MODE_CONNECTOR_DisplayPort);
  1484. if (connector) {
  1485. priv->encoders[priv->num_encoders++] = encoder;
  1486. priv->connectors[priv->num_connectors++] = connector;
  1487. } else {
  1488. SDE_ERROR("dp %d connector init failed\n", i);
  1489. dp_drm_bridge_deinit(display);
  1490. sde_encoder_destroy(encoder);
  1491. }
  1492. /* update display cap to MST_MODE for DP MST encoders */
  1493. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1494. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1495. priv->num_encoders < max_encoders; idx++) {
  1496. info.h_tile_instance[0] = idx;
  1497. encoder = sde_encoder_init(dev, &info);
  1498. if (IS_ERR_OR_NULL(encoder)) {
  1499. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1500. continue;
  1501. }
  1502. rc = dp_mst_drm_bridge_init(display, encoder);
  1503. if (rc) {
  1504. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1505. i, rc);
  1506. sde_encoder_destroy(encoder);
  1507. continue;
  1508. }
  1509. priv->encoders[priv->num_encoders++] = encoder;
  1510. }
  1511. }
  1512. return 0;
  1513. }
  1514. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1515. {
  1516. struct msm_drm_private *priv;
  1517. int i;
  1518. if (!sde_kms) {
  1519. SDE_ERROR("invalid sde_kms\n");
  1520. return;
  1521. } else if (!sde_kms->dev) {
  1522. SDE_ERROR("invalid dev\n");
  1523. return;
  1524. } else if (!sde_kms->dev->dev_private) {
  1525. SDE_ERROR("invalid dev_private\n");
  1526. return;
  1527. }
  1528. priv = sde_kms->dev->dev_private;
  1529. for (i = 0; i < priv->num_crtcs; i++)
  1530. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1531. priv->num_crtcs = 0;
  1532. for (i = 0; i < priv->num_planes; i++)
  1533. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1534. priv->num_planes = 0;
  1535. for (i = 0; i < priv->num_connectors; i++)
  1536. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1537. priv->num_connectors = 0;
  1538. for (i = 0; i < priv->num_encoders; i++)
  1539. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1540. priv->num_encoders = 0;
  1541. _sde_kms_release_displays(sde_kms);
  1542. }
  1543. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1544. {
  1545. struct drm_device *dev;
  1546. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1547. struct drm_crtc *crtc;
  1548. struct msm_drm_private *priv;
  1549. struct sde_mdss_cfg *catalog;
  1550. int primary_planes_idx = 0, i, ret;
  1551. int max_crtc_count;
  1552. u32 sspp_id[MAX_PLANES];
  1553. u32 master_plane_id[MAX_PLANES];
  1554. u32 num_virt_planes = 0;
  1555. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1556. SDE_ERROR("invalid sde_kms\n");
  1557. return -EINVAL;
  1558. }
  1559. dev = sde_kms->dev;
  1560. priv = dev->dev_private;
  1561. catalog = sde_kms->catalog;
  1562. ret = sde_core_irq_domain_add(sde_kms);
  1563. if (ret)
  1564. goto fail_irq;
  1565. /*
  1566. * Query for underlying display drivers, and create connectors,
  1567. * bridges and encoders for them.
  1568. */
  1569. if (!_sde_kms_get_displays(sde_kms))
  1570. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1571. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1572. /* Create the planes */
  1573. for (i = 0; i < catalog->sspp_count; i++) {
  1574. bool primary = true;
  1575. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1576. || primary_planes_idx >= max_crtc_count)
  1577. primary = false;
  1578. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1579. (1UL << max_crtc_count) - 1, 0);
  1580. if (IS_ERR(plane)) {
  1581. SDE_ERROR("sde_plane_init failed\n");
  1582. ret = PTR_ERR(plane);
  1583. goto fail;
  1584. }
  1585. priv->planes[priv->num_planes++] = plane;
  1586. if (primary)
  1587. primary_planes[primary_planes_idx++] = plane;
  1588. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1589. sde_is_custom_client()) {
  1590. int priority =
  1591. catalog->sspp[i].sblk->smart_dma_priority;
  1592. sspp_id[priority - 1] = catalog->sspp[i].id;
  1593. master_plane_id[priority - 1] = plane->base.id;
  1594. num_virt_planes++;
  1595. }
  1596. }
  1597. /* Initialize smart DMA virtual planes */
  1598. for (i = 0; i < num_virt_planes; i++) {
  1599. plane = sde_plane_init(dev, sspp_id[i], false,
  1600. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1601. if (IS_ERR(plane)) {
  1602. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1603. ret = PTR_ERR(plane);
  1604. goto fail;
  1605. }
  1606. priv->planes[priv->num_planes++] = plane;
  1607. }
  1608. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1609. /* Create one CRTC per encoder */
  1610. for (i = 0; i < max_crtc_count; i++) {
  1611. crtc = sde_crtc_init(dev, primary_planes[i]);
  1612. if (IS_ERR(crtc)) {
  1613. ret = PTR_ERR(crtc);
  1614. goto fail;
  1615. }
  1616. priv->crtcs[priv->num_crtcs++] = crtc;
  1617. }
  1618. if (sde_is_custom_client()) {
  1619. /* All CRTCs are compatible with all planes */
  1620. for (i = 0; i < priv->num_planes; i++)
  1621. priv->planes[i]->possible_crtcs =
  1622. (1 << priv->num_crtcs) - 1;
  1623. }
  1624. /* All CRTCs are compatible with all encoders */
  1625. for (i = 0; i < priv->num_encoders; i++)
  1626. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1627. return 0;
  1628. fail:
  1629. _sde_kms_drm_obj_destroy(sde_kms);
  1630. fail_irq:
  1631. sde_core_irq_domain_fini(sde_kms);
  1632. return ret;
  1633. }
  1634. /**
  1635. * sde_kms_timeline_status - provides current timeline status
  1636. * This API should be called without mode config lock.
  1637. * @dev: Pointer to drm device
  1638. */
  1639. void sde_kms_timeline_status(struct drm_device *dev)
  1640. {
  1641. struct drm_crtc *crtc;
  1642. struct drm_connector *conn;
  1643. struct drm_connector_list_iter conn_iter;
  1644. if (!dev) {
  1645. SDE_ERROR("invalid drm device node\n");
  1646. return;
  1647. }
  1648. drm_for_each_crtc(crtc, dev)
  1649. sde_crtc_timeline_status(crtc);
  1650. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1651. /*
  1652. *Probably locked from last close dumping status anyway
  1653. */
  1654. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1655. drm_connector_list_iter_begin(dev, &conn_iter);
  1656. drm_for_each_connector_iter(conn, &conn_iter)
  1657. sde_conn_timeline_status(conn);
  1658. drm_connector_list_iter_end(&conn_iter);
  1659. return;
  1660. }
  1661. mutex_lock(&dev->mode_config.mutex);
  1662. drm_connector_list_iter_begin(dev, &conn_iter);
  1663. drm_for_each_connector_iter(conn, &conn_iter)
  1664. sde_conn_timeline_status(conn);
  1665. drm_connector_list_iter_end(&conn_iter);
  1666. mutex_unlock(&dev->mode_config.mutex);
  1667. }
  1668. static int sde_kms_postinit(struct msm_kms *kms)
  1669. {
  1670. struct sde_kms *sde_kms = to_sde_kms(kms);
  1671. struct drm_device *dev;
  1672. struct drm_crtc *crtc;
  1673. int rc;
  1674. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1675. SDE_ERROR("invalid sde_kms\n");
  1676. return -EINVAL;
  1677. }
  1678. dev = sde_kms->dev;
  1679. rc = _sde_debugfs_init(sde_kms);
  1680. if (rc)
  1681. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1682. drm_for_each_crtc(crtc, dev)
  1683. sde_crtc_post_init(dev, crtc);
  1684. return rc;
  1685. }
  1686. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1687. struct drm_encoder *encoder)
  1688. {
  1689. return rate;
  1690. }
  1691. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1692. struct platform_device *pdev)
  1693. {
  1694. struct drm_device *dev;
  1695. struct msm_drm_private *priv;
  1696. int i;
  1697. if (!sde_kms || !pdev)
  1698. return;
  1699. dev = sde_kms->dev;
  1700. if (!dev)
  1701. return;
  1702. priv = dev->dev_private;
  1703. if (!priv)
  1704. return;
  1705. if (sde_kms->genpd_init) {
  1706. sde_kms->genpd_init = false;
  1707. pm_genpd_remove(&sde_kms->genpd);
  1708. of_genpd_del_provider(pdev->dev.of_node);
  1709. }
  1710. if (sde_kms->vm && sde_kms->vm->vm_ops.vm_deinit)
  1711. sde_kms->vm->vm_ops.vm_deinit(sde_kms, &sde_kms->vm->vm_ops);
  1712. if (sde_kms->hw_intr)
  1713. sde_hw_intr_destroy(sde_kms->hw_intr);
  1714. sde_kms->hw_intr = NULL;
  1715. if (sde_kms->power_event)
  1716. sde_power_handle_unregister_event(
  1717. &priv->phandle, sde_kms->power_event);
  1718. _sde_kms_release_displays(sde_kms);
  1719. _sde_kms_unmap_all_splash_regions(sde_kms);
  1720. /* safe to call these more than once during shutdown */
  1721. _sde_debugfs_destroy(sde_kms);
  1722. _sde_kms_mmu_destroy(sde_kms);
  1723. if (sde_kms->catalog) {
  1724. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1725. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1726. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1727. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1728. }
  1729. }
  1730. if (sde_kms->rm_init)
  1731. sde_rm_destroy(&sde_kms->rm);
  1732. sde_kms->rm_init = false;
  1733. if (sde_kms->catalog)
  1734. sde_hw_catalog_deinit(sde_kms->catalog);
  1735. sde_kms->catalog = NULL;
  1736. if (sde_kms->sid)
  1737. msm_iounmap(pdev, sde_kms->sid);
  1738. sde_kms->sid = NULL;
  1739. if (sde_kms->reg_dma)
  1740. msm_iounmap(pdev, sde_kms->reg_dma);
  1741. sde_kms->reg_dma = NULL;
  1742. if (sde_kms->vbif[VBIF_NRT])
  1743. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1744. sde_kms->vbif[VBIF_NRT] = NULL;
  1745. if (sde_kms->vbif[VBIF_RT])
  1746. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1747. sde_kms->vbif[VBIF_RT] = NULL;
  1748. if (sde_kms->mmio)
  1749. msm_iounmap(pdev, sde_kms->mmio);
  1750. sde_kms->mmio = NULL;
  1751. sde_reg_dma_deinit();
  1752. }
  1753. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1754. {
  1755. int i;
  1756. if (!sde_kms)
  1757. return -EINVAL;
  1758. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1759. struct msm_mmu *mmu;
  1760. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1761. if (!aspace)
  1762. continue;
  1763. mmu = sde_kms->aspace[i]->mmu;
  1764. if (secure_only &&
  1765. !aspace->mmu->funcs->is_domain_secure(mmu))
  1766. continue;
  1767. /* cleanup aspace before detaching */
  1768. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1769. SDE_DEBUG("Detaching domain:%d\n", i);
  1770. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1771. ARRAY_SIZE(iommu_ports));
  1772. aspace->domain_attached = false;
  1773. }
  1774. return 0;
  1775. }
  1776. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1777. {
  1778. int i;
  1779. if (!sde_kms)
  1780. return -EINVAL;
  1781. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1782. struct msm_mmu *mmu;
  1783. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1784. if (!aspace)
  1785. continue;
  1786. mmu = sde_kms->aspace[i]->mmu;
  1787. if (secure_only &&
  1788. !aspace->mmu->funcs->is_domain_secure(mmu))
  1789. continue;
  1790. SDE_DEBUG("Attaching domain:%d\n", i);
  1791. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1792. ARRAY_SIZE(iommu_ports));
  1793. aspace->domain_attached = true;
  1794. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1795. }
  1796. return 0;
  1797. }
  1798. static void sde_kms_destroy(struct msm_kms *kms)
  1799. {
  1800. struct sde_kms *sde_kms;
  1801. struct drm_device *dev;
  1802. if (!kms) {
  1803. SDE_ERROR("invalid kms\n");
  1804. return;
  1805. }
  1806. sde_kms = to_sde_kms(kms);
  1807. dev = sde_kms->dev;
  1808. if (!dev || !dev->dev) {
  1809. SDE_ERROR("invalid device\n");
  1810. return;
  1811. }
  1812. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1813. kfree(sde_kms);
  1814. }
  1815. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1816. struct drm_atomic_state *state)
  1817. {
  1818. struct drm_device *dev = sde_kms->dev;
  1819. struct drm_plane *plane;
  1820. struct drm_plane_state *plane_state;
  1821. struct drm_crtc *crtc;
  1822. struct drm_crtc_state *crtc_state;
  1823. struct drm_connector *conn;
  1824. struct drm_connector_state *conn_state;
  1825. struct drm_connector_list_iter conn_iter;
  1826. int ret = 0;
  1827. drm_for_each_plane(plane, dev) {
  1828. plane_state = drm_atomic_get_plane_state(state, plane);
  1829. if (IS_ERR(plane_state)) {
  1830. ret = PTR_ERR(plane_state);
  1831. SDE_ERROR("error %d getting plane %d state\n",
  1832. ret, DRMID(plane));
  1833. return ret;
  1834. }
  1835. ret = sde_plane_helper_reset_custom_properties(plane,
  1836. plane_state);
  1837. if (ret) {
  1838. SDE_ERROR("error %d resetting plane props %d\n",
  1839. ret, DRMID(plane));
  1840. return ret;
  1841. }
  1842. }
  1843. drm_for_each_crtc(crtc, dev) {
  1844. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1845. if (IS_ERR(crtc_state)) {
  1846. ret = PTR_ERR(crtc_state);
  1847. SDE_ERROR("error %d getting crtc %d state\n",
  1848. ret, DRMID(crtc));
  1849. return ret;
  1850. }
  1851. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1852. if (ret) {
  1853. SDE_ERROR("error %d resetting crtc props %d\n",
  1854. ret, DRMID(crtc));
  1855. return ret;
  1856. }
  1857. }
  1858. drm_connector_list_iter_begin(dev, &conn_iter);
  1859. drm_for_each_connector_iter(conn, &conn_iter) {
  1860. conn_state = drm_atomic_get_connector_state(state, conn);
  1861. if (IS_ERR(conn_state)) {
  1862. ret = PTR_ERR(conn_state);
  1863. SDE_ERROR("error %d getting connector %d state\n",
  1864. ret, DRMID(conn));
  1865. return ret;
  1866. }
  1867. ret = sde_connector_helper_reset_custom_properties(conn,
  1868. conn_state);
  1869. if (ret) {
  1870. SDE_ERROR("error %d resetting connector props %d\n",
  1871. ret, DRMID(conn));
  1872. return ret;
  1873. }
  1874. }
  1875. drm_connector_list_iter_end(&conn_iter);
  1876. return ret;
  1877. }
  1878. static void sde_kms_lastclose(struct msm_kms *kms)
  1879. {
  1880. struct sde_kms *sde_kms;
  1881. struct drm_device *dev;
  1882. struct drm_atomic_state *state;
  1883. struct drm_modeset_acquire_ctx ctx;
  1884. int ret;
  1885. if (!kms) {
  1886. SDE_ERROR("invalid argument\n");
  1887. return;
  1888. }
  1889. sde_kms = to_sde_kms(kms);
  1890. dev = sde_kms->dev;
  1891. drm_modeset_acquire_init(&ctx, 0);
  1892. state = drm_atomic_state_alloc(dev);
  1893. if (!state) {
  1894. ret = -ENOMEM;
  1895. goto out_ctx;
  1896. }
  1897. state->acquire_ctx = &ctx;
  1898. retry:
  1899. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1900. if (ret)
  1901. goto out_state;
  1902. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1903. if (ret)
  1904. goto out_state;
  1905. ret = drm_atomic_commit(state);
  1906. out_state:
  1907. if (ret == -EDEADLK)
  1908. goto backoff;
  1909. drm_atomic_state_put(state);
  1910. out_ctx:
  1911. drm_modeset_drop_locks(&ctx);
  1912. drm_modeset_acquire_fini(&ctx);
  1913. if (ret)
  1914. SDE_ERROR("kms lastclose failed: %d\n", ret);
  1915. return;
  1916. backoff:
  1917. drm_atomic_state_clear(state);
  1918. drm_modeset_backoff(&ctx);
  1919. goto retry;
  1920. }
  1921. static int sde_kms_check_vm_request(struct msm_kms *kms,
  1922. struct drm_atomic_state *state)
  1923. {
  1924. struct sde_kms *sde_kms;
  1925. struct drm_device *dev;
  1926. struct drm_crtc *crtc;
  1927. struct drm_crtc_state *new_cstate, *old_cstate;
  1928. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  1929. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  1930. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  1931. struct sde_vm_ops *vm_ops;
  1932. bool vm_req_active = false;
  1933. enum sde_crtc_idle_pc_state idle_pc_state;
  1934. int rc = 0;
  1935. if (!kms || !state)
  1936. return -EINVAL;
  1937. sde_kms = to_sde_kms(kms);
  1938. dev = sde_kms->dev;
  1939. if (!sde_kms->vm)
  1940. return 0;
  1941. vm_ops = &sde_kms->vm->vm_ops;
  1942. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  1943. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  1944. new_state = to_sde_crtc_state(new_cstate);
  1945. if (!new_cstate->active && !new_cstate->active_changed)
  1946. continue;
  1947. new_vm_req = sde_crtc_get_property(new_state,
  1948. CRTC_PROP_VM_REQ_STATE);
  1949. commit_crtc_cnt++;
  1950. if (old_cstate) {
  1951. old_state = to_sde_crtc_state(old_cstate);
  1952. old_vm_req = sde_crtc_get_property(old_state,
  1953. CRTC_PROP_VM_REQ_STATE);
  1954. }
  1955. /**
  1956. * No active request if the transition is from
  1957. * VM_REQ_NONE to VM_REQ_NONE
  1958. */
  1959. if (new_vm_req || (old_state && old_vm_req))
  1960. vm_req_active = true;
  1961. idle_pc_state = sde_crtc_get_property(new_state,
  1962. CRTC_PROP_IDLE_PC_STATE);
  1963. active_crtc = crtc;
  1964. }
  1965. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1966. if (!crtc->state->active)
  1967. continue;
  1968. global_crtc_cnt++;
  1969. global_active_crtc = crtc;
  1970. }
  1971. /* Check for single crtc commits only on valid VM requests */
  1972. if (vm_req_active && active_crtc && global_active_crtc &&
  1973. (commit_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  1974. global_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  1975. active_crtc != global_active_crtc)) {
  1976. SDE_ERROR(
  1977. "failed to switch VM due to CRTC concurrencies: MAX_CNT: %d active_cnt: %d global_cnt: %d active_crtc: %d global_crtc: %d\n",
  1978. sde_kms->catalog->max_trusted_vm_displays,
  1979. commit_crtc_cnt, global_crtc_cnt, active_crtc,
  1980. global_active_crtc);
  1981. return -E2BIG;
  1982. }
  1983. if (!vm_req_active)
  1984. return 0;
  1985. /* disable idle-pc before releasing the HW */
  1986. if ((new_vm_req == VM_REQ_RELEASE) &&
  1987. (idle_pc_state == IDLE_PC_ENABLE)) {
  1988. SDE_ERROR("failed to switch VM since idle-pc is enabled\n");
  1989. return -EINVAL;
  1990. }
  1991. mutex_lock(&sde_kms->vm->vm_res_lock);
  1992. if (vm_ops->vm_request_valid)
  1993. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  1994. if (rc)
  1995. SDE_ERROR(
  1996. "failed to complete vm transition request. old_state = %d, new_state = %d, hw_ownership: %d\n",
  1997. old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  1998. mutex_unlock(&sde_kms->vm->vm_res_lock);
  1999. return rc;
  2000. }
  2001. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2002. struct drm_atomic_state *state)
  2003. {
  2004. struct sde_kms *sde_kms;
  2005. struct drm_device *dev;
  2006. struct drm_crtc *crtc;
  2007. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2008. struct drm_crtc_state *crtc_state;
  2009. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2010. bool sec_session = false, global_sec_session = false;
  2011. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2012. int i;
  2013. if (!kms || !state) {
  2014. return -EINVAL;
  2015. SDE_ERROR("invalid arguments\n");
  2016. }
  2017. sde_kms = to_sde_kms(kms);
  2018. dev = sde_kms->dev;
  2019. /* iterate state object for active secure/non-secure crtc */
  2020. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2021. if (!crtc_state->active)
  2022. continue;
  2023. active_crtc_cnt++;
  2024. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2025. &fb_sec, &fb_sec_dir);
  2026. if (fb_sec_dir)
  2027. sec_session = true;
  2028. cur_crtc = crtc;
  2029. }
  2030. /* iterate global list for active and secure/non-secure crtc */
  2031. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2032. if (!crtc->state->active)
  2033. continue;
  2034. global_active_crtc_cnt++;
  2035. /* update only when crtc is not the same as current crtc */
  2036. if (crtc != cur_crtc) {
  2037. fb_ns = fb_sec = fb_sec_dir = 0;
  2038. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2039. &fb_sec, &fb_sec_dir);
  2040. if (fb_sec_dir)
  2041. global_sec_session = true;
  2042. global_crtc = crtc;
  2043. }
  2044. }
  2045. if (!global_sec_session && !sec_session)
  2046. return 0;
  2047. /*
  2048. * - fail crtc commit, if secure-camera/secure-ui session is
  2049. * in-progress in any other display
  2050. * - fail secure-camera/secure-ui crtc commit, if any other display
  2051. * session is in-progress
  2052. */
  2053. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2054. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2055. SDE_ERROR(
  2056. "crtc%d secure check failed global_active:%d active:%d\n",
  2057. cur_crtc ? cur_crtc->base.id : -1,
  2058. global_active_crtc_cnt, active_crtc_cnt);
  2059. return -EPERM;
  2060. /*
  2061. * As only one crtc is allowed during secure session, the crtc
  2062. * in this commit should match with the global crtc
  2063. */
  2064. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2065. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2066. cur_crtc->base.id, sec_session,
  2067. global_crtc->base.id, global_sec_session);
  2068. return -EPERM;
  2069. }
  2070. return 0;
  2071. }
  2072. static int sde_kms_atomic_check(struct msm_kms *kms,
  2073. struct drm_atomic_state *state)
  2074. {
  2075. struct sde_kms *sde_kms;
  2076. struct drm_device *dev;
  2077. int ret;
  2078. if (!kms || !state)
  2079. return -EINVAL;
  2080. sde_kms = to_sde_kms(kms);
  2081. dev = sde_kms->dev;
  2082. SDE_ATRACE_BEGIN("atomic_check");
  2083. if (sde_kms_is_suspend_blocked(dev)) {
  2084. SDE_DEBUG("suspended, skip atomic_check\n");
  2085. ret = -EBUSY;
  2086. goto end;
  2087. }
  2088. ret = drm_atomic_helper_check(dev, state);
  2089. if (ret)
  2090. goto end;
  2091. /*
  2092. * Check if any secure transition(moving CRTC between secure and
  2093. * non-secure state and vice-versa) is allowed or not. when moving
  2094. * to secure state, planes with fb_mode set to dir_translated only can
  2095. * be staged on the CRTC, and only one CRTC can be active during
  2096. * Secure state
  2097. */
  2098. ret = sde_kms_check_secure_transition(kms, state);
  2099. if (ret)
  2100. goto end;
  2101. ret = sde_kms_check_vm_request(kms, state);
  2102. if (ret)
  2103. SDE_ERROR("vm switch request checks failed\n");
  2104. end:
  2105. SDE_ATRACE_END("atomic_check");
  2106. return ret;
  2107. }
  2108. static struct msm_gem_address_space*
  2109. _sde_kms_get_address_space(struct msm_kms *kms,
  2110. unsigned int domain)
  2111. {
  2112. struct sde_kms *sde_kms;
  2113. if (!kms) {
  2114. SDE_ERROR("invalid kms\n");
  2115. return NULL;
  2116. }
  2117. sde_kms = to_sde_kms(kms);
  2118. if (!sde_kms) {
  2119. SDE_ERROR("invalid sde_kms\n");
  2120. return NULL;
  2121. }
  2122. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2123. return NULL;
  2124. return (sde_kms->aspace[domain] &&
  2125. sde_kms->aspace[domain]->domain_attached) ?
  2126. sde_kms->aspace[domain] : NULL;
  2127. }
  2128. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2129. unsigned int domain)
  2130. {
  2131. struct sde_kms *sde_kms;
  2132. struct msm_gem_address_space *aspace;
  2133. if (!kms) {
  2134. SDE_ERROR("invalid kms\n");
  2135. return NULL;
  2136. }
  2137. sde_kms = to_sde_kms(kms);
  2138. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2139. SDE_ERROR("invalid params\n");
  2140. return NULL;
  2141. }
  2142. aspace = _sde_kms_get_address_space(kms, domain);
  2143. return (aspace && aspace->domain_attached) ?
  2144. msm_gem_get_aspace_device(aspace) : NULL;
  2145. }
  2146. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2147. {
  2148. struct drm_device *dev = NULL;
  2149. struct sde_kms *sde_kms = NULL;
  2150. struct drm_connector *connector = NULL;
  2151. struct drm_connector_list_iter conn_iter;
  2152. struct sde_connector *sde_conn = NULL;
  2153. if (!kms) {
  2154. SDE_ERROR("invalid kms\n");
  2155. return;
  2156. }
  2157. sde_kms = to_sde_kms(kms);
  2158. dev = sde_kms->dev;
  2159. if (!dev) {
  2160. SDE_ERROR("invalid device\n");
  2161. return;
  2162. }
  2163. if (!dev->mode_config.poll_enabled)
  2164. return;
  2165. mutex_lock(&dev->mode_config.mutex);
  2166. drm_connector_list_iter_begin(dev, &conn_iter);
  2167. drm_for_each_connector_iter(connector, &conn_iter) {
  2168. /* Only handle HPD capable connectors. */
  2169. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2170. continue;
  2171. sde_conn = to_sde_connector(connector);
  2172. if (sde_conn->ops.post_open)
  2173. sde_conn->ops.post_open(&sde_conn->base,
  2174. sde_conn->display);
  2175. }
  2176. drm_connector_list_iter_end(&conn_iter);
  2177. mutex_unlock(&dev->mode_config.mutex);
  2178. }
  2179. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2180. struct sde_splash_display *splash_display,
  2181. struct drm_crtc *crtc)
  2182. {
  2183. struct msm_drm_private *priv;
  2184. struct drm_plane *plane;
  2185. struct sde_splash_mem *splash;
  2186. enum sde_sspp plane_id;
  2187. bool is_virtual;
  2188. int i, j;
  2189. if (!sde_kms || !splash_display || !crtc) {
  2190. SDE_ERROR("invalid input args\n");
  2191. return -EINVAL;
  2192. }
  2193. priv = sde_kms->dev->dev_private;
  2194. for (i = 0; i < priv->num_planes; i++) {
  2195. plane = priv->planes[i];
  2196. plane_id = sde_plane_pipe(plane);
  2197. is_virtual = is_sde_plane_virtual(plane);
  2198. splash = splash_display->splash;
  2199. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2200. if ((plane_id != splash_display->pipes[j].sspp) ||
  2201. (splash_display->pipes[j].is_virtual
  2202. != is_virtual))
  2203. continue;
  2204. if (splash && sde_plane_validate_src_addr(plane,
  2205. splash->splash_buf_base,
  2206. splash->splash_buf_size)) {
  2207. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2208. plane_id, crtc->base.id);
  2209. }
  2210. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2211. crtc->base.id, plane_id, is_virtual);
  2212. }
  2213. }
  2214. return 0;
  2215. }
  2216. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  2217. {
  2218. void *display;
  2219. struct dsi_display *dsi_display;
  2220. struct msm_display_info info;
  2221. struct drm_encoder *encoder = NULL;
  2222. struct drm_crtc *crtc = NULL;
  2223. int i, rc = 0;
  2224. struct drm_display_mode *drm_mode = NULL;
  2225. struct drm_device *dev;
  2226. struct msm_drm_private *priv;
  2227. struct sde_kms *sde_kms;
  2228. struct drm_connector_list_iter conn_iter;
  2229. struct drm_connector *connector = NULL;
  2230. struct sde_connector *sde_conn = NULL;
  2231. struct sde_splash_display *splash_display;
  2232. if (!kms) {
  2233. SDE_ERROR("invalid kms\n");
  2234. return -EINVAL;
  2235. }
  2236. sde_kms = to_sde_kms(kms);
  2237. dev = sde_kms->dev;
  2238. if (!dev) {
  2239. SDE_ERROR("invalid device\n");
  2240. return -EINVAL;
  2241. }
  2242. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2243. && (!sde_kms->splash_data.num_splash_regions)) ||
  2244. !sde_kms->splash_data.num_splash_displays) {
  2245. DRM_INFO("cont_splash feature not enabled\n");
  2246. return rc;
  2247. }
  2248. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2249. sde_kms->splash_data.num_splash_displays,
  2250. sde_kms->dsi_display_count);
  2251. /* dsi */
  2252. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2253. display = sde_kms->dsi_displays[i];
  2254. dsi_display = (struct dsi_display *)display;
  2255. splash_display = &sde_kms->splash_data.splash_display[i];
  2256. if (!splash_display->cont_splash_enabled) {
  2257. SDE_DEBUG("display->name = %s splash not enabled\n",
  2258. dsi_display->name);
  2259. continue;
  2260. }
  2261. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2262. if (dsi_display->bridge->base.encoder) {
  2263. encoder = dsi_display->bridge->base.encoder;
  2264. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2265. }
  2266. memset(&info, 0x0, sizeof(info));
  2267. rc = dsi_display_get_info(NULL, &info, display);
  2268. if (rc) {
  2269. SDE_ERROR("dsi get_info %d failed\n", i);
  2270. encoder = NULL;
  2271. continue;
  2272. }
  2273. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2274. ((info.is_connected) ? "true" : "false"),
  2275. info.display_type);
  2276. if (!encoder) {
  2277. SDE_ERROR("encoder not initialized\n");
  2278. return -EINVAL;
  2279. }
  2280. priv = sde_kms->dev->dev_private;
  2281. encoder->crtc = priv->crtcs[i];
  2282. crtc = encoder->crtc;
  2283. splash_display->encoder = encoder;
  2284. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2285. i, crtc->base.id, encoder->base.id);
  2286. mutex_lock(&dev->mode_config.mutex);
  2287. drm_connector_list_iter_begin(dev, &conn_iter);
  2288. drm_for_each_connector_iter(connector, &conn_iter) {
  2289. /**
  2290. * SDE_KMS doesn't attach more than one encoder to
  2291. * a DSI connector. So it is safe to check only with
  2292. * the first encoder entry. Revisit this logic if we
  2293. * ever have to support continuous splash for
  2294. * external displays in MST configuration.
  2295. */
  2296. if (connector->encoder_ids[0] == encoder->base.id)
  2297. break;
  2298. }
  2299. drm_connector_list_iter_end(&conn_iter);
  2300. if (!connector) {
  2301. SDE_ERROR("connector not initialized\n");
  2302. mutex_unlock(&dev->mode_config.mutex);
  2303. return -EINVAL;
  2304. }
  2305. if (connector->funcs->fill_modes) {
  2306. connector->funcs->fill_modes(connector,
  2307. dev->mode_config.max_width,
  2308. dev->mode_config.max_height);
  2309. } else {
  2310. SDE_ERROR("fill_modes api not defined\n");
  2311. mutex_unlock(&dev->mode_config.mutex);
  2312. return -EINVAL;
  2313. }
  2314. mutex_unlock(&dev->mode_config.mutex);
  2315. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2316. /* currently consider modes[0] as the preferred mode */
  2317. drm_mode = list_first_entry(&connector->modes,
  2318. struct drm_display_mode, head);
  2319. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2320. drm_mode->name, drm_mode->type,
  2321. drm_mode->flags);
  2322. /* Update CRTC drm structure */
  2323. crtc->state->active = true;
  2324. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2325. if (rc) {
  2326. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2327. return rc;
  2328. }
  2329. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2330. drm_mode_copy(&crtc->mode, drm_mode);
  2331. /* Update encoder structure */
  2332. sde_encoder_update_caps_for_cont_splash(encoder,
  2333. splash_display, true);
  2334. sde_crtc_update_cont_splash_settings(crtc);
  2335. sde_conn = to_sde_connector(connector);
  2336. if (sde_conn && sde_conn->ops.cont_splash_config)
  2337. sde_conn->ops.cont_splash_config(sde_conn->display);
  2338. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2339. splash_display, crtc);
  2340. if (rc) {
  2341. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2342. return rc;
  2343. }
  2344. }
  2345. return rc;
  2346. }
  2347. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2348. {
  2349. struct sde_kms *sde_kms;
  2350. if (!kms) {
  2351. SDE_ERROR("invalid kms\n");
  2352. return false;
  2353. }
  2354. sde_kms = to_sde_kms(kms);
  2355. return sde_kms->splash_data.num_splash_displays;
  2356. }
  2357. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2358. const struct drm_display_mode *mode,
  2359. const struct msm_resource_caps_info *res, u32 *num_lm)
  2360. {
  2361. struct sde_kms *sde_kms;
  2362. s64 mode_clock_hz = 0;
  2363. s64 max_mdp_clock_hz = 0;
  2364. s64 max_lm_width = 0;
  2365. s64 hdisplay_fp = 0;
  2366. s64 htotal_fp = 0;
  2367. s64 vtotal_fp = 0;
  2368. s64 vrefresh_fp = 0;
  2369. s64 mdp_fudge_factor = 0;
  2370. s64 num_lm_fp = 0;
  2371. s64 lm_clk_fp = 0;
  2372. s64 lm_width_fp = 0;
  2373. int rc = 0;
  2374. if (!num_lm) {
  2375. SDE_ERROR("invalid num_lm pointer\n");
  2376. return -EINVAL;
  2377. }
  2378. /* default to 1 layer mixer */
  2379. *num_lm = 1;
  2380. if (!kms || !mode || !res) {
  2381. SDE_ERROR("invalid input args\n");
  2382. return -EINVAL;
  2383. }
  2384. sde_kms = to_sde_kms(kms);
  2385. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2386. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2387. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2388. htotal_fp = drm_int2fixp(mode->htotal);
  2389. vtotal_fp = drm_int2fixp(mode->vtotal);
  2390. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2391. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2392. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2393. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2394. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2395. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2396. if (mode_clock_hz > max_mdp_clock_hz ||
  2397. hdisplay_fp > max_lm_width) {
  2398. *num_lm = 0;
  2399. do {
  2400. *num_lm += 2;
  2401. num_lm_fp = drm_int2fixp(*num_lm);
  2402. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2403. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2404. if (*num_lm > 4) {
  2405. rc = -EINVAL;
  2406. goto error;
  2407. }
  2408. } while (lm_clk_fp > max_mdp_clock_hz ||
  2409. lm_width_fp > max_lm_width);
  2410. mode_clock_hz = lm_clk_fp;
  2411. }
  2412. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2413. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2414. *num_lm, drm_fixp2int(mode_clock_hz),
  2415. sde_kms->perf.max_core_clk_rate);
  2416. return 0;
  2417. error:
  2418. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2419. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2420. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2421. *num_lm, drm_fixp2int(mode_clock_hz),
  2422. sde_kms->perf.max_core_clk_rate);
  2423. return rc;
  2424. }
  2425. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2426. u32 hdisplay, u32 *num_dsc)
  2427. {
  2428. struct sde_kms *sde_kms;
  2429. uint32_t max_dsc_width;
  2430. if (!num_dsc) {
  2431. SDE_ERROR("invalid num_dsc pointer\n");
  2432. return -EINVAL;
  2433. }
  2434. *num_dsc = 0;
  2435. if (!kms || !hdisplay) {
  2436. SDE_ERROR("invalid input args\n");
  2437. return -EINVAL;
  2438. }
  2439. sde_kms = to_sde_kms(kms);
  2440. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2441. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2442. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2443. hdisplay, max_dsc_width,
  2444. *num_dsc);
  2445. return 0;
  2446. }
  2447. static void _sde_kms_null_commit(struct drm_device *dev,
  2448. struct drm_encoder *enc)
  2449. {
  2450. struct drm_modeset_acquire_ctx ctx;
  2451. struct drm_connector *conn = NULL;
  2452. struct drm_connector *tmp_conn = NULL;
  2453. struct drm_connector_list_iter conn_iter;
  2454. struct drm_atomic_state *state = NULL;
  2455. struct drm_crtc_state *crtc_state = NULL;
  2456. struct drm_connector_state *conn_state = NULL;
  2457. int retry_cnt = 0;
  2458. int ret = 0;
  2459. drm_modeset_acquire_init(&ctx, 0);
  2460. retry:
  2461. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2462. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2463. drm_modeset_backoff(&ctx);
  2464. retry_cnt++;
  2465. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2466. goto retry;
  2467. } else if (WARN_ON(ret)) {
  2468. goto end;
  2469. }
  2470. state = drm_atomic_state_alloc(dev);
  2471. if (!state) {
  2472. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2473. goto end;
  2474. }
  2475. state->acquire_ctx = &ctx;
  2476. drm_connector_list_iter_begin(dev, &conn_iter);
  2477. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2478. if (enc == tmp_conn->state->best_encoder) {
  2479. conn = tmp_conn;
  2480. break;
  2481. }
  2482. }
  2483. drm_connector_list_iter_end(&conn_iter);
  2484. if (!conn) {
  2485. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2486. goto end;
  2487. }
  2488. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2489. conn_state = drm_atomic_get_connector_state(state, conn);
  2490. if (IS_ERR(conn_state)) {
  2491. SDE_ERROR("error %d getting connector %d state\n",
  2492. ret, DRMID(conn));
  2493. goto end;
  2494. }
  2495. crtc_state->active = true;
  2496. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2497. if (ret)
  2498. SDE_ERROR("error %d setting the crtc\n", ret);
  2499. ret = drm_atomic_commit(state);
  2500. if (ret)
  2501. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2502. end:
  2503. if (state)
  2504. drm_atomic_state_put(state);
  2505. drm_modeset_drop_locks(&ctx);
  2506. drm_modeset_acquire_fini(&ctx);
  2507. }
  2508. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2509. struct device *dev)
  2510. {
  2511. int i, ret, crtc_id = 0;
  2512. struct drm_device *ddev = dev_get_drvdata(dev);
  2513. struct drm_connector *conn;
  2514. struct drm_connector_list_iter conn_iter;
  2515. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2516. drm_connector_list_iter_begin(ddev, &conn_iter);
  2517. drm_for_each_connector_iter(conn, &conn_iter) {
  2518. uint64_t lp;
  2519. lp = sde_connector_get_lp(conn);
  2520. if (lp != SDE_MODE_DPMS_LP2)
  2521. continue;
  2522. if (sde_encoder_in_clone_mode(conn->encoder))
  2523. continue;
  2524. ret = sde_encoder_wait_for_event(conn->encoder,
  2525. MSM_ENC_TX_COMPLETE);
  2526. if (ret && ret != -EWOULDBLOCK) {
  2527. SDE_ERROR(
  2528. "[conn: %d] wait for commit done returned %d\n",
  2529. conn->base.id, ret);
  2530. } else if (!ret) {
  2531. crtc_id = drm_crtc_index(conn->state->crtc);
  2532. if (priv->event_thread[crtc_id].thread)
  2533. kthread_flush_worker(
  2534. &priv->event_thread[crtc_id].worker);
  2535. sde_encoder_idle_request(conn->encoder);
  2536. }
  2537. }
  2538. drm_connector_list_iter_end(&conn_iter);
  2539. for (i = 0; i < priv->num_crtcs; i++) {
  2540. if (priv->disp_thread[i].thread)
  2541. kthread_flush_worker(
  2542. &priv->disp_thread[i].worker);
  2543. if (priv->event_thread[i].thread)
  2544. kthread_flush_worker(
  2545. &priv->event_thread[i].worker);
  2546. }
  2547. kthread_flush_worker(&priv->pp_event_worker);
  2548. }
  2549. static int sde_kms_pm_suspend(struct device *dev)
  2550. {
  2551. struct drm_device *ddev;
  2552. struct drm_modeset_acquire_ctx ctx;
  2553. struct drm_connector *conn;
  2554. struct drm_encoder *enc;
  2555. struct drm_connector_list_iter conn_iter;
  2556. struct drm_atomic_state *state = NULL;
  2557. struct sde_kms *sde_kms;
  2558. int ret = 0, num_crtcs = 0;
  2559. if (!dev)
  2560. return -EINVAL;
  2561. ddev = dev_get_drvdata(dev);
  2562. if (!ddev || !ddev_to_msm_kms(ddev))
  2563. return -EINVAL;
  2564. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2565. SDE_EVT32(0);
  2566. /* disable hot-plug polling */
  2567. drm_kms_helper_poll_disable(ddev);
  2568. /* if a display stuck in CS trigger a null commit to complete handoff */
  2569. drm_for_each_encoder(enc, ddev) {
  2570. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2571. _sde_kms_null_commit(ddev, enc);
  2572. }
  2573. /* acquire modeset lock(s) */
  2574. drm_modeset_acquire_init(&ctx, 0);
  2575. retry:
  2576. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2577. if (ret)
  2578. goto unlock;
  2579. /* save current state for resume */
  2580. if (sde_kms->suspend_state)
  2581. drm_atomic_state_put(sde_kms->suspend_state);
  2582. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2583. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2584. ret = PTR_ERR(sde_kms->suspend_state);
  2585. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2586. sde_kms->suspend_state = NULL;
  2587. goto unlock;
  2588. }
  2589. /* create atomic state to disable all CRTCs */
  2590. state = drm_atomic_state_alloc(ddev);
  2591. if (!state) {
  2592. ret = -ENOMEM;
  2593. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2594. goto unlock;
  2595. }
  2596. state->acquire_ctx = &ctx;
  2597. drm_connector_list_iter_begin(ddev, &conn_iter);
  2598. drm_for_each_connector_iter(conn, &conn_iter) {
  2599. struct drm_crtc_state *crtc_state;
  2600. uint64_t lp;
  2601. if (!conn->state || !conn->state->crtc ||
  2602. conn->dpms != DRM_MODE_DPMS_ON ||
  2603. sde_encoder_in_clone_mode(conn->encoder))
  2604. continue;
  2605. lp = sde_connector_get_lp(conn);
  2606. if (lp == SDE_MODE_DPMS_LP1) {
  2607. /* transition LP1->LP2 on pm suspend */
  2608. ret = sde_connector_set_property_for_commit(conn, state,
  2609. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2610. if (ret) {
  2611. DRM_ERROR("failed to set lp2 for conn %d\n",
  2612. conn->base.id);
  2613. drm_connector_list_iter_end(&conn_iter);
  2614. goto unlock;
  2615. }
  2616. }
  2617. if (lp != SDE_MODE_DPMS_LP2) {
  2618. /* force CRTC to be inactive */
  2619. crtc_state = drm_atomic_get_crtc_state(state,
  2620. conn->state->crtc);
  2621. if (IS_ERR_OR_NULL(crtc_state)) {
  2622. DRM_ERROR("failed to get crtc %d state\n",
  2623. conn->state->crtc->base.id);
  2624. drm_connector_list_iter_end(&conn_iter);
  2625. goto unlock;
  2626. }
  2627. if (lp != SDE_MODE_DPMS_LP1)
  2628. crtc_state->active = false;
  2629. ++num_crtcs;
  2630. }
  2631. }
  2632. drm_connector_list_iter_end(&conn_iter);
  2633. /* check for nothing to do */
  2634. if (num_crtcs == 0) {
  2635. DRM_DEBUG("all crtcs are already in the off state\n");
  2636. sde_kms->suspend_block = true;
  2637. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2638. goto unlock;
  2639. }
  2640. /* commit the "disable all" state */
  2641. ret = drm_atomic_commit(state);
  2642. if (ret < 0) {
  2643. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2644. goto unlock;
  2645. }
  2646. sde_kms->suspend_block = true;
  2647. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2648. unlock:
  2649. if (state) {
  2650. drm_atomic_state_put(state);
  2651. state = NULL;
  2652. }
  2653. if (ret == -EDEADLK) {
  2654. drm_modeset_backoff(&ctx);
  2655. goto retry;
  2656. }
  2657. drm_modeset_drop_locks(&ctx);
  2658. drm_modeset_acquire_fini(&ctx);
  2659. /*
  2660. * pm runtime driver avoids multiple runtime_suspend API call by
  2661. * checking runtime_status. However, this call helps when there is a
  2662. * race condition between pm_suspend call and doze_suspend/power_off
  2663. * commit. It removes the extra vote from suspend and adds it back
  2664. * later to allow power collapse during pm_suspend call
  2665. */
  2666. pm_runtime_put_sync(dev);
  2667. pm_runtime_get_noresume(dev);
  2668. /* dump clock state before entering suspend */
  2669. if (sde_kms->pm_suspend_clk_dump)
  2670. _sde_kms_dump_clks_state(sde_kms);
  2671. return ret;
  2672. }
  2673. static int sde_kms_pm_resume(struct device *dev)
  2674. {
  2675. struct drm_device *ddev;
  2676. struct sde_kms *sde_kms;
  2677. struct drm_modeset_acquire_ctx ctx;
  2678. int ret, i;
  2679. if (!dev)
  2680. return -EINVAL;
  2681. ddev = dev_get_drvdata(dev);
  2682. if (!ddev || !ddev_to_msm_kms(ddev))
  2683. return -EINVAL;
  2684. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2685. SDE_EVT32(sde_kms->suspend_state != NULL);
  2686. drm_mode_config_reset(ddev);
  2687. drm_modeset_acquire_init(&ctx, 0);
  2688. retry:
  2689. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2690. if (ret == -EDEADLK) {
  2691. drm_modeset_backoff(&ctx);
  2692. goto retry;
  2693. } else if (WARN_ON(ret)) {
  2694. goto end;
  2695. }
  2696. sde_kms->suspend_block = false;
  2697. if (sde_kms->suspend_state) {
  2698. sde_kms->suspend_state->acquire_ctx = &ctx;
  2699. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2700. ret = drm_atomic_helper_commit_duplicated_state(
  2701. sde_kms->suspend_state, &ctx);
  2702. if (ret != -EDEADLK)
  2703. break;
  2704. drm_modeset_backoff(&ctx);
  2705. }
  2706. if (ret < 0)
  2707. DRM_ERROR("failed to restore state, %d\n", ret);
  2708. drm_atomic_state_put(sde_kms->suspend_state);
  2709. sde_kms->suspend_state = NULL;
  2710. }
  2711. end:
  2712. drm_modeset_drop_locks(&ctx);
  2713. drm_modeset_acquire_fini(&ctx);
  2714. /* enable hot-plug polling */
  2715. drm_kms_helper_poll_enable(ddev);
  2716. return 0;
  2717. }
  2718. static const struct msm_kms_funcs kms_funcs = {
  2719. .hw_init = sde_kms_hw_init,
  2720. .postinit = sde_kms_postinit,
  2721. .irq_preinstall = sde_irq_preinstall,
  2722. .irq_postinstall = sde_irq_postinstall,
  2723. .irq_uninstall = sde_irq_uninstall,
  2724. .irq = sde_irq,
  2725. .lastclose = sde_kms_lastclose,
  2726. .prepare_fence = sde_kms_prepare_fence,
  2727. .prepare_commit = sde_kms_prepare_commit,
  2728. .commit = sde_kms_commit,
  2729. .complete_commit = sde_kms_complete_commit,
  2730. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2731. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2732. .enable_vblank = sde_kms_enable_vblank,
  2733. .disable_vblank = sde_kms_disable_vblank,
  2734. .check_modified_format = sde_format_check_modified_format,
  2735. .atomic_check = sde_kms_atomic_check,
  2736. .get_format = sde_get_msm_format,
  2737. .round_pixclk = sde_kms_round_pixclk,
  2738. .pm_suspend = sde_kms_pm_suspend,
  2739. .pm_resume = sde_kms_pm_resume,
  2740. .destroy = sde_kms_destroy,
  2741. .cont_splash_config = sde_kms_cont_splash_config,
  2742. .register_events = _sde_kms_register_events,
  2743. .get_address_space = _sde_kms_get_address_space,
  2744. .get_address_space_device = _sde_kms_get_address_space_device,
  2745. .postopen = _sde_kms_post_open,
  2746. .check_for_splash = sde_kms_check_for_splash,
  2747. .get_mixer_count = sde_kms_get_mixer_count,
  2748. .get_dsc_count = sde_kms_get_dsc_count,
  2749. };
  2750. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2751. {
  2752. int i;
  2753. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2754. if (!sde_kms->aspace[i])
  2755. continue;
  2756. msm_gem_address_space_put(sde_kms->aspace[i]);
  2757. sde_kms->aspace[i] = NULL;
  2758. }
  2759. return 0;
  2760. }
  2761. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2762. {
  2763. struct msm_mmu *mmu;
  2764. int i, ret;
  2765. int early_map = 0;
  2766. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  2767. return -EINVAL;
  2768. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2769. struct msm_gem_address_space *aspace;
  2770. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2771. if (IS_ERR(mmu)) {
  2772. ret = PTR_ERR(mmu);
  2773. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2774. i, ret);
  2775. continue;
  2776. }
  2777. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2778. mmu, "sde");
  2779. if (IS_ERR(aspace)) {
  2780. ret = PTR_ERR(aspace);
  2781. goto fail;
  2782. }
  2783. sde_kms->aspace[i] = aspace;
  2784. aspace->domain_attached = true;
  2785. /* Mapping splash memory block */
  2786. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2787. sde_kms->splash_data.num_splash_regions) {
  2788. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2789. if (ret) {
  2790. SDE_ERROR("failed to map ret:%d\n", ret);
  2791. goto fail;
  2792. }
  2793. }
  2794. /*
  2795. * disable early-map which would have been enabled during
  2796. * bootup by smmu through the device-tree hint for cont-spash
  2797. */
  2798. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2799. &early_map);
  2800. if (ret) {
  2801. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2802. ret, early_map);
  2803. goto early_map_fail;
  2804. }
  2805. }
  2806. sde_kms->base.aspace = sde_kms->aspace[0];
  2807. return 0;
  2808. early_map_fail:
  2809. _sde_kms_unmap_all_splash_regions(sde_kms);
  2810. fail:
  2811. mmu->funcs->destroy(mmu);
  2812. _sde_kms_mmu_destroy(sde_kms);
  2813. return ret;
  2814. }
  2815. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2816. {
  2817. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2818. return;
  2819. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2820. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2821. sde_kms->catalog);
  2822. if (sde_kms->sid)
  2823. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  2824. }
  2825. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2826. {
  2827. struct sde_vbif_set_qos_params qos_params;
  2828. struct sde_mdss_cfg *catalog;
  2829. if (!sde_kms->catalog)
  2830. return;
  2831. catalog = sde_kms->catalog;
  2832. memset(&qos_params, 0, sizeof(qos_params));
  2833. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2834. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2835. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2836. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2837. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2838. }
  2839. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  2840. {
  2841. struct sde_hw_uidle *uidle;
  2842. if (!sde_kms) {
  2843. SDE_ERROR("invalid kms\n");
  2844. return -EINVAL;
  2845. }
  2846. uidle = sde_kms->hw_uidle;
  2847. if (uidle && uidle->ops.active_override_enable)
  2848. uidle->ops.active_override_enable(uidle, enable);
  2849. return 0;
  2850. }
  2851. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  2852. {
  2853. struct device *cpu_dev;
  2854. int cpu = 0;
  2855. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  2856. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2857. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2858. return;
  2859. }
  2860. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2861. cpu_dev = get_cpu_device(cpu);
  2862. if (!cpu_dev) {
  2863. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2864. cpu);
  2865. continue;
  2866. }
  2867. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2868. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  2869. cpu_irq_latency);
  2870. else
  2871. dev_pm_qos_add_request(cpu_dev,
  2872. &sde_kms->pm_qos_irq_req[cpu],
  2873. DEV_PM_QOS_RESUME_LATENCY,
  2874. cpu_irq_latency);
  2875. }
  2876. }
  2877. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  2878. {
  2879. struct device *cpu_dev;
  2880. int cpu = 0;
  2881. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  2882. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  2883. return;
  2884. }
  2885. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  2886. cpu_dev = get_cpu_device(cpu);
  2887. if (!cpu_dev) {
  2888. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  2889. cpu);
  2890. continue;
  2891. }
  2892. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  2893. dev_pm_qos_remove_request(
  2894. &sde_kms->pm_qos_irq_req[cpu]);
  2895. }
  2896. }
  2897. void sde_kms_irq_enable_notify(struct sde_kms *sde_kms, bool enable)
  2898. {
  2899. if (enable)
  2900. _sde_kms_update_pm_qos_irq_request(sde_kms);
  2901. else
  2902. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  2903. }
  2904. static void sde_kms_irq_affinity_notify(
  2905. struct irq_affinity_notify *affinity_notify,
  2906. const cpumask_t *mask)
  2907. {
  2908. struct msm_drm_private *priv;
  2909. struct sde_kms *sde_kms = container_of(affinity_notify,
  2910. struct sde_kms, affinity_notify);
  2911. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  2912. return;
  2913. priv = sde_kms->dev->dev_private;
  2914. mutex_lock(&priv->phandle.phandle_lock);
  2915. // save irq cpu mask
  2916. sde_kms->irq_cpu_mask = *mask;
  2917. // request vote with updated irq cpu mask
  2918. if (sde_kms->irq_enabled)
  2919. _sde_kms_update_pm_qos_irq_request(sde_kms);
  2920. mutex_unlock(&priv->phandle.phandle_lock);
  2921. }
  2922. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  2923. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2924. {
  2925. struct sde_kms *sde_kms = usr;
  2926. struct msm_kms *msm_kms;
  2927. msm_kms = &sde_kms->base;
  2928. if (!sde_kms)
  2929. return;
  2930. SDE_DEBUG("event_type:%d\n", event_type);
  2931. SDE_EVT32_VERBOSE(event_type);
  2932. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2933. sde_irq_update(msm_kms, true);
  2934. sde_kms->first_kickoff = true;
  2935. if (sde_kms->splash_data.num_splash_displays ||
  2936. sde_in_trusted_vm(sde_kms))
  2937. return;
  2938. sde_vbif_init_memtypes(sde_kms);
  2939. sde_kms_init_shared_hw(sde_kms);
  2940. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2941. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2942. sde_irq_update(msm_kms, false);
  2943. sde_kms->first_kickoff = false;
  2944. if (sde_in_trusted_vm(sde_kms))
  2945. return;
  2946. _sde_kms_active_override(sde_kms, true);
  2947. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  2948. sde_vbif_axi_halt_request(sde_kms);
  2949. }
  2950. }
  2951. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2952. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2953. {
  2954. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2955. int rc = -EINVAL;
  2956. SDE_DEBUG("\n");
  2957. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2958. if (rc > 0)
  2959. rc = 0;
  2960. SDE_EVT32(rc, genpd->device_count);
  2961. return rc;
  2962. }
  2963. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2964. {
  2965. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2966. SDE_DEBUG("\n");
  2967. pm_runtime_put_sync(sde_kms->dev->dev);
  2968. SDE_EVT32(genpd->device_count);
  2969. return 0;
  2970. }
  2971. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  2972. struct sde_splash_data *data)
  2973. {
  2974. int i = 0;
  2975. int ret = 0;
  2976. struct device_node *parent, *node, *node1;
  2977. struct resource r, r1;
  2978. const char *node_name = "splash_region";
  2979. struct sde_splash_mem *mem;
  2980. bool share_splash_mem = false;
  2981. int num_displays, num_regions;
  2982. struct sde_splash_display *splash_display;
  2983. if (!data)
  2984. return -EINVAL;
  2985. memset(data, 0, sizeof(*data));
  2986. parent = of_find_node_by_path("/reserved-memory");
  2987. if (!parent) {
  2988. SDE_ERROR("failed to find reserved-memory node\n");
  2989. return -EINVAL;
  2990. }
  2991. node = of_find_node_by_name(parent, node_name);
  2992. if (!node) {
  2993. SDE_DEBUG("failed to find node %s\n", node_name);
  2994. return -EINVAL;
  2995. }
  2996. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  2997. if (!node1)
  2998. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2999. /**
  3000. * Support sharing a single splash memory for all the built in displays
  3001. * and also independent splash region per displays. Incase of
  3002. * independent splash region for each connected display, dtsi node of
  3003. * cont_splash_region should be collection of all memory regions
  3004. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3005. */
  3006. num_displays = dsi_display_get_num_of_displays();
  3007. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3008. data->num_splash_displays = num_displays;
  3009. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3010. if (num_displays > num_regions) {
  3011. share_splash_mem = true;
  3012. pr_info(":%d displays share same splash buf\n", num_displays);
  3013. }
  3014. for (i = 0; i < num_displays; i++) {
  3015. splash_display = &data->splash_display[i];
  3016. if (!i || !share_splash_mem) {
  3017. if (of_address_to_resource(node, i, &r)) {
  3018. SDE_ERROR("invalid data for:%s\n", node_name);
  3019. return -EINVAL;
  3020. }
  3021. mem = &data->splash_mem[i];
  3022. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3023. SDE_DEBUG("failed to find ramdump memory\n");
  3024. mem->ramdump_base = 0;
  3025. mem->ramdump_size = 0;
  3026. } else {
  3027. mem->ramdump_base = (unsigned long)r1.start;
  3028. mem->ramdump_size = (r1.end - r1.start) + 1;
  3029. }
  3030. mem->splash_buf_base = (unsigned long)r.start;
  3031. mem->splash_buf_size = (r.end - r.start) + 1;
  3032. mem->ref_cnt = 0;
  3033. splash_display->splash = mem;
  3034. data->num_splash_regions++;
  3035. } else {
  3036. data->splash_display[i].splash = &data->splash_mem[0];
  3037. }
  3038. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3039. splash_display->splash->splash_buf_base,
  3040. splash_display->splash->splash_buf_size);
  3041. }
  3042. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3043. return ret;
  3044. }
  3045. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3046. struct platform_device *platformdev)
  3047. {
  3048. int rc = -EINVAL;
  3049. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3050. if (IS_ERR(sde_kms->mmio)) {
  3051. rc = PTR_ERR(sde_kms->mmio);
  3052. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3053. sde_kms->mmio = NULL;
  3054. goto error;
  3055. }
  3056. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3057. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3058. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3059. sde_kms->mmio_len);
  3060. if (rc)
  3061. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3062. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3063. "vbif_phys");
  3064. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3065. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3066. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3067. sde_kms->vbif[VBIF_RT] = NULL;
  3068. goto error;
  3069. }
  3070. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3071. "vbif_phys");
  3072. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3073. sde_kms->vbif_len[VBIF_RT]);
  3074. if (rc)
  3075. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3076. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3077. "vbif_nrt_phys");
  3078. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3079. sde_kms->vbif[VBIF_NRT] = NULL;
  3080. SDE_DEBUG("VBIF NRT is not defined");
  3081. } else {
  3082. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3083. "vbif_nrt_phys");
  3084. rc = sde_dbg_reg_register_base("vbif_nrt",
  3085. sde_kms->vbif[VBIF_NRT],
  3086. sde_kms->vbif_len[VBIF_NRT]);
  3087. if (rc)
  3088. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3089. rc);
  3090. }
  3091. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3092. "regdma_phys");
  3093. if (IS_ERR(sde_kms->reg_dma)) {
  3094. sde_kms->reg_dma = NULL;
  3095. SDE_DEBUG("REG_DMA is not defined");
  3096. } else {
  3097. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3098. "regdma_phys");
  3099. rc = sde_dbg_reg_register_base("reg_dma",
  3100. sde_kms->reg_dma,
  3101. sde_kms->reg_dma_len);
  3102. if (rc)
  3103. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3104. rc);
  3105. }
  3106. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3107. "sid_phys");
  3108. if (IS_ERR(sde_kms->sid)) {
  3109. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3110. sde_kms->sid = NULL;
  3111. } else {
  3112. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3113. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3114. sde_kms->sid_len);
  3115. if (rc)
  3116. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3117. }
  3118. error:
  3119. return rc;
  3120. }
  3121. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3122. struct sde_kms *sde_kms)
  3123. {
  3124. int rc = 0;
  3125. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3126. sde_kms->genpd.name = dev->unique;
  3127. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3128. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3129. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3130. if (rc < 0) {
  3131. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3132. sde_kms->genpd.name, rc);
  3133. return rc;
  3134. }
  3135. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3136. &sde_kms->genpd);
  3137. if (rc < 0) {
  3138. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3139. sde_kms->genpd.name, rc);
  3140. pm_genpd_remove(&sde_kms->genpd);
  3141. return rc;
  3142. }
  3143. sde_kms->genpd_init = true;
  3144. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3145. }
  3146. return rc;
  3147. }
  3148. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3149. struct drm_device *dev,
  3150. struct msm_drm_private *priv)
  3151. {
  3152. struct sde_rm *rm = NULL;
  3153. int i, rc = -EINVAL;
  3154. sde_kms->catalog = sde_hw_catalog_init(dev);
  3155. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3156. rc = PTR_ERR(sde_kms->catalog);
  3157. if (!sde_kms->catalog)
  3158. rc = -EINVAL;
  3159. SDE_ERROR("catalog init failed: %d\n", rc);
  3160. sde_kms->catalog = NULL;
  3161. goto power_error;
  3162. }
  3163. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3164. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3165. /* initialize power domain if defined */
  3166. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3167. if (rc) {
  3168. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3169. goto genpd_err;
  3170. }
  3171. rc = _sde_kms_mmu_init(sde_kms);
  3172. if (rc) {
  3173. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3174. goto power_error;
  3175. }
  3176. /* Initialize reg dma block which is a singleton */
  3177. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3178. sde_kms->dev);
  3179. if (rc) {
  3180. SDE_ERROR("failed: reg dma init failed\n");
  3181. goto power_error;
  3182. }
  3183. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3184. rm = &sde_kms->rm;
  3185. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3186. sde_kms->dev);
  3187. if (rc) {
  3188. SDE_ERROR("rm init failed: %d\n", rc);
  3189. goto power_error;
  3190. }
  3191. sde_kms->rm_init = true;
  3192. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3193. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3194. rc = PTR_ERR(sde_kms->hw_intr);
  3195. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3196. sde_kms->hw_intr = NULL;
  3197. goto hw_intr_init_err;
  3198. }
  3199. /*
  3200. * Attempt continuous splash handoff only if reserved
  3201. * splash memory is found & release resources on any error
  3202. * in finding display hw config in splash
  3203. */
  3204. if (sde_kms->splash_data.num_splash_regions) {
  3205. struct sde_splash_display *display;
  3206. int ret, display_count =
  3207. sde_kms->splash_data.num_splash_displays;
  3208. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3209. &sde_kms->splash_data, sde_kms->catalog);
  3210. for (i = 0; i < display_count; i++) {
  3211. display = &sde_kms->splash_data.splash_display[i];
  3212. /*
  3213. * free splash region on resource init failure and
  3214. * cont-splash disabled case
  3215. */
  3216. if (!display->cont_splash_enabled || ret)
  3217. _sde_kms_free_splash_display_data(
  3218. sde_kms, display);
  3219. }
  3220. }
  3221. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3222. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3223. rc = PTR_ERR(sde_kms->hw_mdp);
  3224. if (!sde_kms->hw_mdp)
  3225. rc = -EINVAL;
  3226. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3227. sde_kms->hw_mdp = NULL;
  3228. goto power_error;
  3229. }
  3230. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3231. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3232. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3233. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3234. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3235. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3236. if (!sde_kms->hw_vbif[vbif_idx])
  3237. rc = -EINVAL;
  3238. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3239. sde_kms->hw_vbif[vbif_idx] = NULL;
  3240. goto power_error;
  3241. }
  3242. }
  3243. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3244. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3245. sde_kms->mmio_len, sde_kms->catalog);
  3246. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3247. rc = PTR_ERR(sde_kms->hw_uidle);
  3248. if (!sde_kms->hw_uidle)
  3249. rc = -EINVAL;
  3250. /* uidle is optional, so do not make it a fatal error */
  3251. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3252. sde_kms->hw_uidle = NULL;
  3253. rc = 0;
  3254. }
  3255. } else {
  3256. sde_kms->hw_uidle = NULL;
  3257. }
  3258. if (sde_kms->sid) {
  3259. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3260. sde_kms->sid_len, sde_kms->catalog);
  3261. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3262. rc = PTR_ERR(sde_kms->hw_sid);
  3263. SDE_ERROR("failed to init sid %ld\n", rc);
  3264. sde_kms->hw_sid = NULL;
  3265. goto power_error;
  3266. }
  3267. }
  3268. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3269. &priv->phandle, "core_clk");
  3270. if (rc) {
  3271. SDE_ERROR("failed to init perf %d\n", rc);
  3272. goto perf_err;
  3273. }
  3274. /*
  3275. * _sde_kms_drm_obj_init should create the DRM related objects
  3276. * i.e. CRTCs, planes, encoders, connectors and so forth
  3277. */
  3278. rc = _sde_kms_drm_obj_init(sde_kms);
  3279. if (rc) {
  3280. SDE_ERROR("modeset init failed: %d\n", rc);
  3281. goto drm_obj_init_err;
  3282. }
  3283. return 0;
  3284. genpd_err:
  3285. drm_obj_init_err:
  3286. sde_core_perf_destroy(&sde_kms->perf);
  3287. hw_intr_init_err:
  3288. perf_err:
  3289. power_error:
  3290. return rc;
  3291. }
  3292. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3293. {
  3294. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3295. int rc = 0;
  3296. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3297. if (rc) {
  3298. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3299. return rc;
  3300. }
  3301. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3302. if (rc) {
  3303. SDE_ERROR("failed to get io irq for KMS");
  3304. return rc;
  3305. }
  3306. return rc;
  3307. }
  3308. static int sde_kms_hw_init(struct msm_kms *kms)
  3309. {
  3310. struct sde_kms *sde_kms;
  3311. struct drm_device *dev;
  3312. struct msm_drm_private *priv;
  3313. struct platform_device *platformdev;
  3314. int i, irq_num, rc = -EINVAL;
  3315. if (!kms) {
  3316. SDE_ERROR("invalid kms\n");
  3317. goto end;
  3318. }
  3319. sde_kms = to_sde_kms(kms);
  3320. dev = sde_kms->dev;
  3321. if (!dev || !dev->dev) {
  3322. SDE_ERROR("invalid device\n");
  3323. goto end;
  3324. }
  3325. platformdev = to_platform_device(dev->dev);
  3326. priv = dev->dev_private;
  3327. if (!priv) {
  3328. SDE_ERROR("invalid private data\n");
  3329. goto end;
  3330. }
  3331. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3332. if (rc)
  3333. goto error;
  3334. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3335. if (rc)
  3336. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3337. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3338. if (rc)
  3339. goto error;
  3340. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3341. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3342. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3343. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3344. mutex_init(&sde_kms->secure_transition_lock);
  3345. atomic_set(&sde_kms->detach_sec_cb, 0);
  3346. atomic_set(&sde_kms->detach_all_cb, 0);
  3347. /*
  3348. * Support format modifiers for compression etc.
  3349. */
  3350. dev->mode_config.allow_fb_modifiers = true;
  3351. /*
  3352. * Handle (re)initializations during power enable
  3353. */
  3354. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3355. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3356. SDE_POWER_EVENT_POST_ENABLE |
  3357. SDE_POWER_EVENT_PRE_DISABLE,
  3358. sde_kms_handle_power_event, sde_kms, "kms");
  3359. if (sde_kms->splash_data.num_splash_displays) {
  3360. SDE_DEBUG("Skipping MDP Resources disable\n");
  3361. } else {
  3362. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3363. sde_power_data_bus_set_quota(&priv->phandle, i,
  3364. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3365. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3366. pm_runtime_put_sync(sde_kms->dev->dev);
  3367. }
  3368. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3369. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3370. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3371. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3372. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3373. if (sde_in_trusted_vm(sde_kms))
  3374. rc = sde_vm_trusted_init(sde_kms);
  3375. else
  3376. rc = sde_vm_primary_init(sde_kms);
  3377. if (rc) {
  3378. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3379. goto error;
  3380. }
  3381. return 0;
  3382. error:
  3383. _sde_kms_hw_destroy(sde_kms, platformdev);
  3384. end:
  3385. return rc;
  3386. }
  3387. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3388. {
  3389. struct msm_drm_private *priv;
  3390. struct sde_kms *sde_kms;
  3391. if (!dev || !dev->dev_private) {
  3392. SDE_ERROR("drm device node invalid\n");
  3393. return ERR_PTR(-EINVAL);
  3394. }
  3395. priv = dev->dev_private;
  3396. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3397. if (!sde_kms) {
  3398. SDE_ERROR("failed to allocate sde kms\n");
  3399. return ERR_PTR(-ENOMEM);
  3400. }
  3401. msm_kms_init(&sde_kms->base, &kms_funcs);
  3402. sde_kms->dev = dev;
  3403. return &sde_kms->base;
  3404. }
  3405. static int _sde_kms_register_events(struct msm_kms *kms,
  3406. struct drm_mode_object *obj, u32 event, bool en)
  3407. {
  3408. int ret = 0;
  3409. struct drm_crtc *crtc = NULL;
  3410. struct drm_connector *conn = NULL;
  3411. struct sde_kms *sde_kms = NULL;
  3412. if (!kms || !obj) {
  3413. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3414. return -EINVAL;
  3415. }
  3416. sde_kms = to_sde_kms(kms);
  3417. switch (obj->type) {
  3418. case DRM_MODE_OBJECT_CRTC:
  3419. crtc = obj_to_crtc(obj);
  3420. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3421. break;
  3422. case DRM_MODE_OBJECT_CONNECTOR:
  3423. conn = obj_to_connector(obj);
  3424. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3425. en);
  3426. break;
  3427. }
  3428. return ret;
  3429. }
  3430. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3431. {
  3432. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3433. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3434. }