cam_soc_util.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _CAM_SOC_UTIL_H_
  6. #define _CAM_SOC_UTIL_H_
  7. #include <linux/types.h>
  8. #include <linux/slab.h>
  9. #include <linux/clk.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/delay.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/debugfs.h>
  17. #include <linux/of_fdt.h>
  18. #include "cam_io_util.h"
  19. #include <media/cam_defs.h>
  20. #define NO_SET_RATE -1
  21. #define INIT_RATE -2
  22. /* maximum number of device block */
  23. #define CAM_SOC_MAX_BLOCK 7
  24. /* maximum number of device base */
  25. #define CAM_SOC_MAX_BASE CAM_SOC_MAX_BLOCK
  26. /* maximum number of device regulator */
  27. #define CAM_SOC_MAX_REGULATOR 10
  28. /* maximum number of device clock */
  29. #define CAM_SOC_MAX_CLK 32
  30. /* DDR device types */
  31. #define DDR_TYPE_LPDDR4 6
  32. #define DDR_TYPE_LPDDR4X 7
  33. #define DDR_TYPE_LPDDR5 8
  34. #define DDR_TYPE_LPDDR5X 9
  35. /* Maximum length of tag while dumping */
  36. #define CAM_SOC_HW_DUMP_TAG_MAX_LEN 32
  37. /**
  38. * enum cam_vote_level - Enum for voting level
  39. *
  40. * @CAM_SUSPEND_VOTE : Suspend vote
  41. * @CAM_MINSVS_VOTE : Min SVS vote
  42. * @CAM_LOWSVS_VOTE : Low SVS vote
  43. * @CAM_SVS_VOTE : SVS vote
  44. * @CAM_SVSL1_VOTE : SVS Plus vote
  45. * @CAM_NOMINAL_VOTE : Nominal vote
  46. * @CAM_NOMINALL1_VOTE: Nominal plus vote
  47. * @CAM_TURBO_VOTE : Turbo vote
  48. * @CAM_MAX_VOTE : Max voting level, This is invalid level.
  49. */
  50. enum cam_vote_level {
  51. CAM_SUSPEND_VOTE,
  52. CAM_MINSVS_VOTE,
  53. CAM_LOWSVS_VOTE,
  54. CAM_SVS_VOTE,
  55. CAM_SVSL1_VOTE,
  56. CAM_NOMINAL_VOTE,
  57. CAM_NOMINALL1_VOTE,
  58. CAM_TURBO_VOTE,
  59. CAM_MAX_VOTE,
  60. };
  61. /* pinctrl states */
  62. #define CAM_SOC_PINCTRL_STATE_SLEEP "cam_suspend"
  63. #define CAM_SOC_PINCTRL_STATE_DEFAULT "cam_default"
  64. /**
  65. * struct cam_soc_reg_map: Information about the mapped register space
  66. *
  67. * @mem_base: Starting location of MAPPED register space
  68. * @mem_cam_base: Starting offset of this register space compared
  69. * to ENTIRE Camera register space
  70. * @size: Size of register space
  71. **/
  72. struct cam_soc_reg_map {
  73. void __iomem *mem_base;
  74. uint32_t mem_cam_base;
  75. resource_size_t size;
  76. };
  77. /**
  78. * struct cam_soc_pinctrl_info: Information about pinctrl data
  79. *
  80. * @pinctrl: pintrl object
  81. * @gpio_state_active: default pinctrl state
  82. * @gpio_state_suspend suspend state of pinctrl
  83. **/
  84. struct cam_soc_pinctrl_info {
  85. struct pinctrl *pinctrl;
  86. struct pinctrl_state *gpio_state_active;
  87. struct pinctrl_state *gpio_state_suspend;
  88. };
  89. /**
  90. * struct cam_soc_gpio_data: Information about the gpio pins
  91. *
  92. * @cam_gpio_common_tbl: It is list of al the gpios present in gpios node
  93. * @cam_gpio_common_tbl_size: It is equal to number of gpios prsent in
  94. * gpios node in DTSI
  95. * @cam_gpio_req_tbl It is list of al the requesetd gpios
  96. * @cam_gpio_req_tbl_size: It is size of requested gpios
  97. **/
  98. struct cam_soc_gpio_data {
  99. struct gpio *cam_gpio_common_tbl;
  100. uint8_t cam_gpio_common_tbl_size;
  101. struct gpio *cam_gpio_req_tbl;
  102. uint8_t cam_gpio_req_tbl_size;
  103. };
  104. /**
  105. * struct cam_hw_soc_info: Soc information pertaining to specific instance of
  106. * Camera hardware driver module
  107. *
  108. * @pdev: Platform device pointer
  109. * @device: Device pointer
  110. * @hw_version: Camera device version
  111. * @index: Instance id for the camera device
  112. * @dev_name: Device Name
  113. * @irq_name: Name of the irq associated with the device
  114. * @label_name: label name
  115. * @irq_line: Irq resource
  116. * @irq_data: Private data that is passed when IRQ is requested
  117. * @compatible: Compatible string associated with the device
  118. * @num_mem_block: Number of entry in the "reg-names"
  119. * @mem_block_name: Array of the reg block name
  120. * @mem_block_cam_base: Array of offset of this register space compared
  121. * to ENTIRE Camera register space
  122. * @mem_block: Associated resource structs
  123. * @reg_map: Array of Mapped register info for the "reg-names"
  124. * @num_reg_map: Number of mapped register space associated
  125. * with mem_block. num_reg_map = num_mem_block in
  126. * most cases
  127. * @reserve_mem: Whether to reserve memory for Mem blocks
  128. * @num_rgltr: Number of regulators
  129. * @rgltr_name: Array of regulator names
  130. * @rgltr_ctrl_support: Whether regulator control is supported
  131. * @rgltr_min_volt: Array of minimum regulator voltage
  132. * @rgltr_max_volt: Array of maximum regulator voltage
  133. * @rgltr_op_mode: Array of regulator operation mode
  134. * @rgltr_type: Array of regulator names
  135. * @rgltr: Array of associated regulator resources
  136. * @rgltr_delay: Array of regulator delay values
  137. * @num_clk: Number of clocks
  138. * @clk_name: Array of clock names
  139. * @clk: Array of associated clock resources
  140. * @clk_rate: 2D array of clock rates representing clock rate
  141. * values at different vote levels
  142. * @prev_clk_level Last vote level
  143. * @src_clk_idx: Source clock index that is rate-controllable
  144. * @clk_level_valid: Indicates whether corresponding level is valid
  145. * @scl_clk_count: Number of scalable clocks present
  146. * @scl_clk_idx: Index of scalable clocks
  147. * @gpio_data: Pointer to gpio info
  148. * @pinctrl_info: Pointer to pinctrl info
  149. * @dentry: Debugfs entry
  150. * @clk_level_override: Clk level set from debugfs
  151. * @clk_control: Enable/disable clk rate control through debugfs
  152. * @cam_cx_ipeak_enable cx-ipeak enable/disable flag
  153. * @cam_cx_ipeak_bit cx-ipeak mask for driver
  154. * @soc_private: Soc private data
  155. */
  156. struct cam_hw_soc_info {
  157. struct platform_device *pdev;
  158. struct device *dev;
  159. uint32_t hw_version;
  160. uint32_t index;
  161. const char *dev_name;
  162. const char *irq_name;
  163. const char *label_name;
  164. struct resource *irq_line;
  165. void *irq_data;
  166. const char *compatible;
  167. uint32_t num_mem_block;
  168. const char *mem_block_name[CAM_SOC_MAX_BLOCK];
  169. uint32_t mem_block_cam_base[CAM_SOC_MAX_BLOCK];
  170. struct resource *mem_block[CAM_SOC_MAX_BLOCK];
  171. struct cam_soc_reg_map reg_map[CAM_SOC_MAX_BASE];
  172. uint32_t num_reg_map;
  173. uint32_t reserve_mem;
  174. uint32_t num_rgltr;
  175. const char *rgltr_name[CAM_SOC_MAX_REGULATOR];
  176. uint32_t rgltr_ctrl_support;
  177. uint32_t rgltr_min_volt[CAM_SOC_MAX_REGULATOR];
  178. uint32_t rgltr_max_volt[CAM_SOC_MAX_REGULATOR];
  179. uint32_t rgltr_op_mode[CAM_SOC_MAX_REGULATOR];
  180. uint32_t rgltr_type[CAM_SOC_MAX_REGULATOR];
  181. struct regulator *rgltr[CAM_SOC_MAX_REGULATOR];
  182. uint32_t rgltr_delay[CAM_SOC_MAX_REGULATOR];
  183. uint32_t use_shared_clk;
  184. uint32_t num_clk;
  185. const char *clk_name[CAM_SOC_MAX_CLK];
  186. struct clk *clk[CAM_SOC_MAX_CLK];
  187. int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
  188. int32_t prev_clk_level;
  189. int32_t src_clk_idx;
  190. bool clk_level_valid[CAM_MAX_VOTE];
  191. int32_t scl_clk_count;
  192. int32_t scl_clk_idx[CAM_SOC_MAX_CLK];
  193. struct cam_soc_gpio_data *gpio_data;
  194. struct cam_soc_pinctrl_info pinctrl_info;
  195. struct dentry *dentry;
  196. uint32_t clk_level_override;
  197. bool clk_control_enable;
  198. bool cam_cx_ipeak_enable;
  199. int32_t cam_cx_ipeak_bit;
  200. void *soc_private;
  201. };
  202. /**
  203. * struct cam_hw_soc_dump_header - SOC dump header
  204. *
  205. * @Brief: soc hw dump header
  206. *
  207. * @tag: Tag name for the header
  208. * @word_size: Size of each word
  209. * @size: Total size of dumped data
  210. */
  211. struct cam_hw_soc_dump_header {
  212. uint8_t tag[CAM_SOC_HW_DUMP_TAG_MAX_LEN];
  213. uint64_t size;
  214. uint32_t word_size;
  215. };
  216. /**
  217. * struct cam_hw_soc_dump_args: SOC Dump args
  218. *
  219. * @request_id: Issue request id
  220. * @offset: Buffer offset, updated as the informaton is dumped
  221. * @buf_handle: Buffer handle of the out buffer
  222. */
  223. struct cam_hw_soc_dump_args {
  224. uint64_t request_id;
  225. size_t offset;
  226. uint32_t buf_handle;
  227. };
  228. /*
  229. * CAM_SOC_GET_REG_MAP_START
  230. *
  231. * @brief: This MACRO will get the mapped starting address
  232. * where the register space can be accessed
  233. *
  234. * @__soc_info: Device soc information
  235. * @__base_index: Index of register space in the HW block
  236. *
  237. * @return: Returns a pointer to the mapped register memory
  238. */
  239. #define CAM_SOC_GET_REG_MAP_START(__soc_info, __base_index) \
  240. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  241. NULL : __soc_info->reg_map[__base_index].mem_base)
  242. /*
  243. * CAM_SOC_GET_REG_MAP_CAM_BASE
  244. *
  245. * @brief: This MACRO will get the cam_base of the
  246. * register space
  247. *
  248. * @__soc_info: Device soc information
  249. * @__base_index: Index of register space in the HW block
  250. *
  251. * @return: Returns an int32_t value.
  252. * Failure: -1
  253. * Success: Starting offset of register space compared
  254. * to entire Camera Register Map
  255. */
  256. #define CAM_SOC_GET_REG_MAP_CAM_BASE(__soc_info, __base_index) \
  257. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  258. -1 : __soc_info->reg_map[__base_index].mem_cam_base)
  259. /*
  260. * CAM_SOC_GET_REG_MAP_SIZE
  261. *
  262. * @brief: This MACRO will get the size of the mapped
  263. * register space
  264. *
  265. * @__soc_info: Device soc information
  266. * @__base_index: Index of register space in the HW block
  267. *
  268. * @return: Returns a uint32_t value.
  269. * Failure: 0
  270. * Success: Non-zero size of mapped register space
  271. */
  272. #define CAM_SOC_GET_REG_MAP_SIZE(__soc_info, __base_index) \
  273. ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
  274. 0 : __soc_info->reg_map[__base_index].size)
  275. /**
  276. * cam_soc_util_get_level_from_string()
  277. *
  278. * @brief: Get the associated vote level for the input string
  279. *
  280. * @string: Input string to compare with.
  281. * @level: Vote level corresponds to input string.
  282. *
  283. * @return: Success or failure
  284. */
  285. int cam_soc_util_get_level_from_string(const char *string,
  286. enum cam_vote_level *level);
  287. /**
  288. * cam_soc_util_get_dt_properties()
  289. *
  290. * @brief: Parse the DT and populate the common properties that
  291. * are part of the soc_info structure - register map,
  292. * clocks, regulators, irq, etc.
  293. *
  294. * @soc_info: Device soc struct to be populated
  295. *
  296. * @return: Success or failure
  297. */
  298. int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info);
  299. /**
  300. * cam_soc_util_request_platform_resource()
  301. *
  302. * @brief: Request regulator, irq, and clock resources
  303. *
  304. * @soc_info: Device soc information
  305. * @handler: Irq handler function pointer
  306. * @irq_data: Irq handler function CB data
  307. *
  308. * @return: Success or failure
  309. */
  310. int cam_soc_util_request_platform_resource(struct cam_hw_soc_info *soc_info,
  311. irq_handler_t handler, void *irq_data);
  312. /**
  313. * cam_soc_util_release_platform_resource()
  314. *
  315. * @brief: Release regulator, irq, and clock resources
  316. *
  317. * @soc_info: Device soc information
  318. *
  319. * @return: Success or failure
  320. */
  321. int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info);
  322. /**
  323. * cam_soc_util_enable_platform_resource()
  324. *
  325. * @brief: Enable regulator, irq resources
  326. *
  327. * @soc_info: Device soc information
  328. * @enable_clocks: Boolean flag:
  329. * TRUE: Enable all clocks in soc_info Now.
  330. * False: Don't enable clocks Now. Driver will
  331. * enable independently.
  332. * @clk_level: Clock level to be applied.
  333. * Applicable only if enable_clocks is true
  334. * Valid range : 0 to (CAM_MAX_VOTE - 1)
  335. * @enable_irq: Boolean flag:
  336. * TRUE: Enable IRQ in soc_info Now.
  337. * False: Don't enable IRQ Now. Driver will
  338. * enable independently.
  339. *
  340. * @return: Success or failure
  341. */
  342. int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
  343. bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq);
  344. /**
  345. * cam_soc_util_disable_platform_resource()
  346. *
  347. * @brief: Disable regulator, irq resources
  348. *
  349. * @soc_info: Device soc information
  350. * @disable_irq: Boolean flag:
  351. * TRUE: Disable IRQ in soc_info Now.
  352. * False: Don't disable IRQ Now. Driver will
  353. * disable independently.
  354. *
  355. * @return: Success or failure
  356. */
  357. int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
  358. bool disable_clocks, bool disable_irq);
  359. /**
  360. * cam_soc_util_get_clk_round_rate()
  361. *
  362. * @brief: Get the rounded clock rate for the given clock's
  363. * clock rate value
  364. *
  365. * @soc_info: Device soc information
  366. * @clk_index: Clock index in soc_info for which round rate is needed
  367. * @clk_rate: Input clock rate for which rounded rate is needed
  368. *
  369. * @return: Rounded clock rate
  370. */
  371. long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
  372. uint32_t clk_index, unsigned long clk_rate);
  373. /**
  374. * cam_soc_util_set_src_clk_rate()
  375. *
  376. * @brief: Set the rate on the source clock.
  377. *
  378. * @soc_info: Device soc information
  379. * @clk_rate: Clock rate associated with the src clk
  380. *
  381. * @return: success or failure
  382. */
  383. int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
  384. int64_t clk_rate);
  385. /**
  386. * cam_soc_util_get_option_clk_by_name()
  387. *
  388. * @brief: Get reference to optional clk using name
  389. *
  390. * @soc_info: Device soc information
  391. * @clk_name: Name of clock to find reference for
  392. * @clk: Clock reference pointer to be filled if Success
  393. * @clk_index: Clk index in the option clk array to be returned
  394. * @clk_rate: Clk rate in the option clk array
  395. *
  396. * @return: 0: Success
  397. * Negative: Failure
  398. */
  399. int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
  400. const char *clk_name, struct clk **clk, int32_t *clk_index,
  401. int32_t *clk_rate);
  402. /**
  403. * cam_soc_util_clk_put()
  404. *
  405. * @brief: Put clock specified in params
  406. *
  407. * @clk: Reference to the Clock that needs to be put
  408. *
  409. * @return: Success or failure
  410. */
  411. int cam_soc_util_clk_put(struct clk **clk);
  412. /**
  413. * cam_soc_util_clk_enable()
  414. *
  415. * @brief: Enable clock specified in params
  416. *
  417. * @clk: Clock that needs to be turned ON
  418. * @clk_name: Clocks name associated with clk
  419. * @clk_rate: Clocks rate associated with clk
  420. *
  421. * @return: Success or failure
  422. */
  423. int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
  424. int32_t clk_rate);
  425. /**
  426. * cam_soc_util_set_clk_rate_level()
  427. *
  428. * @brief: Apply clock rates for the requested level.
  429. * This applies the new requested level for all
  430. * the clocks listed in DT based on their values.
  431. *
  432. * @soc_info: Device soc information
  433. * @clk_level: Clock level number to set
  434. *
  435. * @return: Success or failure
  436. */
  437. int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
  438. enum cam_vote_level clk_level);
  439. /**
  440. * cam_soc_util_clk_disable()
  441. *
  442. * @brief: Disable clock specified in params
  443. *
  444. * @clk: Clock that needs to be turned OFF
  445. * @clk_name: Clocks name associated with clk
  446. *
  447. * @return: Success or failure
  448. */
  449. int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name);
  450. /**
  451. * cam_soc_util_irq_enable()
  452. *
  453. * @brief: Enable IRQ in SOC
  454. *
  455. * @soc_info: Device soc information
  456. *
  457. * @return: Success or failure
  458. */
  459. int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info);
  460. /**
  461. * cam_soc_util_irq_disable()
  462. *
  463. * @brief: Disable IRQ in SOC
  464. *
  465. * @soc_info: Device soc information
  466. *
  467. * @return: Success or failure
  468. */
  469. int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info);
  470. /**
  471. * cam_soc_util_regulator_enable()
  472. *
  473. * @brief: Enable single regulator
  474. *
  475. * @rgltr Regulator that needs to be turned ON
  476. * @rgltr_name Associated Regulator name
  477. * @rgltr_min_volt: Requested minimum volatage
  478. * @rgltr_max_volt: Requested maximum volatage
  479. * @rgltr_op_mode: Requested Load
  480. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  481. *
  482. * @return: Success or failure
  483. */
  484. int cam_soc_util_regulator_enable(struct regulator *rgltr,
  485. const char *rgltr_name,
  486. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  487. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  488. /**
  489. * cam_soc_util_regulator_enable()
  490. *
  491. * @brief: Disable single regulator
  492. *
  493. * @rgltr Regulator that needs to be turned ON
  494. * @rgltr_name Associated Regulator name
  495. * @rgltr_min_volt: Requested minimum volatage
  496. * @rgltr_max_volt: Requested maximum volatage
  497. * @rgltr_op_mode: Requested Load
  498. * @rgltr_delay: Requested delay needed aaftre enabling regulator
  499. *
  500. * @return: Success or failure
  501. */
  502. int cam_soc_util_regulator_disable(struct regulator *rgltr,
  503. const char *rgltr_name,
  504. uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
  505. uint32_t rgltr_op_mode, uint32_t rgltr_delay);
  506. /**
  507. * cam_soc_util_w()
  508. *
  509. * @brief: Camera SOC util for register write
  510. *
  511. * @soc_info: Device soc information
  512. * @base_index: Index of register space in the HW block
  513. * @offset: Offset of register to be read
  514. * @data: Value to be written
  515. *
  516. * @return: Success or Failure
  517. */
  518. static inline int cam_soc_util_w(struct cam_hw_soc_info *soc_info,
  519. uint32_t base_index, uint32_t offset, uint32_t data)
  520. {
  521. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  522. return -EINVAL;
  523. return cam_io_w(data,
  524. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  525. }
  526. /**
  527. * cam_soc_util_w_mb()
  528. *
  529. * @brief: Camera SOC util for register write with memory barrier.
  530. * Memory Barrier is only before the write to ensure the
  531. * order. If need to ensure this write is also flushed
  532. * call wmb() independently in the caller.
  533. *
  534. * @soc_info: Device soc information
  535. * @base_index: Index of register space in the HW block
  536. * @offset: Offset of register to be read
  537. * @data: Value to be written
  538. *
  539. * @return: Success or Failure
  540. */
  541. static inline int cam_soc_util_w_mb(struct cam_hw_soc_info *soc_info,
  542. uint32_t base_index, uint32_t offset, uint32_t data)
  543. {
  544. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  545. return -EINVAL;
  546. return cam_io_w_mb(data,
  547. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  548. }
  549. /**
  550. * cam_soc_util_r()
  551. *
  552. * @brief: Camera SOC util for register read
  553. *
  554. * @soc_info: Device soc information
  555. * @base_index: Index of register space in the HW block
  556. * @offset: Offset of register to be read
  557. *
  558. * @return: Value read from the register address
  559. */
  560. static inline uint32_t cam_soc_util_r(struct cam_hw_soc_info *soc_info,
  561. uint32_t base_index, uint32_t offset)
  562. {
  563. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  564. return 0;
  565. return cam_io_r(
  566. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  567. }
  568. /**
  569. * cam_soc_util_r_mb()
  570. *
  571. * @brief: Camera SOC util for register read with memory barrier.
  572. * Memory Barrier is only before the write to ensure the
  573. * order. If need to ensure this write is also flushed
  574. * call rmb() independently in the caller.
  575. *
  576. * @soc_info: Device soc information
  577. * @base_index: Index of register space in the HW block
  578. * @offset: Offset of register to be read
  579. *
  580. * @return: Value read from the register address
  581. */
  582. static inline uint32_t cam_soc_util_r_mb(struct cam_hw_soc_info *soc_info,
  583. uint32_t base_index, uint32_t offset)
  584. {
  585. if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
  586. return 0;
  587. return cam_io_r_mb(
  588. CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
  589. }
  590. /**
  591. * cam_soc_util_reg_dump()
  592. *
  593. * @brief: Camera SOC util for dumping a range of register
  594. *
  595. * @soc_info: Device soc information
  596. * @base_index: Index of register space in the HW block
  597. * @offset: Start register offset for the dump
  598. * @size: Size specifying the range for dump
  599. *
  600. * @return: Success or Failure
  601. */
  602. int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
  603. uint32_t base_index, uint32_t offset, int size);
  604. void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info);
  605. int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
  606. enum cam_vote_level clk_level);
  607. int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info,
  608. int64_t clk_rate, int clk_idx, int32_t *clk_lvl);
  609. /* Callback to get reg space data for specific HW */
  610. typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type,
  611. void *ctx, struct cam_hw_soc_info **soc_info_ptr,
  612. uint32_t *reg_base_idx);
  613. /**
  614. * cam_soc_util_reg_dump_to_cmd_buf()
  615. *
  616. * @brief: Camera SOC util for dumping sets of register ranges
  617. * command buffer
  618. *
  619. * @ctx: Context info from specific hardware manager
  620. * @cmd_desc: Command buffer descriptor
  621. * @req_id: Last applied req id for which reg dump is required
  622. * @reg_data_cb: Callback function to get reg space info based on type
  623. * in command buffer
  624. * @soc_dump_args: Dump buffer args to dump the soc information.
  625. * @user_triggered_dump: Flag to indicate if the dump request is issued by
  626. * user.
  627. * @return: Success or Failure
  628. */
  629. int cam_soc_util_reg_dump_to_cmd_buf(void *ctx,
  630. struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id,
  631. cam_soc_util_regspace_data_cb reg_data_cb,
  632. struct cam_hw_soc_dump_args *soc_dump_args,
  633. bool user_triggered_dump);
  634. /**
  635. * cam_soc_util_print_clk_freq()
  636. *
  637. * @brief: This function gets the clk rates for each clk from clk
  638. * driver and prints in log
  639. *
  640. * @soc_info: Device soc struct to be populated
  641. *
  642. * @return: success or failure
  643. */
  644. int cam_soc_util_print_clk_freq(struct cam_hw_soc_info *soc_info);
  645. #endif /* _CAM_SOC_UTIL_H_ */