hal_internal.h 38 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_INTERNAL_H_
  19. #define _HAL_INTERNAL_H_
  20. #include "qdf_types.h"
  21. #include "qdf_atomic.h"
  22. #include "qdf_lock.h"
  23. #include "qdf_mem.h"
  24. #include "qdf_nbuf.h"
  25. #include "pld_common.h"
  26. #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
  27. defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
  28. #include "qdf_defer.h"
  29. #include "qdf_timer.h"
  30. #endif
  31. #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params)
  32. #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params)
  33. #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params)
  34. #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params)
  35. #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  36. #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params)
  37. #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params)
  38. #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params)
  39. #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params)
  40. #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params)
  41. #ifdef ENABLE_VERBOSE_DEBUG
  42. extern bool is_hal_verbose_debug_enabled;
  43. #define hal_verbose_debug(params...) \
  44. if (unlikely(is_hal_verbose_debug_enabled)) \
  45. do {\
  46. QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \
  47. } while (0)
  48. #define hal_verbose_hex_dump(params...) \
  49. if (unlikely(is_hal_verbose_debug_enabled)) \
  50. do {\
  51. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \
  52. QDF_TRACE_LEVEL_DEBUG, \
  53. params); \
  54. } while (0)
  55. #else
  56. #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params)
  57. #define hal_verbose_hex_dump(params...) \
  58. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \
  59. params)
  60. #endif
  61. /*
  62. * Given the offset of a field in bytes, returns uint8_t *
  63. */
  64. #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
  65. (((uint8_t *)(_ptr)) + (_off_in_bytes))
  66. /*
  67. * Given the offset of a field in bytes, returns uint32_t *
  68. */
  69. #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
  70. (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
  71. /*
  72. * Given the offset of a field in bytes, returns uint64_t *
  73. */
  74. #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \
  75. (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3))
  76. #define _HAL_MS(_word, _mask, _shift) \
  77. (((_word) & (_mask)) >> (_shift))
  78. /*
  79. * Get number of QWORDS possible for num.
  80. * Its the caller's duty to make sure num is a multiple of QWORD (8)
  81. */
  82. #define HAL_GET_NUM_QWORDS(num) ((num) >> 3)
  83. /*
  84. * Get number of DWORDS possible for num.
  85. * Its the caller's duty to make sure num is a multiple of DWORD (8)
  86. */
  87. #define HAL_GET_NUM_DWORDS(num) ((num) >> 2)
  88. /*
  89. * dp_hal_soc - opaque handle for DP HAL soc
  90. */
  91. struct hal_soc_handle;
  92. typedef struct hal_soc_handle *hal_soc_handle_t;
  93. /**
  94. * hal_ring_desc - opaque handle for DP ring descriptor
  95. */
  96. struct hal_ring_desc;
  97. typedef struct hal_ring_desc *hal_ring_desc_t;
  98. /**
  99. * hal_link_desc - opaque handle for DP link descriptor
  100. */
  101. struct hal_link_desc;
  102. typedef struct hal_link_desc *hal_link_desc_t;
  103. /**
  104. * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
  105. */
  106. struct hal_rxdma_desc;
  107. typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
  108. /**
  109. * hal_buff_addrinfo - opaque handle for DP buffer address info
  110. */
  111. struct hal_buff_addrinfo;
  112. typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
  113. /**
  114. * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info
  115. */
  116. struct hal_rx_mon_desc_info;
  117. typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
  118. struct hal_buf_info;
  119. typedef struct hal_buf_info *hal_buf_info_t;
  120. struct rx_msdu_desc_info;
  121. typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
  122. /* TBD: This should be movded to shared HW header file */
  123. enum hal_srng_ring_id {
  124. /* UMAC rings */
  125. HAL_SRNG_REO2SW0 = 0,
  126. HAL_SRNG_REO2SW1 = 1,
  127. HAL_SRNG_REO2SW2 = 2,
  128. HAL_SRNG_REO2SW3 = 3,
  129. HAL_SRNG_REO2SW4 = 4,
  130. HAL_SRNG_REO2SW5 = 5,
  131. HAL_SRNG_REO2SW6 = 6,
  132. HAL_SRNG_REO2SW7 = 7,
  133. HAL_SRNG_REO2SW8 = 8,
  134. HAL_SRNG_REO2TCL = 9,
  135. HAL_SRNG_SW2REO = 10,
  136. HAL_SRNG_SW2REO1 = 11,
  137. HAL_SRNG_REO_CMD = 12,
  138. HAL_SRNG_REO_STATUS = 13,
  139. /* 14-15 unused */
  140. HAL_SRNG_SW2TCL1 = 16,
  141. HAL_SRNG_SW2TCL2 = 17,
  142. HAL_SRNG_SW2TCL3 = 18,
  143. HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */
  144. HAL_SRNG_SW2TCL5 = 20,
  145. /* 20-23 unused */
  146. HAL_SRNG_SW2TCL_CMD = 24,
  147. HAL_SRNG_TCL_STATUS = 25,
  148. /* 26-31 unused */
  149. HAL_SRNG_CE_0_SRC = 32,
  150. HAL_SRNG_CE_1_SRC = 33,
  151. HAL_SRNG_CE_2_SRC = 34,
  152. HAL_SRNG_CE_3_SRC = 35,
  153. HAL_SRNG_CE_4_SRC = 36,
  154. HAL_SRNG_CE_5_SRC = 37,
  155. HAL_SRNG_CE_6_SRC = 38,
  156. HAL_SRNG_CE_7_SRC = 39,
  157. HAL_SRNG_CE_8_SRC = 40,
  158. HAL_SRNG_CE_9_SRC = 41,
  159. HAL_SRNG_CE_10_SRC = 42,
  160. HAL_SRNG_CE_11_SRC = 43,
  161. /* 44-55 unused */
  162. HAL_SRNG_CE_0_DST = 56,
  163. HAL_SRNG_CE_1_DST = 57,
  164. HAL_SRNG_CE_2_DST = 58,
  165. HAL_SRNG_CE_3_DST = 59,
  166. HAL_SRNG_CE_4_DST = 60,
  167. HAL_SRNG_CE_5_DST = 61,
  168. HAL_SRNG_CE_6_DST = 62,
  169. HAL_SRNG_CE_7_DST = 63,
  170. HAL_SRNG_CE_8_DST = 64,
  171. HAL_SRNG_CE_9_DST = 65,
  172. HAL_SRNG_CE_10_DST = 66,
  173. HAL_SRNG_CE_11_DST = 67,
  174. /* 68-79 unused */
  175. HAL_SRNG_CE_0_DST_STATUS = 80,
  176. HAL_SRNG_CE_1_DST_STATUS = 81,
  177. HAL_SRNG_CE_2_DST_STATUS = 82,
  178. HAL_SRNG_CE_3_DST_STATUS = 83,
  179. HAL_SRNG_CE_4_DST_STATUS = 84,
  180. HAL_SRNG_CE_5_DST_STATUS = 85,
  181. HAL_SRNG_CE_6_DST_STATUS = 86,
  182. HAL_SRNG_CE_7_DST_STATUS = 87,
  183. HAL_SRNG_CE_8_DST_STATUS = 88,
  184. HAL_SRNG_CE_9_DST_STATUS = 89,
  185. HAL_SRNG_CE_10_DST_STATUS = 90,
  186. HAL_SRNG_CE_11_DST_STATUS = 91,
  187. /* 92-103 unused */
  188. HAL_SRNG_WBM_IDLE_LINK = 104,
  189. HAL_SRNG_WBM_SW_RELEASE = 105,
  190. HAL_SRNG_WBM2SW0_RELEASE = 106,
  191. HAL_SRNG_WBM2SW1_RELEASE = 107,
  192. HAL_SRNG_WBM2SW2_RELEASE = 108,
  193. HAL_SRNG_WBM2SW3_RELEASE = 109,
  194. HAL_SRNG_WBM2SW4_RELEASE = 110,
  195. HAL_SRNG_WBM2SW5_RELEASE = 111,
  196. HAL_SRNG_WBM2SW6_RELEASE = 112,
  197. /* 113-127 unused */
  198. HAL_SRNG_UMAC_ID_END = 127,
  199. /* LMAC rings - The following set will be replicated for each LMAC */
  200. HAL_SRNG_LMAC1_ID_START = 128,
  201. HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
  202. #ifdef IPA_OFFLOAD
  203. HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1),
  204. HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2),
  205. HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1),
  206. #else
  207. HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1),
  208. #endif
  209. HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1),
  210. HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1),
  211. HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF =
  212. (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1),
  213. HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1),
  214. HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1),
  215. HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1),
  216. #ifdef WLAN_FEATURE_CIF_CFR
  217. HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
  218. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1),
  219. #else
  220. HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
  221. #endif
  222. /* -142 unused */
  223. HAL_SRNG_LMAC1_ID_END = 143
  224. };
  225. /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
  226. enum hal_ring_type {
  227. REO_DST = 0,
  228. REO_EXCEPTION = 1,
  229. REO_REINJECT = 2,
  230. REO_CMD = 3,
  231. REO_STATUS = 4,
  232. TCL_DATA = 5,
  233. TCL_CMD_CREDIT = 6,
  234. TCL_STATUS = 7,
  235. CE_SRC = 8,
  236. CE_DST = 9,
  237. CE_DST_STATUS = 10,
  238. WBM_IDLE_LINK = 11,
  239. SW2WBM_RELEASE = 12,
  240. WBM2SW_RELEASE = 13,
  241. RXDMA_BUF = 14,
  242. RXDMA_DST = 15,
  243. RXDMA_MONITOR_BUF = 16,
  244. RXDMA_MONITOR_STATUS = 17,
  245. RXDMA_MONITOR_DST = 18,
  246. RXDMA_MONITOR_DESC = 19,
  247. DIR_BUF_RX_DMA_SRC = 20,
  248. #ifdef WLAN_FEATURE_CIF_CFR
  249. WIFI_POS_SRC,
  250. #endif
  251. MAX_RING_TYPES
  252. };
  253. enum SRNG_REGISTERS {
  254. DST_HP = 0,
  255. DST_TP,
  256. DST_ID,
  257. DST_MISC,
  258. DST_HP_ADDR_LSB,
  259. DST_HP_ADDR_MSB,
  260. DST_MSI1_BASE_LSB,
  261. DST_MSI1_BASE_MSB,
  262. DST_MSI1_DATA,
  263. #ifdef CONFIG_BERYLLIUM
  264. DST_MSI2_BASE_LSB,
  265. DST_MSI2_BASE_MSB,
  266. DST_MSI2_DATA,
  267. #endif
  268. DST_BASE_LSB,
  269. DST_BASE_MSB,
  270. DST_PRODUCER_INT_SETUP,
  271. #ifdef CONFIG_BERYLLIUM
  272. DST_PRODUCER_INT2_SETUP,
  273. #endif
  274. SRC_HP,
  275. SRC_TP,
  276. SRC_ID,
  277. SRC_MISC,
  278. SRC_TP_ADDR_LSB,
  279. SRC_TP_ADDR_MSB,
  280. SRC_MSI1_BASE_LSB,
  281. SRC_MSI1_BASE_MSB,
  282. SRC_MSI1_DATA,
  283. SRC_BASE_LSB,
  284. SRC_BASE_MSB,
  285. SRC_CONSUMER_INT_SETUP_IX0,
  286. SRC_CONSUMER_INT_SETUP_IX1,
  287. SRNG_REGISTER_MAX,
  288. };
  289. #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
  290. #define HAL_MAX_LMACS 3
  291. #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
  292. #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
  293. #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS)
  294. enum hal_srng_dir {
  295. HAL_SRNG_SRC_RING,
  296. HAL_SRNG_DST_RING
  297. };
  298. /**
  299. * enum hal_reo_remap_reg - REO remap registers
  300. * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0
  301. * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1
  302. * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2
  303. * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3
  304. */
  305. enum hal_reo_remap_reg {
  306. HAL_REO_REMAP_REG_IX0,
  307. HAL_REO_REMAP_REG_IX1,
  308. HAL_REO_REMAP_REG_IX2,
  309. HAL_REO_REMAP_REG_IX3
  310. };
  311. /* Lock wrappers for SRNG */
  312. #define hal_srng_lock_t qdf_spinlock_t
  313. #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
  314. #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock)
  315. #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock)
  316. #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock)
  317. #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
  318. struct hal_soc;
  319. /**
  320. * dp_hal_ring - opaque handle for DP HAL SRNG
  321. */
  322. struct hal_ring_handle;
  323. typedef struct hal_ring_handle *hal_ring_handle_t;
  324. #define MAX_SRNG_REG_GROUPS 2
  325. /* Hal Srng bit mask
  326. * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down
  327. */
  328. #define HAL_SRNG_FLUSH_EVENT BIT(0)
  329. #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
  330. defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
  331. /**
  332. * struct hal_reg_write_q_elem - delayed register write queue element
  333. * @srng: hal_srng queued for a delayed write
  334. * @addr: iomem address of the register
  335. * @enqueue_val: register value at the time of delayed write enqueue
  336. * @dequeue_val: register value at the time of delayed write dequeue
  337. * @valid: whether this entry is valid or not
  338. * @enqueue_time: enqueue time (qdf_log_timestamp)
  339. * @work_scheduled_time: work scheduled time (qdf_log_timestamp)
  340. * @dequeue_time: dequeue time (qdf_log_timestamp)
  341. */
  342. struct hal_reg_write_q_elem {
  343. struct hal_srng *srng;
  344. void __iomem *addr;
  345. uint32_t enqueue_val;
  346. uint32_t dequeue_val;
  347. uint8_t valid;
  348. qdf_time_t enqueue_time;
  349. qdf_time_t work_scheduled_time;
  350. qdf_time_t dequeue_time;
  351. };
  352. /**
  353. * struct hal_reg_write_srng_stats - srng stats to keep track of register writes
  354. * @enqueues: writes enqueued to delayed work
  355. * @dequeues: writes dequeued from delayed work (not written yet)
  356. * @coalesces: writes not enqueued since srng is already queued up
  357. * @direct: writes not enqueued and written to register directly
  358. * @dequeue_delay: dequeue operation be delayed
  359. */
  360. struct hal_reg_write_srng_stats {
  361. uint32_t enqueues;
  362. uint32_t dequeues;
  363. uint32_t coalesces;
  364. uint32_t direct;
  365. uint32_t dequeue_delay;
  366. };
  367. /**
  368. * enum hal_reg_sched_delay - ENUM for write sched delay histogram
  369. * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us
  370. * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us
  371. * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us
  372. * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us
  373. * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array)
  374. */
  375. enum hal_reg_sched_delay {
  376. REG_WRITE_SCHED_DELAY_SUB_100us,
  377. REG_WRITE_SCHED_DELAY_SUB_1000us,
  378. REG_WRITE_SCHED_DELAY_SUB_5000us,
  379. REG_WRITE_SCHED_DELAY_GT_5000us,
  380. REG_WRITE_SCHED_DELAY_HIST_MAX,
  381. };
  382. /**
  383. * struct hal_reg_write_soc_stats - soc stats to keep track of register writes
  384. * @enqueues: writes enqueued to delayed work
  385. * @dequeues: writes dequeued from delayed work (not written yet)
  386. * @coalesces: writes not enqueued since srng is already queued up
  387. * @direct: writes not enqueud and writted to register directly
  388. * @prevent_l1_fails: prevent l1 API failed
  389. * @q_depth: current queue depth in delayed register write queue
  390. * @max_q_depth: maximum queue for delayed register write queue
  391. * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram
  392. * @dequeue_delay: dequeue operation be delayed
  393. */
  394. struct hal_reg_write_soc_stats {
  395. qdf_atomic_t enqueues;
  396. uint32_t dequeues;
  397. qdf_atomic_t coalesces;
  398. qdf_atomic_t direct;
  399. uint32_t prevent_l1_fails;
  400. qdf_atomic_t q_depth;
  401. uint32_t max_q_depth;
  402. uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
  403. uint32_t dequeue_delay;
  404. };
  405. #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
  406. struct hal_reg_write_tcl_stats {
  407. uint32_t wq_delayed;
  408. uint32_t wq_direct;
  409. uint32_t timer_enq;
  410. uint32_t timer_direct;
  411. uint32_t enq_timer_set;
  412. uint32_t direct_timer_set;
  413. uint32_t timer_reset;
  414. qdf_time_t enq_time;
  415. qdf_time_t deq_time;
  416. uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
  417. };
  418. #endif
  419. #endif
  420. struct hal_offload_info {
  421. uint8_t lro_eligible;
  422. uint8_t tcp_proto;
  423. uint8_t tcp_pure_ack;
  424. uint8_t ipv6_proto;
  425. uint8_t tcp_offset;
  426. uint16_t tcp_csum;
  427. uint16_t tcp_win;
  428. uint32_t tcp_seq_num;
  429. uint32_t tcp_ack_num;
  430. uint32_t flow_id;
  431. };
  432. /* Common SRNG ring structure for source and destination rings */
  433. struct hal_srng {
  434. /* Unique SRNG ring ID */
  435. uint8_t ring_id;
  436. /* Ring initialization done */
  437. uint8_t initialized;
  438. /* Interrupt/MSI value assigned to this ring */
  439. int irq;
  440. /* Physical base address of the ring */
  441. qdf_dma_addr_t ring_base_paddr;
  442. /* Virtual base address of the ring */
  443. uint32_t *ring_base_vaddr;
  444. /* Number of entries in ring */
  445. uint32_t num_entries;
  446. /* Ring size */
  447. uint32_t ring_size;
  448. /* Ring size mask */
  449. uint32_t ring_size_mask;
  450. /* Size of ring entry */
  451. uint32_t entry_size;
  452. /* Interrupt timer threshold – in micro seconds */
  453. uint32_t intr_timer_thres_us;
  454. /* Interrupt batch counter threshold – in number of ring entries */
  455. uint32_t intr_batch_cntr_thres_entries;
  456. /* Applicable only for CE dest ring */
  457. uint32_t prefetch_timer;
  458. /* MSI Address */
  459. qdf_dma_addr_t msi_addr;
  460. /* MSI data */
  461. uint32_t msi_data;
  462. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  463. /* MSI2 Address */
  464. qdf_dma_addr_t msi2_addr;
  465. /* MSI2 data */
  466. uint32_t msi2_data;
  467. #endif
  468. /* Misc flags */
  469. uint32_t flags;
  470. /* Lock for serializing ring index updates */
  471. hal_srng_lock_t lock;
  472. /* Start offset of SRNG register groups for this ring
  473. * TBD: See if this is required - register address can be derived
  474. * from ring ID
  475. */
  476. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  477. /* Ring type/name */
  478. enum hal_ring_type ring_type;
  479. /* Source or Destination ring */
  480. enum hal_srng_dir ring_dir;
  481. union {
  482. struct {
  483. /* SW tail pointer */
  484. uint32_t tp;
  485. /* Shadow head pointer location to be updated by HW */
  486. uint32_t *hp_addr;
  487. /* Cached head pointer */
  488. uint32_t cached_hp;
  489. /* Tail pointer location to be updated by SW – This
  490. * will be a register address and need not be
  491. * accessed through SW structure */
  492. uint32_t *tp_addr;
  493. /* Current SW loop cnt */
  494. uint32_t loop_cnt;
  495. /* max transfer size */
  496. uint16_t max_buffer_length;
  497. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  498. /* near full IRQ supported */
  499. uint16_t nf_irq_support;
  500. /* High threshold for Near full IRQ */
  501. uint16_t high_thresh;
  502. #endif
  503. } dst_ring;
  504. struct {
  505. /* SW head pointer */
  506. uint32_t hp;
  507. /* SW reap head pointer */
  508. uint32_t reap_hp;
  509. /* Shadow tail pointer location to be updated by HW */
  510. uint32_t *tp_addr;
  511. /* Cached tail pointer */
  512. uint32_t cached_tp;
  513. /* Head pointer location to be updated by SW – This
  514. * will be a register address and need not be accessed
  515. * through SW structure */
  516. uint32_t *hp_addr;
  517. /* Low threshold – in number of ring entries */
  518. uint32_t low_threshold;
  519. } src_ring;
  520. } u;
  521. struct hal_soc *hal_soc;
  522. /* Number of times hp/tp updated in runtime resume */
  523. uint32_t flush_count;
  524. /* hal srng event flag*/
  525. unsigned long srng_event;
  526. /* last flushed time stamp */
  527. uint64_t last_flush_ts;
  528. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  529. /* last ring desc entry cleared */
  530. uint32_t last_desc_cleared;
  531. #endif
  532. #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
  533. defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
  534. /* Previous hp/tp (based on ring dir) value written to the reg */
  535. uint32_t last_reg_wr_val;
  536. /* flag to indicate whether srng is already queued for delayed write */
  537. uint8_t reg_write_in_progress;
  538. /* last dequeue elem time stamp */
  539. qdf_time_t last_dequeue_time;
  540. /* srng specific delayed write stats */
  541. struct hal_reg_write_srng_stats wstats;
  542. #endif
  543. };
  544. /* HW SRNG configuration table */
  545. struct hal_hw_srng_config {
  546. int start_ring_id;
  547. uint16_t max_rings;
  548. uint16_t entry_size;
  549. uint32_t reg_start[MAX_SRNG_REG_GROUPS];
  550. uint16_t reg_size[MAX_SRNG_REG_GROUPS];
  551. uint8_t lmac_ring;
  552. enum hal_srng_dir ring_dir;
  553. uint32_t max_size;
  554. bool nf_irq_support;
  555. };
  556. #define MAX_SHADOW_REGISTERS 40
  557. #define MAX_GENERIC_SHADOW_REG 5
  558. /**
  559. * struct shadow_reg_config - Hal soc structure that contains
  560. * the list of generic shadow registers
  561. * @target_register: target reg offset
  562. * @shadow_config_index: shadow config index in shadow config
  563. * list sent to FW
  564. * @va: virtual addr of shadow reg
  565. *
  566. * This structure holds the generic registers that are mapped to
  567. * the shadow region and holds the mapping of the target
  568. * register offset to shadow config index provided to FW during
  569. * init
  570. */
  571. struct shadow_reg_config {
  572. uint32_t target_register;
  573. int shadow_config_index;
  574. uint64_t va;
  575. };
  576. /* REO parameters to be passed to hal_reo_setup */
  577. struct hal_reo_params {
  578. /** rx hash steering enabled or disabled */
  579. bool rx_hash_enabled;
  580. /** reo remap 1 register */
  581. uint32_t remap1;
  582. /** reo remap 2 register */
  583. uint32_t remap2;
  584. /** fragment destination ring */
  585. uint8_t frag_dst_ring;
  586. /* Destination for alternate */
  587. uint8_t alt_dst_ind_0;
  588. /** padding */
  589. uint8_t padding[2];
  590. };
  591. /**
  592. * enum hal_reo_cmd_type: Enum for REO command type
  593. * @CMD_GET_QUEUE_STATS: Get REO queue status/stats
  594. * @CMD_FLUSH_QUEUE: Flush all frames in REO queue
  595. * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
  596. * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked
  597. * earlier with a ‘REO_FLUSH_CACHE’ command
  598. * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
  599. * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
  600. */
  601. enum hal_reo_cmd_type {
  602. CMD_GET_QUEUE_STATS = 0,
  603. CMD_FLUSH_QUEUE = 1,
  604. CMD_FLUSH_CACHE = 2,
  605. CMD_UNBLOCK_CACHE = 3,
  606. CMD_FLUSH_TIMEOUT_LIST = 4,
  607. CMD_UPDATE_RX_REO_QUEUE = 5
  608. };
  609. struct hal_rx_pkt_capture_flags {
  610. uint8_t encrypt_type;
  611. uint8_t fragment_flag;
  612. uint8_t fcs_err;
  613. uint32_t chan_freq;
  614. uint32_t rssi_comb;
  615. uint64_t tsft;
  616. };
  617. struct hal_hw_txrx_ops {
  618. /* init and setup */
  619. void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
  620. struct hal_srng *srng);
  621. void (*hal_srng_src_hw_init)(struct hal_soc *hal,
  622. struct hal_srng *srng);
  623. void (*hal_get_hw_hptp)(struct hal_soc *hal,
  624. hal_ring_handle_t hal_ring_hdl,
  625. uint32_t *headp, uint32_t *tailp,
  626. uint8_t ring_type);
  627. void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams);
  628. void (*hal_setup_link_idle_list)(
  629. struct hal_soc *hal_soc,
  630. qdf_dma_addr_t scatter_bufs_base_paddr[],
  631. void *scatter_bufs_base_vaddr[],
  632. uint32_t num_scatter_bufs,
  633. uint32_t scatter_buf_size,
  634. uint32_t last_buf_end_offset,
  635. uint32_t num_entries);
  636. qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
  637. qdf_iomem_t addr);
  638. void (*hal_reo_set_err_dst_remap)(void *hal_soc);
  639. uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc);
  640. void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid,
  641. uint32_t ba_window_size,
  642. uint32_t start_seq, void *hw_qdesc_vaddr,
  643. qdf_dma_addr_t hw_qdesc_paddr,
  644. int pn_type);
  645. uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg,
  646. uint8_t *ix0_map);
  647. /* tx */
  648. void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
  649. void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map,
  650. uint8_t id);
  651. void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid,
  652. uint8_t id,
  653. uint8_t dscp);
  654. void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
  655. void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
  656. uint8_t pool_id, uint32_t desc_id,
  657. uint8_t type);
  658. void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type);
  659. void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index);
  660. void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index);
  661. void (*hal_tx_comp_get_status)(void *desc, void *ts,
  662. struct hal_soc *hal);
  663. uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc);
  664. uint8_t (*hal_get_wbm_internal_error)(void *hal_desc);
  665. void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
  666. void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl,
  667. hal_ring_handle_t hal_ring_hdl);
  668. uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc);
  669. /* rx */
  670. uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
  671. void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr,
  672. struct mon_rx_status *rs);
  673. uint8_t (*hal_rx_get_tlv)(void *rx_tlv);
  674. void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr,
  675. void *ppdu_info_handle);
  676. void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level);
  677. void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end,
  678. uint8_t dbg_level);
  679. uint32_t (*hal_get_link_desc_size)(void);
  680. uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
  681. uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
  682. uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
  683. void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
  684. void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
  685. void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b,
  686. void *h);
  687. uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
  688. void *ppdu_info,
  689. hal_soc_handle_t hal_soc_hdl,
  690. qdf_nbuf_t nbuf);
  691. void (*hal_rx_wbm_err_info_get)(void *wbm_desc,
  692. void *wbm_er_info);
  693. void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart,
  694. uint8_t dbg_level);
  695. void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map);
  696. void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp,
  697. uint8_t id);
  698. void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
  699. /* rx */
  700. uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
  701. uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
  702. uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
  703. uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
  704. uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
  705. uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf);
  706. uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf);
  707. void (*hal_rx_print_pn)(uint8_t *buf);
  708. uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf);
  709. uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf);
  710. uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf);
  711. bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf);
  712. uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf);
  713. uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf);
  714. uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf);
  715. uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf);
  716. QDF_STATUS
  717. (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr);
  718. QDF_STATUS
  719. (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr);
  720. QDF_STATUS
  721. (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr);
  722. QDF_STATUS
  723. (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
  724. uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
  725. bool (*hal_rx_is_unicast)(uint8_t *buf);
  726. uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf);
  727. uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr,
  728. void *rxdma_dst_ring_desc);
  729. uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
  730. uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
  731. void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr);
  732. void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0);
  733. void * (*hal_ent_mpdu_desc_info)(void *hw_addr);
  734. void * (*hal_dst_mpdu_desc_info)(void *hw_addr);
  735. uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf);
  736. uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf);
  737. uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf);
  738. uint8_t (*hal_rx_get_filter_category)(uint8_t *buf);
  739. uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf);
  740. void (*hal_reo_config)(struct hal_soc *soc,
  741. uint32_t reg_val,
  742. struct hal_reo_params *reo_params);
  743. uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf);
  744. bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf);
  745. bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf);
  746. uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf);
  747. uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf);
  748. void
  749. (*hal_rx_msdu_get_flow_params)(
  750. uint8_t *buf,
  751. bool *flow_invalid,
  752. bool *flow_timeout,
  753. uint32_t *flow_index);
  754. uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf);
  755. uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf);
  756. void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle);
  757. void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle);
  758. void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf,
  759. void *msdu_pkt_metadata);
  760. uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf);
  761. uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf);
  762. bool (*hal_rx_get_udp_proto)(uint8_t *buf);
  763. bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf);
  764. uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
  765. bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
  766. uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
  767. void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc,
  768. hal_rx_mon_desc_info_t mon_desc_info);
  769. uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc);
  770. uint32_t (*hal_rx_msdu_end_offset_get)(void);
  771. uint32_t (*hal_rx_attn_offset_get)(void);
  772. uint32_t (*hal_rx_msdu_start_offset_get)(void);
  773. uint32_t (*hal_rx_mpdu_start_offset_get)(void);
  774. uint32_t (*hal_rx_mpdu_end_offset_get)(void);
  775. uint32_t (*hal_rx_pkt_tlv_offset_get)(void);
  776. void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst,
  777. uint32_t table_offset,
  778. uint8_t *rx_flow);
  779. void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring,
  780. uint32_t num_rings,
  781. uint32_t *remap1,
  782. uint32_t *remap2);
  783. uint32_t (*hal_rx_flow_setup_cmem_fse)(
  784. struct hal_soc *soc, uint32_t cmem_ba,
  785. uint32_t table_offset, uint8_t *rx_flow);
  786. uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc,
  787. uint32_t fse_offset);
  788. void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc,
  789. uint32_t fse_offset,
  790. uint32_t *fse, qdf_size_t len);
  791. void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf,
  792. uint32_t *reo_destination_indication);
  793. uint8_t (*hal_tx_get_num_tcl_banks)(void);
  794. uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid);
  795. void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie,
  796. qdf_dma_addr_t link_desc_paddr);
  797. void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl,
  798. hal_ring_handle_t hal_ring_hdl);
  799. void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr);
  800. void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
  801. uint8_t ac, uint32_t *value);
  802. void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
  803. uint8_t ac, uint32_t value);
  804. uint32_t (*hal_get_reo_reg_base_offset)(void);
  805. void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size,
  806. uint16_t *rx_mon_pkt_tlv_size);
  807. uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf);
  808. uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr);
  809. void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl,
  810. uint8_t *buf, uint8_t dbg_level);
  811. int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv,
  812. struct hal_offload_info *offload_info);
  813. uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf);
  814. uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf);
  815. uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf);
  816. uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf);
  817. int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params);
  818. int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset,
  819. uint32_t *l4_hdr_offset);
  820. uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf);
  821. uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf);
  822. void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num);
  823. void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn);
  824. uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf);
  825. uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl,
  826. void *msdu_link_desc);
  827. void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
  828. void *msdu_desc_info, uint32_t dst_ind,
  829. uint32_t nbuf_len);
  830. void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl,
  831. void *mpdu_desc_info, uint32_t seq_no);
  832. uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf);
  833. uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf);
  834. uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf);
  835. uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf);
  836. uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf);
  837. uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf);
  838. uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf);
  839. uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf);
  840. uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc);
  841. uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc);
  842. void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl,
  843. void *src_srng_desc,
  844. hal_buff_addrinfo_t buf_addr_info,
  845. uint8_t bm_action);
  846. void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl,
  847. hal_buf_info_t buf_info_hdl);
  848. void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc,
  849. struct hal_buf_info *buf_info);
  850. void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry,
  851. qdf_dma_addr_t paddr,
  852. uint32_t cookie, uint8_t manager);
  853. uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl);
  854. uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc);
  855. void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr,
  856. uint32_t *ip_csum_err,
  857. uint32_t *tcp_udp_csum_err);
  858. void (*hal_rx_mpdu_desc_info_get)(void *desc_addr,
  859. void *mpdu_desc_info_hdl);
  860. uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc);
  861. uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc);
  862. bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf);
  863. uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr);
  864. uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr);
  865. void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr,
  866. struct hal_rx_pkt_capture_flags *flags);
  867. uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr);
  868. uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr);
  869. void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf,
  870. uint8_t *priv_data,
  871. uint32_t len);
  872. void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf,
  873. uint8_t *priv_data,
  874. uint32_t len);
  875. void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len);
  876. void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf,
  877. void *mpdu_desc_info_hdl);
  878. /* REO CMD and STATUS */
  879. int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl,
  880. hal_ring_handle_t hal_ring_hdl,
  881. enum hal_reo_cmd_type cmd,
  882. void *params);
  883. QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl,
  884. hal_ring_desc_t reo_desc,
  885. void *st_handle,
  886. uint32_t tlv, int *num_ref);
  887. uint8_t (*hal_get_tlv_hdr_size)(void);
  888. };
  889. /**
  890. * struct hal_soc_stats - Hal layer stats
  891. * @reg_write_fail: number of failed register writes
  892. * @wstats: delayed register write stats
  893. * @shadow_reg_write_fail: shadow reg write failure stats
  894. * @shadow_reg_write_succ: shadow reg write success stats
  895. *
  896. * This structure holds all the statistics at HAL layer.
  897. */
  898. struct hal_soc_stats {
  899. uint32_t reg_write_fail;
  900. #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
  901. defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
  902. struct hal_reg_write_soc_stats wstats;
  903. #endif
  904. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  905. uint32_t shadow_reg_write_fail;
  906. uint32_t shadow_reg_write_succ;
  907. #endif
  908. };
  909. #ifdef ENABLE_HAL_REG_WR_HISTORY
  910. /* The history size should always be a power of 2 */
  911. #define HAL_REG_WRITE_HIST_SIZE 8
  912. /**
  913. * struct hal_reg_write_fail_entry - Record of
  914. * register write which failed.
  915. * @timestamp: timestamp of reg write failure
  916. * @reg_offset: offset of register where the write failed
  917. * @write_val: the value which was to be written
  918. * @read_val: the value read back from the register after write
  919. */
  920. struct hal_reg_write_fail_entry {
  921. uint64_t timestamp;
  922. uint32_t reg_offset;
  923. uint32_t write_val;
  924. uint32_t read_val;
  925. };
  926. /**
  927. * struct hal_reg_write_fail_history - Hal layer history
  928. * of all the register write failures.
  929. * @index: index to add the new record
  930. * @record: array of all the records in history
  931. *
  932. * This structure holds the history of register write
  933. * failures at HAL layer.
  934. */
  935. struct hal_reg_write_fail_history {
  936. qdf_atomic_t index;
  937. struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE];
  938. };
  939. #endif
  940. /**
  941. * struct hal_soc - HAL context to be used to access SRNG APIs
  942. * (currently used by data path and
  943. * transport (CE) modules)
  944. * @list_shadow_reg_config: array of generic regs mapped to
  945. * shadow regs
  946. * @num_generic_shadow_regs_configured: number of generic regs
  947. * mapped to shadow regs
  948. */
  949. struct hal_soc {
  950. /* HIF handle to access HW registers */
  951. struct hif_opaque_softc *hif_handle;
  952. /* QDF device handle */
  953. qdf_device_t qdf_dev;
  954. /* Device base address */
  955. void *dev_base_addr;
  956. /* Device base address for ce - qca5018 target */
  957. void *dev_base_addr_ce;
  958. /* HAL internal state for all SRNG rings.
  959. * TODO: See if this is required
  960. */
  961. struct hal_srng srng_list[HAL_SRNG_ID_MAX];
  962. /* Remote pointer memory for HW/FW updates */
  963. uint32_t *shadow_rdptr_mem_vaddr;
  964. qdf_dma_addr_t shadow_rdptr_mem_paddr;
  965. /* Shared memory for ring pointer updates from host to FW */
  966. uint32_t *shadow_wrptr_mem_vaddr;
  967. qdf_dma_addr_t shadow_wrptr_mem_paddr;
  968. /* REO blocking resource index */
  969. uint8_t reo_res_bitmap;
  970. uint8_t index;
  971. uint32_t target_type;
  972. /* shadow register configuration */
  973. struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS];
  974. int num_shadow_registers_configured;
  975. bool use_register_windowing;
  976. uint32_t register_window;
  977. qdf_spinlock_t register_access_lock;
  978. /* Static window map configuration for multiple window write*/
  979. bool static_window_map;
  980. /* srng table */
  981. struct hal_hw_srng_config *hw_srng_table;
  982. int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX];
  983. struct hal_hw_txrx_ops *ops;
  984. /* Indicate srngs initialization */
  985. bool init_phase;
  986. /* Hal level stats */
  987. struct hal_soc_stats stats;
  988. #ifdef ENABLE_HAL_REG_WR_HISTORY
  989. struct hal_reg_write_fail_history *reg_wr_fail_hist;
  990. #endif
  991. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  992. /* queue(array) to hold register writes */
  993. struct hal_reg_write_q_elem *reg_write_queue;
  994. /* delayed work to be queued into workqueue */
  995. qdf_work_t reg_write_work;
  996. /* workqueue for delayed register writes */
  997. qdf_workqueue_t *reg_write_wq;
  998. /* write index used by caller to enqueue delayed work */
  999. qdf_atomic_t write_idx;
  1000. /* read index used by worker thread to dequeue/write registers */
  1001. uint32_t read_idx;
  1002. #endif /*FEATURE_HAL_DELAYED_REG_WRITE */
  1003. #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
  1004. /* delayed work for TCL reg write to be queued into workqueue */
  1005. qdf_work_t tcl_reg_write_work;
  1006. /* workqueue for TCL delayed register writes */
  1007. qdf_workqueue_t *tcl_reg_write_wq;
  1008. /* flag denotes whether TCL delayed write work is active */
  1009. qdf_atomic_t tcl_work_active;
  1010. /* flag indiactes TCL write happening from direct context */
  1011. bool tcl_direct;
  1012. /* timer to handle the pending TCL reg writes */
  1013. qdf_timer_t tcl_reg_write_timer;
  1014. /* stats related to TCL reg write */
  1015. struct hal_reg_write_tcl_stats tcl_stats;
  1016. #endif /* FEATURE_HAL_DELAYED_REG_WRITE_V2 */
  1017. qdf_atomic_t active_work_cnt;
  1018. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  1019. struct shadow_reg_config
  1020. list_shadow_reg_config[MAX_GENERIC_SHADOW_REG];
  1021. int num_generic_shadow_regs_configured;
  1022. #endif
  1023. };
  1024. #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
  1025. defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
  1026. /**
  1027. * hal_delayed_reg_write() - delayed regiter write
  1028. * @hal_soc: HAL soc handle
  1029. * @srng: hal srng
  1030. * @addr: iomem address
  1031. * @value: value to be written
  1032. *
  1033. * Return: none
  1034. */
  1035. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  1036. struct hal_srng *srng,
  1037. void __iomem *addr,
  1038. uint32_t value);
  1039. #endif
  1040. void hal_qca6750_attach(struct hal_soc *hal_soc);
  1041. void hal_qca6490_attach(struct hal_soc *hal_soc);
  1042. void hal_qca6390_attach(struct hal_soc *hal_soc);
  1043. void hal_qca6290_attach(struct hal_soc *hal_soc);
  1044. void hal_qca8074_attach(struct hal_soc *hal_soc);
  1045. void hal_wcn7850_attach(struct hal_soc *hal_soc);
  1046. /*
  1047. * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
  1048. * dp_hal_soc handle type
  1049. * @hal_soc - hal_soc type
  1050. *
  1051. * Return: hal_soc_handle_t type
  1052. */
  1053. static inline
  1054. hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc)
  1055. {
  1056. return (hal_soc_handle_t)hal_soc;
  1057. }
  1058. /*
  1059. * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque
  1060. * dp_hal_ring handle type
  1061. * @hal_srng - hal_srng type
  1062. *
  1063. * Return: hal_ring_handle_t type
  1064. */
  1065. static inline
  1066. hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng)
  1067. {
  1068. return (hal_ring_handle_t)hal_srng;
  1069. }
  1070. /*
  1071. * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle
  1072. * @hal_ring - hal_ring_handle_t type
  1073. *
  1074. * Return: hal_srng pointer type
  1075. */
  1076. static inline
  1077. struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
  1078. {
  1079. return (struct hal_srng *)hal_ring;
  1080. }
  1081. #endif /* _HAL_INTERNAL_H_ */