dp_li_rx.c 29 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_li_rx.h"
  24. #include "dp_peer.h"
  25. #include "hal_rx.h"
  26. #include "hal_li_rx.h"
  27. #include "hal_api.h"
  28. #include "hal_li_api.h"
  29. #include "qdf_nbuf.h"
  30. #ifdef MESH_MODE_SUPPORT
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "dp_internal.h"
  34. #include "dp_ipa.h"
  35. #ifdef WIFI_MONITOR_SUPPORT
  36. #include <dp_mon.h>
  37. #endif
  38. #ifdef FEATURE_WDS
  39. #include "dp_txrx_wds.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #include "dp_rx_buffer_pool.h"
  43. static inline
  44. bool is_sa_da_idx_valid(struct dp_soc *soc, uint8_t *rx_tlv_hdr,
  45. qdf_nbuf_t nbuf, struct hal_rx_msdu_metadata msdu_info)
  46. {
  47. if ((qdf_nbuf_is_sa_valid(nbuf) &&
  48. (msdu_info.sa_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))) ||
  49. (!qdf_nbuf_is_da_mcbc(nbuf) && qdf_nbuf_is_da_valid(nbuf) &&
  50. (msdu_info.da_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))))
  51. return false;
  52. return true;
  53. }
  54. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  55. #if defined(FEATURE_MCL_REPEATER) && defined(FEATURE_MEC)
  56. /**
  57. * dp_rx_mec_check_wrapper() - wrapper to dp_rx_mcast_echo_check
  58. * @soc: core DP main context
  59. * @peer: dp peer handler
  60. * @rx_tlv_hdr: start of the rx TLV header
  61. * @nbuf: pkt buffer
  62. *
  63. * Return: bool (true if it is a looped back pkt else false)
  64. */
  65. static inline bool dp_rx_mec_check_wrapper(struct dp_soc *soc,
  66. struct dp_peer *peer,
  67. uint8_t *rx_tlv_hdr,
  68. qdf_nbuf_t nbuf)
  69. {
  70. return dp_rx_mcast_echo_check(soc, peer, rx_tlv_hdr, nbuf);
  71. }
  72. #else
  73. static inline bool dp_rx_mec_check_wrapper(struct dp_soc *soc,
  74. struct dp_peer *peer,
  75. uint8_t *rx_tlv_hdr,
  76. qdf_nbuf_t nbuf)
  77. {
  78. return false;
  79. }
  80. #endif
  81. #endif
  82. #ifndef QCA_HOST_MODE_WIFI_DISABLE
  83. static bool
  84. dp_rx_intrabss_ucast_check_li(struct dp_soc *soc, qdf_nbuf_t nbuf,
  85. struct dp_peer *ta_peer,
  86. struct hal_rx_msdu_metadata *msdu_metadata,
  87. uint8_t *p_tx_vdev_id)
  88. {
  89. uint16_t da_peer_id;
  90. struct dp_peer *da_peer;
  91. struct dp_ast_entry *ast_entry;
  92. if (!qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf))
  93. return false;
  94. ast_entry = soc->ast_table[msdu_metadata->da_idx];
  95. if (!ast_entry)
  96. return false;
  97. if (ast_entry->type == CDP_TXRX_AST_TYPE_DA) {
  98. ast_entry->is_active = TRUE;
  99. return false;
  100. }
  101. da_peer_id = ast_entry->peer_id;
  102. /* TA peer cannot be same as peer(DA) on which AST is present
  103. * this indicates a change in topology and that AST entries
  104. * are yet to be updated.
  105. */
  106. if ((da_peer_id == ta_peer->peer_id) ||
  107. (da_peer_id == HTT_INVALID_PEER))
  108. return false;
  109. da_peer = dp_peer_get_ref_by_id(soc, da_peer_id,
  110. DP_MOD_ID_RX);
  111. if (!da_peer)
  112. return false;
  113. *p_tx_vdev_id = da_peer->vdev->vdev_id;
  114. /* If the source or destination peer in the isolation
  115. * list then dont forward instead push to bridge stack.
  116. */
  117. if (dp_get_peer_isolation(ta_peer) ||
  118. dp_get_peer_isolation(da_peer) ||
  119. (da_peer->vdev->vdev_id != ta_peer->vdev->vdev_id)) {
  120. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  121. return false;
  122. }
  123. if (da_peer->bss_peer) {
  124. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  125. return false;
  126. }
  127. dp_peer_unref_delete(da_peer, DP_MOD_ID_RX);
  128. return true;
  129. }
  130. /*
  131. * dp_rx_intrabss_fwd_li() - Implements the Intra-BSS forwarding logic
  132. *
  133. * @soc: core txrx main context
  134. * @ta_peer : source peer entry
  135. * @rx_tlv_hdr : start address of rx tlvs
  136. * @nbuf : nbuf that has to be intrabss forwarded
  137. *
  138. * Return: bool: true if it is forwarded else false
  139. */
  140. static bool
  141. dp_rx_intrabss_fwd_li(struct dp_soc *soc,
  142. struct dp_peer *ta_peer,
  143. uint8_t *rx_tlv_hdr,
  144. qdf_nbuf_t nbuf,
  145. struct hal_rx_msdu_metadata msdu_metadata)
  146. {
  147. uint8_t tx_vdev_id;
  148. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  149. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  150. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  151. tid_stats.tid_rx_stats[ring_id][tid];
  152. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  153. * source, then clone the pkt and send the cloned pkt for
  154. * intra BSS forwarding and original pkt up the network stack
  155. * Note: how do we handle multicast pkts. do we forward
  156. * all multicast pkts as is or let a higher layer module
  157. * like igmpsnoop decide whether to forward or not with
  158. * Mcast enhancement.
  159. */
  160. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer)
  161. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  162. nbuf, tid_stats);
  163. if (dp_rx_intrabss_eapol_drop_check(soc, ta_peer, rx_tlv_hdr,
  164. nbuf))
  165. return true;
  166. if (dp_rx_intrabss_ucast_check_li(soc, nbuf, ta_peer,
  167. &msdu_metadata, &tx_vdev_id))
  168. return dp_rx_intrabss_ucast_fwd(soc, ta_peer, tx_vdev_id,
  169. rx_tlv_hdr, nbuf, tid_stats);
  170. return false;
  171. }
  172. #endif
  173. /**
  174. * dp_rx_process_li() - Brain of the Rx processing functionality
  175. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  176. * @int_ctx: per interrupt context
  177. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  178. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  179. * @quota: No. of units (packets) that can be serviced in one shot.
  180. *
  181. * This function implements the core of Rx functionality. This is
  182. * expected to handle only non-error frames.
  183. *
  184. * Return: uint32_t: No. of elements processed
  185. */
  186. uint32_t dp_rx_process_li(struct dp_intr *int_ctx,
  187. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  188. uint32_t quota)
  189. {
  190. hal_ring_desc_t ring_desc;
  191. hal_ring_desc_t last_prefetched_hw_desc;
  192. hal_soc_handle_t hal_soc;
  193. struct dp_rx_desc *rx_desc = NULL;
  194. struct dp_rx_desc *last_prefetched_sw_desc = NULL;
  195. qdf_nbuf_t nbuf, next;
  196. bool near_full;
  197. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  198. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  199. uint32_t num_pending = 0;
  200. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  201. uint16_t msdu_len = 0;
  202. uint16_t peer_id;
  203. uint8_t vdev_id;
  204. struct dp_peer *peer;
  205. struct dp_vdev *vdev;
  206. uint32_t pkt_len = 0;
  207. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  208. struct hal_rx_msdu_desc_info msdu_desc_info;
  209. enum hal_reo_error_status error;
  210. uint32_t peer_mdata;
  211. uint8_t *rx_tlv_hdr;
  212. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  213. uint8_t mac_id = 0;
  214. struct dp_pdev *rx_pdev;
  215. struct dp_srng *dp_rxdma_srng;
  216. struct rx_desc_pool *rx_desc_pool;
  217. struct dp_soc *soc = int_ctx->soc;
  218. struct cdp_tid_rx_stats *tid_stats;
  219. qdf_nbuf_t nbuf_head;
  220. qdf_nbuf_t nbuf_tail;
  221. qdf_nbuf_t deliver_list_head;
  222. qdf_nbuf_t deliver_list_tail;
  223. uint32_t num_rx_bufs_reaped = 0;
  224. uint32_t intr_id;
  225. struct hif_opaque_softc *scn;
  226. int32_t tid = 0;
  227. bool is_prev_msdu_last = true;
  228. uint32_t rx_ol_pkt_cnt = 0;
  229. uint32_t num_entries = 0;
  230. struct hal_rx_msdu_metadata msdu_metadata;
  231. QDF_STATUS status;
  232. qdf_nbuf_t ebuf_head;
  233. qdf_nbuf_t ebuf_tail;
  234. uint8_t pkt_capture_offload = 0;
  235. int max_reap_limit;
  236. DP_HIST_INIT();
  237. qdf_assert_always(soc && hal_ring_hdl);
  238. hal_soc = soc->hal_soc;
  239. qdf_assert_always(hal_soc);
  240. scn = soc->hif_handle;
  241. hif_pm_runtime_mark_dp_rx_busy(scn);
  242. intr_id = int_ctx->dp_intr_id;
  243. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  244. more_data:
  245. /* reset local variables here to be re-used in the function */
  246. nbuf_head = NULL;
  247. nbuf_tail = NULL;
  248. deliver_list_head = NULL;
  249. deliver_list_tail = NULL;
  250. peer = NULL;
  251. vdev = NULL;
  252. num_rx_bufs_reaped = 0;
  253. ebuf_head = NULL;
  254. ebuf_tail = NULL;
  255. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  256. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  257. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  258. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  259. qdf_mem_zero(head, sizeof(head));
  260. qdf_mem_zero(tail, sizeof(tail));
  261. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  262. /*
  263. * Need API to convert from hal_ring pointer to
  264. * Ring Type / Ring Id combo
  265. */
  266. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  267. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  268. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  269. goto done;
  270. }
  271. if (!num_pending)
  272. num_pending = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, 0);
  273. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_pending);
  274. if (num_pending > quota)
  275. num_pending = quota;
  276. last_prefetched_hw_desc = dp_srng_dst_prefetch(hal_soc, hal_ring_hdl,
  277. num_pending);
  278. /*
  279. * start reaping the buffers from reo ring and queue
  280. * them in per vdev queue.
  281. * Process the received pkts in a different per vdev loop.
  282. */
  283. while (qdf_likely(num_pending)) {
  284. ring_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  285. if (qdf_unlikely(!ring_desc))
  286. break;
  287. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  288. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  289. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  290. soc, hal_ring_hdl, error);
  291. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  292. 1);
  293. /* Don't know how to deal with this -- assert */
  294. qdf_assert(0);
  295. }
  296. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  297. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  298. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  299. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  300. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  301. break;
  302. }
  303. rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, rx_buf_cookie);
  304. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  305. ring_desc, rx_desc);
  306. if (QDF_IS_STATUS_ERROR(status)) {
  307. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  308. qdf_assert_always(!rx_desc->unmapped);
  309. dp_ipa_reo_ctx_buf_mapping_lock(soc,
  310. reo_ring_num);
  311. dp_ipa_handle_rx_buf_smmu_mapping(
  312. soc,
  313. rx_desc->nbuf,
  314. RX_DATA_BUFFER_SIZE,
  315. false);
  316. qdf_nbuf_unmap_nbytes_single(
  317. soc->osdev,
  318. rx_desc->nbuf,
  319. QDF_DMA_FROM_DEVICE,
  320. RX_DATA_BUFFER_SIZE);
  321. rx_desc->unmapped = 1;
  322. dp_ipa_reo_ctx_buf_mapping_unlock(soc,
  323. reo_ring_num);
  324. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  325. rx_desc->pool_id);
  326. dp_rx_add_to_free_desc_list(
  327. &head[rx_desc->pool_id],
  328. &tail[rx_desc->pool_id],
  329. rx_desc);
  330. }
  331. continue;
  332. }
  333. /*
  334. * this is a unlikely scenario where the host is reaping
  335. * a descriptor which it already reaped just a while ago
  336. * but is yet to replenish it back to HW.
  337. * In this case host will dump the last 128 descriptors
  338. * including the software descriptor rx_desc and assert.
  339. */
  340. if (qdf_unlikely(!rx_desc->in_use)) {
  341. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  342. dp_info_rl("Reaping rx_desc not in use!");
  343. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  344. ring_desc, rx_desc);
  345. /* ignore duplicate RX desc and continue to process */
  346. /* Pop out the descriptor */
  347. continue;
  348. }
  349. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  350. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  351. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  352. dp_info_rl("Nbuf sanity check failure!");
  353. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  354. ring_desc, rx_desc);
  355. rx_desc->in_err_state = 1;
  356. continue;
  357. }
  358. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  359. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  360. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  361. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  362. ring_desc, rx_desc);
  363. }
  364. /* Get MPDU DESC info */
  365. hal_rx_mpdu_desc_info_get_li(ring_desc, &mpdu_desc_info);
  366. /* Get MSDU DESC info */
  367. hal_rx_msdu_desc_info_get_li(ring_desc, &msdu_desc_info);
  368. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  369. HAL_MSDU_F_MSDU_CONTINUATION)) {
  370. /* previous msdu has end bit set, so current one is
  371. * the new MPDU
  372. */
  373. if (is_prev_msdu_last) {
  374. /* For new MPDU check if we can read complete
  375. * MPDU by comparing the number of buffers
  376. * available and number of buffers needed to
  377. * reap this MPDU
  378. */
  379. if ((msdu_desc_info.msdu_len /
  380. (RX_DATA_BUFFER_SIZE -
  381. soc->rx_pkt_tlv_size) + 1) >
  382. num_pending) {
  383. DP_STATS_INC(soc,
  384. rx.msdu_scatter_wait_break,
  385. 1);
  386. dp_rx_cookie_reset_invalid_bit(
  387. ring_desc);
  388. /* As we are going to break out of the
  389. * loop because of unavailability of
  390. * descs to form complete SG, we need to
  391. * reset the TP in the REO destination
  392. * ring.
  393. */
  394. hal_srng_dst_dec_tp(hal_soc,
  395. hal_ring_hdl);
  396. break;
  397. }
  398. is_prev_msdu_last = false;
  399. }
  400. }
  401. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  402. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  403. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  404. HAL_MPDU_F_RAW_AMPDU))
  405. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  406. if (!is_prev_msdu_last &&
  407. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  408. is_prev_msdu_last = true;
  409. rx_bufs_reaped[rx_desc->pool_id]++;
  410. peer_mdata = mpdu_desc_info.peer_meta_data;
  411. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  412. dp_rx_peer_metadata_peer_id_get_li(soc, peer_mdata);
  413. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  414. DP_PEER_METADATA_VDEV_ID_GET_LI(peer_mdata);
  415. /* to indicate whether this msdu is rx offload */
  416. pkt_capture_offload =
  417. DP_PEER_METADATA_OFFLOAD_GET_LI(peer_mdata);
  418. /*
  419. * save msdu flags first, last and continuation msdu in
  420. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  421. * length to nbuf->cb. This ensures the info required for
  422. * per pkt processing is always in the same cache line.
  423. * This helps in improving throughput for smaller pkt
  424. * sizes.
  425. */
  426. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  427. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  428. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  429. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  430. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  431. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  432. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  433. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  434. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  435. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  436. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  437. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  438. qdf_nbuf_set_tid_val(rx_desc->nbuf,
  439. HAL_RX_REO_QUEUE_NUMBER_GET(ring_desc));
  440. /* set reo dest indication */
  441. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  442. rx_desc->nbuf,
  443. HAL_RX_REO_MSDU_REO_DST_IND_GET(ring_desc));
  444. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  445. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  446. /*
  447. * move unmap after scattered msdu waiting break logic
  448. * in case double skb unmap happened.
  449. */
  450. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  451. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  452. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  453. rx_desc_pool->buf_size,
  454. false);
  455. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  456. QDF_DMA_FROM_DEVICE,
  457. rx_desc_pool->buf_size);
  458. rx_desc->unmapped = 1;
  459. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  460. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  461. ebuf_tail, rx_desc);
  462. /*
  463. * if continuation bit is set then we have MSDU spread
  464. * across multiple buffers, let us not decrement quota
  465. * till we reap all buffers of that MSDU.
  466. */
  467. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf))) {
  468. quota -= 1;
  469. num_pending -= 1;
  470. }
  471. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  472. &tail[rx_desc->pool_id], rx_desc);
  473. num_rx_bufs_reaped++;
  474. dp_rx_prefetch_hw_sw_nbuf_desc(soc, hal_soc, num_pending,
  475. hal_ring_hdl,
  476. &last_prefetched_hw_desc,
  477. &last_prefetched_sw_desc);
  478. /*
  479. * only if complete msdu is received for scatter case,
  480. * then allow break.
  481. */
  482. if (is_prev_msdu_last &&
  483. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  484. max_reap_limit))
  485. break;
  486. }
  487. done:
  488. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  489. DP_STATS_INCC(soc,
  490. rx.ring_packets[qdf_get_smp_processor_id()][reo_ring_num],
  491. num_rx_bufs_reaped, num_rx_bufs_reaped);
  492. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  493. /*
  494. * continue with next mac_id if no pkts were reaped
  495. * from that pool
  496. */
  497. if (!rx_bufs_reaped[mac_id])
  498. continue;
  499. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_id];
  500. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  501. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  502. rx_desc_pool, rx_bufs_reaped[mac_id],
  503. &head[mac_id], &tail[mac_id]);
  504. }
  505. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  506. /* Peer can be NULL is case of LFR */
  507. if (qdf_likely(peer))
  508. vdev = NULL;
  509. /*
  510. * BIG loop where each nbuf is dequeued from global queue,
  511. * processed and queued back on a per vdev basis. These nbufs
  512. * are sent to stack as and when we run out of nbufs
  513. * or a new nbuf dequeued from global queue has a different
  514. * vdev when compared to previous nbuf.
  515. */
  516. nbuf = nbuf_head;
  517. while (nbuf) {
  518. next = nbuf->next;
  519. dp_rx_prefetch_nbuf_data(nbuf, next);
  520. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  521. nbuf = next;
  522. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  523. continue;
  524. }
  525. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  526. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  527. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  528. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  529. peer_id, vdev_id)) {
  530. dp_rx_deliver_to_stack(soc, vdev, peer,
  531. deliver_list_head,
  532. deliver_list_tail);
  533. deliver_list_head = NULL;
  534. deliver_list_tail = NULL;
  535. }
  536. /* Get TID from struct cb->tid_val, save to tid */
  537. if (qdf_nbuf_is_rx_chfrag_start(nbuf)) {
  538. tid = qdf_nbuf_get_tid_val(nbuf);
  539. if (tid >= CDP_MAX_DATA_TIDS) {
  540. DP_STATS_INC(soc, rx.err.rx_invalid_tid_err, 1);
  541. qdf_nbuf_free(nbuf);
  542. nbuf = next;
  543. continue;
  544. }
  545. }
  546. if (qdf_unlikely(!peer)) {
  547. peer = dp_peer_get_ref_by_id(soc, peer_id,
  548. DP_MOD_ID_RX);
  549. } else if (peer && peer->peer_id != peer_id) {
  550. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  551. peer = dp_peer_get_ref_by_id(soc, peer_id,
  552. DP_MOD_ID_RX);
  553. }
  554. if (peer) {
  555. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  556. qdf_dp_trace_set_track(nbuf, QDF_RX);
  557. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  558. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  559. QDF_NBUF_RX_PKT_DATA_TRACK;
  560. }
  561. rx_bufs_used++;
  562. if (qdf_likely(peer)) {
  563. vdev = peer->vdev;
  564. } else {
  565. nbuf->next = NULL;
  566. dp_rx_deliver_to_pkt_capture_no_peer(
  567. soc, nbuf, pkt_capture_offload);
  568. if (!pkt_capture_offload)
  569. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  570. nbuf = next;
  571. continue;
  572. }
  573. if (qdf_unlikely(!vdev)) {
  574. qdf_nbuf_free(nbuf);
  575. nbuf = next;
  576. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  577. continue;
  578. }
  579. /* when hlos tid override is enabled, save tid in
  580. * skb->priority
  581. */
  582. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  583. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  584. qdf_nbuf_set_priority(nbuf, tid);
  585. rx_pdev = vdev->pdev;
  586. DP_RX_TID_SAVE(nbuf, tid);
  587. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  588. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  589. soc->wlan_cfg_ctx)) ||
  590. dp_rx_pkt_tracepoints_enabled())
  591. qdf_nbuf_set_timestamp(nbuf);
  592. tid_stats =
  593. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  594. /*
  595. * Check if DMA completed -- msdu_done is the last bit
  596. * to be written
  597. */
  598. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(nbuf))) {
  599. if (qdf_unlikely(!hal_rx_attn_msdu_done_get_li(
  600. rx_tlv_hdr))) {
  601. dp_err_rl("MSDU DONE failure");
  602. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  603. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  604. QDF_TRACE_LEVEL_INFO);
  605. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  606. qdf_assert(0);
  607. qdf_nbuf_free(nbuf);
  608. nbuf = next;
  609. continue;
  610. } else if (qdf_unlikely(hal_rx_attn_msdu_len_err_get_li(
  611. rx_tlv_hdr))) {
  612. DP_STATS_INC(soc, rx.err.msdu_len_err, 1);
  613. qdf_nbuf_free(nbuf);
  614. nbuf = next;
  615. continue;
  616. }
  617. }
  618. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  619. /*
  620. * First IF condition:
  621. * 802.11 Fragmented pkts are reinjected to REO
  622. * HW block as SG pkts and for these pkts we only
  623. * need to pull the RX TLVS header length.
  624. * Second IF condition:
  625. * The below condition happens when an MSDU is spread
  626. * across multiple buffers. This can happen in two cases
  627. * 1. The nbuf size is smaller then the received msdu.
  628. * ex: we have set the nbuf size to 2048 during
  629. * nbuf_alloc. but we received an msdu which is
  630. * 2304 bytes in size then this msdu is spread
  631. * across 2 nbufs.
  632. *
  633. * 2. AMSDUs when RAW mode is enabled.
  634. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  635. * across 1st nbuf and 2nd nbuf and last MSDU is
  636. * spread across 2nd nbuf and 3rd nbuf.
  637. *
  638. * for these scenarios let us create a skb frag_list and
  639. * append these buffers till the last MSDU of the AMSDU
  640. * Third condition:
  641. * This is the most likely case, we receive 802.3 pkts
  642. * decapsulated by HW, here we need to set the pkt length.
  643. */
  644. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  645. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  646. bool is_mcbc, is_sa_vld, is_da_vld;
  647. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  648. rx_tlv_hdr);
  649. is_sa_vld =
  650. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  651. rx_tlv_hdr);
  652. is_da_vld =
  653. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  654. rx_tlv_hdr);
  655. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  656. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  657. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  658. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  659. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  660. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  661. nbuf = dp_rx_sg_create(soc, nbuf);
  662. next = nbuf->next;
  663. if (qdf_nbuf_is_raw_frame(nbuf)) {
  664. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  665. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  666. } else {
  667. qdf_nbuf_free(nbuf);
  668. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  669. dp_info_rl("scatter msdu len %d, dropped",
  670. msdu_len);
  671. nbuf = next;
  672. continue;
  673. }
  674. } else {
  675. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  676. pkt_len = msdu_len +
  677. msdu_metadata.l3_hdr_pad +
  678. soc->rx_pkt_tlv_size;
  679. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  680. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  681. }
  682. /*
  683. * process frame for mulitpass phrase processing
  684. */
  685. if (qdf_unlikely(vdev->multipass_en)) {
  686. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  687. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  688. qdf_nbuf_free(nbuf);
  689. nbuf = next;
  690. continue;
  691. }
  692. }
  693. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  694. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  695. DP_STATS_INC(peer, rx.policy_check_drop, 1);
  696. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  697. /* Drop & free packet */
  698. qdf_nbuf_free(nbuf);
  699. /* Statistics */
  700. nbuf = next;
  701. continue;
  702. }
  703. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  704. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  705. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  706. rx_tlv_hdr) ==
  707. false))) {
  708. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  709. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  710. qdf_nbuf_free(nbuf);
  711. nbuf = next;
  712. continue;
  713. }
  714. /*
  715. * Drop non-EAPOL frames from unauthorized peer.
  716. */
  717. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize) &&
  718. !qdf_nbuf_is_raw_frame(nbuf)) {
  719. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  720. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  721. if (!is_eapol) {
  722. DP_STATS_INC(peer,
  723. rx.peer_unauth_rx_pkt_drop, 1);
  724. qdf_nbuf_free(nbuf);
  725. nbuf = next;
  726. continue;
  727. }
  728. }
  729. if (soc->process_rx_status)
  730. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  731. /* Update the protocol tag in SKB based on CCE metadata */
  732. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  733. reo_ring_num, false, true);
  734. /* Update the flow tag in SKB based on FSE metadata */
  735. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  736. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  737. reo_ring_num, tid_stats);
  738. if (qdf_unlikely(vdev->mesh_vdev)) {
  739. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  740. == QDF_STATUS_SUCCESS) {
  741. dp_rx_info("%pK: mesh pkt filtered", soc);
  742. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  743. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  744. 1);
  745. qdf_nbuf_free(nbuf);
  746. nbuf = next;
  747. continue;
  748. }
  749. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  750. }
  751. if (qdf_likely(vdev->rx_decap_type ==
  752. htt_cmn_pkt_type_ethernet) &&
  753. qdf_likely(!vdev->mesh_vdev)) {
  754. /* WDS Destination Address Learning */
  755. dp_rx_da_learn(soc, rx_tlv_hdr, peer, nbuf);
  756. /* Due to HW issue, sometimes we see that the sa_idx
  757. * and da_idx are invalid with sa_valid and da_valid
  758. * bits set
  759. *
  760. * in this case we also see that value of
  761. * sa_sw_peer_id is set as 0
  762. *
  763. * Drop the packet if sa_idx and da_idx OOB or
  764. * sa_sw_peerid is 0
  765. */
  766. if (!is_sa_da_idx_valid(soc, rx_tlv_hdr, nbuf,
  767. msdu_metadata)) {
  768. qdf_nbuf_free(nbuf);
  769. nbuf = next;
  770. DP_STATS_INC(soc, rx.err.invalid_sa_da_idx, 1);
  771. continue;
  772. }
  773. if (qdf_unlikely(dp_rx_mec_check_wrapper(soc,
  774. peer,
  775. rx_tlv_hdr,
  776. nbuf))) {
  777. /* this is a looped back MCBC pkt,drop it */
  778. DP_STATS_INC_PKT(peer, rx.mec_drop, 1,
  779. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  780. qdf_nbuf_free(nbuf);
  781. nbuf = next;
  782. continue;
  783. }
  784. /* WDS Source Port Learning */
  785. if (qdf_likely(vdev->wds_enabled))
  786. dp_rx_wds_srcport_learn(soc,
  787. rx_tlv_hdr,
  788. peer,
  789. nbuf,
  790. msdu_metadata);
  791. /* Intrabss-fwd */
  792. if (dp_rx_check_ap_bridge(vdev))
  793. if (dp_rx_intrabss_fwd_li(soc, peer, rx_tlv_hdr,
  794. nbuf,
  795. msdu_metadata)) {
  796. nbuf = next;
  797. tid_stats->intrabss_cnt++;
  798. continue; /* Get next desc */
  799. }
  800. }
  801. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  802. dp_rx_update_stats(soc, nbuf);
  803. DP_RX_LIST_APPEND(deliver_list_head,
  804. deliver_list_tail,
  805. nbuf);
  806. DP_STATS_INC_PKT(peer, rx.to_stack, 1,
  807. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  808. if (qdf_unlikely(peer->in_twt))
  809. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  810. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  811. tid_stats->delivered_to_stack++;
  812. nbuf = next;
  813. }
  814. if (qdf_likely(deliver_list_head)) {
  815. if (qdf_likely(peer)) {
  816. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  817. pkt_capture_offload,
  818. deliver_list_head);
  819. if (!pkt_capture_offload)
  820. dp_rx_deliver_to_stack(soc, vdev, peer,
  821. deliver_list_head,
  822. deliver_list_tail);
  823. } else {
  824. nbuf = deliver_list_head;
  825. while (nbuf) {
  826. next = nbuf->next;
  827. nbuf->next = NULL;
  828. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  829. nbuf = next;
  830. }
  831. }
  832. }
  833. if (qdf_likely(peer))
  834. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  835. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  836. if (quota) {
  837. num_pending =
  838. dp_rx_srng_get_num_pending(hal_soc,
  839. hal_ring_hdl,
  840. num_entries,
  841. &near_full);
  842. if (num_pending) {
  843. DP_STATS_INC(soc, rx.hp_oos2, 1);
  844. if (!hif_exec_should_yield(scn, intr_id))
  845. goto more_data;
  846. if (qdf_unlikely(near_full)) {
  847. DP_STATS_INC(soc, rx.near_full, 1);
  848. goto more_data;
  849. }
  850. }
  851. }
  852. if (vdev && vdev->osif_fisa_flush)
  853. vdev->osif_fisa_flush(soc, reo_ring_num);
  854. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  855. vdev->osif_gro_flush(vdev->osif_vdev,
  856. reo_ring_num);
  857. }
  858. }
  859. /* Update histogram statistics by looping through pdev's */
  860. DP_RX_HIST_STATS_PER_PDEV();
  861. return rx_bufs_used; /* Assume no scale factor for now */
  862. }
  863. QDF_STATUS dp_rx_desc_pool_init_li(struct dp_soc *soc,
  864. struct rx_desc_pool *rx_desc_pool,
  865. uint32_t pool_id)
  866. {
  867. return dp_rx_desc_pool_init_generic(soc, rx_desc_pool, pool_id);
  868. }
  869. void dp_rx_desc_pool_deinit_li(struct dp_soc *soc,
  870. struct rx_desc_pool *rx_desc_pool,
  871. uint32_t pool_id)
  872. {
  873. }
  874. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_li(
  875. struct dp_soc *soc,
  876. void *ring_desc,
  877. struct dp_rx_desc **r_rx_desc)
  878. {
  879. struct hal_buf_info buf_info = {0};
  880. hal_soc_handle_t hal_soc = soc->hal_soc;
  881. /* only cookie and rbm will be valid in buf_info */
  882. hal_rx_buf_cookie_rbm_get(hal_soc, (uint32_t *)ring_desc,
  883. &buf_info);
  884. if (qdf_unlikely(buf_info.rbm !=
  885. HAL_RX_BUF_RBM_SW3_BM(soc->wbm_sw0_bm_id))) {
  886. /* TODO */
  887. /* Call appropriate handler */
  888. DP_STATS_INC(soc, rx.err.invalid_rbm, 1);
  889. dp_rx_err("%pK: Invalid RBM %d", soc, buf_info.rbm);
  890. return QDF_STATUS_E_INVAL;
  891. }
  892. *r_rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, buf_info.sw_cookie);
  893. return QDF_STATUS_SUCCESS;
  894. }