sde_hw_intf.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _SDE_HW_INTF_H
  6. #define _SDE_HW_INTF_H
  7. #include "sde_hw_catalog.h"
  8. #include "sde_hw_mdss.h"
  9. #include "sde_hw_util.h"
  10. #include "sde_hw_blk.h"
  11. #include "sde_kms.h"
  12. struct sde_hw_intf;
  13. /* intf timing settings */
  14. struct intf_timing_params {
  15. u32 width; /* active width */
  16. u32 height; /* active height */
  17. u32 xres; /* Display panel width */
  18. u32 yres; /* Display panel height */
  19. u32 h_back_porch;
  20. u32 h_front_porch;
  21. u32 v_back_porch;
  22. u32 v_front_porch;
  23. u32 hsync_pulse_width;
  24. u32 vsync_pulse_width;
  25. u32 hsync_polarity;
  26. u32 vsync_polarity;
  27. u32 border_clr;
  28. u32 underflow_clr;
  29. u32 hsync_skew;
  30. u32 v_front_porch_fixed;
  31. bool wide_bus_en; /* for DP only */
  32. bool compression_en;
  33. u32 extra_dto_cycles; /* for DP only */
  34. bool dsc_4hs_merge; /* DSC 4HS merge */
  35. };
  36. struct intf_prog_fetch {
  37. u8 enable;
  38. /* vsync counter for the front porch pixel line */
  39. u32 fetch_start;
  40. };
  41. struct intf_status {
  42. u8 is_en; /* interface timing engine is enabled or not */
  43. u32 frame_count; /* frame count since timing engine enabled */
  44. u32 line_count; /* current line count including blanking */
  45. };
  46. struct intf_avr_params {
  47. u32 default_fps;
  48. u32 min_fps;
  49. u32 avr_mode; /* 0 - disable, 1 - continuous, 2 - one-shot */
  50. };
  51. /**
  52. * struct sde_hw_intf_ops : Interface to the interface Hw driver functions
  53. * Assumption is these functions will be called after clocks are enabled
  54. * @ setup_timing_gen : programs the timing engine
  55. * @ setup_prog_fetch : enables/disables the programmable fetch logic
  56. * @ setup_rot_start : enables/disables the rotator start trigger
  57. * @ enable_timing: enable/disable timing engine
  58. * @ get_status: returns if timing engine is enabled or not
  59. * @ setup_misr: enables/disables MISR in HW register
  60. * @ collect_misr: reads and stores MISR data from HW register
  61. * @ get_line_count: reads current vertical line counter
  62. * @bind_pingpong_blk: enable/disable the connection with pingpong which will
  63. * feed pixels to this interface
  64. */
  65. struct sde_hw_intf_ops {
  66. void (*setup_timing_gen)(struct sde_hw_intf *intf,
  67. const struct intf_timing_params *p,
  68. const struct sde_format *fmt);
  69. void (*setup_prg_fetch)(struct sde_hw_intf *intf,
  70. const struct intf_prog_fetch *fetch);
  71. void (*setup_rot_start)(struct sde_hw_intf *intf,
  72. const struct intf_prog_fetch *fetch);
  73. void (*enable_timing)(struct sde_hw_intf *intf,
  74. u8 enable);
  75. void (*get_status)(struct sde_hw_intf *intf,
  76. struct intf_status *status);
  77. void (*setup_misr)(struct sde_hw_intf *intf,
  78. bool enable, u32 frame_count);
  79. int (*collect_misr)(struct sde_hw_intf *intf,
  80. bool nonblock, u32 *misr_value);
  81. /**
  82. * returns the current scan line count of the display
  83. * video mode panels use get_line_count whereas get_vsync_info
  84. * is used for command mode panels
  85. */
  86. u32 (*get_line_count)(struct sde_hw_intf *intf);
  87. void (*bind_pingpong_blk)(struct sde_hw_intf *intf,
  88. bool enable,
  89. const enum sde_pingpong pp);
  90. /**
  91. * enables vysnc generation and sets up init value of
  92. * read pointer and programs the tear check cofiguration
  93. */
  94. int (*setup_tearcheck)(struct sde_hw_intf *intf,
  95. struct sde_hw_tear_check *cfg);
  96. /**
  97. * enables tear check block
  98. */
  99. int (*enable_tearcheck)(struct sde_hw_intf *intf,
  100. bool enable);
  101. /**
  102. * updates tearcheck configuration
  103. */
  104. void (*update_tearcheck)(struct sde_hw_intf *intf,
  105. struct sde_hw_tear_check *cfg);
  106. /**
  107. * read, modify, write to either set or clear listening to external TE
  108. * @Return: 1 if TE was originally connected, 0 if not, or -ERROR
  109. */
  110. int (*connect_external_te)(struct sde_hw_intf *intf,
  111. bool enable_external_te);
  112. /**
  113. * provides the programmed and current
  114. * line_count
  115. */
  116. int (*get_vsync_info)(struct sde_hw_intf *intf,
  117. struct sde_hw_pp_vsync_info *info);
  118. /**
  119. * configure and enable the autorefresh config
  120. */
  121. int (*setup_autorefresh)(struct sde_hw_intf *intf,
  122. struct sde_hw_autorefresh *cfg);
  123. /**
  124. * retrieve autorefresh config from hardware
  125. */
  126. int (*get_autorefresh)(struct sde_hw_intf *intf,
  127. struct sde_hw_autorefresh *cfg);
  128. /**
  129. * poll until write pointer transmission starts
  130. * @Return: 0 on success, -ETIMEDOUT on timeout
  131. */
  132. int (*poll_timeout_wr_ptr)(struct sde_hw_intf *intf, u32 timeout_us);
  133. /**
  134. * Select vsync signal for tear-effect configuration
  135. */
  136. void (*vsync_sel)(struct sde_hw_intf *intf, u32 vsync_source);
  137. /**
  138. * Program the AVR_TOTAL for min fps rate
  139. */
  140. int (*avr_setup)(struct sde_hw_intf *intf,
  141. const struct intf_timing_params *params,
  142. const struct intf_avr_params *avr_params);
  143. /**
  144. * Signal the trigger on each commit for AVR
  145. */
  146. void (*avr_trigger)(struct sde_hw_intf *ctx);
  147. /**
  148. * Enable AVR and select the mode
  149. */
  150. void (*avr_ctrl)(struct sde_hw_intf *intf,
  151. const struct intf_avr_params *avr_params);
  152. /**
  153. * Enable/disable 64 bit compressed data input to interface block
  154. */
  155. void (*enable_compressed_input)(struct sde_hw_intf *intf,
  156. bool compression_en, bool dsc_4hs_merge);
  157. };
  158. struct sde_hw_intf {
  159. struct sde_hw_blk base;
  160. struct sde_hw_blk_reg_map hw;
  161. /* intf */
  162. enum sde_intf idx;
  163. const struct sde_intf_cfg *cap;
  164. const struct sde_mdss_cfg *mdss;
  165. struct split_pipe_cfg cfg;
  166. /* ops */
  167. struct sde_hw_intf_ops ops;
  168. };
  169. /**
  170. * to_sde_hw_intf - convert base object sde_hw_base to container
  171. * @hw: Pointer to base hardware block
  172. * return: Pointer to hardware block container
  173. */
  174. static inline struct sde_hw_intf *to_sde_hw_intf(struct sde_hw_blk *hw)
  175. {
  176. return container_of(hw, struct sde_hw_intf, base);
  177. }
  178. /**
  179. * sde_hw_intf_init(): Initializes the intf driver for the passed
  180. * interface idx.
  181. * @idx: interface index for which driver object is required
  182. * @addr: mapped register io address of MDP
  183. * @m : pointer to mdss catalog data
  184. */
  185. struct sde_hw_intf *sde_hw_intf_init(enum sde_intf idx,
  186. void __iomem *addr,
  187. struct sde_mdss_cfg *m);
  188. /**
  189. * sde_hw_intf_destroy(): Destroys INTF driver context
  190. * @intf: Pointer to INTF driver context
  191. */
  192. void sde_hw_intf_destroy(struct sde_hw_intf *intf);
  193. #endif /*_SDE_HW_INTF_H */