hal_rx.h 77 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_RX_H_
  19. #define _HAL_RX_H_
  20. #include <hal_api.h>
  21. #include "hal_rx_hw_defines.h"
  22. #include "hal_hw_headers.h"
  23. /*************************************
  24. * Ring desc offset/shift/masks
  25. *************************************/
  26. #define HAL_INVALID_PPDU_ID 0xFFFFFFFF
  27. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  28. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  29. #define HAL_RX_MASK(block, field) block##_##field##_MASK
  30. #define HAL_RX_GET(_ptr, block, field) \
  31. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  32. HAL_RX_MASK(block, field)) >> \
  33. HAL_RX_LSB(block, field))
  34. #define HAL_RX_GET_64(_ptr, block, field) \
  35. (((*((volatile uint64_t *)(_ptr) + \
  36. (HAL_RX_OFFSET(block, field) >> 3))) & \
  37. HAL_RX_MASK(block, field)) >> \
  38. HAL_RX_LSB(block, field))
  39. #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \
  40. (*(uint32_t *)(((uint8_t *)_ptr) + \
  41. _wrd ## _ ## _field ## _OFFSET) |= \
  42. (((_val) << _wrd ## _ ## _field ## _LSB) & \
  43. _wrd ## _ ## _field ## _MASK))
  44. /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */
  45. #ifndef RX_DATA_BUFFER_SIZE
  46. #define RX_DATA_BUFFER_SIZE 2048
  47. #endif
  48. #ifndef RX_MONITOR_BUFFER_SIZE
  49. #define RX_MONITOR_BUFFER_SIZE 2048
  50. #endif
  51. /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes
  52. * including buffer reservation, buffer alignment and skb shared info size.
  53. */
  54. #define RX_MON_STATUS_BASE_BUF_SIZE 2048
  55. #define RX_MON_STATUS_BUF_ALIGN 128
  56. #define RX_MON_STATUS_BUF_RESERVATION 128
  57. #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \
  58. (RX_MON_STATUS_BUF_RESERVATION + \
  59. RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE))
  60. /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */
  61. #define HAL_RX_NON_QOS_TID 16
  62. enum {
  63. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  64. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  65. HAL_HW_RX_DECAP_FORMAT_ETH2,
  66. HAL_HW_RX_DECAP_FORMAT_8023,
  67. };
  68. /**
  69. * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons
  70. *
  71. * @reo_psh_rsn: REO push reason
  72. * @reo_err_code: REO Error code
  73. * @rxdma_psh_rsn: RXDMA push reason
  74. * @rxdma_err_code: RXDMA Error code
  75. * @reserved_1: Reserved bits
  76. * @wbm_err_src: WBM error source
  77. * @pool_id: pool ID, indicates which rxdma pool
  78. * @reserved_2: Reserved bits
  79. */
  80. struct hal_wbm_err_desc_info {
  81. uint16_t reo_psh_rsn:2,
  82. reo_err_code:5,
  83. rxdma_psh_rsn:2,
  84. rxdma_err_code:5,
  85. reserved_1:2;
  86. uint8_t wbm_err_src:3,
  87. pool_id:2,
  88. msdu_continued:1,
  89. reserved_2:2;
  90. };
  91. /**
  92. * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info
  93. * @first_buffer: First buffer of MSDU
  94. * @last_buffer: Last buffer of MSDU
  95. * @is_decap_raw: Is RAW Frame
  96. * @reserved_1: Reserved
  97. *
  98. * MSDU with continuation:
  99. * -----------------------------------------------------------
  100. * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 |
  101. * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 |
  102. * | is_decap_raw:1/0 | Same as earlier | Same as earlier|
  103. * -----------------------------------------------------------
  104. *
  105. * Single buffer MSDU:
  106. * ------------------
  107. * | first_buffer:1 |
  108. * | last_buffer :1 |
  109. * | is_decap_raw:1/0 |
  110. * ------------------
  111. */
  112. struct hal_rx_mon_dest_buf_info {
  113. uint8_t first_buffer:1,
  114. last_buffer:1,
  115. is_decap_raw:1,
  116. reserved_1:5;
  117. };
  118. /**
  119. * struct hal_rx_msdu_metadata:Structure to hold rx fast path information.
  120. *
  121. * @l3_hdr_pad: l3 header padding
  122. * @reserved: Reserved bits
  123. * @sa_sw_peer_id: sa sw peer id
  124. * @sa_idx: sa index
  125. * @da_idx: da index
  126. */
  127. struct hal_rx_msdu_metadata {
  128. uint32_t l3_hdr_pad:16,
  129. sa_sw_peer_id:16;
  130. uint32_t sa_idx:16,
  131. da_idx:16;
  132. };
  133. struct hal_proto_params {
  134. uint8_t tcp_proto;
  135. uint8_t udp_proto;
  136. uint8_t ipv6_proto;
  137. };
  138. /**
  139. * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason"
  140. *
  141. * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected
  142. * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing
  143. */
  144. enum hal_reo_error_status {
  145. HAL_REO_ERROR_DETECTED = 0,
  146. HAL_REO_ROUTING_INSTRUCTION = 1,
  147. };
  148. /**
  149. * @msdu_flags: [0] first_msdu_in_mpdu
  150. * [1] last_msdu_in_mpdu
  151. * [2] msdu_continuation - MSDU spread across buffers
  152. * [23] sa_is_valid - SA match in peer table
  153. * [24] sa_idx_timeout - Timeout while searching for SA match
  154. * [25] da_is_valid - Used to identtify intra-bss forwarding
  155. * [26] da_is_MCBC
  156. * [27] da_idx_timeout - Timeout while searching for DA match
  157. *
  158. */
  159. struct hal_rx_msdu_desc_info {
  160. uint32_t msdu_flags;
  161. uint16_t msdu_len; /* 14 bits for length */
  162. };
  163. /**
  164. * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO
  165. *
  166. * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU
  167. * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU
  168. * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation
  169. * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST
  170. * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out
  171. * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST
  172. * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address
  173. * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out
  174. */
  175. enum hal_rx_msdu_desc_flags {
  176. HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0),
  177. HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1),
  178. HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2),
  179. HAL_MSDU_F_SA_IS_VALID = (0x1 << 23),
  180. HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24),
  181. HAL_MSDU_F_DA_IS_VALID = (0x1 << 25),
  182. HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26),
  183. HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27)
  184. };
  185. /*
  186. * @msdu_count: no. of msdus in the MPDU
  187. * @mpdu_seq: MPDU sequence number
  188. * @mpdu_flags [0] Fragment flag
  189. * [1] MPDU_retry_bit
  190. * [2] AMPDU flag
  191. * [3] raw_ampdu
  192. * @peer_meta_data: Upper bits containing peer id, vdev id
  193. * @bar_frame: indicates if received frame is a bar frame
  194. */
  195. struct hal_rx_mpdu_desc_info {
  196. uint16_t msdu_count;
  197. uint16_t mpdu_seq; /* 12 bits for length */
  198. uint32_t mpdu_flags;
  199. uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */
  200. uint16_t bar_frame;
  201. };
  202. /**
  203. * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO
  204. *
  205. * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation)
  206. * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU
  207. * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU
  208. * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU
  209. */
  210. enum hal_rx_mpdu_desc_flags {
  211. HAL_MPDU_F_FRAGMENT = (0x1 << 20),
  212. HAL_MPDU_F_RETRY_BIT = (0x1 << 21),
  213. HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22),
  214. HAL_MPDU_F_RAW_AMPDU = (0x1 << 30)
  215. };
  216. /* Return Buffer manager ID */
  217. #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0
  218. #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1
  219. #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2
  220. #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3
  221. #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id)
  222. #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1)
  223. #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2)
  224. #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3)
  225. #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4)
  226. #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5)
  227. #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6)
  228. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0
  229. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  230. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  231. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4
  232. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  233. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  234. /*
  235. * macro to set the LSW of the nbuf data physical address
  236. * to the rxdma ring entry
  237. */
  238. #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \
  239. ((*(((unsigned int *) buff_addr_info) + \
  240. (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
  241. (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \
  242. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK)
  243. /*
  244. * macro to set the LSB of MSW of the nbuf data physical address
  245. * to the rxdma ring entry
  246. */
  247. #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \
  248. ((*(((unsigned int *) buff_addr_info) + \
  249. (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
  250. (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \
  251. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK)
  252. #ifdef DP_RX_DESC_COOKIE_INVALIDATE
  253. #define HAL_RX_COOKIE_INVALID_MASK 0x80000000
  254. /*
  255. * macro to get the invalid bit for sw cookie
  256. */
  257. #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \
  258. ((*(((unsigned int *)buff_addr_info) + \
  259. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  260. HAL_RX_COOKIE_INVALID_MASK)
  261. /*
  262. * macro to set the invalid bit for sw cookie
  263. */
  264. #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \
  265. ((*(((unsigned int *)buff_addr_info) + \
  266. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  267. HAL_RX_COOKIE_INVALID_MASK)
  268. /*
  269. * macro to reset the invalid bit for sw cookie
  270. */
  271. #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \
  272. ((*(((unsigned int *)buff_addr_info) + \
  273. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  274. ~HAL_RX_COOKIE_INVALID_MASK)
  275. #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \
  276. (HAL_RX_BUF_COOKIE_INVALID_GET(& \
  277. (((struct reo_destination_ring *) \
  278. reo_desc)->buf_or_link_desc_addr_info)))
  279. #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \
  280. (HAL_RX_BUF_COOKIE_INVALID_SET(& \
  281. (((struct reo_destination_ring *) \
  282. reo_desc)->buf_or_link_desc_addr_info)))
  283. #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000
  284. #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \
  285. ((*(((unsigned int *)buff_addr_info) + \
  286. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  287. HAL_RX_LINK_COOKIE_INVALID_MASK)
  288. #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \
  289. ((*(((unsigned int *)buff_addr_info) + \
  290. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  291. HAL_RX_LINK_COOKIE_INVALID_MASK)
  292. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \
  293. (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \
  294. (((struct reo_destination_ring *) \
  295. reo_desc)->buf_or_link_desc_addr_info)))
  296. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \
  297. (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \
  298. (((struct reo_destination_ring *) \
  299. reo_desc)->buf_or_link_desc_addr_info)))
  300. #endif
  301. /* TODO: Convert the following structure fields accesseses to offsets */
  302. #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \
  303. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  304. (((struct reo_destination_ring *) \
  305. reo_desc)->buf_or_link_desc_addr_info)))
  306. #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \
  307. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  308. (((struct reo_destination_ring *) \
  309. reo_desc)->buf_or_link_desc_addr_info)))
  310. #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \
  311. (HAL_RX_BUF_COOKIE_INVALID_RESET(& \
  312. (((struct reo_destination_ring *) \
  313. reo_desc)->buf_or_link_desc_addr_info)))
  314. #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \
  315. HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \
  316. _field, _val)
  317. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0
  318. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  319. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  320. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  321. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  322. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \
  323. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \
  324. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB))
  325. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4
  326. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  327. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  328. #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \
  329. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  330. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \
  331. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \
  332. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB))
  333. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0
  334. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
  335. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
  336. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0
  337. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1
  338. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
  339. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  340. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  341. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \
  342. (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \
  343. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  344. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  345. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  346. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \
  347. (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \
  348. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK)
  349. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  350. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  351. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  352. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  353. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  354. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  355. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  356. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK)
  357. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0
  358. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3
  359. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8
  360. #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \
  361. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  362. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \
  363. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \
  364. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB))
  365. #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \
  366. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  367. (((struct reo_destination_ring *) \
  368. reo_desc)->buf_or_link_desc_addr_info)))
  369. #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \
  370. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  371. (((struct reo_destination_ring *) \
  372. reo_desc)->buf_or_link_desc_addr_info)))
  373. static inline uint32_t
  374. hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl,
  375. rx_msdu_desc_info_t msdu_desc_info_hdl)
  376. {
  377. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  378. return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl);
  379. }
  380. /*
  381. *hal_rx_msdu_desc_info_get: Gets the flags related to MSDU descriptor.
  382. * Specifically flags needed are: first_msdu_in_mpdu,
  383. * last_msdu_in_mpdu, msdu_continuation, sa_is_valid,
  384. * sa_idx_timeout, da_is_valid, da_idx_timeout, da_is_MCBC
  385. *
  386. *@hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current
  387. * descriptor
  388. *@msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor
  389. *
  390. *Return: void
  391. */
  392. static inline void
  393. hal_rx_msdu_desc_info_get(hal_soc_handle_t hal_soc_hdl,
  394. void *desc_addr,
  395. struct hal_rx_msdu_desc_info *msdu_desc_info)
  396. {
  397. struct reo_destination_ring *reo_dst_ring;
  398. uint32_t *msdu_info;
  399. reo_dst_ring = (struct reo_destination_ring *) desc_addr;
  400. msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details;
  401. msdu_desc_info->msdu_flags = hal_rx_msdu_flags_get(
  402. hal_soc_hdl,
  403. (struct rx_msdu_desc_info *)msdu_info);
  404. msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info);
  405. }
  406. /*
  407. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  408. * pre-header.
  409. */
  410. static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl,
  411. void *hw_desc_addr)
  412. {
  413. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  414. return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr);
  415. }
  416. /**
  417. * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params
  418. * @hal_soc_hdl: hal soc handle
  419. * @desc_addr: ring descriptor
  420. * @mpdu_desc_info: Buffer to fill the mpdu desc info params
  421. *
  422. * Return: None
  423. */
  424. static inline void
  425. hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr,
  426. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  427. {
  428. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  429. return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr,
  430. mpdu_desc_info);
  431. }
  432. #define HAL_RX_NUM_MSDU_DESC 6
  433. #define HAL_RX_MAX_SAVED_RING_DESC 16
  434. /* TODO: rework the structure */
  435. struct hal_rx_msdu_list {
  436. struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
  437. uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC];
  438. uint8_t rbm[HAL_RX_NUM_MSDU_DESC];
  439. /* physical address of the msdu */
  440. uint64_t paddr[HAL_RX_NUM_MSDU_DESC];
  441. };
  442. struct hal_buf_info {
  443. uint64_t paddr;
  444. uint32_t sw_cookie;
  445. uint8_t rbm;
  446. };
  447. /* This special cookie value will be used to indicate FW allocated buffers
  448. * received through RXDMA2SW ring for RXDMA WARs
  449. */
  450. #define HAL_RX_COOKIE_SPECIAL 0x1fffff
  451. /**
  452. * enum hal_reo_error_code: Indicates that type of buffer or descriptor
  453. *
  454. * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer
  455. * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link
  456. * descriptor
  457. */
  458. enum hal_rx_reo_buf_type {
  459. HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0,
  460. HAL_RX_REO_MSDU_LINK_DESC_TYPE,
  461. };
  462. /**
  463. * enum hal_reo_error_code: Error code describing the type of error detected
  464. *
  465. * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the
  466. * REO_ENTRANCE ring is set to 0
  467. * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set
  468. * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session
  469. * having been setup
  470. * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN,
  471. * Retry bit set: duplicate frame
  472. * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame
  473. * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame)
  474. * received with 2K jump in SN
  475. * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN
  476. * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received
  477. * with SN falling within the OOR window
  478. * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the
  479. * OOR window
  480. * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session
  481. * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN
  482. * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet
  483. * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  484. * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor
  485. * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  486. * of the pn_error_detected_flag been set in the REO Queue descriptor
  487. * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of
  488. * the queue descriptor(address) being blocked as SW/FW seems to be currently
  489. * in the process of making updates to this descriptor
  490. */
  491. enum hal_reo_error_code {
  492. HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0,
  493. HAL_REO_ERR_QUEUE_DESC_INVALID,
  494. HAL_REO_ERR_AMPDU_IN_NON_BA,
  495. HAL_REO_ERR_NON_BA_DUPLICATE,
  496. HAL_REO_ERR_BA_DUPLICATE,
  497. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP,
  498. HAL_REO_ERR_BAR_FRAME_2K_JUMP,
  499. HAL_REO_ERR_REGULAR_FRAME_OOR,
  500. HAL_REO_ERR_BAR_FRAME_OOR,
  501. HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION,
  502. HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN,
  503. HAL_REO_ERR_PN_CHECK_FAILED,
  504. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET,
  505. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET,
  506. HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET,
  507. HAL_REO_ERR_MAX
  508. };
  509. /**
  510. * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected
  511. *
  512. * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow
  513. * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO
  514. * overflow
  515. * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving
  516. * incomplete
  517. * MPDU from the PHY
  518. * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed
  519. * @ HAL_RXDMA_ERR_DECRYPT : Decryption error
  520. * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error
  521. * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be
  522. * encrypted but wasn’t
  523. * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error
  524. * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded
  525. * the max allowed
  526. * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error
  527. * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error
  528. * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout
  529. * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout
  530. * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout
  531. * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request
  532. * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors
  533. */
  534. enum hal_rxdma_error_code {
  535. HAL_RXDMA_ERR_OVERFLOW = 0,
  536. HAL_RXDMA_ERR_MPDU_LENGTH,
  537. HAL_RXDMA_ERR_FCS,
  538. HAL_RXDMA_ERR_DECRYPT,
  539. HAL_RXDMA_ERR_TKIP_MIC,
  540. HAL_RXDMA_ERR_UNENCRYPTED,
  541. HAL_RXDMA_ERR_MSDU_LEN,
  542. HAL_RXDMA_ERR_MSDU_LIMIT,
  543. HAL_RXDMA_ERR_WIFI_PARSE,
  544. HAL_RXDMA_ERR_AMSDU_PARSE,
  545. HAL_RXDMA_ERR_SA_TIMEOUT,
  546. HAL_RXDMA_ERR_DA_TIMEOUT,
  547. HAL_RXDMA_ERR_FLOW_TIMEOUT,
  548. HAL_RXDMA_ERR_FLUSH_REQUEST,
  549. HAL_RXDMA_ERR_WAR = 31,
  550. HAL_RXDMA_ERR_MAX
  551. };
  552. /**
  553. * HW BM action settings in WBM release ring
  554. */
  555. #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0
  556. #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1
  557. /**
  558. * enum hal_rx_wbm_error_source: Indicates which module initiated the
  559. * release of this buffer or descriptor
  560. *
  561. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  562. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  563. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  564. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  565. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  566. */
  567. enum hal_rx_wbm_error_source {
  568. HAL_RX_WBM_ERR_SRC_TQM = 0,
  569. HAL_RX_WBM_ERR_SRC_RXDMA,
  570. HAL_RX_WBM_ERR_SRC_REO,
  571. HAL_RX_WBM_ERR_SRC_FW,
  572. HAL_RX_WBM_ERR_SRC_SW,
  573. };
  574. /**
  575. * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor
  576. * released
  577. *
  578. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  579. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  580. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  581. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  582. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  583. */
  584. enum hal_rx_wbm_buf_type {
  585. HAL_RX_WBM_BUF_TYPE_REL_BUF = 0,
  586. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC,
  587. HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC,
  588. HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC,
  589. HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC,
  590. };
  591. #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
  592. //#include "hal_rx_be.h"
  593. /*
  594. * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address
  595. *
  596. * @nbuf: Network buffer
  597. * Returns: flag to indicate whether the nbuf has MC/BC address
  598. */
  599. static inline uint32_t
  600. hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl,
  601. qdf_nbuf_t nbuf)
  602. {
  603. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  604. return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf);
  605. }
  606. /**
  607. * hal_rx_priv_info_set_in_tlv(): Save the private info to
  608. * the reserved bytes of rx_tlv_hdr
  609. * @buf: start of rx_tlv_hdr
  610. * @wbm_er_info: hal_wbm_err_desc_info structure
  611. * Return: void
  612. */
  613. static inline void
  614. hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl,
  615. uint8_t *buf, uint8_t *priv_data,
  616. uint32_t len)
  617. {
  618. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  619. return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf,
  620. priv_data,
  621. len);
  622. }
  623. /*
  624. * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from
  625. * reo_entrance_ring descriptor
  626. *
  627. * @reo_ent_desc: reo_entrance_ring descriptor
  628. * Returns: value of rxdma_push_reason
  629. */
  630. static inline
  631. uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc)
  632. {
  633. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  634. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)),
  635. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK,
  636. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB);
  637. }
  638. /**
  639. * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from
  640. * reo_entrance_ring descriptor
  641. * @reo_ent_desc: reo_entrance_ring descriptor
  642. * Return: value of rxdma_error_code
  643. */
  644. static inline
  645. uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc)
  646. {
  647. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  648. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)),
  649. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK,
  650. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB);
  651. }
  652. /**
  653. * hal_rx_priv_info_get_from_tlv(): retrieve the private data from
  654. * the reserved bytes of rx_tlv_hdr.
  655. * @buf: start of rx_tlv_hdr
  656. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  657. * Return: void
  658. */
  659. static inline void
  660. hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl,
  661. uint8_t *buf, uint8_t *wbm_er_info,
  662. uint32_t len)
  663. {
  664. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  665. return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf,
  666. wbm_er_info,
  667. len);
  668. }
  669. static inline void
  670. hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size,
  671. uint16_t *rx_mon_pkt_tlv_size)
  672. {
  673. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  674. return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size,
  675. rx_mon_pkt_tlv_size);
  676. }
  677. /*
  678. * hal_rx_encryption_info_valid(): Returns encryption type.
  679. *
  680. * @hal_soc_hdl: hal soc handle
  681. * @buf: rx_tlv_hdr of the received packet
  682. *
  683. * Return: encryption type
  684. */
  685. static inline uint32_t
  686. hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  687. {
  688. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  689. return hal_soc->ops->hal_rx_encryption_info_valid(buf);
  690. }
  691. /*
  692. * hal_rx_print_pn: Prints the PN of rx packet.
  693. * @hal_soc_hdl: hal soc handle
  694. * @buf: rx_tlv_hdr of the received packet
  695. *
  696. * Return: void
  697. */
  698. static inline void
  699. hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  700. {
  701. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  702. hal_soc->ops->hal_rx_print_pn(buf);
  703. }
  704. /**
  705. * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the
  706. * l3_header padding from rx_msdu_end TLV
  707. *
  708. * @buf: pointer to the start of RX PKT TLV headers
  709. * Return: number of l3 header padding bytes
  710. */
  711. static inline uint32_t
  712. hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl,
  713. uint8_t *buf)
  714. {
  715. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  716. return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf);
  717. }
  718. /**
  719. * hal_rx_msdu_end_sa_idx_get(): API to get the
  720. * sa_idx from rx_msdu_end TLV
  721. *
  722. * @ buf: pointer to the start of RX PKT TLV headers
  723. * Return: sa_idx (SA AST index)
  724. */
  725. static inline uint16_t
  726. hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl,
  727. uint8_t *buf)
  728. {
  729. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  730. return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf);
  731. }
  732. /**
  733. * hal_rx_msdu_end_sa_is_valid_get(): API to get the
  734. * sa_is_valid bit from rx_msdu_end TLV
  735. *
  736. * @ buf: pointer to the start of RX PKT TLV headers
  737. * Return: sa_is_valid bit
  738. */
  739. static inline uint8_t
  740. hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  741. uint8_t *buf)
  742. {
  743. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  744. return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf);
  745. }
  746. /**
  747. * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length
  748. * from rx_msdu_start TLV
  749. *
  750. * @buf: pointer to the start of RX PKT TLV headers
  751. * @len: msdu length
  752. *
  753. * Return: none
  754. */
  755. static inline void
  756. hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  757. uint32_t len)
  758. {
  759. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  760. return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len);
  761. }
  762. /**
  763. * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO
  764. *
  765. * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame
  766. * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame
  767. * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame
  768. * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame
  769. * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame
  770. * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame
  771. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame
  772. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame
  773. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame
  774. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame
  775. * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported
  776. * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit
  777. */
  778. enum hal_rx_mpdu_info_sw_frame_group_id_type {
  779. HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0,
  780. HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA,
  781. HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA,
  782. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA,
  783. HAL_MPDU_SW_FRAME_GROUP_MGMT,
  784. HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8,
  785. HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12,
  786. HAL_MPDU_SW_FRAME_GROUP_CTRL = 20,
  787. HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25,
  788. HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28,
  789. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31,
  790. HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36,
  791. HAL_MPDU_SW_FRAME_GROUP_MAX = 37,
  792. };
  793. /**
  794. * hal_rx_mpdu_start_mpdu_qos_control_valid_get():
  795. * Retrieve qos control valid bit from the tlv.
  796. * @hal_soc_hdl: hal_soc handle
  797. * @buf: pointer to rx pkt TLV.
  798. *
  799. * Return: qos control value.
  800. */
  801. static inline uint32_t
  802. hal_rx_mpdu_start_mpdu_qos_control_valid_get(
  803. hal_soc_handle_t hal_soc_hdl,
  804. uint8_t *buf)
  805. {
  806. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  807. if ((!hal_soc) || (!hal_soc->ops)) {
  808. hal_err("hal handle is NULL");
  809. QDF_BUG(0);
  810. return QDF_STATUS_E_INVAL;
  811. }
  812. if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get)
  813. return hal_soc->ops->
  814. hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf);
  815. return QDF_STATUS_E_INVAL;
  816. }
  817. /**
  818. * hal_rx_is_unicast: check packet is unicast frame or not.
  819. * @hal_soc_hdl: hal_soc handle
  820. * @buf: pointer to rx pkt TLV.
  821. *
  822. * Return: true on unicast.
  823. */
  824. static inline bool
  825. hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  826. {
  827. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  828. return hal_soc->ops->hal_rx_is_unicast(buf);
  829. }
  830. /**
  831. * hal_rx_tid_get: get tid based on qos control valid.
  832. * @hal_soc_hdl: hal soc handle
  833. * @buf: pointer to rx pkt TLV.
  834. *
  835. * Return: tid
  836. */
  837. static inline uint32_t
  838. hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  839. {
  840. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  841. return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf);
  842. }
  843. /**
  844. * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id
  845. * @hal_soc_hdl: hal soc handle
  846. * @buf: pointer to rx pkt TLV.
  847. *
  848. * Return: sw peer_id
  849. */
  850. static inline uint32_t
  851. hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  852. uint8_t *buf)
  853. {
  854. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  855. return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf);
  856. }
  857. /*
  858. * hal_rx_mpdu_get_tods(): API to get the tods info
  859. * from rx_mpdu_start
  860. *
  861. * @buf: pointer to the start of RX PKT TLV header
  862. * Return: uint32_t(to_ds)
  863. */
  864. static inline uint32_t
  865. hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  866. {
  867. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  868. return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf);
  869. }
  870. /*
  871. * hal_rx_mpdu_get_fr_ds(): API to get the from ds info
  872. * from rx_mpdu_start
  873. * @hal_soc_hdl: hal soc handle
  874. * @buf: pointer to the start of RX PKT TLV header
  875. *
  876. * Return: uint32_t(fr_ds)
  877. */
  878. static inline uint32_t
  879. hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  880. {
  881. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  882. return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf);
  883. }
  884. /*
  885. * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu
  886. * @hal_soc_hdl: hal soc handle
  887. * @buf: pointer to the start of RX PKT TLV headera
  888. * @mac_addr: pointer to mac address
  889. *
  890. * Return: success/failure
  891. */
  892. static inline
  893. QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl,
  894. uint8_t *buf, uint8_t *mac_addr)
  895. {
  896. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  897. return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr);
  898. }
  899. /*
  900. * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu
  901. * in the packet
  902. * @hal_soc_hdl: hal soc handle
  903. * @buf: pointer to the start of RX PKT TLV header
  904. * @mac_addr: pointer to mac address
  905. *
  906. * Return: success/failure
  907. */
  908. static inline
  909. QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl,
  910. uint8_t *buf, uint8_t *mac_addr)
  911. {
  912. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  913. return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr);
  914. }
  915. /*
  916. * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu
  917. * in the packet
  918. * @hal_soc_hdl: hal soc handle
  919. * @buf: pointer to the start of RX PKT TLV header
  920. * @mac_addr: pointer to mac address
  921. *
  922. * Return: success/failure
  923. */
  924. static inline
  925. QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl,
  926. uint8_t *buf, uint8_t *mac_addr)
  927. {
  928. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  929. return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr);
  930. }
  931. /*
  932. * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu
  933. * in the packet
  934. * @hal_soc_hdl: hal_soc handle
  935. * @buf: pointer to the start of RX PKT TLV header
  936. * @mac_addr: pointer to mac address
  937. * Return: success/failure
  938. */
  939. static inline
  940. QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl,
  941. uint8_t *buf, uint8_t *mac_addr)
  942. {
  943. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  944. return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr);
  945. }
  946. /**
  947. * hal_rx_msdu_end_da_idx_get: API to get da_idx
  948. * from rx_msdu_end TLV
  949. *
  950. * @ buf: pointer to the start of RX PKT TLV headers
  951. * Return: da index
  952. */
  953. static inline uint16_t
  954. hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  955. {
  956. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  957. return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf);
  958. }
  959. /**
  960. * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid
  961. * from rx_msdu_end TLV
  962. * @hal_soc_hdl: hal soc handle
  963. * @ buf: pointer to the start of RX PKT TLV headers
  964. *
  965. * Return: da_is_valid
  966. */
  967. static inline uint8_t
  968. hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  969. uint8_t *buf)
  970. {
  971. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  972. return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf);
  973. }
  974. /**
  975. * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
  976. * from rx_msdu_end TLV
  977. *
  978. * @buf: pointer to the start of RX PKT TLV headers
  979. *
  980. * Return: da_is_mcbc
  981. */
  982. static inline uint8_t
  983. hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  984. {
  985. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  986. return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf);
  987. }
  988. /**
  989. * hal_rx_msdu_end_first_msdu_get: API to get first msdu status
  990. * from rx_msdu_end TLV
  991. * @hal_soc_hdl: hal soc handle
  992. * @buf: pointer to the start of RX PKT TLV headers
  993. *
  994. * Return: first_msdu
  995. */
  996. static inline uint8_t
  997. hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl,
  998. uint8_t *buf)
  999. {
  1000. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1001. return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf);
  1002. }
  1003. /**
  1004. * hal_rx_msdu_end_last_msdu_get: API to get last msdu status
  1005. * from rx_msdu_end TLV
  1006. * @hal_soc_hdl: hal soc handle
  1007. * @buf: pointer to the start of RX PKT TLV headers
  1008. *
  1009. * Return: last_msdu
  1010. */
  1011. static inline uint8_t
  1012. hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1013. uint8_t *buf)
  1014. {
  1015. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1016. return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf);
  1017. }
  1018. /**
  1019. * hal_rx_msdu_cce_metadata_get: API to get CCE metadata
  1020. * from rx_msdu_end TLV
  1021. * @buf: pointer to the start of RX PKT TLV headers
  1022. * Return: cce_meta_data
  1023. */
  1024. static inline uint16_t
  1025. hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1026. uint8_t *buf)
  1027. {
  1028. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1029. return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf);
  1030. }
  1031. /*******************************************************************************
  1032. * RX REO ERROR APIS
  1033. ******************************************************************************/
  1034. /**
  1035. * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details
  1036. * @msdu_link_ptr - msdu link ptr
  1037. * @hal - pointer to hal_soc
  1038. * Return - Pointer to rx_msdu_details structure
  1039. *
  1040. */
  1041. static inline
  1042. void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr,
  1043. struct hal_soc *hal_soc)
  1044. {
  1045. return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr);
  1046. }
  1047. /**
  1048. * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
  1049. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1050. * @hal - pointer to hal_soc
  1051. * Return - Pointer to rx_msdu_desc_info structure.
  1052. *
  1053. */
  1054. static inline
  1055. void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr,
  1056. struct hal_soc *hal_soc)
  1057. {
  1058. return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr);
  1059. }
  1060. /**
  1061. * hal_rx_reo_buf_paddr_get: Gets the physical address and
  1062. * cookie from the REO destination ring element
  1063. *
  1064. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1065. * the current descriptor
  1066. * @ buf_info: structure to return the buffer information
  1067. * Return: void
  1068. */
  1069. static inline
  1070. void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc,
  1071. struct hal_buf_info *buf_info)
  1072. {
  1073. struct reo_destination_ring *reo_ring =
  1074. (struct reo_destination_ring *)rx_desc;
  1075. buf_info->paddr =
  1076. (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
  1077. ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
  1078. }
  1079. /**
  1080. * hal_rx_buf_cookie_rbm_get: Gets the physical address and
  1081. * cookie from the REO entrance ring element
  1082. *
  1083. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1084. * the current descriptor
  1085. * @ buf_info: structure to return the buffer information
  1086. * @ msdu_cnt: pointer to msdu count in MPDU
  1087. * Return: void
  1088. */
  1089. static inline
  1090. void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl,
  1091. uint32_t *buf_addr_info,
  1092. struct hal_buf_info *buf_info)
  1093. {
  1094. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1095. return hal_soc->ops->hal_rx_buf_cookie_rbm_get(
  1096. (hal_buff_addrinfo_t)buf_addr_info,
  1097. buf_info);
  1098. }
  1099. /**
  1100. * hal_rx_msdu_link_desc_get(): API to get the MSDU information
  1101. * from the MSDU link descriptor
  1102. *
  1103. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  1104. * MSDU link descriptor (struct rx_msdu_link)
  1105. *
  1106. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  1107. *
  1108. * @num_msdus: Number of MSDUs in the MPDU
  1109. *
  1110. * Return: void
  1111. */
  1112. static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl,
  1113. void *msdu_link_desc,
  1114. struct hal_rx_msdu_list *msdu_list,
  1115. uint16_t *num_msdus)
  1116. {
  1117. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1118. struct rx_msdu_details *msdu_details;
  1119. struct rx_msdu_desc_info *msdu_desc_info;
  1120. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1121. int i;
  1122. struct hal_buf_info buf_info;
  1123. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  1124. dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK",
  1125. __func__, __LINE__, msdu_link, msdu_details);
  1126. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  1127. /* num_msdus received in mpdu descriptor may be incorrect
  1128. * sometimes due to HW issue. Check msdu buffer address also
  1129. */
  1130. if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET(
  1131. &msdu_details[i].buffer_addr_info_details) == 0))
  1132. break;
  1133. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  1134. &msdu_details[i].buffer_addr_info_details) == 0) {
  1135. /* set the last msdu bit in the prev msdu_desc_info */
  1136. msdu_desc_info =
  1137. hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc);
  1138. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1139. break;
  1140. }
  1141. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  1142. hal_soc);
  1143. /* set first MSDU bit or the last MSDU bit */
  1144. if (!i)
  1145. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1146. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  1147. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1148. msdu_list->msdu_info[i].msdu_flags =
  1149. hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info);
  1150. msdu_list->msdu_info[i].msdu_len =
  1151. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  1152. /* addr field in buf_info will not be valid */
  1153. hal_rx_buf_cookie_rbm_get(
  1154. hal_soc_hdl,
  1155. (uint32_t *)&msdu_details[i].buffer_addr_info_details,
  1156. &buf_info);
  1157. msdu_list->sw_cookie[i] = buf_info.sw_cookie;
  1158. msdu_list->rbm[i] = buf_info.rbm;
  1159. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  1160. &msdu_details[i].buffer_addr_info_details) |
  1161. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  1162. &msdu_details[i].buffer_addr_info_details) << 32;
  1163. dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d",
  1164. __func__, __LINE__, i, msdu_list->sw_cookie[i]);
  1165. }
  1166. *num_msdus = i;
  1167. }
  1168. /**
  1169. * hal_rx_is_pn_error() - Indicate if this error was caused by a
  1170. * PN check failure
  1171. *
  1172. * @reo_desc: opaque pointer used by HAL to get the REO destination entry
  1173. *
  1174. * Return: true: error caused by PN check, false: other error
  1175. */
  1176. static inline bool hal_rx_reo_is_pn_error(uint32_t error_code)
  1177. {
  1178. return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) ||
  1179. (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ?
  1180. true : false;
  1181. }
  1182. /**
  1183. * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in
  1184. * the sequence number
  1185. *
  1186. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1187. *
  1188. * Return: true: error caused by 2K jump, false: other error
  1189. */
  1190. static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code)
  1191. {
  1192. return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) ||
  1193. (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ?
  1194. true : false;
  1195. }
  1196. /**
  1197. * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR
  1198. *
  1199. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1200. *
  1201. * Return: true: error caused by OOR, false: other error
  1202. */
  1203. static inline bool hal_rx_reo_is_oor_error(uint32_t error_code)
  1204. {
  1205. return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ?
  1206. true : false;
  1207. }
  1208. /**
  1209. * hal_dump_wbm_rel_desc() - dump wbm release descriptor
  1210. * @hal_desc: hardware descriptor pointer
  1211. *
  1212. * This function will print wbm release descriptor
  1213. *
  1214. * Return: none
  1215. */
  1216. static inline void hal_dump_wbm_rel_desc(void *src_srng_desc)
  1217. {
  1218. uint32_t *wbm_comp = (uint32_t *)src_srng_desc;
  1219. uint32_t i;
  1220. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1221. "Current Rx wbm release descriptor is");
  1222. for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) {
  1223. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1224. "DWORD[i] = 0x%x", wbm_comp[i]);
  1225. }
  1226. }
  1227. /**
  1228. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  1229. *
  1230. * @ hal_soc_hdl : HAL version of the SOC pointer
  1231. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  1232. * @ buf_addr_info : void pointer to the buffer_addr_info
  1233. * @ bm_action : put in IDLE list or release to MSDU_LIST
  1234. *
  1235. * Return: void
  1236. */
  1237. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  1238. static inline
  1239. void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl,
  1240. void *src_srng_desc,
  1241. hal_buff_addrinfo_t buf_addr_info,
  1242. uint8_t bm_action)
  1243. {
  1244. /*
  1245. * The offsets for fields used in this function are same in
  1246. * wbm_release_ring for Lithium and wbm_release_ring_tx
  1247. * for Beryllium. hence we can use wbm_release_ring directly.
  1248. */
  1249. struct wbm_release_ring *wbm_rel_srng =
  1250. (struct wbm_release_ring *)src_srng_desc;
  1251. uint32_t addr_31_0;
  1252. uint8_t addr_39_32;
  1253. /* Structure copy !!! */
  1254. wbm_rel_srng->released_buff_or_desc_addr_info =
  1255. *((struct buffer_addr_info *)buf_addr_info);
  1256. addr_31_0 =
  1257. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0;
  1258. addr_39_32 =
  1259. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32;
  1260. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  1261. RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW);
  1262. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION,
  1263. bm_action);
  1264. HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
  1265. BUFFER_OR_DESC_TYPE,
  1266. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC);
  1267. /* WBM error is indicated when any of the link descriptors given to
  1268. * WBM has a NULL address, and one those paths is the link descriptors
  1269. * released from host after processing RXDMA errors,
  1270. * or from Rx defrag path, and we want to add an assert here to ensure
  1271. * host is not releasing descriptors with NULL address.
  1272. */
  1273. if (qdf_unlikely(!addr_31_0 && !addr_39_32)) {
  1274. hal_dump_wbm_rel_desc(src_srng_desc);
  1275. qdf_assert_always(0);
  1276. }
  1277. }
  1278. /**
  1279. * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the
  1280. * BUFFER_ADDR_INFO, give the RX descriptor
  1281. * (Assumption -- BUFFER_ADDR_INFO is the
  1282. * first field in the descriptor structure)
  1283. */
  1284. #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \
  1285. ((hal_link_desc_t)(ring_desc))
  1286. #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1287. #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1288. /*******************************************************************************
  1289. * RX WBM ERROR APIS
  1290. ******************************************************************************/
  1291. #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1292. (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \
  1293. WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \
  1294. WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB)
  1295. /**
  1296. * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed
  1297. * the frame to this release ring
  1298. *
  1299. * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this
  1300. * frame to this queue
  1301. * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per
  1302. * received routing instructions. No error within REO was detected
  1303. */
  1304. enum hal_rx_wbm_reo_push_reason {
  1305. HAL_RX_WBM_REO_PSH_RSN_ERROR = 0,
  1306. HAL_RX_WBM_REO_PSH_RSN_ROUTE,
  1307. };
  1308. /**
  1309. * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to
  1310. * this release ring
  1311. *
  1312. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed
  1313. * this frame to this queue
  1314. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue
  1315. * per received routing instructions. No error within RXDMA was detected
  1316. */
  1317. enum hal_rx_wbm_rxdma_push_reason {
  1318. HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0,
  1319. HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE,
  1320. };
  1321. static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start,
  1322. uint8_t dbg_level,
  1323. struct hal_soc *hal)
  1324. {
  1325. hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level);
  1326. }
  1327. /**
  1328. * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured
  1329. * human readable format.
  1330. * @ msdu_end: pointer the msdu_end TLV in pkt.
  1331. * @ dbg_level: log level.
  1332. *
  1333. * Return: void
  1334. */
  1335. static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc,
  1336. struct rx_msdu_end *msdu_end,
  1337. uint8_t dbg_level)
  1338. {
  1339. hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level);
  1340. }
  1341. /**
  1342. * hal_srng_ring_id_get: API to retrieve ring id from hal ring
  1343. * structure
  1344. * @hal_ring: pointer to hal_srng structure
  1345. *
  1346. * Return: ring_id
  1347. */
  1348. static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl)
  1349. {
  1350. return ((struct hal_srng *)hal_ring_hdl)->ring_id;
  1351. }
  1352. /* Rx MSDU link pointer info */
  1353. struct hal_rx_msdu_link_ptr_info {
  1354. struct rx_msdu_link msdu_link;
  1355. struct hal_buf_info msdu_link_buf_info;
  1356. };
  1357. #define DOT11_SEQ_FRAG_MASK 0x000f
  1358. #define DOT11_FC1_MORE_FRAG_OFFSET 0x04
  1359. /**
  1360. * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number
  1361. *
  1362. * @nbuf: Network buffer
  1363. * Returns: rx fragment number
  1364. */
  1365. static inline
  1366. uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc,
  1367. uint8_t *buf)
  1368. {
  1369. return hal_soc->ops->hal_rx_get_rx_fragment_number(buf);
  1370. }
  1371. /*
  1372. * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid
  1373. * @hal_soc_hdl: hal soc handle
  1374. * @nbuf: Network buffer
  1375. *
  1376. * Return: value of sequence control valid field
  1377. */
  1378. static inline
  1379. uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl,
  1380. uint8_t *buf)
  1381. {
  1382. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1383. return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf);
  1384. }
  1385. /*
  1386. * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid
  1387. * @hal_soc_hdl: hal soc handle
  1388. * @nbuf: Network buffer
  1389. *
  1390. * Returns: value of frame control valid field
  1391. */
  1392. static inline
  1393. uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl,
  1394. uint8_t *buf)
  1395. {
  1396. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1397. return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf);
  1398. }
  1399. /**
  1400. * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid
  1401. * @hal_soc_hdl: hal soc handle
  1402. * @nbuf: Network buffer
  1403. * Returns: value of mpdu 4th address valid field
  1404. */
  1405. static inline
  1406. bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl,
  1407. uint8_t *buf)
  1408. {
  1409. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1410. return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf);
  1411. }
  1412. /*
  1413. * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info
  1414. *
  1415. * @rx_mpdu_desc_info: HAL view of rx mpdu desc info
  1416. * Returns: None
  1417. */
  1418. static inline void
  1419. hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info)
  1420. {
  1421. qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info));
  1422. }
  1423. /*
  1424. * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr
  1425. *
  1426. * @msdu_link_ptr: HAL view of msdu link ptr
  1427. * @size: number of msdu link pointers
  1428. * Returns: None
  1429. */
  1430. static inline
  1431. void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr,
  1432. int size)
  1433. {
  1434. qdf_mem_zero(msdu_link_ptr, (sizeof(*msdu_link_ptr) * size));
  1435. }
  1436. /**
  1437. * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and
  1438. * save it to hal_wbm_err_desc_info structure passed by caller
  1439. * @wbm_desc: wbm ring descriptor
  1440. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  1441. * Return: void
  1442. */
  1443. static inline
  1444. void hal_rx_wbm_err_info_get(void *wbm_desc,
  1445. struct hal_wbm_err_desc_info *wbm_er_info,
  1446. hal_soc_handle_t hal_soc_hdl)
  1447. {
  1448. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1449. hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info);
  1450. }
  1451. /**
  1452. * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation
  1453. * bit from wbm release ring descriptor
  1454. * @wbm_desc: wbm ring descriptor
  1455. * Return: uint8_t
  1456. */
  1457. static inline
  1458. uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl,
  1459. void *wbm_desc)
  1460. {
  1461. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1462. return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc);
  1463. }
  1464. /**
  1465. * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status
  1466. *
  1467. * @ hal_soc: HAL version of the SOC pointer
  1468. * @ hw_desc_addr: Start address of Rx HW TLVs
  1469. * @ rs: Status for monitor mode
  1470. *
  1471. * Return: void
  1472. */
  1473. static inline
  1474. void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl,
  1475. void *hw_desc_addr,
  1476. struct mon_rx_status *rs)
  1477. {
  1478. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1479. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs);
  1480. }
  1481. /*
  1482. * hal_rx_get_tlv(): API to get the tlv
  1483. *
  1484. * @hal_soc: HAL version of the SOC pointer
  1485. * @rx_tlv: TLV data extracted from the rx packet
  1486. * Return: uint8_t
  1487. */
  1488. static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv)
  1489. {
  1490. return hal_soc->ops->hal_rx_get_tlv(rx_tlv);
  1491. }
  1492. /*
  1493. * hal_rx_msdu_start_nss_get(): API to get the NSS
  1494. * Interval from rx_msdu_start
  1495. *
  1496. * @hal_soc: HAL version of the SOC pointer
  1497. * @buf: pointer to the start of RX PKT TLV header
  1498. * Return: uint32_t(nss)
  1499. */
  1500. static inline
  1501. uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1502. {
  1503. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1504. return hal_soc->ops->hal_rx_msdu_start_nss_get(buf);
  1505. }
  1506. /**
  1507. * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured
  1508. * human readable format.
  1509. * @ msdu_start: pointer the msdu_start TLV in pkt.
  1510. * @ dbg_level: log level.
  1511. *
  1512. * Return: void
  1513. */
  1514. static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc,
  1515. struct rx_msdu_start *msdu_start,
  1516. uint8_t dbg_level)
  1517. {
  1518. hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level);
  1519. }
  1520. /**
  1521. * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start
  1522. * info details
  1523. *
  1524. * @ buf - Pointer to buffer containing rx pkt tlvs.
  1525. *
  1526. *
  1527. */
  1528. static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl,
  1529. uint8_t *buf)
  1530. {
  1531. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1532. return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf);
  1533. }
  1534. /*
  1535. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  1536. * Interval from rx_msdu_start
  1537. *
  1538. * @buf: pointer to the start of RX PKT TLV header
  1539. * Return: uint32_t(reception_type)
  1540. */
  1541. static inline
  1542. uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl,
  1543. uint8_t *buf)
  1544. {
  1545. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1546. return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf);
  1547. }
  1548. /**
  1549. * hal_reo_status_get_header_generic - Process reo desc info
  1550. * @d - Pointer to reo descriptior
  1551. * @b - tlv type info
  1552. * @h - Pointer to hal_reo_status_header where info to be stored
  1553. * @hal- pointer to hal_soc structure
  1554. * Return - none.
  1555. *
  1556. */
  1557. static inline
  1558. void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b,
  1559. void *h, struct hal_soc *hal_soc)
  1560. {
  1561. hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h);
  1562. }
  1563. /**
  1564. * hal_rx_desc_is_first_msdu() - Check if first msdu
  1565. *
  1566. * @hal_soc_hdl: hal_soc handle
  1567. * @hw_desc_addr: hardware descriptor address
  1568. *
  1569. * Return: 0 - success/ non-zero failure
  1570. */
  1571. static inline
  1572. uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl,
  1573. void *hw_desc_addr)
  1574. {
  1575. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1576. return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr);
  1577. }
  1578. static inline uint32_t
  1579. hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr)
  1580. {
  1581. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1582. return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr);
  1583. }
  1584. static inline
  1585. bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl,
  1586. uint8_t *rx_tlv_hdr)
  1587. {
  1588. uint8_t decap_format;
  1589. if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) {
  1590. decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl,
  1591. rx_tlv_hdr);
  1592. if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW)
  1593. return true;
  1594. }
  1595. return false;
  1596. }
  1597. /**
  1598. * hal_rx_msdu_fse_metadata_get: API to get FSE metadata
  1599. * from rx_msdu_end TLV
  1600. * @buf: pointer to the start of RX PKT TLV headers
  1601. *
  1602. * Return: fse metadata value from MSDU END TLV
  1603. */
  1604. static inline uint32_t
  1605. hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1606. uint8_t *buf)
  1607. {
  1608. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1609. return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf);
  1610. }
  1611. /**
  1612. * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from
  1613. * <struct buffer_addr_info> structure
  1614. * @buf_addr_info: pointer to <struct buffer_addr_info> structure
  1615. * @buf_info: structure to return the buffer information including
  1616. * paddr/cookie
  1617. *
  1618. * return: None
  1619. */
  1620. static inline
  1621. void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info,
  1622. struct hal_buf_info *buf_info)
  1623. {
  1624. buf_info->paddr =
  1625. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  1626. ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  1627. }
  1628. /**
  1629. * hal_rx_msdu_flow_idx_get: API to get flow index
  1630. * from rx_msdu_end TLV
  1631. * @buf: pointer to the start of RX PKT TLV headers
  1632. *
  1633. * Return: flow index value from MSDU END TLV
  1634. */
  1635. static inline uint32_t
  1636. hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl,
  1637. uint8_t *buf)
  1638. {
  1639. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1640. return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf);
  1641. }
  1642. /**
  1643. * hal_rx_msdu_get_reo_destination_indication: API to get reo
  1644. * destination index from rx_msdu_end TLV
  1645. * @buf: pointer to the start of RX PKT TLV headers
  1646. * @reo_destination_indication: pointer to return value of
  1647. * reo_destination_indication
  1648. *
  1649. * Return: reo_destination_indication value from MSDU END TLV
  1650. */
  1651. static inline void
  1652. hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl,
  1653. uint8_t *buf,
  1654. uint32_t *reo_destination_indication)
  1655. {
  1656. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1657. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf,
  1658. reo_destination_indication);
  1659. }
  1660. /**
  1661. * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout
  1662. * from rx_msdu_end TLV
  1663. * @buf: pointer to the start of RX PKT TLV headers
  1664. *
  1665. * Return: flow index timeout value from MSDU END TLV
  1666. */
  1667. static inline bool
  1668. hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl,
  1669. uint8_t *buf)
  1670. {
  1671. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1672. return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf);
  1673. }
  1674. /**
  1675. * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid
  1676. * from rx_msdu_end TLV
  1677. * @buf: pointer to the start of RX PKT TLV headers
  1678. *
  1679. * Return: flow index invalid value from MSDU END TLV
  1680. */
  1681. static inline bool
  1682. hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl,
  1683. uint8_t *buf)
  1684. {
  1685. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1686. return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf);
  1687. }
  1688. /**
  1689. * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id
  1690. * @hal_soc_hdl: hal_soc handle
  1691. * @rx_tlv_hdr: Rx_tlv_hdr
  1692. * @rxdma_dst_ring_desc: Rx HW descriptor
  1693. *
  1694. * Return: ppdu id
  1695. */
  1696. static inline
  1697. uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl,
  1698. void *rx_tlv_hdr,
  1699. void *rxdma_dst_ring_desc)
  1700. {
  1701. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1702. return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr,
  1703. rxdma_dst_ring_desc);
  1704. }
  1705. /**
  1706. * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id
  1707. * @hal_soc_hdl: hal_soc handle
  1708. * @buf: rx tlv address
  1709. *
  1710. * Return: sw peer id
  1711. */
  1712. static inline
  1713. uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  1714. uint8_t *buf)
  1715. {
  1716. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1717. return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf);
  1718. }
  1719. static inline
  1720. void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl,
  1721. void *link_desc_addr)
  1722. {
  1723. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1724. return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr);
  1725. }
  1726. static inline
  1727. void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl,
  1728. void *msdu_addr)
  1729. {
  1730. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1731. return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr);
  1732. }
  1733. static inline
  1734. void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1735. void *hw_addr)
  1736. {
  1737. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1738. return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr);
  1739. }
  1740. static inline
  1741. void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1742. void *hw_addr)
  1743. {
  1744. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1745. return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr);
  1746. }
  1747. static inline
  1748. uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl,
  1749. uint8_t *buf)
  1750. {
  1751. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1752. return hal_soc->ops->hal_rx_get_fc_valid(buf);
  1753. }
  1754. static inline
  1755. uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1756. {
  1757. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1758. return hal_soc->ops->hal_rx_get_to_ds_flag(buf);
  1759. }
  1760. static inline
  1761. uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl,
  1762. uint8_t *buf)
  1763. {
  1764. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1765. return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf);
  1766. }
  1767. static inline
  1768. uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl,
  1769. uint8_t *buf)
  1770. {
  1771. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1772. return hal_soc->ops->hal_rx_get_filter_category(buf);
  1773. }
  1774. static inline
  1775. uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl,
  1776. uint8_t *buf)
  1777. {
  1778. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1779. return hal_soc->ops->hal_rx_get_ppdu_id(buf);
  1780. }
  1781. /**
  1782. * hal_reo_config(): Set reo config parameters
  1783. * @soc: hal soc handle
  1784. * @reg_val: value to be set
  1785. * @reo_params: reo parameters
  1786. *
  1787. * Return: void
  1788. */
  1789. static inline
  1790. void hal_reo_config(struct hal_soc *hal_soc,
  1791. uint32_t reg_val,
  1792. struct hal_reo_params *reo_params)
  1793. {
  1794. hal_soc->ops->hal_reo_config(hal_soc,
  1795. reg_val,
  1796. reo_params);
  1797. }
  1798. /**
  1799. * hal_rx_msdu_get_flow_params: API to get flow index,
  1800. * flow index invalid and flow index timeout from rx_msdu_end TLV
  1801. * @buf: pointer to the start of RX PKT TLV headers
  1802. * @flow_invalid: pointer to return value of flow_idx_valid
  1803. * @flow_timeout: pointer to return value of flow_idx_timeout
  1804. * @flow_index: pointer to return value of flow_idx
  1805. *
  1806. * Return: none
  1807. */
  1808. static inline void
  1809. hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl,
  1810. uint8_t *buf,
  1811. bool *flow_invalid,
  1812. bool *flow_timeout,
  1813. uint32_t *flow_index)
  1814. {
  1815. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1816. hal_soc->ops->hal_rx_msdu_get_flow_params(buf,
  1817. flow_invalid,
  1818. flow_timeout,
  1819. flow_index);
  1820. }
  1821. static inline
  1822. uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl,
  1823. uint8_t *buf)
  1824. {
  1825. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1826. return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf);
  1827. }
  1828. static inline
  1829. uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl,
  1830. uint8_t *buf)
  1831. {
  1832. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1833. return hal_soc->ops->hal_rx_get_rx_sequence(buf);
  1834. }
  1835. static inline void
  1836. hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl,
  1837. void *rx_tlv,
  1838. void *ppdu_info)
  1839. {
  1840. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1841. if (hal_soc->ops->hal_rx_get_bb_info)
  1842. hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info);
  1843. }
  1844. static inline void
  1845. hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl,
  1846. void *rx_tlv,
  1847. void *ppdu_info)
  1848. {
  1849. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1850. if (hal_soc->ops->hal_rx_get_rtt_info)
  1851. hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info);
  1852. }
  1853. /**
  1854. * hal_rx_msdu_metadata_get(): API to get the
  1855. * fast path information from rx_msdu_end TLV
  1856. *
  1857. * @ hal_soc_hdl: DP soc handle
  1858. * @ buf: pointer to the start of RX PKT TLV headers
  1859. * @ msdu_metadata: Structure to hold msdu end information
  1860. * Return: none
  1861. */
  1862. static inline void
  1863. hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  1864. struct hal_rx_msdu_metadata *msdu_md)
  1865. {
  1866. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1867. return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md);
  1868. }
  1869. /**
  1870. * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum
  1871. * from rx_msdu_end TLV
  1872. * @buf: pointer to the start of RX PKT TLV headers
  1873. *
  1874. * Return: cumulative_l4_checksum
  1875. */
  1876. static inline uint16_t
  1877. hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl,
  1878. uint8_t *buf)
  1879. {
  1880. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1881. if (!hal_soc || !hal_soc->ops) {
  1882. hal_err("hal handle is NULL");
  1883. QDF_BUG(0);
  1884. return 0;
  1885. }
  1886. if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum)
  1887. return 0;
  1888. return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf);
  1889. }
  1890. /**
  1891. * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length
  1892. * from rx_msdu_end TLV
  1893. * @buf: pointer to the start of RX PKT TLV headers
  1894. *
  1895. * Return: cumulative_ip_length
  1896. */
  1897. static inline uint16_t
  1898. hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl,
  1899. uint8_t *buf)
  1900. {
  1901. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1902. if (!hal_soc || !hal_soc->ops) {
  1903. hal_err("hal handle is NULL");
  1904. QDF_BUG(0);
  1905. return 0;
  1906. }
  1907. if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length)
  1908. return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf);
  1909. return 0;
  1910. }
  1911. /**
  1912. * hal_rx_get_udp_proto: API to get UDP proto field
  1913. * from rx_msdu_start TLV
  1914. * @buf: pointer to the start of RX PKT TLV headers
  1915. *
  1916. * Return: UDP proto field value
  1917. */
  1918. static inline bool
  1919. hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1920. {
  1921. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1922. if (!hal_soc || !hal_soc->ops) {
  1923. hal_err("hal handle is NULL");
  1924. QDF_BUG(0);
  1925. return 0;
  1926. }
  1927. if (hal_soc->ops->hal_rx_get_udp_proto)
  1928. return hal_soc->ops->hal_rx_get_udp_proto(buf);
  1929. return 0;
  1930. }
  1931. /**
  1932. * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation
  1933. * from rx_msdu_end TLV
  1934. * @buf: pointer to the start of RX PKT TLV headers
  1935. *
  1936. * Return: flow_agg_continuation bit field value
  1937. */
  1938. static inline bool
  1939. hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl,
  1940. uint8_t *buf)
  1941. {
  1942. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1943. if (!hal_soc || !hal_soc->ops) {
  1944. hal_err("hal handle is NULL");
  1945. QDF_BUG(0);
  1946. return 0;
  1947. }
  1948. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation)
  1949. return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf);
  1950. return 0;
  1951. }
  1952. /**
  1953. * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from
  1954. * rx_msdu_end TLV
  1955. * @buf: pointer to the start of RX PKT TLV headers
  1956. *
  1957. * Return: flow_agg count value
  1958. */
  1959. static inline uint8_t
  1960. hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl,
  1961. uint8_t *buf)
  1962. {
  1963. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1964. if (!hal_soc || !hal_soc->ops) {
  1965. hal_err("hal handle is NULL");
  1966. QDF_BUG(0);
  1967. return 0;
  1968. }
  1969. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count)
  1970. return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf);
  1971. return 0;
  1972. }
  1973. /**
  1974. * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV
  1975. * @buf: pointer to the start of RX PKT TLV headers
  1976. *
  1977. * Return: fisa flow_agg timeout bit value
  1978. */
  1979. static inline bool
  1980. hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1981. {
  1982. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1983. if (!hal_soc || !hal_soc->ops) {
  1984. hal_err("hal handle is NULL");
  1985. QDF_BUG(0);
  1986. return 0;
  1987. }
  1988. if (hal_soc->ops->hal_rx_get_fisa_timeout)
  1989. return hal_soc->ops->hal_rx_get_fisa_timeout(buf);
  1990. return 0;
  1991. }
  1992. /**
  1993. * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv
  1994. * tag is valid
  1995. *
  1996. * @hal_soc_hdl: HAL SOC handle
  1997. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  1998. *
  1999. * Return: true if RX_MPDU_START tlv tag is valid, else false
  2000. */
  2001. static inline uint8_t
  2002. hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl,
  2003. void *rx_tlv_hdr)
  2004. {
  2005. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2006. if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid)
  2007. return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr);
  2008. return 0;
  2009. }
  2010. /**
  2011. * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc
  2012. * buffer addr info
  2013. * @link_desc_va: pointer to current msdu link Desc
  2014. * @next_addr_info: buffer to save next msdu link Desc buffer addr info
  2015. *
  2016. * return: None
  2017. */
  2018. static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info(
  2019. void *link_desc_va,
  2020. struct buffer_addr_info *next_addr_info)
  2021. {
  2022. struct rx_msdu_link *msdu_link = link_desc_va;
  2023. if (!msdu_link) {
  2024. qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info));
  2025. return;
  2026. }
  2027. *next_addr_info = msdu_link->next_msdu_link_desc_addr_info;
  2028. }
  2029. /**
  2030. * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc
  2031. * buffer addr info
  2032. * @link_desc_va: pointer to current msdu link Desc
  2033. *
  2034. * return: None
  2035. */
  2036. static inline
  2037. void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va)
  2038. {
  2039. struct rx_msdu_link *msdu_link = link_desc_va;
  2040. if (msdu_link)
  2041. qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info,
  2042. sizeof(msdu_link->next_msdu_link_desc_addr_info));
  2043. }
  2044. /**
  2045. * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid
  2046. *
  2047. * @buf_addr_info: pointer to buf_addr_info structure
  2048. *
  2049. * return: true: has valid paddr, false: not.
  2050. */
  2051. static inline
  2052. bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info)
  2053. {
  2054. return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ?
  2055. false : true;
  2056. }
  2057. /**
  2058. * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from
  2059. * rx_pkt_tlvs structure
  2060. *
  2061. * @hal_soc_hdl: HAL SOC handle
  2062. * return: msdu_end_tlv offset value
  2063. */
  2064. static inline
  2065. uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  2066. {
  2067. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2068. if (!hal_soc || !hal_soc->ops) {
  2069. hal_err("hal handle is NULL");
  2070. QDF_BUG(0);
  2071. return 0;
  2072. }
  2073. return hal_soc->ops->hal_rx_msdu_end_offset_get();
  2074. }
  2075. /**
  2076. * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from
  2077. * rx_pkt_tlvs structure
  2078. *
  2079. * @hal_soc_hdl: HAL SOC handle
  2080. * return: msdu_start_tlv offset value
  2081. */
  2082. static inline
  2083. uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  2084. {
  2085. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2086. if (!hal_soc || !hal_soc->ops) {
  2087. hal_err("hal handle is NULL");
  2088. QDF_BUG(0);
  2089. return 0;
  2090. }
  2091. return hal_soc->ops->hal_rx_msdu_start_offset_get();
  2092. }
  2093. /**
  2094. * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from
  2095. * rx_pkt_tlvs structure
  2096. *
  2097. * @hal_soc_hdl: HAL SOC handle
  2098. * return: mpdu_start_tlv offset value
  2099. */
  2100. static inline
  2101. uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  2102. {
  2103. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2104. if (!hal_soc || !hal_soc->ops) {
  2105. hal_err("hal handle is NULL");
  2106. QDF_BUG(0);
  2107. return 0;
  2108. }
  2109. return hal_soc->ops->hal_rx_mpdu_start_offset_get();
  2110. }
  2111. static inline
  2112. uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl)
  2113. {
  2114. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2115. if (!hal_soc || !hal_soc->ops) {
  2116. hal_err("hal handle is NULL");
  2117. QDF_BUG(0);
  2118. return 0;
  2119. }
  2120. return hal_soc->ops->hal_rx_pkt_tlv_offset_get();
  2121. }
  2122. /**
  2123. * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from
  2124. * rx_pkt_tlvs structure
  2125. *
  2126. * @hal_soc_hdl: HAL SOC handle
  2127. * return: mpdu_end_tlv offset value
  2128. */
  2129. static inline
  2130. uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  2131. {
  2132. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2133. if (!hal_soc || !hal_soc->ops) {
  2134. hal_err("hal handle is NULL");
  2135. QDF_BUG(0);
  2136. return 0;
  2137. }
  2138. return hal_soc->ops->hal_rx_mpdu_end_offset_get();
  2139. }
  2140. /**
  2141. * hal_rx_attn_offset_get(): Get the ATTENTION offset from
  2142. * rx_pkt_tlvs structure
  2143. *
  2144. * @hal_soc_hdl: HAL SOC handle
  2145. * return: attn_tlv offset value
  2146. */
  2147. static inline
  2148. uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl)
  2149. {
  2150. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2151. if (!hal_soc || !hal_soc->ops) {
  2152. hal_err("hal handle is NULL");
  2153. QDF_BUG(0);
  2154. return 0;
  2155. }
  2156. return hal_soc->ops->hal_rx_attn_offset_get();
  2157. }
  2158. /**
  2159. * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
  2160. * @msdu_details_ptr - Pointer to msdu_details_ptr
  2161. * @hal - pointer to hal_soc
  2162. * Return - Pointer to rx_msdu_desc_info structure.
  2163. *
  2164. */
  2165. static inline
  2166. void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr,
  2167. struct hal_soc *hal_soc)
  2168. {
  2169. return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr(
  2170. msdu_details_ptr);
  2171. }
  2172. static inline void
  2173. hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl,
  2174. uint8_t *buf, uint8_t dbg_level)
  2175. {
  2176. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2177. hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level);
  2178. }
  2179. //TODO - Change the names to not include tlv names
  2180. static inline uint16_t
  2181. hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2182. {
  2183. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2184. return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf);
  2185. }
  2186. static inline uint32_t
  2187. hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2188. {
  2189. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2190. return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf);
  2191. }
  2192. static inline uint32_t
  2193. hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2194. {
  2195. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2196. return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf);
  2197. }
  2198. static inline uint16_t
  2199. hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2200. {
  2201. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2202. return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf);
  2203. }
  2204. static inline int
  2205. hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl,
  2206. uint8_t *rx_pkt_tlv,
  2207. struct hal_offload_info *offload_info)
  2208. {
  2209. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2210. return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv,
  2211. offload_info);
  2212. }
  2213. static inline int
  2214. hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  2215. void *proto_params)
  2216. {
  2217. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2218. return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params);
  2219. }
  2220. static inline int
  2221. hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  2222. uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset)
  2223. {
  2224. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2225. return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf,
  2226. l3_hdr_offset,
  2227. l4_hdr_offset);
  2228. }
  2229. static inline uint32_t
  2230. hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2231. {
  2232. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2233. return hal_soc->ops->hal_rx_tlv_mic_err_get(buf);
  2234. }
  2235. /*
  2236. * hal_rx_tlv_get_pkt_type(): API to get the pkt type
  2237. * from rx_msdu_start
  2238. *
  2239. * @buf: pointer to the start of RX PKT TLV header
  2240. * Return: uint32_t(pkt type)
  2241. */
  2242. static inline uint32_t
  2243. hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2244. {
  2245. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2246. return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf);
  2247. }
  2248. static inline void
  2249. hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl,
  2250. uint8_t *buf, uint64_t *pn_num)
  2251. {
  2252. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2253. hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num);
  2254. }
  2255. static inline uint8_t *
  2256. hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2257. {
  2258. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2259. return hal_soc->ops->hal_rx_pkt_hdr_get(buf);
  2260. }
  2261. static inline uint32_t
  2262. hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2263. {
  2264. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2265. return hal_soc->ops->hal_rx_tlv_sgi_get(buf);
  2266. }
  2267. static inline uint32_t
  2268. hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2269. {
  2270. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2271. return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf);
  2272. }
  2273. static inline uint32_t
  2274. hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2275. {
  2276. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2277. return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf);
  2278. }
  2279. static inline uint32_t
  2280. hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2281. {
  2282. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2283. return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf);
  2284. }
  2285. static inline uint32_t
  2286. hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2287. {
  2288. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2289. return hal_soc->ops->hal_rx_tlv_bw_get(buf);
  2290. }
  2291. static inline uint32_t
  2292. hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl,
  2293. hal_ring_desc_t ring_desc)
  2294. {
  2295. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2296. return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc);
  2297. }
  2298. /**
  2299. * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager"
  2300. * from the BUFFER_ADDR_INFO structure
  2301. * given a REO destination ring descriptor.
  2302. * @ ring_desc: RX(REO/WBM release) destination ring descriptor
  2303. *
  2304. * Return: uint8_t (value of the return_buffer_manager)
  2305. */
  2306. static inline uint8_t
  2307. hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl,
  2308. hal_ring_desc_t ring_desc)
  2309. {
  2310. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2311. return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc);
  2312. }
  2313. /*
  2314. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  2315. * rxdma ring entry.
  2316. * @rxdma_entry: descriptor entry
  2317. * @paddr: physical address of nbuf data pointer.
  2318. * @cookie: SW cookie used as a index to SW rx desc.
  2319. * @manager: who owns the nbuf (host, NSS, etc...).
  2320. *
  2321. */
  2322. static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl,
  2323. void *rxdma_entry,
  2324. qdf_dma_addr_t paddr,
  2325. uint32_t cookie,
  2326. uint8_t manager)
  2327. {
  2328. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2329. return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry,
  2330. paddr,
  2331. cookie,
  2332. manager);
  2333. }
  2334. static inline uint32_t
  2335. hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2336. {
  2337. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2338. return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc);
  2339. }
  2340. static inline void
  2341. hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr,
  2342. uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err)
  2343. {
  2344. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2345. return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr,
  2346. ip_csum_err,
  2347. tcp_udp_csum_err);
  2348. }
  2349. static inline void
  2350. hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl,
  2351. uint8_t *rx_tlv_hdr,
  2352. struct hal_rx_pkt_capture_flags *flags)
  2353. {
  2354. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2355. return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr,
  2356. flags);
  2357. }
  2358. static inline uint8_t
  2359. hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2360. {
  2361. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2362. return hal_soc->ops->hal_rx_err_status_get(rx_desc);
  2363. }
  2364. static inline uint8_t
  2365. hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2366. {
  2367. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2368. return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc);
  2369. }
  2370. /**
  2371. * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit
  2372. * from rx mpdu info
  2373. * @buf: pointer to rx_pkt_tlvs
  2374. *
  2375. * No input validdataion, since this function is supposed to be
  2376. * called from fastpath.
  2377. *
  2378. * Return: ampdu flag
  2379. */
  2380. static inline bool
  2381. hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2382. {
  2383. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2384. return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf);
  2385. }
  2386. #endif /* _HAL_RX_H */