dp_tx.c 144 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  44. #include <dp_swlm.h>
  45. #endif
  46. /* Flag to skip CCE classify when mesh or tid override enabled */
  47. #define DP_TX_SKIP_CCE_CLASSIFY \
  48. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  49. /* TODO Add support in TSO */
  50. #define DP_DESC_NUM_FRAG(x) 0
  51. /* disable TQM_BYPASS */
  52. #define TQM_BYPASS_WAR 0
  53. /* invalid peer id for reinject*/
  54. #define DP_INVALID_PEER 0XFFFE
  55. /*mapping between hal encrypt type and cdp_sec_type*/
  56. #define MAX_CDP_SEC_TYPE 12
  57. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  58. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  59. HAL_TX_ENCRYPT_TYPE_WEP_128,
  60. HAL_TX_ENCRYPT_TYPE_WEP_104,
  61. HAL_TX_ENCRYPT_TYPE_WEP_40,
  62. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  63. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  64. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  65. HAL_TX_ENCRYPT_TYPE_WAPI,
  66. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  67. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  69. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  70. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  71. /**
  72. * dp_update_tx_desc_stats - Update the increase or decrease in
  73. * outstanding tx desc count
  74. * values on pdev and soc
  75. * @vdev: DP pdev handle
  76. *
  77. * Return: void
  78. */
  79. static inline void
  80. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  81. {
  82. int32_t tx_descs_cnt =
  83. qdf_atomic_read(&pdev->num_tx_outstanding);
  84. if (pdev->tx_descs_max < tx_descs_cnt)
  85. pdev->tx_descs_max = tx_descs_cnt;
  86. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  87. pdev->tx_descs_max);
  88. }
  89. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  90. static inline void
  91. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  92. {
  93. }
  94. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  95. #ifdef QCA_TX_LIMIT_CHECK
  96. /**
  97. * dp_tx_limit_check - Check if allocated tx descriptors reached
  98. * soc max limit and pdev max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  110. soc->num_tx_allowed) {
  111. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  112. "%s: queued packets are more than max tx, drop the frame",
  113. __func__);
  114. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  115. return true;
  116. }
  117. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  118. pdev->num_tx_allowed) {
  119. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  120. "%s: queued packets are more than max tx, drop the frame",
  121. __func__);
  122. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  123. return true;
  124. }
  125. return false;
  126. }
  127. /**
  128. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  129. * reached soc max limit
  130. * @vdev: DP vdev handle
  131. *
  132. * Return: true if allocated tx descriptors reached max configured value, else
  133. * false
  134. */
  135. static inline bool
  136. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  137. {
  138. struct dp_pdev *pdev = vdev->pdev;
  139. struct dp_soc *soc = pdev->soc;
  140. if (qdf_atomic_read(&soc->num_tx_exception) >=
  141. soc->num_msdu_exception_desc) {
  142. dp_info("exc packets are more than max drop the exc pkt");
  143. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  144. return true;
  145. }
  146. return false;
  147. }
  148. /**
  149. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  150. * @vdev: DP pdev handle
  151. *
  152. * Return: void
  153. */
  154. static inline void
  155. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  156. {
  157. struct dp_soc *soc = pdev->soc;
  158. qdf_atomic_inc(&pdev->num_tx_outstanding);
  159. qdf_atomic_inc(&soc->num_tx_outstanding);
  160. dp_update_tx_desc_stats(pdev);
  161. }
  162. /**
  163. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  164. * @vdev: DP pdev handle
  165. *
  166. * Return: void
  167. */
  168. static inline void
  169. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  170. {
  171. struct dp_soc *soc = pdev->soc;
  172. qdf_atomic_dec(&pdev->num_tx_outstanding);
  173. qdf_atomic_dec(&soc->num_tx_outstanding);
  174. dp_update_tx_desc_stats(pdev);
  175. }
  176. #else //QCA_TX_LIMIT_CHECK
  177. static inline bool
  178. dp_tx_limit_check(struct dp_vdev *vdev)
  179. {
  180. return false;
  181. }
  182. static inline bool
  183. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  184. {
  185. return false;
  186. }
  187. static inline void
  188. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  189. {
  190. qdf_atomic_inc(&pdev->num_tx_outstanding);
  191. dp_update_tx_desc_stats(pdev);
  192. }
  193. static inline void
  194. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  195. {
  196. qdf_atomic_dec(&pdev->num_tx_outstanding);
  197. dp_update_tx_desc_stats(pdev);
  198. }
  199. #endif //QCA_TX_LIMIT_CHECK
  200. #if defined(FEATURE_TSO)
  201. /**
  202. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  203. *
  204. * @soc - core txrx main context
  205. * @seg_desc - tso segment descriptor
  206. * @num_seg_desc - tso number segment descriptor
  207. */
  208. static void dp_tx_tso_unmap_segment(
  209. struct dp_soc *soc,
  210. struct qdf_tso_seg_elem_t *seg_desc,
  211. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  212. {
  213. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  214. if (qdf_unlikely(!seg_desc)) {
  215. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  216. __func__, __LINE__);
  217. qdf_assert(0);
  218. } else if (qdf_unlikely(!num_seg_desc)) {
  219. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  220. __func__, __LINE__);
  221. qdf_assert(0);
  222. } else {
  223. bool is_last_seg;
  224. /* no tso segment left to do dma unmap */
  225. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  226. return;
  227. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  228. true : false;
  229. qdf_nbuf_unmap_tso_segment(soc->osdev,
  230. seg_desc, is_last_seg);
  231. num_seg_desc->num_seg.tso_cmn_num_seg--;
  232. }
  233. }
  234. /**
  235. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  236. * back to the freelist
  237. *
  238. * @soc - soc device handle
  239. * @tx_desc - Tx software descriptor
  240. */
  241. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  242. struct dp_tx_desc_s *tx_desc)
  243. {
  244. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  245. if (qdf_unlikely(!tx_desc->tso_desc)) {
  246. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  247. "%s %d TSO desc is NULL!",
  248. __func__, __LINE__);
  249. qdf_assert(0);
  250. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  251. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  252. "%s %d TSO num desc is NULL!",
  253. __func__, __LINE__);
  254. qdf_assert(0);
  255. } else {
  256. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  257. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  258. /* Add the tso num segment into the free list */
  259. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  260. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  261. tx_desc->tso_num_desc);
  262. tx_desc->tso_num_desc = NULL;
  263. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  264. }
  265. /* Add the tso segment into the free list*/
  266. dp_tx_tso_desc_free(soc,
  267. tx_desc->pool_id, tx_desc->tso_desc);
  268. tx_desc->tso_desc = NULL;
  269. }
  270. }
  271. #else
  272. static void dp_tx_tso_unmap_segment(
  273. struct dp_soc *soc,
  274. struct qdf_tso_seg_elem_t *seg_desc,
  275. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  276. {
  277. }
  278. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  279. struct dp_tx_desc_s *tx_desc)
  280. {
  281. }
  282. #endif
  283. /**
  284. * dp_tx_desc_release() - Release Tx Descriptor
  285. * @tx_desc : Tx Descriptor
  286. * @desc_pool_id: Descriptor Pool ID
  287. *
  288. * Deallocate all resources attached to Tx descriptor and free the Tx
  289. * descriptor.
  290. *
  291. * Return:
  292. */
  293. static void
  294. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  295. {
  296. struct dp_pdev *pdev = tx_desc->pdev;
  297. struct dp_soc *soc;
  298. uint8_t comp_status = 0;
  299. qdf_assert(pdev);
  300. soc = pdev->soc;
  301. dp_tx_outstanding_dec(pdev);
  302. if (tx_desc->frm_type == dp_tx_frm_tso)
  303. dp_tx_tso_desc_release(soc, tx_desc);
  304. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  305. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  306. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  307. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  308. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  309. qdf_atomic_dec(&soc->num_tx_exception);
  310. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  311. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  312. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  313. soc->hal_soc);
  314. else
  315. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  316. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  317. "Tx Completion Release desc %d status %d outstanding %d",
  318. tx_desc->id, comp_status,
  319. qdf_atomic_read(&pdev->num_tx_outstanding));
  320. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  321. return;
  322. }
  323. /**
  324. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  325. * @vdev: DP vdev Handle
  326. * @nbuf: skb
  327. * @msdu_info: msdu_info required to create HTT metadata
  328. *
  329. * Prepares and fills HTT metadata in the frame pre-header for special frames
  330. * that should be transmitted using varying transmit parameters.
  331. * There are 2 VDEV modes that currently needs this special metadata -
  332. * 1) Mesh Mode
  333. * 2) DSRC Mode
  334. *
  335. * Return: HTT metadata size
  336. *
  337. */
  338. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  339. struct dp_tx_msdu_info_s *msdu_info)
  340. {
  341. uint32_t *meta_data = msdu_info->meta_data;
  342. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  343. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  344. uint8_t htt_desc_size;
  345. /* Size rounded of multiple of 8 bytes */
  346. uint8_t htt_desc_size_aligned;
  347. uint8_t *hdr = NULL;
  348. /*
  349. * Metadata - HTT MSDU Extension header
  350. */
  351. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  352. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  353. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  354. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  355. meta_data[0])) {
  356. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  357. htt_desc_size_aligned)) {
  358. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  359. htt_desc_size_aligned);
  360. if (!nbuf) {
  361. /*
  362. * qdf_nbuf_realloc_headroom won't do skb_clone
  363. * as skb_realloc_headroom does. so, no free is
  364. * needed here.
  365. */
  366. DP_STATS_INC(vdev,
  367. tx_i.dropped.headroom_insufficient,
  368. 1);
  369. qdf_print(" %s[%d] skb_realloc_headroom failed",
  370. __func__, __LINE__);
  371. return 0;
  372. }
  373. }
  374. /* Fill and add HTT metaheader */
  375. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  376. if (!hdr) {
  377. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  378. "Error in filling HTT metadata");
  379. return 0;
  380. }
  381. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  382. } else if (vdev->opmode == wlan_op_mode_ocb) {
  383. /* Todo - Add support for DSRC */
  384. }
  385. return htt_desc_size_aligned;
  386. }
  387. /**
  388. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  389. * @tso_seg: TSO segment to process
  390. * @ext_desc: Pointer to MSDU extension descriptor
  391. *
  392. * Return: void
  393. */
  394. #if defined(FEATURE_TSO)
  395. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  396. void *ext_desc)
  397. {
  398. uint8_t num_frag;
  399. uint32_t tso_flags;
  400. /*
  401. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  402. * tcp_flag_mask
  403. *
  404. * Checksum enable flags are set in TCL descriptor and not in Extension
  405. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  406. */
  407. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  408. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  409. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  410. tso_seg->tso_flags.ip_len);
  411. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  412. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  413. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  414. uint32_t lo = 0;
  415. uint32_t hi = 0;
  416. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  417. (tso_seg->tso_frags[num_frag].length));
  418. qdf_dmaaddr_to_32s(
  419. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  420. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  421. tso_seg->tso_frags[num_frag].length);
  422. }
  423. return;
  424. }
  425. #else
  426. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  427. void *ext_desc)
  428. {
  429. return;
  430. }
  431. #endif
  432. #if defined(FEATURE_TSO)
  433. /**
  434. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  435. * allocated and free them
  436. *
  437. * @soc: soc handle
  438. * @free_seg: list of tso segments
  439. * @msdu_info: msdu descriptor
  440. *
  441. * Return - void
  442. */
  443. static void dp_tx_free_tso_seg_list(
  444. struct dp_soc *soc,
  445. struct qdf_tso_seg_elem_t *free_seg,
  446. struct dp_tx_msdu_info_s *msdu_info)
  447. {
  448. struct qdf_tso_seg_elem_t *next_seg;
  449. while (free_seg) {
  450. next_seg = free_seg->next;
  451. dp_tx_tso_desc_free(soc,
  452. msdu_info->tx_queue.desc_pool_id,
  453. free_seg);
  454. free_seg = next_seg;
  455. }
  456. }
  457. /**
  458. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  459. * allocated and free them
  460. *
  461. * @soc: soc handle
  462. * @free_num_seg: list of tso number segments
  463. * @msdu_info: msdu descriptor
  464. * Return - void
  465. */
  466. static void dp_tx_free_tso_num_seg_list(
  467. struct dp_soc *soc,
  468. struct qdf_tso_num_seg_elem_t *free_num_seg,
  469. struct dp_tx_msdu_info_s *msdu_info)
  470. {
  471. struct qdf_tso_num_seg_elem_t *next_num_seg;
  472. while (free_num_seg) {
  473. next_num_seg = free_num_seg->next;
  474. dp_tso_num_seg_free(soc,
  475. msdu_info->tx_queue.desc_pool_id,
  476. free_num_seg);
  477. free_num_seg = next_num_seg;
  478. }
  479. }
  480. /**
  481. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  482. * do dma unmap for each segment
  483. *
  484. * @soc: soc handle
  485. * @free_seg: list of tso segments
  486. * @num_seg_desc: tso number segment descriptor
  487. *
  488. * Return - void
  489. */
  490. static void dp_tx_unmap_tso_seg_list(
  491. struct dp_soc *soc,
  492. struct qdf_tso_seg_elem_t *free_seg,
  493. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  494. {
  495. struct qdf_tso_seg_elem_t *next_seg;
  496. if (qdf_unlikely(!num_seg_desc)) {
  497. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  498. return;
  499. }
  500. while (free_seg) {
  501. next_seg = free_seg->next;
  502. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  503. free_seg = next_seg;
  504. }
  505. }
  506. #ifdef FEATURE_TSO_STATS
  507. /**
  508. * dp_tso_get_stats_idx: Retrieve the tso packet id
  509. * @pdev - pdev handle
  510. *
  511. * Return: id
  512. */
  513. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  514. {
  515. uint32_t stats_idx;
  516. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  517. % CDP_MAX_TSO_PACKETS);
  518. return stats_idx;
  519. }
  520. #else
  521. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  522. {
  523. return 0;
  524. }
  525. #endif /* FEATURE_TSO_STATS */
  526. /**
  527. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  528. * free the tso segments descriptor and
  529. * tso num segments descriptor
  530. *
  531. * @soc: soc handle
  532. * @msdu_info: msdu descriptor
  533. * @tso_seg_unmap: flag to show if dma unmap is necessary
  534. *
  535. * Return - void
  536. */
  537. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  538. struct dp_tx_msdu_info_s *msdu_info,
  539. bool tso_seg_unmap)
  540. {
  541. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  542. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  543. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  544. tso_info->tso_num_seg_list;
  545. /* do dma unmap for each segment */
  546. if (tso_seg_unmap)
  547. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  548. /* free all tso number segment descriptor though looks only have 1 */
  549. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  550. /* free all tso segment descriptor */
  551. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  552. }
  553. /**
  554. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  555. * @vdev: virtual device handle
  556. * @msdu: network buffer
  557. * @msdu_info: meta data associated with the msdu
  558. *
  559. * Return: QDF_STATUS_SUCCESS success
  560. */
  561. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  562. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  563. {
  564. struct qdf_tso_seg_elem_t *tso_seg;
  565. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  566. struct dp_soc *soc = vdev->pdev->soc;
  567. struct dp_pdev *pdev = vdev->pdev;
  568. struct qdf_tso_info_t *tso_info;
  569. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  570. tso_info = &msdu_info->u.tso_info;
  571. tso_info->curr_seg = NULL;
  572. tso_info->tso_seg_list = NULL;
  573. tso_info->num_segs = num_seg;
  574. msdu_info->frm_type = dp_tx_frm_tso;
  575. tso_info->tso_num_seg_list = NULL;
  576. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  577. while (num_seg) {
  578. tso_seg = dp_tx_tso_desc_alloc(
  579. soc, msdu_info->tx_queue.desc_pool_id);
  580. if (tso_seg) {
  581. tso_seg->next = tso_info->tso_seg_list;
  582. tso_info->tso_seg_list = tso_seg;
  583. num_seg--;
  584. } else {
  585. dp_err_rl("Failed to alloc tso seg desc");
  586. DP_STATS_INC_PKT(vdev->pdev,
  587. tso_stats.tso_no_mem_dropped, 1,
  588. qdf_nbuf_len(msdu));
  589. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  590. return QDF_STATUS_E_NOMEM;
  591. }
  592. }
  593. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  594. tso_num_seg = dp_tso_num_seg_alloc(soc,
  595. msdu_info->tx_queue.desc_pool_id);
  596. if (tso_num_seg) {
  597. tso_num_seg->next = tso_info->tso_num_seg_list;
  598. tso_info->tso_num_seg_list = tso_num_seg;
  599. } else {
  600. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  601. __func__);
  602. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  603. return QDF_STATUS_E_NOMEM;
  604. }
  605. msdu_info->num_seg =
  606. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  607. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  608. msdu_info->num_seg);
  609. if (!(msdu_info->num_seg)) {
  610. /*
  611. * Free allocated TSO seg desc and number seg desc,
  612. * do unmap for segments if dma map has done.
  613. */
  614. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  615. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  616. return QDF_STATUS_E_INVAL;
  617. }
  618. tso_info->curr_seg = tso_info->tso_seg_list;
  619. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  620. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  621. msdu, msdu_info->num_seg);
  622. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  623. tso_info->msdu_stats_idx);
  624. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  625. return QDF_STATUS_SUCCESS;
  626. }
  627. #else
  628. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  629. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  630. {
  631. return QDF_STATUS_E_NOMEM;
  632. }
  633. #endif
  634. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  635. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  636. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  637. /**
  638. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  639. * @vdev: DP Vdev handle
  640. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  641. * @desc_pool_id: Descriptor Pool ID
  642. *
  643. * Return:
  644. */
  645. static
  646. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  647. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  648. {
  649. uint8_t i;
  650. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  651. struct dp_tx_seg_info_s *seg_info;
  652. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  653. struct dp_soc *soc = vdev->pdev->soc;
  654. /* Allocate an extension descriptor */
  655. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  656. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  657. if (!msdu_ext_desc) {
  658. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  659. return NULL;
  660. }
  661. if (msdu_info->exception_fw &&
  662. qdf_unlikely(vdev->mesh_vdev)) {
  663. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  664. &msdu_info->meta_data[0],
  665. sizeof(struct htt_tx_msdu_desc_ext2_t));
  666. qdf_atomic_inc(&soc->num_tx_exception);
  667. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  668. }
  669. switch (msdu_info->frm_type) {
  670. case dp_tx_frm_sg:
  671. case dp_tx_frm_me:
  672. case dp_tx_frm_raw:
  673. seg_info = msdu_info->u.sg_info.curr_seg;
  674. /* Update the buffer pointers in MSDU Extension Descriptor */
  675. for (i = 0; i < seg_info->frag_cnt; i++) {
  676. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  677. seg_info->frags[i].paddr_lo,
  678. seg_info->frags[i].paddr_hi,
  679. seg_info->frags[i].len);
  680. }
  681. break;
  682. case dp_tx_frm_tso:
  683. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  684. &cached_ext_desc[0]);
  685. break;
  686. default:
  687. break;
  688. }
  689. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  690. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  691. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  692. msdu_ext_desc->vaddr);
  693. return msdu_ext_desc;
  694. }
  695. /**
  696. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  697. *
  698. * @skb: skb to be traced
  699. * @msdu_id: msdu_id of the packet
  700. * @vdev_id: vdev_id of the packet
  701. *
  702. * Return: None
  703. */
  704. #ifdef DP_DISABLE_TX_PKT_TRACE
  705. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  706. uint8_t vdev_id)
  707. {
  708. }
  709. #else
  710. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  711. uint8_t vdev_id)
  712. {
  713. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  714. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  715. DPTRACE(qdf_dp_trace_ptr(skb,
  716. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  717. QDF_TRACE_DEFAULT_PDEV_ID,
  718. qdf_nbuf_data_addr(skb),
  719. sizeof(qdf_nbuf_data(skb)),
  720. msdu_id, vdev_id, 0));
  721. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  722. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  723. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  724. msdu_id, QDF_TX));
  725. }
  726. #endif
  727. #ifdef QCA_SUPPORT_WDS_EXTENDED
  728. /**
  729. * dp_is_tx_extended() - Configure AST override from peer ast entry
  730. *
  731. * @vdev: DP vdev handle
  732. * @tx_exc_metadata: Handle that holds exception path metadata
  733. *
  734. * Return: if this packet needs to exception to FW or not
  735. * (false: exception to wlan FW, true: do not exception)
  736. */
  737. static inline bool
  738. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  739. *tx_exc_metadata)
  740. {
  741. if (qdf_likely(!vdev->wds_ext_enabled))
  742. return false;
  743. if (tx_exc_metadata && !tx_exc_metadata->is_wds_extended)
  744. return false;
  745. return true;
  746. }
  747. /**
  748. * dp_tx_wds_ext() - Configure AST override from peer ast entry
  749. *
  750. * @soc: DP soc handle
  751. * @vdev: DP vdev handle
  752. * @peer_id: peer_id of the peer for which packet is destined
  753. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  754. *
  755. * Return: None
  756. */
  757. static inline void
  758. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  759. struct dp_tx_msdu_info_s *msdu_info)
  760. {
  761. struct dp_peer *peer = NULL;
  762. msdu_info->search_type = vdev->search_type;
  763. msdu_info->ast_idx = vdev->bss_ast_idx;
  764. msdu_info->ast_hash = vdev->bss_ast_hash;
  765. if (qdf_likely(!vdev->wds_ext_enabled))
  766. return;
  767. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_TX);
  768. if (qdf_unlikely(!peer))
  769. return;
  770. msdu_info->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  771. msdu_info->ast_idx = peer->self_ast_entry->ast_idx;
  772. msdu_info->ast_hash = peer->self_ast_entry->ast_hash_value;
  773. dp_peer_unref_delete(peer, DP_MOD_ID_TX);
  774. msdu_info->exception_fw = 0;
  775. }
  776. #else
  777. static inline bool
  778. dp_is_tx_extended(struct dp_vdev *vdev, struct cdp_tx_exception_metadata
  779. *tx_exc_metadata)
  780. {
  781. return false;
  782. }
  783. static inline void
  784. dp_tx_wds_ext(struct dp_soc *soc, struct dp_vdev *vdev, uint16_t peer_id,
  785. struct dp_tx_msdu_info_s *msdu_info)
  786. {
  787. msdu_info->search_type = vdev->search_type;
  788. msdu_info->ast_idx = vdev->bss_ast_idx;
  789. msdu_info->ast_hash = vdev->bss_ast_hash;
  790. }
  791. #endif
  792. /**
  793. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  794. * @vdev: DP vdev handle
  795. * @nbuf: skb
  796. * @desc_pool_id: Descriptor pool ID
  797. * @meta_data: Metadata to the fw
  798. * @tx_exc_metadata: Handle that holds exception path metadata
  799. * Allocate and prepare Tx descriptor with msdu information.
  800. *
  801. * Return: Pointer to Tx Descriptor on success,
  802. * NULL on failure
  803. */
  804. static
  805. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  806. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  807. struct dp_tx_msdu_info_s *msdu_info,
  808. struct cdp_tx_exception_metadata *tx_exc_metadata)
  809. {
  810. uint8_t align_pad;
  811. uint8_t is_exception = 0;
  812. uint8_t htt_hdr_size;
  813. struct dp_tx_desc_s *tx_desc;
  814. struct dp_pdev *pdev = vdev->pdev;
  815. struct dp_soc *soc = pdev->soc;
  816. if (dp_tx_limit_check(vdev))
  817. return NULL;
  818. /* Allocate software Tx descriptor */
  819. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  820. if (qdf_unlikely(!tx_desc)) {
  821. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  822. return NULL;
  823. }
  824. dp_tx_outstanding_inc(pdev);
  825. /* Initialize the SW tx descriptor */
  826. tx_desc->nbuf = nbuf;
  827. tx_desc->frm_type = dp_tx_frm_std;
  828. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  829. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  830. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  831. tx_desc->vdev_id = vdev->vdev_id;
  832. tx_desc->pdev = pdev;
  833. tx_desc->msdu_ext_desc = NULL;
  834. tx_desc->pkt_offset = 0;
  835. tx_desc->length = qdf_nbuf_headlen(nbuf);
  836. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  837. if (qdf_unlikely(vdev->multipass_en)) {
  838. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  839. goto failure;
  840. }
  841. if (qdf_unlikely(dp_is_tx_extended(vdev, tx_exc_metadata)))
  842. return tx_desc;
  843. /*
  844. * For special modes (vdev_type == ocb or mesh), data frames should be
  845. * transmitted using varying transmit parameters (tx spec) which include
  846. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  847. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  848. * These frames are sent as exception packets to firmware.
  849. *
  850. * HW requirement is that metadata should always point to a
  851. * 8-byte aligned address. So we add alignment pad to start of buffer.
  852. * HTT Metadata should be ensured to be multiple of 8-bytes,
  853. * to get 8-byte aligned start address along with align_pad added
  854. *
  855. * |-----------------------------|
  856. * | |
  857. * |-----------------------------| <-----Buffer Pointer Address given
  858. * | | ^ in HW descriptor (aligned)
  859. * | HTT Metadata | |
  860. * | | |
  861. * | | | Packet Offset given in descriptor
  862. * | | |
  863. * |-----------------------------| |
  864. * | Alignment Pad | v
  865. * |-----------------------------| <----- Actual buffer start address
  866. * | SKB Data | (Unaligned)
  867. * | |
  868. * | |
  869. * | |
  870. * | |
  871. * | |
  872. * |-----------------------------|
  873. */
  874. if (qdf_unlikely((msdu_info->exception_fw)) ||
  875. (vdev->opmode == wlan_op_mode_ocb) ||
  876. (tx_exc_metadata &&
  877. tx_exc_metadata->is_tx_sniffer)) {
  878. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  879. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  880. DP_STATS_INC(vdev,
  881. tx_i.dropped.headroom_insufficient, 1);
  882. goto failure;
  883. }
  884. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  885. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  886. "qdf_nbuf_push_head failed");
  887. goto failure;
  888. }
  889. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  890. msdu_info);
  891. if (htt_hdr_size == 0)
  892. goto failure;
  893. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  894. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  895. is_exception = 1;
  896. tx_desc->length -= tx_desc->pkt_offset;
  897. }
  898. #if !TQM_BYPASS_WAR
  899. if (is_exception || tx_exc_metadata)
  900. #endif
  901. {
  902. /* Temporary WAR due to TQM VP issues */
  903. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  904. qdf_atomic_inc(&soc->num_tx_exception);
  905. }
  906. return tx_desc;
  907. failure:
  908. dp_tx_desc_release(tx_desc, desc_pool_id);
  909. return NULL;
  910. }
  911. /**
  912. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  913. * @vdev: DP vdev handle
  914. * @nbuf: skb
  915. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  916. * @desc_pool_id : Descriptor Pool ID
  917. *
  918. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  919. * information. For frames wth fragments, allocate and prepare
  920. * an MSDU extension descriptor
  921. *
  922. * Return: Pointer to Tx Descriptor on success,
  923. * NULL on failure
  924. */
  925. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  926. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  927. uint8_t desc_pool_id)
  928. {
  929. struct dp_tx_desc_s *tx_desc;
  930. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  931. struct dp_pdev *pdev = vdev->pdev;
  932. struct dp_soc *soc = pdev->soc;
  933. if (dp_tx_limit_check(vdev))
  934. return NULL;
  935. /* Allocate software Tx descriptor */
  936. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  937. if (!tx_desc) {
  938. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  939. return NULL;
  940. }
  941. dp_tx_outstanding_inc(pdev);
  942. /* Initialize the SW tx descriptor */
  943. tx_desc->nbuf = nbuf;
  944. tx_desc->frm_type = msdu_info->frm_type;
  945. tx_desc->tx_encap_type = vdev->tx_encap_type;
  946. tx_desc->vdev_id = vdev->vdev_id;
  947. tx_desc->pdev = pdev;
  948. tx_desc->pkt_offset = 0;
  949. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  950. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  951. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  952. /* Handle scattered frames - TSO/SG/ME */
  953. /* Allocate and prepare an extension descriptor for scattered frames */
  954. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  955. if (!msdu_ext_desc) {
  956. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  957. "%s Tx Extension Descriptor Alloc Fail",
  958. __func__);
  959. goto failure;
  960. }
  961. #if TQM_BYPASS_WAR
  962. /* Temporary WAR due to TQM VP issues */
  963. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  964. qdf_atomic_inc(&soc->num_tx_exception);
  965. #endif
  966. if (qdf_unlikely(msdu_info->exception_fw))
  967. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  968. tx_desc->msdu_ext_desc = msdu_ext_desc;
  969. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  970. tx_desc->dma_addr = msdu_ext_desc->paddr;
  971. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  972. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  973. else
  974. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  975. return tx_desc;
  976. failure:
  977. dp_tx_desc_release(tx_desc, desc_pool_id);
  978. return NULL;
  979. }
  980. /**
  981. * dp_tx_prepare_raw() - Prepare RAW packet TX
  982. * @vdev: DP vdev handle
  983. * @nbuf: buffer pointer
  984. * @seg_info: Pointer to Segment info Descriptor to be prepared
  985. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  986. * descriptor
  987. *
  988. * Return:
  989. */
  990. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  991. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  992. {
  993. qdf_nbuf_t curr_nbuf = NULL;
  994. uint16_t total_len = 0;
  995. qdf_dma_addr_t paddr;
  996. int32_t i;
  997. int32_t mapped_buf_num = 0;
  998. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  999. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1000. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1001. /* Continue only if frames are of DATA type */
  1002. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1003. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1004. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1005. "Pkt. recd is of not data type");
  1006. goto error;
  1007. }
  1008. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1009. if (vdev->raw_mode_war &&
  1010. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1011. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1012. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1013. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1014. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1015. /*
  1016. * Number of nbuf's must not exceed the size of the frags
  1017. * array in seg_info.
  1018. */
  1019. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1020. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1021. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1022. goto error;
  1023. }
  1024. if (QDF_STATUS_SUCCESS !=
  1025. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1026. curr_nbuf,
  1027. QDF_DMA_TO_DEVICE,
  1028. curr_nbuf->len)) {
  1029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1030. "%s dma map error ", __func__);
  1031. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1032. goto error;
  1033. }
  1034. /* Update the count of mapped nbuf's */
  1035. mapped_buf_num++;
  1036. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1037. seg_info->frags[i].paddr_lo = paddr;
  1038. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1039. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1040. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1041. total_len += qdf_nbuf_len(curr_nbuf);
  1042. }
  1043. seg_info->frag_cnt = i;
  1044. seg_info->total_len = total_len;
  1045. seg_info->next = NULL;
  1046. sg_info->curr_seg = seg_info;
  1047. msdu_info->frm_type = dp_tx_frm_raw;
  1048. msdu_info->num_seg = 1;
  1049. return nbuf;
  1050. error:
  1051. i = 0;
  1052. while (nbuf) {
  1053. curr_nbuf = nbuf;
  1054. if (i < mapped_buf_num) {
  1055. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1056. QDF_DMA_TO_DEVICE,
  1057. curr_nbuf->len);
  1058. i++;
  1059. }
  1060. nbuf = qdf_nbuf_next(nbuf);
  1061. qdf_nbuf_free(curr_nbuf);
  1062. }
  1063. return NULL;
  1064. }
  1065. /**
  1066. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1067. * @soc: DP soc handle
  1068. * @nbuf: Buffer pointer
  1069. *
  1070. * unmap the chain of nbufs that belong to this RAW frame.
  1071. *
  1072. * Return: None
  1073. */
  1074. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1075. qdf_nbuf_t nbuf)
  1076. {
  1077. qdf_nbuf_t cur_nbuf = nbuf;
  1078. do {
  1079. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1080. QDF_DMA_TO_DEVICE,
  1081. cur_nbuf->len);
  1082. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1083. } while (cur_nbuf);
  1084. }
  1085. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1086. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  1087. { \
  1088. qdf_nbuf_t nbuf_local; \
  1089. struct dp_vdev *vdev_local = vdev_hdl; \
  1090. do { \
  1091. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  1092. break; \
  1093. nbuf_local = nbuf; \
  1094. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  1095. htt_cmn_pkt_type_raw)) \
  1096. break; \
  1097. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  1098. break; \
  1099. else if (qdf_nbuf_is_tso((nbuf_local))) \
  1100. break; \
  1101. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  1102. (nbuf_local), \
  1103. NULL, 1, 0); \
  1104. } while (0); \
  1105. }
  1106. #else
  1107. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  1108. #endif
  1109. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1110. /**
  1111. * dp_tx_update_stats() - Update soc level tx stats
  1112. * @soc: DP soc handle
  1113. * @nbuf: packet being transmitted
  1114. *
  1115. * Returns: none
  1116. */
  1117. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1118. qdf_nbuf_t nbuf)
  1119. {
  1120. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1121. }
  1122. /**
  1123. * dp_tx_attempt_coalescing() - Check and attempt TCL register write coalescing
  1124. * @soc: Datapath soc handle
  1125. * @tx_desc: tx packet descriptor
  1126. * @tid: TID for pkt transmission
  1127. *
  1128. * Returns: 1, if coalescing is to be done
  1129. * 0, if coalescing is not to be done
  1130. */
  1131. static inline int
  1132. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1133. struct dp_tx_desc_s *tx_desc,
  1134. uint8_t tid)
  1135. {
  1136. struct dp_swlm *swlm = &soc->swlm;
  1137. union swlm_data swlm_query_data;
  1138. struct dp_swlm_tcl_data tcl_data;
  1139. QDF_STATUS status;
  1140. int ret;
  1141. if (qdf_unlikely(!swlm->is_enabled))
  1142. return 0;
  1143. tcl_data.nbuf = tx_desc->nbuf;
  1144. tcl_data.tid = tid;
  1145. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1146. swlm_query_data.tcl_data = &tcl_data;
  1147. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1148. if (QDF_IS_STATUS_ERROR(status)) {
  1149. dp_swlm_tcl_reset_session_data(soc);
  1150. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1151. return 0;
  1152. }
  1153. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1154. if (ret) {
  1155. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1156. } else {
  1157. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1158. }
  1159. return ret;
  1160. }
  1161. /**
  1162. * dp_tx_ring_access_end() - HAL ring access end for data transmission
  1163. * @soc: Datapath soc handle
  1164. * @hal_ring_hdl: HAL ring handle
  1165. * @coalesce: Coalesce the current write or not
  1166. *
  1167. * Returns: none
  1168. */
  1169. static inline void
  1170. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1171. int coalesce)
  1172. {
  1173. if (coalesce)
  1174. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1175. else
  1176. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1177. }
  1178. #else
  1179. static inline void dp_tx_update_stats(struct dp_soc *soc,
  1180. qdf_nbuf_t nbuf)
  1181. {
  1182. }
  1183. static inline int
  1184. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1185. struct dp_tx_desc_s *tx_desc,
  1186. uint8_t tid)
  1187. {
  1188. return 0;
  1189. }
  1190. static inline void
  1191. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1192. int coalesce)
  1193. {
  1194. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1195. }
  1196. #endif
  1197. /**
  1198. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  1199. * @soc: DP Soc Handle
  1200. * @vdev: DP vdev handle
  1201. * @tx_desc: Tx Descriptor Handle
  1202. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1203. * @fw_metadata: Metadata to send to Target Firmware along with frame
  1204. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  1205. * @tx_exc_metadata: Handle that holds exception path meta data
  1206. *
  1207. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1208. * from software Tx descriptor
  1209. *
  1210. * Return: QDF_STATUS_SUCCESS: success
  1211. * QDF_STATUS_E_RESOURCES: Error return
  1212. */
  1213. static QDF_STATUS
  1214. dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1215. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  1216. struct cdp_tx_exception_metadata *tx_exc_metadata,
  1217. struct dp_tx_msdu_info_s *msdu_info)
  1218. {
  1219. void *hal_tx_desc;
  1220. uint32_t *hal_tx_desc_cached;
  1221. int coalesce = 0;
  1222. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1223. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  1224. uint8_t tid = msdu_info->tid;
  1225. /*
  1226. * Setting it initialization statically here to avoid
  1227. * a memset call jump with qdf_mem_set call
  1228. */
  1229. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1230. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1231. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1232. tx_exc_metadata->sec_type : vdev->sec_type);
  1233. /* Return Buffer Manager ID */
  1234. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1235. hal_ring_handle_t hal_ring_hdl = NULL;
  1236. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1237. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1238. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1239. return QDF_STATUS_E_RESOURCES;
  1240. }
  1241. hal_tx_desc_cached = (void *) cached_desc;
  1242. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1243. tx_desc->dma_addr, bm_id, tx_desc->id,
  1244. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  1245. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1246. vdev->lmac_id);
  1247. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1248. msdu_info->search_type);
  1249. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1250. msdu_info->ast_idx);
  1251. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1252. vdev->dscp_tid_map_id);
  1253. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1254. sec_type_map[sec_type]);
  1255. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1256. (msdu_info->ast_hash & 0xF));
  1257. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1258. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1259. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1260. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1261. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1262. vdev->hal_desc_addr_search_flags);
  1263. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1264. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1265. /* verify checksum offload configuration*/
  1266. if (vdev->csum_enabled &&
  1267. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1268. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1269. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1270. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1271. }
  1272. if (tid != HTT_TX_EXT_TID_INVALID)
  1273. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1274. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1275. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1276. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1277. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1278. soc->wlan_cfg_ctx)))
  1279. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1280. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1281. tx_desc->length,
  1282. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  1283. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  1284. tx_desc->id);
  1285. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1286. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1287. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1288. "%s %d : HAL RING Access Failed -- %pK",
  1289. __func__, __LINE__, hal_ring_hdl);
  1290. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1291. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1292. return status;
  1293. }
  1294. /* Sync cached descriptor with HW */
  1295. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1296. if (qdf_unlikely(!hal_tx_desc)) {
  1297. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1298. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1299. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1300. goto ring_access_fail;
  1301. }
  1302. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1303. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1304. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1305. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid);
  1306. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1307. dp_tx_update_stats(soc, tx_desc->nbuf);
  1308. status = QDF_STATUS_SUCCESS;
  1309. ring_access_fail:
  1310. if (hif_pm_runtime_get(soc->hif_handle,
  1311. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1312. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1313. hif_pm_runtime_put(soc->hif_handle,
  1314. RTPM_ID_DW_TX_HW_ENQUEUE);
  1315. } else {
  1316. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1317. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1318. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1319. }
  1320. return status;
  1321. }
  1322. /**
  1323. * dp_cce_classify() - Classify the frame based on CCE rules
  1324. * @vdev: DP vdev handle
  1325. * @nbuf: skb
  1326. *
  1327. * Classify frames based on CCE rules
  1328. * Return: bool( true if classified,
  1329. * else false)
  1330. */
  1331. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1332. {
  1333. qdf_ether_header_t *eh = NULL;
  1334. uint16_t ether_type;
  1335. qdf_llc_t *llcHdr;
  1336. qdf_nbuf_t nbuf_clone = NULL;
  1337. qdf_dot3_qosframe_t *qos_wh = NULL;
  1338. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1339. /*
  1340. * In case of mesh packets or hlos tid override enabled,
  1341. * don't do any classification
  1342. */
  1343. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1344. & DP_TX_SKIP_CCE_CLASSIFY))
  1345. return false;
  1346. }
  1347. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1348. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1349. ether_type = eh->ether_type;
  1350. llcHdr = (qdf_llc_t *)(nbuf->data +
  1351. sizeof(qdf_ether_header_t));
  1352. } else {
  1353. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1354. /* For encrypted packets don't do any classification */
  1355. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1356. return false;
  1357. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1358. if (qdf_unlikely(
  1359. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1360. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1361. ether_type = *(uint16_t *)(nbuf->data
  1362. + QDF_IEEE80211_4ADDR_HDR_LEN
  1363. + sizeof(qdf_llc_t)
  1364. - sizeof(ether_type));
  1365. llcHdr = (qdf_llc_t *)(nbuf->data +
  1366. QDF_IEEE80211_4ADDR_HDR_LEN);
  1367. } else {
  1368. ether_type = *(uint16_t *)(nbuf->data
  1369. + QDF_IEEE80211_3ADDR_HDR_LEN
  1370. + sizeof(qdf_llc_t)
  1371. - sizeof(ether_type));
  1372. llcHdr = (qdf_llc_t *)(nbuf->data +
  1373. QDF_IEEE80211_3ADDR_HDR_LEN);
  1374. }
  1375. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1376. && (ether_type ==
  1377. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1378. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1379. return true;
  1380. }
  1381. }
  1382. return false;
  1383. }
  1384. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1385. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1386. sizeof(*llcHdr));
  1387. nbuf_clone = qdf_nbuf_clone(nbuf);
  1388. if (qdf_unlikely(nbuf_clone)) {
  1389. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1390. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1391. qdf_nbuf_pull_head(nbuf_clone,
  1392. sizeof(qdf_net_vlanhdr_t));
  1393. }
  1394. }
  1395. } else {
  1396. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1397. nbuf_clone = qdf_nbuf_clone(nbuf);
  1398. if (qdf_unlikely(nbuf_clone)) {
  1399. qdf_nbuf_pull_head(nbuf_clone,
  1400. sizeof(qdf_net_vlanhdr_t));
  1401. }
  1402. }
  1403. }
  1404. if (qdf_unlikely(nbuf_clone))
  1405. nbuf = nbuf_clone;
  1406. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1407. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1408. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1409. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1410. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1411. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1412. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1413. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1414. if (qdf_unlikely(nbuf_clone))
  1415. qdf_nbuf_free(nbuf_clone);
  1416. return true;
  1417. }
  1418. if (qdf_unlikely(nbuf_clone))
  1419. qdf_nbuf_free(nbuf_clone);
  1420. return false;
  1421. }
  1422. /**
  1423. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1424. * @vdev: DP vdev handle
  1425. * @nbuf: skb
  1426. *
  1427. * Extract the DSCP or PCP information from frame and map into TID value.
  1428. *
  1429. * Return: void
  1430. */
  1431. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1432. struct dp_tx_msdu_info_s *msdu_info)
  1433. {
  1434. uint8_t tos = 0, dscp_tid_override = 0;
  1435. uint8_t *hdr_ptr, *L3datap;
  1436. uint8_t is_mcast = 0;
  1437. qdf_ether_header_t *eh = NULL;
  1438. qdf_ethervlan_header_t *evh = NULL;
  1439. uint16_t ether_type;
  1440. qdf_llc_t *llcHdr;
  1441. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1442. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1443. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1444. eh = (qdf_ether_header_t *)nbuf->data;
  1445. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1446. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1447. } else {
  1448. qdf_dot3_qosframe_t *qos_wh =
  1449. (qdf_dot3_qosframe_t *) nbuf->data;
  1450. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1451. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1452. return;
  1453. }
  1454. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1455. ether_type = eh->ether_type;
  1456. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1457. /*
  1458. * Check if packet is dot3 or eth2 type.
  1459. */
  1460. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1461. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1462. sizeof(*llcHdr));
  1463. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1464. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1465. sizeof(*llcHdr);
  1466. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1467. + sizeof(*llcHdr) +
  1468. sizeof(qdf_net_vlanhdr_t));
  1469. } else {
  1470. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1471. sizeof(*llcHdr);
  1472. }
  1473. } else {
  1474. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1475. evh = (qdf_ethervlan_header_t *) eh;
  1476. ether_type = evh->ether_type;
  1477. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1478. }
  1479. }
  1480. /*
  1481. * Find priority from IP TOS DSCP field
  1482. */
  1483. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1484. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1485. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1486. /* Only for unicast frames */
  1487. if (!is_mcast) {
  1488. /* send it on VO queue */
  1489. msdu_info->tid = DP_VO_TID;
  1490. }
  1491. } else {
  1492. /*
  1493. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1494. * from TOS byte.
  1495. */
  1496. tos = ip->ip_tos;
  1497. dscp_tid_override = 1;
  1498. }
  1499. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1500. /* TODO
  1501. * use flowlabel
  1502. *igmpmld cases to be handled in phase 2
  1503. */
  1504. unsigned long ver_pri_flowlabel;
  1505. unsigned long pri;
  1506. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1507. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1508. DP_IPV6_PRIORITY_SHIFT;
  1509. tos = pri;
  1510. dscp_tid_override = 1;
  1511. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1512. msdu_info->tid = DP_VO_TID;
  1513. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1514. /* Only for unicast frames */
  1515. if (!is_mcast) {
  1516. /* send ucast arp on VO queue */
  1517. msdu_info->tid = DP_VO_TID;
  1518. }
  1519. }
  1520. /*
  1521. * Assign all MCAST packets to BE
  1522. */
  1523. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1524. if (is_mcast) {
  1525. tos = 0;
  1526. dscp_tid_override = 1;
  1527. }
  1528. }
  1529. if (dscp_tid_override == 1) {
  1530. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1531. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1532. }
  1533. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1534. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1535. return;
  1536. }
  1537. /**
  1538. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1539. * @vdev: DP vdev handle
  1540. * @nbuf: skb
  1541. *
  1542. * Software based TID classification is required when more than 2 DSCP-TID
  1543. * mapping tables are needed.
  1544. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1545. *
  1546. * Return: void
  1547. */
  1548. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1549. struct dp_tx_msdu_info_s *msdu_info)
  1550. {
  1551. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1552. /*
  1553. * skip_sw_tid_classification flag will set in below cases-
  1554. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1555. * 2. hlos_tid_override enabled for vdev
  1556. * 3. mesh mode enabled for vdev
  1557. */
  1558. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1559. /* Update tid in msdu_info from skb priority */
  1560. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1561. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1562. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1563. return;
  1564. }
  1565. return;
  1566. }
  1567. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1568. }
  1569. #ifdef FEATURE_WLAN_TDLS
  1570. /**
  1571. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1572. * @soc: datapath SOC
  1573. * @vdev: datapath vdev
  1574. * @tx_desc: TX descriptor
  1575. *
  1576. * Return: None
  1577. */
  1578. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1579. struct dp_vdev *vdev,
  1580. struct dp_tx_desc_s *tx_desc)
  1581. {
  1582. if (vdev) {
  1583. if (vdev->is_tdls_frame) {
  1584. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1585. vdev->is_tdls_frame = false;
  1586. }
  1587. }
  1588. }
  1589. /**
  1590. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1591. * @soc: dp_soc handle
  1592. * @tx_desc: TX descriptor
  1593. * @vdev: datapath vdev handle
  1594. *
  1595. * Return: None
  1596. */
  1597. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1598. struct dp_tx_desc_s *tx_desc)
  1599. {
  1600. struct hal_tx_completion_status ts = {0};
  1601. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1602. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1603. DP_MOD_ID_TDLS);
  1604. if (qdf_unlikely(!vdev)) {
  1605. dp_err_rl("vdev is null!");
  1606. goto error;
  1607. }
  1608. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1609. if (vdev->tx_non_std_data_callback.func) {
  1610. qdf_nbuf_set_next(nbuf, NULL);
  1611. vdev->tx_non_std_data_callback.func(
  1612. vdev->tx_non_std_data_callback.ctxt,
  1613. nbuf, ts.status);
  1614. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1615. return;
  1616. } else {
  1617. dp_err_rl("callback func is null");
  1618. }
  1619. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1620. error:
  1621. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1622. qdf_nbuf_free(nbuf);
  1623. }
  1624. /**
  1625. * dp_tx_msdu_single_map() - do nbuf map
  1626. * @vdev: DP vdev handle
  1627. * @tx_desc: DP TX descriptor pointer
  1628. * @nbuf: skb pointer
  1629. *
  1630. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1631. * operation done in other component.
  1632. *
  1633. * Return: QDF_STATUS
  1634. */
  1635. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1636. struct dp_tx_desc_s *tx_desc,
  1637. qdf_nbuf_t nbuf)
  1638. {
  1639. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1640. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1641. nbuf,
  1642. QDF_DMA_TO_DEVICE,
  1643. nbuf->len);
  1644. else
  1645. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1646. QDF_DMA_TO_DEVICE);
  1647. }
  1648. #else
  1649. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1650. struct dp_vdev *vdev,
  1651. struct dp_tx_desc_s *tx_desc)
  1652. {
  1653. }
  1654. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1655. struct dp_tx_desc_s *tx_desc)
  1656. {
  1657. }
  1658. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1659. struct dp_tx_desc_s *tx_desc,
  1660. qdf_nbuf_t nbuf)
  1661. {
  1662. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1663. nbuf,
  1664. QDF_DMA_TO_DEVICE,
  1665. nbuf->len);
  1666. }
  1667. #endif
  1668. #ifdef MESH_MODE_SUPPORT
  1669. /**
  1670. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1671. * @soc: datapath SOC
  1672. * @vdev: datapath vdev
  1673. * @tx_desc: TX descriptor
  1674. *
  1675. * Return: None
  1676. */
  1677. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1678. struct dp_vdev *vdev,
  1679. struct dp_tx_desc_s *tx_desc)
  1680. {
  1681. if (qdf_unlikely(vdev->mesh_vdev))
  1682. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1683. }
  1684. /**
  1685. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1686. * @soc: dp_soc handle
  1687. * @tx_desc: TX descriptor
  1688. * @vdev: datapath vdev handle
  1689. *
  1690. * Return: None
  1691. */
  1692. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1693. struct dp_tx_desc_s *tx_desc)
  1694. {
  1695. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1696. struct dp_vdev *vdev = NULL;
  1697. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1698. qdf_nbuf_free(nbuf);
  1699. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1700. } else {
  1701. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1702. DP_MOD_ID_MESH);
  1703. if (vdev && vdev->osif_tx_free_ext)
  1704. vdev->osif_tx_free_ext((nbuf));
  1705. else
  1706. qdf_nbuf_free(nbuf);
  1707. if (vdev)
  1708. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1709. }
  1710. }
  1711. #else
  1712. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1713. struct dp_vdev *vdev,
  1714. struct dp_tx_desc_s *tx_desc)
  1715. {
  1716. }
  1717. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1718. struct dp_tx_desc_s *tx_desc)
  1719. {
  1720. }
  1721. #endif
  1722. /**
  1723. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1724. * @vdev: DP vdev handle
  1725. * @nbuf: skb
  1726. *
  1727. * Return: 1 if frame needs to be dropped else 0
  1728. */
  1729. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1730. {
  1731. struct dp_pdev *pdev = NULL;
  1732. struct dp_ast_entry *src_ast_entry = NULL;
  1733. struct dp_ast_entry *dst_ast_entry = NULL;
  1734. struct dp_soc *soc = NULL;
  1735. qdf_assert(vdev);
  1736. pdev = vdev->pdev;
  1737. qdf_assert(pdev);
  1738. soc = pdev->soc;
  1739. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1740. (soc, dstmac, vdev->pdev->pdev_id);
  1741. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1742. (soc, srcmac, vdev->pdev->pdev_id);
  1743. if (dst_ast_entry && src_ast_entry) {
  1744. if (dst_ast_entry->peer_id ==
  1745. src_ast_entry->peer_id)
  1746. return 1;
  1747. }
  1748. return 0;
  1749. }
  1750. /**
  1751. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1752. * @vdev: DP vdev handle
  1753. * @nbuf: skb
  1754. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1755. * @meta_data: Metadata to the fw
  1756. * @tx_q: Tx queue to be used for this Tx frame
  1757. * @peer_id: peer_id of the peer in case of NAWDS frames
  1758. * @tx_exc_metadata: Handle that holds exception path metadata
  1759. *
  1760. * Return: NULL on success,
  1761. * nbuf when it fails to send
  1762. */
  1763. qdf_nbuf_t
  1764. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1765. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1766. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1767. {
  1768. struct dp_pdev *pdev = vdev->pdev;
  1769. struct dp_soc *soc = pdev->soc;
  1770. struct dp_tx_desc_s *tx_desc;
  1771. QDF_STATUS status;
  1772. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1773. uint16_t htt_tcl_metadata = 0;
  1774. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1775. uint8_t tid = msdu_info->tid;
  1776. struct cdp_tid_tx_stats *tid_stats = NULL;
  1777. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1778. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1779. msdu_info, tx_exc_metadata);
  1780. if (!tx_desc) {
  1781. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1782. vdev, tx_q->desc_pool_id);
  1783. drop_code = TX_DESC_ERR;
  1784. goto fail_return;
  1785. }
  1786. if (qdf_unlikely(soc->cce_disable)) {
  1787. if (dp_cce_classify(vdev, nbuf) == true) {
  1788. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1789. tid = DP_VO_TID;
  1790. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1791. }
  1792. }
  1793. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1794. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1795. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1796. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1797. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1798. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1799. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1800. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1801. peer_id);
  1802. } else
  1803. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1804. if (msdu_info->exception_fw)
  1805. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1806. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1807. !pdev->enhanced_stats_en);
  1808. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1809. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1810. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1811. /* Handle failure */
  1812. dp_err("qdf_nbuf_map failed");
  1813. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1814. drop_code = TX_DMA_MAP_ERR;
  1815. goto release_desc;
  1816. }
  1817. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1818. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1819. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  1820. tx_exc_metadata, msdu_info);
  1821. if (status != QDF_STATUS_SUCCESS) {
  1822. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1823. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1824. __func__, tx_desc, tx_q->ring_id);
  1825. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1826. QDF_DMA_TO_DEVICE,
  1827. nbuf->len);
  1828. drop_code = TX_HW_ENQUEUE;
  1829. goto release_desc;
  1830. }
  1831. return NULL;
  1832. release_desc:
  1833. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1834. fail_return:
  1835. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1836. tid_stats = &pdev->stats.tid_stats.
  1837. tid_tx_stats[tx_q->ring_id][tid];
  1838. tid_stats->swdrop_cnt[drop_code]++;
  1839. return nbuf;
  1840. }
  1841. /**
  1842. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1843. * @soc: Soc handle
  1844. * @desc: software Tx descriptor to be processed
  1845. *
  1846. * Return: none
  1847. */
  1848. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1849. struct dp_tx_desc_s *desc)
  1850. {
  1851. qdf_nbuf_t nbuf = desc->nbuf;
  1852. /* nbuf already freed in vdev detach path */
  1853. if (!nbuf)
  1854. return;
  1855. /* If it is TDLS mgmt, don't unmap or free the frame */
  1856. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1857. return dp_non_std_tx_comp_free_buff(soc, desc);
  1858. /* 0 : MSDU buffer, 1 : MLE */
  1859. if (desc->msdu_ext_desc) {
  1860. /* TSO free */
  1861. if (hal_tx_ext_desc_get_tso_enable(
  1862. desc->msdu_ext_desc->vaddr)) {
  1863. /* unmap eash TSO seg before free the nbuf */
  1864. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1865. desc->tso_num_desc);
  1866. qdf_nbuf_free(nbuf);
  1867. return;
  1868. }
  1869. }
  1870. /* If it's ME frame, dont unmap the cloned nbuf's */
  1871. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1872. goto nbuf_free;
  1873. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  1874. QDF_DMA_TO_DEVICE, nbuf->len);
  1875. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1876. return dp_mesh_tx_comp_free_buff(soc, desc);
  1877. nbuf_free:
  1878. qdf_nbuf_free(nbuf);
  1879. }
  1880. /**
  1881. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1882. * @vdev: DP vdev handle
  1883. * @nbuf: skb
  1884. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1885. *
  1886. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1887. *
  1888. * Return: NULL on success,
  1889. * nbuf when it fails to send
  1890. */
  1891. #if QDF_LOCK_STATS
  1892. noinline
  1893. #else
  1894. #endif
  1895. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1896. struct dp_tx_msdu_info_s *msdu_info)
  1897. {
  1898. uint32_t i;
  1899. struct dp_pdev *pdev = vdev->pdev;
  1900. struct dp_soc *soc = pdev->soc;
  1901. struct dp_tx_desc_s *tx_desc;
  1902. bool is_cce_classified = false;
  1903. QDF_STATUS status;
  1904. uint16_t htt_tcl_metadata = 0;
  1905. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1906. struct cdp_tid_tx_stats *tid_stats = NULL;
  1907. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1908. if (qdf_unlikely(soc->cce_disable)) {
  1909. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1910. if (is_cce_classified) {
  1911. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1912. msdu_info->tid = DP_VO_TID;
  1913. }
  1914. }
  1915. if (msdu_info->frm_type == dp_tx_frm_me)
  1916. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1917. i = 0;
  1918. /* Print statement to track i and num_seg */
  1919. /*
  1920. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1921. * descriptors using information in msdu_info
  1922. */
  1923. while (i < msdu_info->num_seg) {
  1924. /*
  1925. * Setup Tx descriptor for an MSDU, and MSDU extension
  1926. * descriptor
  1927. */
  1928. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1929. tx_q->desc_pool_id);
  1930. if (!tx_desc) {
  1931. if (msdu_info->frm_type == dp_tx_frm_me) {
  1932. prep_desc_fail++;
  1933. dp_tx_me_free_buf(pdev,
  1934. (void *)(msdu_info->u.sg_info
  1935. .curr_seg->frags[0].vaddr));
  1936. if (prep_desc_fail == msdu_info->num_seg) {
  1937. /*
  1938. * Unmap is needed only if descriptor
  1939. * preparation failed for all segments.
  1940. */
  1941. qdf_nbuf_unmap(soc->osdev,
  1942. msdu_info->u.sg_info.
  1943. curr_seg->nbuf,
  1944. QDF_DMA_TO_DEVICE);
  1945. }
  1946. /*
  1947. * Free the nbuf for the current segment
  1948. * and make it point to the next in the list.
  1949. * For me, there are as many segments as there
  1950. * are no of clients.
  1951. */
  1952. qdf_nbuf_free(msdu_info->u.sg_info
  1953. .curr_seg->nbuf);
  1954. if (msdu_info->u.sg_info.curr_seg->next) {
  1955. msdu_info->u.sg_info.curr_seg =
  1956. msdu_info->u.sg_info
  1957. .curr_seg->next;
  1958. nbuf = msdu_info->u.sg_info
  1959. .curr_seg->nbuf;
  1960. }
  1961. i++;
  1962. continue;
  1963. }
  1964. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1965. dp_tx_tso_unmap_segment(soc,
  1966. msdu_info->u.tso_info.
  1967. curr_seg,
  1968. msdu_info->u.tso_info.
  1969. tso_num_seg_list);
  1970. if (msdu_info->u.tso_info.curr_seg->next) {
  1971. msdu_info->u.tso_info.curr_seg =
  1972. msdu_info->u.tso_info.curr_seg->next;
  1973. i++;
  1974. continue;
  1975. }
  1976. }
  1977. goto done;
  1978. }
  1979. if (msdu_info->frm_type == dp_tx_frm_me) {
  1980. tx_desc->me_buffer =
  1981. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1982. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1983. }
  1984. if (is_cce_classified)
  1985. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1986. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1987. if (msdu_info->exception_fw) {
  1988. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1989. }
  1990. /*
  1991. * For frames with multiple segments (TSO, ME), jump to next
  1992. * segment.
  1993. */
  1994. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1995. if (msdu_info->u.tso_info.curr_seg->next) {
  1996. msdu_info->u.tso_info.curr_seg =
  1997. msdu_info->u.tso_info.curr_seg->next;
  1998. /*
  1999. * If this is a jumbo nbuf, then increment the
  2000. * number of nbuf users for each additional
  2001. * segment of the msdu. This will ensure that
  2002. * the skb is freed only after receiving tx
  2003. * completion for all segments of an nbuf
  2004. */
  2005. qdf_nbuf_inc_users(nbuf);
  2006. /* Check with MCL if this is needed */
  2007. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2008. */
  2009. }
  2010. }
  2011. /*
  2012. * Enqueue the Tx MSDU descriptor to HW for transmit
  2013. */
  2014. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, htt_tcl_metadata,
  2015. NULL, msdu_info);
  2016. if (status != QDF_STATUS_SUCCESS) {
  2017. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2018. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2019. __func__, tx_desc, tx_q->ring_id);
  2020. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2021. tid_stats = &pdev->stats.tid_stats.
  2022. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2023. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2024. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2025. if (msdu_info->frm_type == dp_tx_frm_me) {
  2026. hw_enq_fail++;
  2027. if (hw_enq_fail == msdu_info->num_seg) {
  2028. /*
  2029. * Unmap is needed only if enqueue
  2030. * failed for all segments.
  2031. */
  2032. qdf_nbuf_unmap(soc->osdev,
  2033. msdu_info->u.sg_info.
  2034. curr_seg->nbuf,
  2035. QDF_DMA_TO_DEVICE);
  2036. }
  2037. /*
  2038. * Free the nbuf for the current segment
  2039. * and make it point to the next in the list.
  2040. * For me, there are as many segments as there
  2041. * are no of clients.
  2042. */
  2043. qdf_nbuf_free(msdu_info->u.sg_info
  2044. .curr_seg->nbuf);
  2045. if (msdu_info->u.sg_info.curr_seg->next) {
  2046. msdu_info->u.sg_info.curr_seg =
  2047. msdu_info->u.sg_info
  2048. .curr_seg->next;
  2049. nbuf = msdu_info->u.sg_info
  2050. .curr_seg->nbuf;
  2051. }
  2052. i++;
  2053. continue;
  2054. }
  2055. /*
  2056. * For TSO frames, the nbuf users increment done for
  2057. * the current segment has to be reverted, since the
  2058. * hw enqueue for this segment failed
  2059. */
  2060. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2061. msdu_info->u.tso_info.curr_seg) {
  2062. /*
  2063. * unmap and free current,
  2064. * retransmit remaining segments
  2065. */
  2066. dp_tx_comp_free_buf(soc, tx_desc);
  2067. i++;
  2068. continue;
  2069. }
  2070. goto done;
  2071. }
  2072. /*
  2073. * TODO
  2074. * if tso_info structure can be modified to have curr_seg
  2075. * as first element, following 2 blocks of code (for TSO and SG)
  2076. * can be combined into 1
  2077. */
  2078. /*
  2079. * For Multicast-Unicast converted packets,
  2080. * each converted frame (for a client) is represented as
  2081. * 1 segment
  2082. */
  2083. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2084. (msdu_info->frm_type == dp_tx_frm_me)) {
  2085. if (msdu_info->u.sg_info.curr_seg->next) {
  2086. msdu_info->u.sg_info.curr_seg =
  2087. msdu_info->u.sg_info.curr_seg->next;
  2088. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2089. }
  2090. }
  2091. i++;
  2092. }
  2093. nbuf = NULL;
  2094. done:
  2095. return nbuf;
  2096. }
  2097. /**
  2098. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2099. * for SG frames
  2100. * @vdev: DP vdev handle
  2101. * @nbuf: skb
  2102. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2103. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2104. *
  2105. * Return: NULL on success,
  2106. * nbuf when it fails to send
  2107. */
  2108. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2109. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2110. {
  2111. uint32_t cur_frag, nr_frags, i;
  2112. qdf_dma_addr_t paddr;
  2113. struct dp_tx_sg_info_s *sg_info;
  2114. sg_info = &msdu_info->u.sg_info;
  2115. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2116. if (QDF_STATUS_SUCCESS !=
  2117. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2118. QDF_DMA_TO_DEVICE,
  2119. qdf_nbuf_headlen(nbuf))) {
  2120. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2121. "dma map error");
  2122. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2123. qdf_nbuf_free(nbuf);
  2124. return NULL;
  2125. }
  2126. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2127. seg_info->frags[0].paddr_lo = paddr;
  2128. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2129. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2130. seg_info->frags[0].vaddr = (void *) nbuf;
  2131. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2132. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2133. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2134. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2135. "frag dma map error");
  2136. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2137. goto map_err;
  2138. }
  2139. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2140. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2141. seg_info->frags[cur_frag + 1].paddr_hi =
  2142. ((uint64_t) paddr) >> 32;
  2143. seg_info->frags[cur_frag + 1].len =
  2144. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2145. }
  2146. seg_info->frag_cnt = (cur_frag + 1);
  2147. seg_info->total_len = qdf_nbuf_len(nbuf);
  2148. seg_info->next = NULL;
  2149. sg_info->curr_seg = seg_info;
  2150. msdu_info->frm_type = dp_tx_frm_sg;
  2151. msdu_info->num_seg = 1;
  2152. return nbuf;
  2153. map_err:
  2154. /* restore paddr into nbuf before calling unmap */
  2155. qdf_nbuf_mapped_paddr_set(nbuf,
  2156. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2157. ((uint64_t)
  2158. seg_info->frags[0].paddr_hi) << 32));
  2159. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2160. QDF_DMA_TO_DEVICE,
  2161. seg_info->frags[0].len);
  2162. for (i = 1; i <= cur_frag; i++) {
  2163. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2164. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2165. seg_info->frags[i].paddr_hi) << 32),
  2166. seg_info->frags[i].len,
  2167. QDF_DMA_TO_DEVICE);
  2168. }
  2169. qdf_nbuf_free(nbuf);
  2170. return NULL;
  2171. }
  2172. /**
  2173. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2174. * @vdev: DP vdev handle
  2175. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2176. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2177. *
  2178. * Return: NULL on failure,
  2179. * nbuf when extracted successfully
  2180. */
  2181. static
  2182. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2183. struct dp_tx_msdu_info_s *msdu_info,
  2184. uint16_t ppdu_cookie)
  2185. {
  2186. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2187. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2188. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2189. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2190. (msdu_info->meta_data[5], 1);
  2191. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2192. (msdu_info->meta_data[5], 1);
  2193. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2194. (msdu_info->meta_data[6], ppdu_cookie);
  2195. msdu_info->exception_fw = 1;
  2196. msdu_info->is_tx_sniffer = 1;
  2197. }
  2198. #ifdef MESH_MODE_SUPPORT
  2199. /**
  2200. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2201. and prepare msdu_info for mesh frames.
  2202. * @vdev: DP vdev handle
  2203. * @nbuf: skb
  2204. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2205. *
  2206. * Return: NULL on failure,
  2207. * nbuf when extracted successfully
  2208. */
  2209. static
  2210. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2211. struct dp_tx_msdu_info_s *msdu_info)
  2212. {
  2213. struct meta_hdr_s *mhdr;
  2214. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2215. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2216. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2217. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2218. msdu_info->exception_fw = 0;
  2219. goto remove_meta_hdr;
  2220. }
  2221. msdu_info->exception_fw = 1;
  2222. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2223. meta_data->host_tx_desc_pool = 1;
  2224. meta_data->update_peer_cache = 1;
  2225. meta_data->learning_frame = 1;
  2226. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2227. meta_data->power = mhdr->power;
  2228. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2229. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2230. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2231. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2232. meta_data->dyn_bw = 1;
  2233. meta_data->valid_pwr = 1;
  2234. meta_data->valid_mcs_mask = 1;
  2235. meta_data->valid_nss_mask = 1;
  2236. meta_data->valid_preamble_type = 1;
  2237. meta_data->valid_retries = 1;
  2238. meta_data->valid_bw_info = 1;
  2239. }
  2240. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2241. meta_data->encrypt_type = 0;
  2242. meta_data->valid_encrypt_type = 1;
  2243. meta_data->learning_frame = 0;
  2244. }
  2245. meta_data->valid_key_flags = 1;
  2246. meta_data->key_flags = (mhdr->keyix & 0x3);
  2247. remove_meta_hdr:
  2248. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2249. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2250. "qdf_nbuf_pull_head failed");
  2251. qdf_nbuf_free(nbuf);
  2252. return NULL;
  2253. }
  2254. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2255. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2256. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  2257. " tid %d to_fw %d",
  2258. __func__, msdu_info->meta_data[0],
  2259. msdu_info->meta_data[1],
  2260. msdu_info->meta_data[2],
  2261. msdu_info->meta_data[3],
  2262. msdu_info->meta_data[4],
  2263. msdu_info->meta_data[5],
  2264. msdu_info->tid, msdu_info->exception_fw);
  2265. return nbuf;
  2266. }
  2267. #else
  2268. static
  2269. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2270. struct dp_tx_msdu_info_s *msdu_info)
  2271. {
  2272. return nbuf;
  2273. }
  2274. #endif
  2275. /**
  2276. * dp_check_exc_metadata() - Checks if parameters are valid
  2277. * @tx_exc - holds all exception path parameters
  2278. *
  2279. * Returns true when all the parameters are valid else false
  2280. *
  2281. */
  2282. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2283. {
  2284. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  2285. HTT_INVALID_TID);
  2286. bool invalid_encap_type =
  2287. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2288. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2289. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2290. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2291. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2292. tx_exc->ppdu_cookie == 0);
  2293. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2294. invalid_cookie) {
  2295. return false;
  2296. }
  2297. return true;
  2298. }
  2299. #ifdef ATH_SUPPORT_IQUE
  2300. /**
  2301. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2302. * @vdev: vdev handle
  2303. * @nbuf: skb
  2304. *
  2305. * Return: true on success,
  2306. * false on failure
  2307. */
  2308. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2309. {
  2310. qdf_ether_header_t *eh;
  2311. /* Mcast to Ucast Conversion*/
  2312. if (qdf_likely(!vdev->mcast_enhancement_en))
  2313. return true;
  2314. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2315. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2316. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2317. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2318. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2319. qdf_nbuf_len(nbuf));
  2320. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2321. QDF_STATUS_SUCCESS) {
  2322. return false;
  2323. }
  2324. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2325. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2326. QDF_STATUS_SUCCESS) {
  2327. return false;
  2328. }
  2329. }
  2330. }
  2331. return true;
  2332. }
  2333. #else
  2334. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2335. {
  2336. return true;
  2337. }
  2338. #endif
  2339. /**
  2340. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2341. * @nbuf: qdf_nbuf_t
  2342. * @vdev: struct dp_vdev *
  2343. *
  2344. * Allow packet for processing only if it is for peer client which is
  2345. * connected with same vap. Drop packet if client is connected to
  2346. * different vap.
  2347. *
  2348. * Return: QDF_STATUS
  2349. */
  2350. static inline QDF_STATUS
  2351. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2352. {
  2353. struct dp_ast_entry *dst_ast_entry = NULL;
  2354. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2355. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2356. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2357. return QDF_STATUS_SUCCESS;
  2358. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2359. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2360. eh->ether_dhost,
  2361. vdev->vdev_id);
  2362. /* If there is no ast entry, return failure */
  2363. if (qdf_unlikely(!dst_ast_entry)) {
  2364. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2365. return QDF_STATUS_E_FAILURE;
  2366. }
  2367. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2368. return QDF_STATUS_SUCCESS;
  2369. }
  2370. /**
  2371. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2372. * @soc: DP soc handle
  2373. * @vdev_id: id of DP vdev handle
  2374. * @nbuf: skb
  2375. * @tx_exc_metadata: Handle that holds exception path meta data
  2376. *
  2377. * Entry point for Core Tx layer (DP_TX) invoked from
  2378. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2379. *
  2380. * Return: NULL on success,
  2381. * nbuf when it fails to send
  2382. */
  2383. qdf_nbuf_t
  2384. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2385. qdf_nbuf_t nbuf,
  2386. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2387. {
  2388. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2389. qdf_ether_header_t *eh = NULL;
  2390. struct dp_tx_msdu_info_s msdu_info;
  2391. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2392. DP_MOD_ID_TX_EXCEPTION);
  2393. if (qdf_unlikely(!vdev))
  2394. goto fail;
  2395. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2396. if (!tx_exc_metadata)
  2397. goto fail;
  2398. msdu_info.tid = tx_exc_metadata->tid;
  2399. dp_tx_wds_ext(soc, vdev, tx_exc_metadata->peer_id, &msdu_info);
  2400. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2401. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2402. QDF_MAC_ADDR_REF(nbuf->data));
  2403. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2404. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2405. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2406. "Invalid parameters in exception path");
  2407. goto fail;
  2408. }
  2409. /* Basic sanity checks for unsupported packets */
  2410. /* MESH mode */
  2411. if (qdf_unlikely(vdev->mesh_vdev)) {
  2412. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2413. "Mesh mode is not supported in exception path");
  2414. goto fail;
  2415. }
  2416. /*
  2417. * Classify the frame and call corresponding
  2418. * "prepare" function which extracts the segment (TSO)
  2419. * and fragmentation information (for TSO , SG, ME, or Raw)
  2420. * into MSDU_INFO structure which is later used to fill
  2421. * SW and HW descriptors.
  2422. */
  2423. if (qdf_nbuf_is_tso(nbuf)) {
  2424. dp_verbose_debug("TSO frame %pK", vdev);
  2425. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2426. qdf_nbuf_len(nbuf));
  2427. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2428. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2429. qdf_nbuf_len(nbuf));
  2430. return nbuf;
  2431. }
  2432. goto send_multiple;
  2433. }
  2434. /* SG */
  2435. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2436. struct dp_tx_seg_info_s seg_info = {0};
  2437. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2438. if (!nbuf)
  2439. return NULL;
  2440. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2441. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2442. qdf_nbuf_len(nbuf));
  2443. goto send_multiple;
  2444. }
  2445. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2446. return NULL;
  2447. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2448. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2449. qdf_nbuf_len(nbuf));
  2450. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2451. tx_exc_metadata->ppdu_cookie);
  2452. }
  2453. /*
  2454. * Get HW Queue to use for this frame.
  2455. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2456. * dedicated for data and 1 for command.
  2457. * "queue_id" maps to one hardware ring.
  2458. * With each ring, we also associate a unique Tx descriptor pool
  2459. * to minimize lock contention for these resources.
  2460. */
  2461. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2462. /*
  2463. * Check exception descriptors
  2464. */
  2465. if (dp_tx_exception_limit_check(vdev))
  2466. goto fail;
  2467. /* Single linear frame */
  2468. /*
  2469. * If nbuf is a simple linear frame, use send_single function to
  2470. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2471. * SRNG. There is no need to setup a MSDU extension descriptor.
  2472. */
  2473. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2474. tx_exc_metadata->peer_id, tx_exc_metadata);
  2475. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2476. return nbuf;
  2477. send_multiple:
  2478. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2479. fail:
  2480. if (vdev)
  2481. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2482. dp_verbose_debug("pkt send failed");
  2483. return nbuf;
  2484. }
  2485. /**
  2486. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2487. * in exception path in special case to avoid regular exception path chk.
  2488. * @soc: DP soc handle
  2489. * @vdev_id: id of DP vdev handle
  2490. * @nbuf: skb
  2491. * @tx_exc_metadata: Handle that holds exception path meta data
  2492. *
  2493. * Entry point for Core Tx layer (DP_TX) invoked from
  2494. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2495. *
  2496. * Return: NULL on success,
  2497. * nbuf when it fails to send
  2498. */
  2499. qdf_nbuf_t
  2500. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2501. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2502. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2503. {
  2504. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2505. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2506. DP_MOD_ID_TX_EXCEPTION);
  2507. if (qdf_unlikely(!vdev))
  2508. goto fail;
  2509. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2510. == QDF_STATUS_E_FAILURE)) {
  2511. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2512. goto fail;
  2513. }
  2514. /* Unref count as it will agin be taken inside dp_tx_exception */
  2515. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2516. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2517. fail:
  2518. if (vdev)
  2519. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2520. dp_verbose_debug("pkt send failed");
  2521. return nbuf;
  2522. }
  2523. /**
  2524. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2525. * @soc: DP soc handle
  2526. * @vdev_id: DP vdev handle
  2527. * @nbuf: skb
  2528. *
  2529. * Entry point for Core Tx layer (DP_TX) invoked from
  2530. * hard_start_xmit in OSIF/HDD
  2531. *
  2532. * Return: NULL on success,
  2533. * nbuf when it fails to send
  2534. */
  2535. #ifdef MESH_MODE_SUPPORT
  2536. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2537. qdf_nbuf_t nbuf)
  2538. {
  2539. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2540. struct meta_hdr_s *mhdr;
  2541. qdf_nbuf_t nbuf_mesh = NULL;
  2542. qdf_nbuf_t nbuf_clone = NULL;
  2543. struct dp_vdev *vdev;
  2544. uint8_t no_enc_frame = 0;
  2545. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2546. if (!nbuf_mesh) {
  2547. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2548. "qdf_nbuf_unshare failed");
  2549. return nbuf;
  2550. }
  2551. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2552. if (!vdev) {
  2553. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2554. "vdev is NULL for vdev_id %d", vdev_id);
  2555. return nbuf;
  2556. }
  2557. nbuf = nbuf_mesh;
  2558. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2559. if ((vdev->sec_type != cdp_sec_type_none) &&
  2560. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2561. no_enc_frame = 1;
  2562. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2563. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2564. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2565. !no_enc_frame) {
  2566. nbuf_clone = qdf_nbuf_clone(nbuf);
  2567. if (!nbuf_clone) {
  2568. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2569. "qdf_nbuf_clone failed");
  2570. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2571. return nbuf;
  2572. }
  2573. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2574. }
  2575. if (nbuf_clone) {
  2576. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2577. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2578. } else {
  2579. qdf_nbuf_free(nbuf_clone);
  2580. }
  2581. }
  2582. if (no_enc_frame)
  2583. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2584. else
  2585. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2586. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2587. if ((!nbuf) && no_enc_frame) {
  2588. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2589. }
  2590. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2591. return nbuf;
  2592. }
  2593. #else
  2594. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2595. qdf_nbuf_t nbuf)
  2596. {
  2597. return dp_tx_send(soc, vdev_id, nbuf);
  2598. }
  2599. #endif
  2600. /**
  2601. * dp_tx_nawds_handler() - NAWDS handler
  2602. *
  2603. * @soc: DP soc handle
  2604. * @vdev_id: id of DP vdev handle
  2605. * @msdu_info: msdu_info required to create HTT metadata
  2606. * @nbuf: skb
  2607. *
  2608. * This API transfers the multicast frames with the peer id
  2609. * on NAWDS enabled peer.
  2610. * Return: none
  2611. */
  2612. static inline
  2613. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2614. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2615. {
  2616. struct dp_peer *peer = NULL;
  2617. qdf_nbuf_t nbuf_clone = NULL;
  2618. uint16_t peer_id = DP_INVALID_PEER;
  2619. uint16_t sa_peer_id = DP_INVALID_PEER;
  2620. struct dp_ast_entry *ast_entry = NULL;
  2621. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2622. qdf_spin_lock_bh(&soc->ast_lock);
  2623. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2624. (soc,
  2625. (uint8_t *)(eh->ether_shost),
  2626. vdev->pdev->pdev_id);
  2627. if (ast_entry)
  2628. sa_peer_id = ast_entry->peer_id;
  2629. qdf_spin_unlock_bh(&soc->ast_lock);
  2630. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2631. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2632. if (!peer->bss_peer && peer->nawds_enabled) {
  2633. peer_id = peer->peer_id;
  2634. /* Multicast packets needs to be
  2635. * dropped in case of intra bss forwarding
  2636. */
  2637. if (sa_peer_id == peer->peer_id) {
  2638. QDF_TRACE(QDF_MODULE_ID_DP,
  2639. QDF_TRACE_LEVEL_DEBUG,
  2640. " %s: multicast packet", __func__);
  2641. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2642. continue;
  2643. }
  2644. nbuf_clone = qdf_nbuf_clone(nbuf);
  2645. if (!nbuf_clone) {
  2646. QDF_TRACE(QDF_MODULE_ID_DP,
  2647. QDF_TRACE_LEVEL_ERROR,
  2648. FL("nbuf clone failed"));
  2649. break;
  2650. }
  2651. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2652. msdu_info, peer_id,
  2653. NULL);
  2654. if (nbuf_clone) {
  2655. QDF_TRACE(QDF_MODULE_ID_DP,
  2656. QDF_TRACE_LEVEL_DEBUG,
  2657. FL("pkt send failed"));
  2658. qdf_nbuf_free(nbuf_clone);
  2659. } else {
  2660. if (peer_id != DP_INVALID_PEER)
  2661. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2662. 1, qdf_nbuf_len(nbuf));
  2663. }
  2664. }
  2665. }
  2666. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2667. }
  2668. /**
  2669. * dp_tx_send() - Transmit a frame on a given VAP
  2670. * @soc: DP soc handle
  2671. * @vdev_id: id of DP vdev handle
  2672. * @nbuf: skb
  2673. *
  2674. * Entry point for Core Tx layer (DP_TX) invoked from
  2675. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2676. * cases
  2677. *
  2678. * Return: NULL on success,
  2679. * nbuf when it fails to send
  2680. */
  2681. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2682. qdf_nbuf_t nbuf)
  2683. {
  2684. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2685. uint16_t peer_id = HTT_INVALID_PEER;
  2686. /*
  2687. * doing a memzero is causing additional function call overhead
  2688. * so doing static stack clearing
  2689. */
  2690. struct dp_tx_msdu_info_s msdu_info = {0};
  2691. struct dp_vdev *vdev = NULL;
  2692. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2693. return nbuf;
  2694. /*
  2695. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2696. * this in per packet path.
  2697. *
  2698. * As in this path vdev memory is already protected with netdev
  2699. * tx lock
  2700. */
  2701. vdev = soc->vdev_id_map[vdev_id];
  2702. if (qdf_unlikely(!vdev))
  2703. return nbuf;
  2704. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2705. QDF_MAC_ADDR_REF(nbuf->data));
  2706. /*
  2707. * Set Default Host TID value to invalid TID
  2708. * (TID override disabled)
  2709. */
  2710. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2711. dp_tx_wds_ext(soc, vdev, peer_id, &msdu_info);
  2712. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2713. if (qdf_unlikely(vdev->mesh_vdev)) {
  2714. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2715. &msdu_info);
  2716. if (!nbuf_mesh) {
  2717. dp_verbose_debug("Extracting mesh metadata failed");
  2718. return nbuf;
  2719. }
  2720. nbuf = nbuf_mesh;
  2721. }
  2722. /*
  2723. * Get HW Queue to use for this frame.
  2724. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2725. * dedicated for data and 1 for command.
  2726. * "queue_id" maps to one hardware ring.
  2727. * With each ring, we also associate a unique Tx descriptor pool
  2728. * to minimize lock contention for these resources.
  2729. */
  2730. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2731. /*
  2732. * TCL H/W supports 2 DSCP-TID mapping tables.
  2733. * Table 1 - Default DSCP-TID mapping table
  2734. * Table 2 - 1 DSCP-TID override table
  2735. *
  2736. * If we need a different DSCP-TID mapping for this vap,
  2737. * call tid_classify to extract DSCP/ToS from frame and
  2738. * map to a TID and store in msdu_info. This is later used
  2739. * to fill in TCL Input descriptor (per-packet TID override).
  2740. */
  2741. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2742. /*
  2743. * Classify the frame and call corresponding
  2744. * "prepare" function which extracts the segment (TSO)
  2745. * and fragmentation information (for TSO , SG, ME, or Raw)
  2746. * into MSDU_INFO structure which is later used to fill
  2747. * SW and HW descriptors.
  2748. */
  2749. if (qdf_nbuf_is_tso(nbuf)) {
  2750. dp_verbose_debug("TSO frame %pK", vdev);
  2751. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2752. qdf_nbuf_len(nbuf));
  2753. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2754. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2755. qdf_nbuf_len(nbuf));
  2756. return nbuf;
  2757. }
  2758. goto send_multiple;
  2759. }
  2760. /* SG */
  2761. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2762. struct dp_tx_seg_info_s seg_info = {0};
  2763. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2764. if (!nbuf)
  2765. return NULL;
  2766. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2767. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2768. qdf_nbuf_len(nbuf));
  2769. goto send_multiple;
  2770. }
  2771. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2772. return NULL;
  2773. /* RAW */
  2774. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2775. struct dp_tx_seg_info_s seg_info = {0};
  2776. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2777. if (!nbuf)
  2778. return NULL;
  2779. dp_verbose_debug("Raw frame %pK", vdev);
  2780. goto send_multiple;
  2781. }
  2782. if (qdf_unlikely(vdev->nawds_enabled)) {
  2783. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2784. qdf_nbuf_data(nbuf);
  2785. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2786. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2787. peer_id = DP_INVALID_PEER;
  2788. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2789. 1, qdf_nbuf_len(nbuf));
  2790. }
  2791. /* Single linear frame */
  2792. /*
  2793. * If nbuf is a simple linear frame, use send_single function to
  2794. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2795. * SRNG. There is no need to setup a MSDU extension descriptor.
  2796. */
  2797. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2798. return nbuf;
  2799. send_multiple:
  2800. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2801. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2802. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2803. return nbuf;
  2804. }
  2805. /**
  2806. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2807. * case to vaoid check in perpkt path.
  2808. * @soc: DP soc handle
  2809. * @vdev_id: id of DP vdev handle
  2810. * @nbuf: skb
  2811. *
  2812. * Entry point for Core Tx layer (DP_TX) invoked from
  2813. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2814. * with special condition to avoid per pkt check in dp_tx_send
  2815. *
  2816. * Return: NULL on success,
  2817. * nbuf when it fails to send
  2818. */
  2819. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2820. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2821. {
  2822. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2823. struct dp_vdev *vdev = NULL;
  2824. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2825. return nbuf;
  2826. /*
  2827. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2828. * this in per packet path.
  2829. *
  2830. * As in this path vdev memory is already protected with netdev
  2831. * tx lock
  2832. */
  2833. vdev = soc->vdev_id_map[vdev_id];
  2834. if (qdf_unlikely(!vdev))
  2835. return nbuf;
  2836. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2837. == QDF_STATUS_E_FAILURE)) {
  2838. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2839. return nbuf;
  2840. }
  2841. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2842. }
  2843. /**
  2844. * dp_tx_reinject_handler() - Tx Reinject Handler
  2845. * @soc: datapath soc handle
  2846. * @vdev: datapath vdev handle
  2847. * @tx_desc: software descriptor head pointer
  2848. * @status : Tx completion status from HTT descriptor
  2849. *
  2850. * This function reinjects frames back to Target.
  2851. * Todo - Host queue needs to be added
  2852. *
  2853. * Return: none
  2854. */
  2855. static
  2856. void dp_tx_reinject_handler(struct dp_soc *soc,
  2857. struct dp_vdev *vdev,
  2858. struct dp_tx_desc_s *tx_desc,
  2859. uint8_t *status)
  2860. {
  2861. struct dp_peer *peer = NULL;
  2862. uint32_t peer_id = HTT_INVALID_PEER;
  2863. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2864. qdf_nbuf_t nbuf_copy = NULL;
  2865. struct dp_tx_msdu_info_s msdu_info;
  2866. #ifdef WDS_VENDOR_EXTENSION
  2867. int is_mcast = 0, is_ucast = 0;
  2868. int num_peers_3addr = 0;
  2869. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2870. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2871. #endif
  2872. qdf_assert(vdev);
  2873. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2874. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2876. "%s Tx reinject path", __func__);
  2877. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2878. qdf_nbuf_len(tx_desc->nbuf));
  2879. #ifdef WDS_VENDOR_EXTENSION
  2880. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2881. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2882. } else {
  2883. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2884. }
  2885. is_ucast = !is_mcast;
  2886. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2887. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2888. if (peer->bss_peer)
  2889. continue;
  2890. /* Detect wds peers that use 3-addr framing for mcast.
  2891. * if there are any, the bss_peer is used to send the
  2892. * the mcast frame using 3-addr format. all wds enabled
  2893. * peers that use 4-addr framing for mcast frames will
  2894. * be duplicated and sent as 4-addr frames below.
  2895. */
  2896. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2897. num_peers_3addr = 1;
  2898. break;
  2899. }
  2900. }
  2901. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2902. #endif
  2903. if (qdf_unlikely(vdev->mesh_vdev)) {
  2904. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2905. } else {
  2906. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2907. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2908. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2909. #ifdef WDS_VENDOR_EXTENSION
  2910. /*
  2911. * . if 3-addr STA, then send on BSS Peer
  2912. * . if Peer WDS enabled and accept 4-addr mcast,
  2913. * send mcast on that peer only
  2914. * . if Peer WDS enabled and accept 4-addr ucast,
  2915. * send ucast on that peer only
  2916. */
  2917. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2918. (peer->wds_enabled &&
  2919. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2920. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2921. #else
  2922. ((peer->bss_peer &&
  2923. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2924. #endif
  2925. peer_id = DP_INVALID_PEER;
  2926. nbuf_copy = qdf_nbuf_copy(nbuf);
  2927. if (!nbuf_copy) {
  2928. QDF_TRACE(QDF_MODULE_ID_DP,
  2929. QDF_TRACE_LEVEL_DEBUG,
  2930. FL("nbuf copy failed"));
  2931. break;
  2932. }
  2933. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2934. nbuf_copy,
  2935. &msdu_info,
  2936. peer_id,
  2937. NULL);
  2938. if (nbuf_copy) {
  2939. QDF_TRACE(QDF_MODULE_ID_DP,
  2940. QDF_TRACE_LEVEL_DEBUG,
  2941. FL("pkt send failed"));
  2942. qdf_nbuf_free(nbuf_copy);
  2943. }
  2944. }
  2945. }
  2946. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2947. }
  2948. qdf_nbuf_free(nbuf);
  2949. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2950. }
  2951. /**
  2952. * dp_tx_inspect_handler() - Tx Inspect Handler
  2953. * @soc: datapath soc handle
  2954. * @vdev: datapath vdev handle
  2955. * @tx_desc: software descriptor head pointer
  2956. * @status : Tx completion status from HTT descriptor
  2957. *
  2958. * Handles Tx frames sent back to Host for inspection
  2959. * (ProxyARP)
  2960. *
  2961. * Return: none
  2962. */
  2963. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2964. struct dp_vdev *vdev,
  2965. struct dp_tx_desc_s *tx_desc,
  2966. uint8_t *status)
  2967. {
  2968. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2969. "%s Tx inspect path",
  2970. __func__);
  2971. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2972. qdf_nbuf_len(tx_desc->nbuf));
  2973. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2974. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2975. }
  2976. #ifdef FEATURE_PERPKT_INFO
  2977. /**
  2978. * dp_get_completion_indication_for_stack() - send completion to stack
  2979. * @soc : dp_soc handle
  2980. * @pdev: dp_pdev handle
  2981. * @peer: dp peer handle
  2982. * @ts: transmit completion status structure
  2983. * @netbuf: Buffer pointer for free
  2984. *
  2985. * This function is used for indication whether buffer needs to be
  2986. * sent to stack for freeing or not
  2987. */
  2988. QDF_STATUS
  2989. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2990. struct dp_pdev *pdev,
  2991. struct dp_peer *peer,
  2992. struct hal_tx_completion_status *ts,
  2993. qdf_nbuf_t netbuf,
  2994. uint64_t time_latency)
  2995. {
  2996. struct tx_capture_hdr *ppdu_hdr;
  2997. uint16_t peer_id = ts->peer_id;
  2998. uint32_t ppdu_id = ts->ppdu_id;
  2999. uint8_t first_msdu = ts->first_msdu;
  3000. uint8_t last_msdu = ts->last_msdu;
  3001. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  3002. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  3003. !pdev->latency_capture_enable))
  3004. return QDF_STATUS_E_NOSUPPORT;
  3005. if (!peer) {
  3006. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3007. FL("Peer Invalid"));
  3008. return QDF_STATUS_E_INVAL;
  3009. }
  3010. if (pdev->mcopy_mode) {
  3011. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  3012. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  3013. * for each MPDU
  3014. */
  3015. if (pdev->mcopy_mode == M_COPY) {
  3016. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  3017. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  3018. return QDF_STATUS_E_INVAL;
  3019. }
  3020. }
  3021. if (!first_msdu)
  3022. return QDF_STATUS_E_INVAL;
  3023. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  3024. pdev->m_copy_id.tx_peer_id = peer_id;
  3025. }
  3026. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  3027. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  3028. if (!netbuf) {
  3029. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3030. FL("No headroom"));
  3031. return QDF_STATUS_E_NOMEM;
  3032. }
  3033. }
  3034. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  3035. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3036. FL("No headroom"));
  3037. return QDF_STATUS_E_NOMEM;
  3038. }
  3039. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  3040. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  3041. QDF_MAC_ADDR_SIZE);
  3042. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  3043. QDF_MAC_ADDR_SIZE);
  3044. ppdu_hdr->ppdu_id = ppdu_id;
  3045. ppdu_hdr->peer_id = peer_id;
  3046. ppdu_hdr->first_msdu = first_msdu;
  3047. ppdu_hdr->last_msdu = last_msdu;
  3048. if (qdf_unlikely(pdev->latency_capture_enable)) {
  3049. ppdu_hdr->tsf = ts->tsf;
  3050. ppdu_hdr->time_latency = time_latency;
  3051. }
  3052. return QDF_STATUS_SUCCESS;
  3053. }
  3054. /**
  3055. * dp_send_completion_to_stack() - send completion to stack
  3056. * @soc : dp_soc handle
  3057. * @pdev: dp_pdev handle
  3058. * @peer_id: peer_id of the peer for which completion came
  3059. * @ppdu_id: ppdu_id
  3060. * @netbuf: Buffer pointer for free
  3061. *
  3062. * This function is used to send completion to stack
  3063. * to free buffer
  3064. */
  3065. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3066. uint16_t peer_id, uint32_t ppdu_id,
  3067. qdf_nbuf_t netbuf)
  3068. {
  3069. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  3070. netbuf, peer_id,
  3071. WDI_NO_VAL, pdev->pdev_id);
  3072. }
  3073. #else
  3074. static QDF_STATUS
  3075. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  3076. struct dp_pdev *pdev,
  3077. struct dp_peer *peer,
  3078. struct hal_tx_completion_status *ts,
  3079. qdf_nbuf_t netbuf,
  3080. uint64_t time_latency)
  3081. {
  3082. return QDF_STATUS_E_NOSUPPORT;
  3083. }
  3084. static void
  3085. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  3086. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  3087. {
  3088. }
  3089. #endif
  3090. #ifdef MESH_MODE_SUPPORT
  3091. /**
  3092. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3093. * in mesh meta header
  3094. * @tx_desc: software descriptor head pointer
  3095. * @ts: pointer to tx completion stats
  3096. * Return: none
  3097. */
  3098. static
  3099. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3100. struct hal_tx_completion_status *ts)
  3101. {
  3102. struct meta_hdr_s *mhdr;
  3103. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3104. if (!tx_desc->msdu_ext_desc) {
  3105. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3106. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3107. "netbuf %pK offset %d",
  3108. netbuf, tx_desc->pkt_offset);
  3109. return;
  3110. }
  3111. }
  3112. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  3113. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3114. "netbuf %pK offset %lu", netbuf,
  3115. sizeof(struct meta_hdr_s));
  3116. return;
  3117. }
  3118. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  3119. mhdr->rssi = ts->ack_frame_rssi;
  3120. mhdr->band = tx_desc->pdev->operating_channel.band;
  3121. mhdr->channel = tx_desc->pdev->operating_channel.num;
  3122. }
  3123. #else
  3124. static
  3125. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3126. struct hal_tx_completion_status *ts)
  3127. {
  3128. }
  3129. #endif
  3130. #ifdef QCA_PEER_EXT_STATS
  3131. /*
  3132. * dp_tx_compute_tid_delay() - Compute per TID delay
  3133. * @stats: Per TID delay stats
  3134. * @tx_desc: Software Tx descriptor
  3135. *
  3136. * Compute the software enqueue and hw enqueue delays and
  3137. * update the respective histograms
  3138. *
  3139. * Return: void
  3140. */
  3141. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3142. struct dp_tx_desc_s *tx_desc)
  3143. {
  3144. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3145. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3146. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3147. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3148. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3149. timestamp_hw_enqueue = tx_desc->timestamp;
  3150. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3151. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3152. timestamp_hw_enqueue);
  3153. /*
  3154. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3155. */
  3156. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3157. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3158. }
  3159. /*
  3160. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3161. * @peer: DP peer context
  3162. * @tx_desc: Tx software descriptor
  3163. * @tid: Transmission ID
  3164. * @ring_id: Rx CPU context ID/CPU_ID
  3165. *
  3166. * Update the peer extended stats. These are enhanced other
  3167. * delay stats per msdu level.
  3168. *
  3169. * Return: void
  3170. */
  3171. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3172. struct dp_tx_desc_s *tx_desc,
  3173. uint8_t tid, uint8_t ring_id)
  3174. {
  3175. struct dp_pdev *pdev = peer->vdev->pdev;
  3176. struct dp_soc *soc = NULL;
  3177. struct cdp_peer_ext_stats *pext_stats = NULL;
  3178. soc = pdev->soc;
  3179. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3180. return;
  3181. pext_stats = peer->pext_stats;
  3182. qdf_assert(pext_stats);
  3183. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3184. /*
  3185. * For non-TID packets use the TID 9
  3186. */
  3187. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3188. tid = CDP_MAX_DATA_TIDS - 1;
  3189. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3190. tx_desc);
  3191. }
  3192. #else
  3193. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3194. struct dp_tx_desc_s *tx_desc,
  3195. uint8_t tid, uint8_t ring_id)
  3196. {
  3197. }
  3198. #endif
  3199. /**
  3200. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3201. * to pass in correct fields
  3202. *
  3203. * @vdev: pdev handle
  3204. * @tx_desc: tx descriptor
  3205. * @tid: tid value
  3206. * @ring_id: TCL or WBM ring number for transmit path
  3207. * Return: none
  3208. */
  3209. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3210. struct dp_tx_desc_s *tx_desc,
  3211. uint8_t tid, uint8_t ring_id)
  3212. {
  3213. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3214. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3215. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3216. return;
  3217. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3218. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3219. timestamp_hw_enqueue = tx_desc->timestamp;
  3220. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3221. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3222. timestamp_hw_enqueue);
  3223. interframe_delay = (uint32_t)(timestamp_ingress -
  3224. vdev->prev_tx_enq_tstamp);
  3225. /*
  3226. * Delay in software enqueue
  3227. */
  3228. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3229. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3230. /*
  3231. * Delay between packet enqueued to HW and Tx completion
  3232. */
  3233. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3234. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3235. /*
  3236. * Update interframe delay stats calculated at hardstart receive point.
  3237. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3238. * interframe delay will not be calculate correctly for 1st frame.
  3239. * On the other side, this will help in avoiding extra per packet check
  3240. * of !vdev->prev_tx_enq_tstamp.
  3241. */
  3242. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3243. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3244. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3245. }
  3246. #ifdef DISABLE_DP_STATS
  3247. static
  3248. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3249. {
  3250. }
  3251. #else
  3252. static
  3253. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3254. {
  3255. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3256. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3257. if (subtype != QDF_PROTO_INVALID)
  3258. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3259. }
  3260. #endif
  3261. /**
  3262. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3263. * per wbm ring
  3264. *
  3265. * @tx_desc: software descriptor head pointer
  3266. * @ts: Tx completion status
  3267. * @peer: peer handle
  3268. * @ring_id: ring number
  3269. *
  3270. * Return: None
  3271. */
  3272. static inline void
  3273. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3274. struct hal_tx_completion_status *ts,
  3275. struct dp_peer *peer, uint8_t ring_id)
  3276. {
  3277. struct dp_pdev *pdev = peer->vdev->pdev;
  3278. struct dp_soc *soc = NULL;
  3279. uint8_t mcs, pkt_type;
  3280. uint8_t tid = ts->tid;
  3281. uint32_t length;
  3282. struct cdp_tid_tx_stats *tid_stats;
  3283. if (!pdev)
  3284. return;
  3285. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3286. tid = CDP_MAX_DATA_TIDS - 1;
  3287. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3288. soc = pdev->soc;
  3289. mcs = ts->mcs;
  3290. pkt_type = ts->pkt_type;
  3291. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3292. dp_err("Release source is not from TQM");
  3293. return;
  3294. }
  3295. length = qdf_nbuf_len(tx_desc->nbuf);
  3296. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3297. if (qdf_unlikely(pdev->delay_stats_flag))
  3298. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3299. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3300. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3301. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3302. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3303. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3304. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3305. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3306. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3307. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3308. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3309. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3310. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3311. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3312. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3313. /*
  3314. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3315. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3316. * are no completions for failed cases. Hence updating tx_failed from
  3317. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3318. * then this has to be removed
  3319. */
  3320. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3321. peer->stats.tx.dropped.fw_rem_notx +
  3322. peer->stats.tx.dropped.fw_rem_tx +
  3323. peer->stats.tx.dropped.age_out +
  3324. peer->stats.tx.dropped.fw_reason1 +
  3325. peer->stats.tx.dropped.fw_reason2 +
  3326. peer->stats.tx.dropped.fw_reason3;
  3327. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3328. tid_stats->tqm_status_cnt[ts->status]++;
  3329. }
  3330. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3331. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3332. return;
  3333. }
  3334. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3335. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3336. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3337. /*
  3338. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3339. * Return from here if HTT PPDU events are enabled.
  3340. */
  3341. if (!(soc->process_tx_status))
  3342. return;
  3343. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3344. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3345. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3346. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3347. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3348. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3349. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3350. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3351. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3352. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3353. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3354. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3355. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3356. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3357. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3358. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3359. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3360. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3361. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3362. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3363. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3364. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3365. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3366. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3367. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3368. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3369. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3370. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  3371. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  3372. &peer->stats, ts->peer_id,
  3373. UPDATE_PEER_STATS, pdev->pdev_id);
  3374. #endif
  3375. }
  3376. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3377. /**
  3378. * dp_tx_flow_pool_lock() - take flow pool lock
  3379. * @soc: core txrx main context
  3380. * @tx_desc: tx desc
  3381. *
  3382. * Return: None
  3383. */
  3384. static inline
  3385. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3386. struct dp_tx_desc_s *tx_desc)
  3387. {
  3388. struct dp_tx_desc_pool_s *pool;
  3389. uint8_t desc_pool_id;
  3390. desc_pool_id = tx_desc->pool_id;
  3391. pool = &soc->tx_desc[desc_pool_id];
  3392. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3393. }
  3394. /**
  3395. * dp_tx_flow_pool_unlock() - release flow pool lock
  3396. * @soc: core txrx main context
  3397. * @tx_desc: tx desc
  3398. *
  3399. * Return: None
  3400. */
  3401. static inline
  3402. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3403. struct dp_tx_desc_s *tx_desc)
  3404. {
  3405. struct dp_tx_desc_pool_s *pool;
  3406. uint8_t desc_pool_id;
  3407. desc_pool_id = tx_desc->pool_id;
  3408. pool = &soc->tx_desc[desc_pool_id];
  3409. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3410. }
  3411. #else
  3412. static inline
  3413. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3414. {
  3415. }
  3416. static inline
  3417. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3418. {
  3419. }
  3420. #endif
  3421. /**
  3422. * dp_tx_notify_completion() - Notify tx completion for this desc
  3423. * @soc: core txrx main context
  3424. * @vdev: datapath vdev handle
  3425. * @tx_desc: tx desc
  3426. * @netbuf: buffer
  3427. * @status: tx status
  3428. *
  3429. * Return: none
  3430. */
  3431. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3432. struct dp_vdev *vdev,
  3433. struct dp_tx_desc_s *tx_desc,
  3434. qdf_nbuf_t netbuf,
  3435. uint8_t status)
  3436. {
  3437. void *osif_dev;
  3438. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3439. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3440. qdf_assert(tx_desc);
  3441. dp_tx_flow_pool_lock(soc, tx_desc);
  3442. if (!vdev ||
  3443. !vdev->osif_vdev) {
  3444. dp_tx_flow_pool_unlock(soc, tx_desc);
  3445. return;
  3446. }
  3447. osif_dev = vdev->osif_vdev;
  3448. tx_compl_cbk = vdev->tx_comp;
  3449. dp_tx_flow_pool_unlock(soc, tx_desc);
  3450. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3451. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3452. if (tx_compl_cbk)
  3453. tx_compl_cbk(netbuf, osif_dev, flag);
  3454. }
  3455. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3456. * @pdev: pdev handle
  3457. * @tid: tid value
  3458. * @txdesc_ts: timestamp from txdesc
  3459. * @ppdu_id: ppdu id
  3460. *
  3461. * Return: none
  3462. */
  3463. #ifdef FEATURE_PERPKT_INFO
  3464. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3465. struct dp_peer *peer,
  3466. uint8_t tid,
  3467. uint64_t txdesc_ts,
  3468. uint32_t ppdu_id)
  3469. {
  3470. uint64_t delta_ms;
  3471. struct cdp_tx_sojourn_stats *sojourn_stats;
  3472. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  3473. return;
  3474. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3475. tid >= CDP_DATA_TID_MAX))
  3476. return;
  3477. if (qdf_unlikely(!pdev->sojourn_buf))
  3478. return;
  3479. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3480. qdf_nbuf_data(pdev->sojourn_buf);
  3481. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3482. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3483. txdesc_ts;
  3484. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3485. delta_ms);
  3486. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3487. sojourn_stats->num_msdus[tid] = 1;
  3488. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3489. peer->avg_sojourn_msdu[tid].internal;
  3490. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3491. pdev->sojourn_buf, HTT_INVALID_PEER,
  3492. WDI_NO_VAL, pdev->pdev_id);
  3493. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3494. sojourn_stats->num_msdus[tid] = 0;
  3495. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3496. }
  3497. #else
  3498. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3499. struct dp_peer *peer,
  3500. uint8_t tid,
  3501. uint64_t txdesc_ts,
  3502. uint32_t ppdu_id)
  3503. {
  3504. }
  3505. #endif
  3506. /**
  3507. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3508. * @soc: DP Soc handle
  3509. * @tx_desc: software Tx descriptor
  3510. * @ts : Tx completion status from HAL/HTT descriptor
  3511. *
  3512. * Return: none
  3513. */
  3514. static inline void
  3515. dp_tx_comp_process_desc(struct dp_soc *soc,
  3516. struct dp_tx_desc_s *desc,
  3517. struct hal_tx_completion_status *ts,
  3518. struct dp_peer *peer)
  3519. {
  3520. uint64_t time_latency = 0;
  3521. /*
  3522. * m_copy/tx_capture modes are not supported for
  3523. * scatter gather packets
  3524. */
  3525. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3526. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3527. desc->timestamp);
  3528. }
  3529. if (!(desc->msdu_ext_desc)) {
  3530. if (QDF_STATUS_SUCCESS ==
  3531. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3532. return;
  3533. }
  3534. if (QDF_STATUS_SUCCESS ==
  3535. dp_get_completion_indication_for_stack(soc,
  3536. desc->pdev,
  3537. peer, ts,
  3538. desc->nbuf,
  3539. time_latency)) {
  3540. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3541. QDF_DMA_TO_DEVICE,
  3542. desc->nbuf->len);
  3543. dp_send_completion_to_stack(soc,
  3544. desc->pdev,
  3545. ts->peer_id,
  3546. ts->ppdu_id,
  3547. desc->nbuf);
  3548. return;
  3549. }
  3550. }
  3551. dp_tx_comp_free_buf(soc, desc);
  3552. }
  3553. #ifdef DISABLE_DP_STATS
  3554. /**
  3555. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3556. * @soc: core txrx main context
  3557. * @tx_desc: tx desc
  3558. * @status: tx status
  3559. *
  3560. * Return: none
  3561. */
  3562. static inline
  3563. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3564. struct dp_vdev *vdev,
  3565. struct dp_tx_desc_s *tx_desc,
  3566. uint8_t status)
  3567. {
  3568. }
  3569. #else
  3570. static inline
  3571. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3572. struct dp_vdev *vdev,
  3573. struct dp_tx_desc_s *tx_desc,
  3574. uint8_t status)
  3575. {
  3576. void *osif_dev;
  3577. ol_txrx_stats_rx_fp stats_cbk;
  3578. uint8_t pkt_type;
  3579. qdf_assert(tx_desc);
  3580. if (!vdev ||
  3581. !vdev->osif_vdev ||
  3582. !vdev->stats_cb)
  3583. return;
  3584. osif_dev = vdev->osif_vdev;
  3585. stats_cbk = vdev->stats_cb;
  3586. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3587. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3588. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3589. &pkt_type);
  3590. }
  3591. #endif
  3592. /**
  3593. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3594. * @soc: DP soc handle
  3595. * @tx_desc: software descriptor head pointer
  3596. * @ts: Tx completion status
  3597. * @peer: peer handle
  3598. * @ring_id: ring number
  3599. *
  3600. * Return: none
  3601. */
  3602. static inline
  3603. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3604. struct dp_tx_desc_s *tx_desc,
  3605. struct hal_tx_completion_status *ts,
  3606. struct dp_peer *peer, uint8_t ring_id)
  3607. {
  3608. uint32_t length;
  3609. qdf_ether_header_t *eh;
  3610. struct dp_vdev *vdev = NULL;
  3611. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3612. enum qdf_dp_tx_rx_status dp_status;
  3613. if (!nbuf) {
  3614. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3615. goto out;
  3616. }
  3617. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3618. length = qdf_nbuf_len(nbuf);
  3619. dp_status = dp_tx_hw_to_qdf(ts->status);
  3620. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3621. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3622. QDF_TRACE_DEFAULT_PDEV_ID,
  3623. qdf_nbuf_data_addr(nbuf),
  3624. sizeof(qdf_nbuf_data(nbuf)),
  3625. tx_desc->id, ts->status, dp_status));
  3626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3627. "-------------------- \n"
  3628. "Tx Completion Stats: \n"
  3629. "-------------------- \n"
  3630. "ack_frame_rssi = %d \n"
  3631. "first_msdu = %d \n"
  3632. "last_msdu = %d \n"
  3633. "msdu_part_of_amsdu = %d \n"
  3634. "rate_stats valid = %d \n"
  3635. "bw = %d \n"
  3636. "pkt_type = %d \n"
  3637. "stbc = %d \n"
  3638. "ldpc = %d \n"
  3639. "sgi = %d \n"
  3640. "mcs = %d \n"
  3641. "ofdma = %d \n"
  3642. "tones_in_ru = %d \n"
  3643. "tsf = %d \n"
  3644. "ppdu_id = %d \n"
  3645. "transmit_cnt = %d \n"
  3646. "tid = %d \n"
  3647. "peer_id = %d\n",
  3648. ts->ack_frame_rssi, ts->first_msdu,
  3649. ts->last_msdu, ts->msdu_part_of_amsdu,
  3650. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3651. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3652. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3653. ts->transmit_cnt, ts->tid, ts->peer_id);
  3654. /* Update SoC level stats */
  3655. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3656. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3657. if (!peer) {
  3658. dp_info_rl("peer is null or deletion in progress");
  3659. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3660. goto out;
  3661. }
  3662. vdev = peer->vdev;
  3663. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3664. /* Update per-packet stats for mesh mode */
  3665. if (qdf_unlikely(vdev->mesh_vdev) &&
  3666. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3667. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3668. /* Update peer level stats */
  3669. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3670. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3671. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3672. if ((peer->vdev->tx_encap_type ==
  3673. htt_cmn_pkt_type_ethernet) &&
  3674. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3675. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3676. }
  3677. }
  3678. } else {
  3679. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3680. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3681. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3682. if (qdf_unlikely(peer->in_twt)) {
  3683. DP_STATS_INC_PKT(peer,
  3684. tx.tx_success_twt,
  3685. 1, length);
  3686. }
  3687. }
  3688. }
  3689. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3690. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3691. #ifdef QCA_SUPPORT_RDK_STATS
  3692. if (soc->rdkstats_enabled)
  3693. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3694. tx_desc->timestamp,
  3695. ts->ppdu_id);
  3696. #endif
  3697. out:
  3698. return;
  3699. }
  3700. /**
  3701. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3702. * @soc: core txrx main context
  3703. * @comp_head: software descriptor head pointer
  3704. * @ring_id: ring number
  3705. *
  3706. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3707. * and release the software descriptors after processing is complete
  3708. *
  3709. * Return: none
  3710. */
  3711. static void
  3712. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3713. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3714. {
  3715. struct dp_tx_desc_s *desc;
  3716. struct dp_tx_desc_s *next;
  3717. struct hal_tx_completion_status ts;
  3718. struct dp_peer *peer = NULL;
  3719. uint16_t peer_id = DP_INVALID_PEER;
  3720. qdf_nbuf_t netbuf;
  3721. desc = comp_head;
  3722. while (desc) {
  3723. if (peer_id != desc->peer_id) {
  3724. if (peer)
  3725. dp_peer_unref_delete(peer,
  3726. DP_MOD_ID_TX_COMP);
  3727. peer_id = desc->peer_id;
  3728. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3729. DP_MOD_ID_TX_COMP);
  3730. }
  3731. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3732. struct dp_pdev *pdev = desc->pdev;
  3733. if (qdf_likely(peer)) {
  3734. /*
  3735. * Increment peer statistics
  3736. * Minimal statistics update done here
  3737. */
  3738. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3739. desc->length);
  3740. if (desc->tx_status !=
  3741. HAL_TX_TQM_RR_FRAME_ACKED)
  3742. DP_STATS_INC(peer, tx.tx_failed, 1);
  3743. }
  3744. qdf_assert(pdev);
  3745. dp_tx_outstanding_dec(pdev);
  3746. /*
  3747. * Calling a QDF WRAPPER here is creating signifcant
  3748. * performance impact so avoided the wrapper call here
  3749. */
  3750. next = desc->next;
  3751. qdf_mem_unmap_nbytes_single(soc->osdev,
  3752. desc->dma_addr,
  3753. QDF_DMA_TO_DEVICE,
  3754. desc->length);
  3755. qdf_nbuf_free(desc->nbuf);
  3756. dp_tx_desc_free(soc, desc, desc->pool_id);
  3757. desc = next;
  3758. continue;
  3759. }
  3760. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3761. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3762. netbuf = desc->nbuf;
  3763. /* check tx complete notification */
  3764. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3765. dp_tx_notify_completion(soc, peer->vdev, desc,
  3766. netbuf, ts.status);
  3767. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3768. next = desc->next;
  3769. dp_tx_desc_release(desc, desc->pool_id);
  3770. desc = next;
  3771. }
  3772. if (peer)
  3773. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3774. }
  3775. /**
  3776. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3777. * @soc: Handle to DP soc structure
  3778. * @tx_desc: software descriptor head pointer
  3779. * @status : Tx completion status from HTT descriptor
  3780. * @ring_id: ring number
  3781. *
  3782. * This function will process HTT Tx indication messages from Target
  3783. *
  3784. * Return: none
  3785. */
  3786. static
  3787. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3788. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3789. uint8_t ring_id)
  3790. {
  3791. uint8_t tx_status;
  3792. struct dp_pdev *pdev;
  3793. struct dp_vdev *vdev;
  3794. struct hal_tx_completion_status ts = {0};
  3795. uint32_t *htt_desc = (uint32_t *)status;
  3796. struct dp_peer *peer;
  3797. struct cdp_tid_tx_stats *tid_stats = NULL;
  3798. struct htt_soc *htt_handle;
  3799. uint8_t vdev_id;
  3800. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3801. htt_handle = (struct htt_soc *)soc->htt_handle;
  3802. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3803. /*
  3804. * There can be scenario where WBM consuming descriptor enqueued
  3805. * from TQM2WBM first and TQM completion can happen before MEC
  3806. * notification comes from FW2WBM. Avoid access any field of tx
  3807. * descriptor in case of MEC notify.
  3808. */
  3809. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3810. /*
  3811. * Get vdev id from HTT status word in case of MEC
  3812. * notification
  3813. */
  3814. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3815. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3816. return;
  3817. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3818. DP_MOD_ID_HTT_COMP);
  3819. if (!vdev)
  3820. return;
  3821. dp_tx_mec_handler(vdev, status);
  3822. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3823. return;
  3824. }
  3825. /*
  3826. * If the descriptor is already freed in vdev_detach,
  3827. * continue to next descriptor
  3828. */
  3829. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3830. QDF_TRACE(QDF_MODULE_ID_DP,
  3831. QDF_TRACE_LEVEL_INFO,
  3832. "Descriptor freed in vdev_detach %d",
  3833. tx_desc->id);
  3834. return;
  3835. }
  3836. pdev = tx_desc->pdev;
  3837. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3838. QDF_TRACE(QDF_MODULE_ID_DP,
  3839. QDF_TRACE_LEVEL_INFO,
  3840. "pdev in down state %d",
  3841. tx_desc->id);
  3842. dp_tx_comp_free_buf(soc, tx_desc);
  3843. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3844. return;
  3845. }
  3846. qdf_assert(tx_desc->pdev);
  3847. vdev_id = tx_desc->vdev_id;
  3848. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3849. DP_MOD_ID_HTT_COMP);
  3850. if (!vdev)
  3851. return;
  3852. switch (tx_status) {
  3853. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3854. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3855. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3856. {
  3857. uint8_t tid;
  3858. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3859. ts.peer_id =
  3860. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3861. htt_desc[2]);
  3862. ts.tid =
  3863. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3864. htt_desc[2]);
  3865. } else {
  3866. ts.peer_id = HTT_INVALID_PEER;
  3867. ts.tid = HTT_INVALID_TID;
  3868. }
  3869. ts.ppdu_id =
  3870. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3871. htt_desc[1]);
  3872. ts.ack_frame_rssi =
  3873. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3874. htt_desc[1]);
  3875. ts.tsf = htt_desc[3];
  3876. ts.first_msdu = 1;
  3877. ts.last_msdu = 1;
  3878. tid = ts.tid;
  3879. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3880. tid = CDP_MAX_DATA_TIDS - 1;
  3881. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3882. if (qdf_unlikely(pdev->delay_stats_flag))
  3883. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3884. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3885. tid_stats->htt_status_cnt[tx_status]++;
  3886. }
  3887. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3888. DP_MOD_ID_HTT_COMP);
  3889. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3890. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3891. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3892. if (qdf_likely(peer))
  3893. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3894. break;
  3895. }
  3896. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3897. {
  3898. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3899. break;
  3900. }
  3901. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3902. {
  3903. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3904. break;
  3905. }
  3906. default:
  3907. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3908. "%s Invalid HTT tx_status %d\n",
  3909. __func__, tx_status);
  3910. break;
  3911. }
  3912. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3913. }
  3914. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3915. static inline
  3916. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3917. {
  3918. bool limit_hit = false;
  3919. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3920. limit_hit =
  3921. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3922. if (limit_hit)
  3923. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3924. return limit_hit;
  3925. }
  3926. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3927. {
  3928. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3929. }
  3930. #else
  3931. static inline
  3932. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3933. {
  3934. return false;
  3935. }
  3936. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3937. {
  3938. return false;
  3939. }
  3940. #endif
  3941. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3942. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3943. uint32_t quota)
  3944. {
  3945. void *tx_comp_hal_desc;
  3946. uint8_t buffer_src;
  3947. uint8_t pool_id;
  3948. uint32_t tx_desc_id;
  3949. struct dp_tx_desc_s *tx_desc = NULL;
  3950. struct dp_tx_desc_s *head_desc = NULL;
  3951. struct dp_tx_desc_s *tail_desc = NULL;
  3952. uint32_t num_processed = 0;
  3953. uint32_t count;
  3954. uint32_t num_avail_for_reap = 0;
  3955. bool force_break = false;
  3956. DP_HIST_INIT();
  3957. more_data:
  3958. /* Re-initialize local variables to be re-used */
  3959. head_desc = NULL;
  3960. tail_desc = NULL;
  3961. count = 0;
  3962. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3963. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3964. return 0;
  3965. }
  3966. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3967. if (num_avail_for_reap >= quota)
  3968. num_avail_for_reap = quota;
  3969. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3970. /* Find head descriptor from completion ring */
  3971. while (qdf_likely(num_avail_for_reap)) {
  3972. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3973. if (qdf_unlikely(!tx_comp_hal_desc))
  3974. break;
  3975. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3976. /* If this buffer was not released by TQM or FW, then it is not
  3977. * Tx completion indication, assert */
  3978. if (qdf_unlikely(buffer_src !=
  3979. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3980. (qdf_unlikely(buffer_src !=
  3981. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3982. uint8_t wbm_internal_error;
  3983. dp_err_rl(
  3984. "Tx comp release_src != TQM | FW but from %d",
  3985. buffer_src);
  3986. hal_dump_comp_desc(tx_comp_hal_desc);
  3987. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3988. /* When WBM sees NULL buffer_addr_info in any of
  3989. * ingress rings it sends an error indication,
  3990. * with wbm_internal_error=1, to a specific ring.
  3991. * The WBM2SW ring used to indicate these errors is
  3992. * fixed in HW, and that ring is being used as Tx
  3993. * completion ring. These errors are not related to
  3994. * Tx completions, and should just be ignored
  3995. */
  3996. wbm_internal_error = hal_get_wbm_internal_error(
  3997. soc->hal_soc,
  3998. tx_comp_hal_desc);
  3999. if (wbm_internal_error) {
  4000. dp_err_rl("Tx comp wbm_internal_error!!");
  4001. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4002. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4003. buffer_src)
  4004. dp_handle_wbm_internal_error(
  4005. soc,
  4006. tx_comp_hal_desc,
  4007. hal_tx_comp_get_buffer_type(
  4008. tx_comp_hal_desc));
  4009. } else {
  4010. dp_err_rl("Tx comp wbm_internal_error false");
  4011. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4012. }
  4013. continue;
  4014. }
  4015. /* Get descriptor id */
  4016. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  4017. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  4018. DP_TX_DESC_ID_POOL_OS;
  4019. /* Find Tx descriptor */
  4020. tx_desc = dp_tx_desc_find(soc, pool_id,
  4021. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  4022. DP_TX_DESC_ID_PAGE_OS,
  4023. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  4024. DP_TX_DESC_ID_OFFSET_OS);
  4025. /*
  4026. * If the release source is FW, process the HTT status
  4027. */
  4028. if (qdf_unlikely(buffer_src ==
  4029. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4030. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4031. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4032. htt_tx_status);
  4033. dp_tx_process_htt_completion(soc, tx_desc,
  4034. htt_tx_status, ring_id);
  4035. } else {
  4036. tx_desc->peer_id =
  4037. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  4038. tx_desc->tx_status =
  4039. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4040. /*
  4041. * If the fast completion mode is enabled extended
  4042. * metadata from descriptor is not copied
  4043. */
  4044. if (qdf_likely(tx_desc->flags &
  4045. DP_TX_DESC_FLAG_SIMPLE))
  4046. goto add_to_pool;
  4047. /*
  4048. * If the descriptor is already freed in vdev_detach,
  4049. * continue to next descriptor
  4050. */
  4051. if (qdf_unlikely
  4052. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4053. !tx_desc->flags)) {
  4054. QDF_TRACE(QDF_MODULE_ID_DP,
  4055. QDF_TRACE_LEVEL_INFO,
  4056. "Descriptor freed in vdev_detach %d",
  4057. tx_desc_id);
  4058. continue;
  4059. }
  4060. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4061. QDF_TRACE(QDF_MODULE_ID_DP,
  4062. QDF_TRACE_LEVEL_INFO,
  4063. "pdev in down state %d",
  4064. tx_desc_id);
  4065. dp_tx_comp_free_buf(soc, tx_desc);
  4066. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4067. goto next_desc;
  4068. }
  4069. /* Pool id is not matching. Error */
  4070. if (tx_desc->pool_id != pool_id) {
  4071. QDF_TRACE(QDF_MODULE_ID_DP,
  4072. QDF_TRACE_LEVEL_FATAL,
  4073. "Tx Comp pool id %d not matched %d",
  4074. pool_id, tx_desc->pool_id);
  4075. qdf_assert_always(0);
  4076. }
  4077. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4078. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4079. QDF_TRACE(QDF_MODULE_ID_DP,
  4080. QDF_TRACE_LEVEL_FATAL,
  4081. "Txdesc invalid, flgs = %x,id = %d",
  4082. tx_desc->flags, tx_desc_id);
  4083. qdf_assert_always(0);
  4084. }
  4085. /* Collect hw completion contents */
  4086. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4087. &tx_desc->comp, 1);
  4088. add_to_pool:
  4089. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4090. /* First ring descriptor on the cycle */
  4091. if (!head_desc) {
  4092. head_desc = tx_desc;
  4093. tail_desc = tx_desc;
  4094. }
  4095. tail_desc->next = tx_desc;
  4096. tx_desc->next = NULL;
  4097. tail_desc = tx_desc;
  4098. }
  4099. next_desc:
  4100. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4101. /*
  4102. * Processed packet count is more than given quota
  4103. * stop to processing
  4104. */
  4105. count++;
  4106. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  4107. break;
  4108. }
  4109. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4110. /* Process the reaped descriptors */
  4111. if (head_desc)
  4112. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4113. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4114. if (num_processed >= quota)
  4115. force_break = true;
  4116. if (!force_break &&
  4117. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4118. hal_ring_hdl)) {
  4119. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4120. if (!hif_exec_should_yield(soc->hif_handle,
  4121. int_ctx->dp_intr_id))
  4122. goto more_data;
  4123. }
  4124. }
  4125. DP_TX_HIST_STATS_PER_PDEV();
  4126. return num_processed;
  4127. }
  4128. #ifdef FEATURE_WLAN_TDLS
  4129. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4130. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4131. {
  4132. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4133. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4134. DP_MOD_ID_TDLS);
  4135. if (!vdev) {
  4136. dp_err("vdev handle for id %d is NULL", vdev_id);
  4137. return NULL;
  4138. }
  4139. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4140. vdev->is_tdls_frame = true;
  4141. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4142. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4143. }
  4144. #endif
  4145. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4146. {
  4147. struct wlan_cfg_dp_soc_ctxt *cfg;
  4148. struct dp_soc *soc;
  4149. soc = vdev->pdev->soc;
  4150. if (!soc)
  4151. return;
  4152. cfg = soc->wlan_cfg_ctx;
  4153. if (!cfg)
  4154. return;
  4155. if (vdev->opmode == wlan_op_mode_ndi)
  4156. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4157. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4158. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4159. (vdev->subtype == wlan_op_subtype_p2p_go))
  4160. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4161. else
  4162. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4163. }
  4164. /**
  4165. * dp_tx_vdev_attach() - attach vdev to dp tx
  4166. * @vdev: virtual device instance
  4167. *
  4168. * Return: QDF_STATUS_SUCCESS: success
  4169. * QDF_STATUS_E_RESOURCES: Error return
  4170. */
  4171. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4172. {
  4173. int pdev_id;
  4174. /*
  4175. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4176. */
  4177. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4178. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4179. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4180. vdev->vdev_id);
  4181. pdev_id =
  4182. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4183. vdev->pdev->pdev_id);
  4184. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4185. /*
  4186. * Set HTT Extension Valid bit to 0 by default
  4187. */
  4188. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4189. dp_tx_vdev_update_search_flags(vdev);
  4190. dp_tx_vdev_update_feature_flags(vdev);
  4191. return QDF_STATUS_SUCCESS;
  4192. }
  4193. #ifndef FEATURE_WDS
  4194. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4195. {
  4196. return false;
  4197. }
  4198. #endif
  4199. /**
  4200. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4201. * @vdev: virtual device instance
  4202. *
  4203. * Return: void
  4204. *
  4205. */
  4206. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4207. {
  4208. struct dp_soc *soc = vdev->pdev->soc;
  4209. /*
  4210. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4211. * for TDLS link
  4212. *
  4213. * Enable AddrY (SA based search) only for non-WDS STA and
  4214. * ProxySTA VAP (in HKv1) modes.
  4215. *
  4216. * In all other VAP modes, only DA based search should be
  4217. * enabled
  4218. */
  4219. if (vdev->opmode == wlan_op_mode_sta &&
  4220. vdev->tdls_link_connected)
  4221. vdev->hal_desc_addr_search_flags =
  4222. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4223. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4224. !dp_tx_da_search_override(vdev))
  4225. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4226. else
  4227. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4228. /* Set search type only when peer map v2 messaging is enabled
  4229. * as we will have the search index (AST hash) only when v2 is
  4230. * enabled
  4231. */
  4232. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  4233. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  4234. else
  4235. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4236. }
  4237. static inline bool
  4238. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4239. struct dp_vdev *vdev,
  4240. struct dp_tx_desc_s *tx_desc)
  4241. {
  4242. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4243. return false;
  4244. /*
  4245. * if vdev is given, then only check whether desc
  4246. * vdev match. if vdev is NULL, then check whether
  4247. * desc pdev match.
  4248. */
  4249. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4250. (tx_desc->pdev == pdev);
  4251. }
  4252. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4253. /**
  4254. * dp_tx_desc_flush() - release resources associated
  4255. * to TX Desc
  4256. *
  4257. * @dp_pdev: Handle to DP pdev structure
  4258. * @vdev: virtual device instance
  4259. * NULL: no specific Vdev is required and check all allcated TX desc
  4260. * on this pdev.
  4261. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4262. *
  4263. * @force_free:
  4264. * true: flush the TX desc.
  4265. * false: only reset the Vdev in each allocated TX desc
  4266. * that associated to current Vdev.
  4267. *
  4268. * This function will go through the TX desc pool to flush
  4269. * the outstanding TX data or reset Vdev to NULL in associated TX
  4270. * Desc.
  4271. */
  4272. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4273. bool force_free)
  4274. {
  4275. uint8_t i;
  4276. uint32_t j;
  4277. uint32_t num_desc, page_id, offset;
  4278. uint16_t num_desc_per_page;
  4279. struct dp_soc *soc = pdev->soc;
  4280. struct dp_tx_desc_s *tx_desc = NULL;
  4281. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4282. if (!vdev && !force_free) {
  4283. dp_err("Reset TX desc vdev, Vdev param is required!");
  4284. return;
  4285. }
  4286. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4287. tx_desc_pool = &soc->tx_desc[i];
  4288. if (!(tx_desc_pool->pool_size) ||
  4289. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4290. !(tx_desc_pool->desc_pages.cacheable_pages))
  4291. continue;
  4292. /*
  4293. * Add flow pool lock protection in case pool is freed
  4294. * due to all tx_desc is recycled when handle TX completion.
  4295. * this is not necessary when do force flush as:
  4296. * a. double lock will happen if dp_tx_desc_release is
  4297. * also trying to acquire it.
  4298. * b. dp interrupt has been disabled before do force TX desc
  4299. * flush in dp_pdev_deinit().
  4300. */
  4301. if (!force_free)
  4302. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4303. num_desc = tx_desc_pool->pool_size;
  4304. num_desc_per_page =
  4305. tx_desc_pool->desc_pages.num_element_per_page;
  4306. for (j = 0; j < num_desc; j++) {
  4307. page_id = j / num_desc_per_page;
  4308. offset = j % num_desc_per_page;
  4309. if (qdf_unlikely(!(tx_desc_pool->
  4310. desc_pages.cacheable_pages)))
  4311. break;
  4312. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4313. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4314. /*
  4315. * Free TX desc if force free is
  4316. * required, otherwise only reset vdev
  4317. * in this TX desc.
  4318. */
  4319. if (force_free) {
  4320. dp_tx_comp_free_buf(soc, tx_desc);
  4321. dp_tx_desc_release(tx_desc, i);
  4322. } else {
  4323. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4324. }
  4325. }
  4326. }
  4327. if (!force_free)
  4328. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4329. }
  4330. }
  4331. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4332. /**
  4333. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4334. *
  4335. * @soc: Handle to DP soc structure
  4336. * @tx_desc: pointer of one TX desc
  4337. * @desc_pool_id: TX Desc pool id
  4338. */
  4339. static inline void
  4340. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4341. uint8_t desc_pool_id)
  4342. {
  4343. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4344. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4345. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4346. }
  4347. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4348. bool force_free)
  4349. {
  4350. uint8_t i, num_pool;
  4351. uint32_t j;
  4352. uint32_t num_desc, page_id, offset;
  4353. uint16_t num_desc_per_page;
  4354. struct dp_soc *soc = pdev->soc;
  4355. struct dp_tx_desc_s *tx_desc = NULL;
  4356. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4357. if (!vdev && !force_free) {
  4358. dp_err("Reset TX desc vdev, Vdev param is required!");
  4359. return;
  4360. }
  4361. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4362. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4363. for (i = 0; i < num_pool; i++) {
  4364. tx_desc_pool = &soc->tx_desc[i];
  4365. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4366. continue;
  4367. num_desc_per_page =
  4368. tx_desc_pool->desc_pages.num_element_per_page;
  4369. for (j = 0; j < num_desc; j++) {
  4370. page_id = j / num_desc_per_page;
  4371. offset = j % num_desc_per_page;
  4372. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4373. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4374. if (force_free) {
  4375. dp_tx_comp_free_buf(soc, tx_desc);
  4376. dp_tx_desc_release(tx_desc, i);
  4377. } else {
  4378. dp_tx_desc_reset_vdev(soc, tx_desc,
  4379. i);
  4380. }
  4381. }
  4382. }
  4383. }
  4384. }
  4385. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4386. /**
  4387. * dp_tx_vdev_detach() - detach vdev from dp tx
  4388. * @vdev: virtual device instance
  4389. *
  4390. * Return: QDF_STATUS_SUCCESS: success
  4391. * QDF_STATUS_E_RESOURCES: Error return
  4392. */
  4393. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4394. {
  4395. struct dp_pdev *pdev = vdev->pdev;
  4396. /* Reset TX desc associated to this Vdev as NULL */
  4397. dp_tx_desc_flush(pdev, vdev, false);
  4398. dp_tx_vdev_multipass_deinit(vdev);
  4399. return QDF_STATUS_SUCCESS;
  4400. }
  4401. /**
  4402. * dp_tx_pdev_attach() - attach pdev to dp tx
  4403. * @pdev: physical device instance
  4404. *
  4405. * Return: QDF_STATUS_SUCCESS: success
  4406. * QDF_STATUS_E_RESOURCES: Error return
  4407. */
  4408. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  4409. {
  4410. struct dp_soc *soc = pdev->soc;
  4411. /* Initialize Flow control counters */
  4412. qdf_atomic_init(&pdev->num_tx_outstanding);
  4413. pdev->tx_descs_max = 0;
  4414. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  4415. /* Initialize descriptors in TCL Ring */
  4416. hal_tx_init_data_ring(soc->hal_soc,
  4417. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  4418. }
  4419. return QDF_STATUS_SUCCESS;
  4420. }
  4421. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4422. /* Pools will be allocated dynamically */
  4423. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4424. int num_desc)
  4425. {
  4426. uint8_t i;
  4427. for (i = 0; i < num_pool; i++) {
  4428. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4429. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4430. }
  4431. return QDF_STATUS_SUCCESS;
  4432. }
  4433. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4434. int num_desc)
  4435. {
  4436. return QDF_STATUS_SUCCESS;
  4437. }
  4438. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4439. {
  4440. }
  4441. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4442. {
  4443. uint8_t i;
  4444. for (i = 0; i < num_pool; i++)
  4445. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4446. }
  4447. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4448. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4449. int num_desc)
  4450. {
  4451. uint8_t i, count;
  4452. /* Allocate software Tx descriptor pools */
  4453. for (i = 0; i < num_pool; i++) {
  4454. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4455. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4456. FL("Tx Desc Pool alloc %d failed %pK"),
  4457. i, soc);
  4458. goto fail;
  4459. }
  4460. }
  4461. return QDF_STATUS_SUCCESS;
  4462. fail:
  4463. for (count = 0; count < i; count++)
  4464. dp_tx_desc_pool_free(soc, count);
  4465. return QDF_STATUS_E_NOMEM;
  4466. }
  4467. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4468. int num_desc)
  4469. {
  4470. uint8_t i;
  4471. for (i = 0; i < num_pool; i++) {
  4472. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4473. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4474. FL("Tx Desc Pool init %d failed %pK"),
  4475. i, soc);
  4476. return QDF_STATUS_E_NOMEM;
  4477. }
  4478. }
  4479. return QDF_STATUS_SUCCESS;
  4480. }
  4481. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4482. {
  4483. uint8_t i;
  4484. for (i = 0; i < num_pool; i++)
  4485. dp_tx_desc_pool_deinit(soc, i);
  4486. }
  4487. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4488. {
  4489. uint8_t i;
  4490. for (i = 0; i < num_pool; i++)
  4491. dp_tx_desc_pool_free(soc, i);
  4492. }
  4493. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4494. /**
  4495. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4496. * @soc: core txrx main context
  4497. * @num_pool: number of pools
  4498. *
  4499. */
  4500. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4501. {
  4502. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4503. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4504. }
  4505. /**
  4506. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4507. * @soc: core txrx main context
  4508. * @num_pool: number of pools
  4509. *
  4510. */
  4511. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4512. {
  4513. dp_tx_tso_desc_pool_free(soc, num_pool);
  4514. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4515. }
  4516. /**
  4517. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4518. * @soc: core txrx main context
  4519. *
  4520. * This function frees all tx related descriptors as below
  4521. * 1. Regular TX descriptors (static pools)
  4522. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4523. * 3. TSO descriptors
  4524. *
  4525. */
  4526. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4527. {
  4528. uint8_t num_pool;
  4529. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4530. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4531. dp_tx_ext_desc_pool_free(soc, num_pool);
  4532. dp_tx_delete_static_pools(soc, num_pool);
  4533. }
  4534. /**
  4535. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4536. * @soc: core txrx main context
  4537. *
  4538. * This function de-initializes all tx related descriptors as below
  4539. * 1. Regular TX descriptors (static pools)
  4540. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4541. * 3. TSO descriptors
  4542. *
  4543. */
  4544. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4545. {
  4546. uint8_t num_pool;
  4547. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4548. dp_tx_flow_control_deinit(soc);
  4549. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4550. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4551. dp_tx_deinit_static_pools(soc, num_pool);
  4552. }
  4553. /**
  4554. * dp_tso_attach() - TSO attach handler
  4555. * @txrx_soc: Opaque Dp handle
  4556. *
  4557. * Reserve TSO descriptor buffers
  4558. *
  4559. * Return: QDF_STATUS_E_FAILURE on failure or
  4560. * QDF_STATUS_SUCCESS on success
  4561. */
  4562. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4563. uint8_t num_pool,
  4564. uint16_t num_desc)
  4565. {
  4566. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4567. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4568. return QDF_STATUS_E_FAILURE;
  4569. }
  4570. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4571. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4572. num_pool, soc);
  4573. return QDF_STATUS_E_FAILURE;
  4574. }
  4575. return QDF_STATUS_SUCCESS;
  4576. }
  4577. /**
  4578. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4579. * @soc: DP soc handle
  4580. * @num_pool: Number of pools
  4581. * @num_desc: Number of descriptors
  4582. *
  4583. * Initialize TSO descriptor pools
  4584. *
  4585. * Return: QDF_STATUS_E_FAILURE on failure or
  4586. * QDF_STATUS_SUCCESS on success
  4587. */
  4588. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4589. uint8_t num_pool,
  4590. uint16_t num_desc)
  4591. {
  4592. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4593. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4594. return QDF_STATUS_E_FAILURE;
  4595. }
  4596. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4597. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4598. num_pool, soc);
  4599. return QDF_STATUS_E_FAILURE;
  4600. }
  4601. return QDF_STATUS_SUCCESS;
  4602. }
  4603. /**
  4604. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4605. * @soc: core txrx main context
  4606. *
  4607. * This function allocates memory for following descriptor pools
  4608. * 1. regular sw tx descriptor pools (static pools)
  4609. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4610. * 3. TSO descriptor pools
  4611. *
  4612. * Return: QDF_STATUS_SUCCESS: success
  4613. * QDF_STATUS_E_RESOURCES: Error return
  4614. */
  4615. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4616. {
  4617. uint8_t num_pool;
  4618. uint32_t num_desc;
  4619. uint32_t num_ext_desc;
  4620. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4621. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4622. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4623. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4624. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4625. __func__, num_pool, num_desc);
  4626. if ((num_pool > MAX_TXDESC_POOLS) ||
  4627. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4628. goto fail1;
  4629. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4630. goto fail1;
  4631. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4632. goto fail2;
  4633. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4634. return QDF_STATUS_SUCCESS;
  4635. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4636. goto fail3;
  4637. return QDF_STATUS_SUCCESS;
  4638. fail3:
  4639. dp_tx_ext_desc_pool_free(soc, num_pool);
  4640. fail2:
  4641. dp_tx_delete_static_pools(soc, num_pool);
  4642. fail1:
  4643. return QDF_STATUS_E_RESOURCES;
  4644. }
  4645. /**
  4646. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4647. * @soc: core txrx main context
  4648. *
  4649. * This function initializes the following TX descriptor pools
  4650. * 1. regular sw tx descriptor pools (static pools)
  4651. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4652. * 3. TSO descriptor pools
  4653. *
  4654. * Return: QDF_STATUS_SUCCESS: success
  4655. * QDF_STATUS_E_RESOURCES: Error return
  4656. */
  4657. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4658. {
  4659. uint8_t num_pool;
  4660. uint32_t num_desc;
  4661. uint32_t num_ext_desc;
  4662. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4663. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4664. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4665. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4666. goto fail1;
  4667. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4668. goto fail2;
  4669. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4670. return QDF_STATUS_SUCCESS;
  4671. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4672. goto fail3;
  4673. dp_tx_flow_control_init(soc);
  4674. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4675. return QDF_STATUS_SUCCESS;
  4676. fail3:
  4677. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4678. fail2:
  4679. dp_tx_deinit_static_pools(soc, num_pool);
  4680. fail1:
  4681. return QDF_STATUS_E_RESOURCES;
  4682. }
  4683. /**
  4684. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4685. * @txrx_soc: dp soc handle
  4686. *
  4687. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4688. * QDF_STATUS_E_FAILURE
  4689. */
  4690. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4691. {
  4692. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4693. uint8_t num_pool;
  4694. uint32_t num_desc;
  4695. uint32_t num_ext_desc;
  4696. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4697. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4698. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4699. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4700. return QDF_STATUS_E_FAILURE;
  4701. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4702. return QDF_STATUS_E_FAILURE;
  4703. return QDF_STATUS_SUCCESS;
  4704. }
  4705. /**
  4706. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4707. * @txrx_soc: dp soc handle
  4708. *
  4709. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4710. */
  4711. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4712. {
  4713. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4714. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4715. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4716. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4717. return QDF_STATUS_SUCCESS;
  4718. }